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tcg/ppc: Fix failure in tcg_out_mem_long
[qemu.git] / tcg / tcg.c
CommitLineData
c896fe29
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
c896fe29
FB		 25/* define it to use liveness analysis (better code) */
26#define USE_LIVENESS_ANALYSIS
8f2e8c07 27#define USE_TCG_OPTIMIZATIONS
c896fe29 28
cca82982
AJ		 29#include "config.h"
30
813da627
RH		 31/* Define to jump the ELF file used to communicate with GDB. */
32#undef DEBUG_JIT
33
a6c6f76c 34#if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
cca82982
AJ		 35/* define it to suppress various consistency checks (faster) */
36#define NDEBUG
37#endif
38
ca10f867 39#include "qemu-common.h"
1de7afc9
PB		 40#include "qemu/host-utils.h"
41#include "qemu/timer.h"
c896fe29 42
c5d3c498 43/* Note: the long term plan is to reduce the dependencies on the QEMU
c896fe29
FB		 44 CPU definitions. Currently they are used for qemu_ld/st
45 instructions */
46#define NO_CPU_IO_DEFS
47#include "cpu.h"
c896fe29
FB		 48
49#include "tcg-op.h"
813da627 50
edee2579 51#if UINTPTR_MAX == UINT32_MAX
813da627 52# define ELF_CLASS ELFCLASS32
edee2579
RH		 53#else
54# define ELF_CLASS ELFCLASS64
813da627
RH		 55#endif
56#ifdef HOST_WORDS_BIGENDIAN
57# define ELF_DATA ELFDATA2MSB
58#else
59# define ELF_DATA ELFDATA2LSB
60#endif
61
c896fe29
FB		 62#include "elf.h"
63
c0ad3001 64/* Forward declarations for functions declared in tcg-target.c and used here. */
e4d58b41
RH		 65static void tcg_target_init(TCGContext *s);
66static void tcg_target_qemu_prologue(TCGContext *s);
1813e175 67static void patch_reloc(tcg_insn_unit *code_ptr, int type,
2ba7fae2 68 intptr_t value, intptr_t addend);
c896fe29 69
497a22eb
RH		 70/* The CIE and FDE header definitions will be common to all hosts. */
71typedef struct {
72 uint32_t len __attribute__((aligned((sizeof(void *)))));
73 uint32_t id;
74 uint8_t version;
75 char augmentation[1];
76 uint8_t code_align;
77 uint8_t data_align;
78 uint8_t return_column;
79} DebugFrameCIE;
80
81typedef struct QEMU_PACKED {
82 uint32_t len __attribute__((aligned((sizeof(void *)))));
83 uint32_t cie_offset;
edee2579
RH		 84 uintptr_t func_start;
85 uintptr_t func_len;
497a22eb
RH		 86} DebugFrameFDEHeader;
87
2c90784a
RH		 88typedef struct QEMU_PACKED {
89 DebugFrameCIE cie;
90 DebugFrameFDEHeader fde;
91} DebugFrameHeader;
92
813da627 93static void tcg_register_jit_int(void *buf, size_t size,
2c90784a
RH		 94 const void *debug_frame,
95 size_t debug_frame_size)
813da627
RH		 96 __attribute__((unused));
97
c0ad3001
SW		 98/* Forward declarations for functions declared and used in tcg-target.c. */
99static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str);
2a534aff 100static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
a05b5b9b 101 intptr_t arg2);
2a534aff 102static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
c0ad3001 103static void tcg_out_movi(TCGContext *s, TCGType type,
2a534aff 104 TCGReg ret, tcg_target_long arg);
c0ad3001
SW		 105static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
106 const int *const_args);
2a534aff 107static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
a05b5b9b 108 intptr_t arg2);
cf066674 109static void tcg_out_call(TCGContext *s, tcg_insn_unit *target);
f6c6afc1 110static int tcg_target_const_match(tcg_target_long val, TCGType type,
c0ad3001 111 const TCGArgConstraint *arg_ct);
9ecefc84
RH		 112static void tcg_out_tb_init(TCGContext *s);
113static void tcg_out_tb_finalize(TCGContext *s);
114
c0ad3001 115
8399ad59 116TCGOpDef tcg_op_defs[] = {
0e2029a0 117#define DEF(s, oargs, iargs, cargs, flags) { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags },
c896fe29
FB		 118#include "tcg-opc.h"
119#undef DEF
c896fe29 120};
2a24374a 121const size_t tcg_op_defs_max = ARRAY_SIZE(tcg_op_defs);
c896fe29 122
b1d8e52e
BS		 123static TCGRegSet tcg_target_available_regs[2];
124static TCGRegSet tcg_target_call_clobber_regs;
c896fe29 125
1813e175 126#if TCG_TARGET_INSN_UNIT_SIZE == 1
4196dca6 127static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v)
c896fe29
FB		 128{
129 *s->code_ptr++ = v;
130}
131
4196dca6
PM		 132static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p,
133 uint8_t v)
5c53bb81 134{
1813e175 135 *p = v;
5c53bb81 136}
1813e175 137#endif
5c53bb81 138
1813e175 139#if TCG_TARGET_INSN_UNIT_SIZE <= 2
4196dca6 140static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v)
c896fe29 141{
1813e175
RH		 142 if (TCG_TARGET_INSN_UNIT_SIZE == 2) {
143 *s->code_ptr++ = v;
144 } else {
145 tcg_insn_unit *p = s->code_ptr;
146 memcpy(p, &v, sizeof(v));
147 s->code_ptr = p + (2 / TCG_TARGET_INSN_UNIT_SIZE);
148 }
c896fe29
FB		 149}
150
4196dca6
PM		 151static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p,
152 uint16_t v)
5c53bb81 153{
1813e175
RH		 154 if (TCG_TARGET_INSN_UNIT_SIZE == 2) {
155 *p = v;
156 } else {
157 memcpy(p, &v, sizeof(v));
158 }
5c53bb81 159}
1813e175 160#endif
5c53bb81 161
1813e175 162#if TCG_TARGET_INSN_UNIT_SIZE <= 4
4196dca6 163static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v)
c896fe29 164{
1813e175
RH		 165 if (TCG_TARGET_INSN_UNIT_SIZE == 4) {
166 *s->code_ptr++ = v;
167 } else {
168 tcg_insn_unit *p = s->code_ptr;
169 memcpy(p, &v, sizeof(v));
170 s->code_ptr = p + (4 / TCG_TARGET_INSN_UNIT_SIZE);
171 }
c896fe29
FB		 172}
173
4196dca6
PM		 174static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p,
175 uint32_t v)
5c53bb81 176{
1813e175
RH		 177 if (TCG_TARGET_INSN_UNIT_SIZE == 4) {
178 *p = v;
179 } else {
180 memcpy(p, &v, sizeof(v));
181 }
5c53bb81 182}
1813e175 183#endif
5c53bb81 184
1813e175 185#if TCG_TARGET_INSN_UNIT_SIZE <= 8
4196dca6 186static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v)
ac26eb69 187{
1813e175
RH		 188 if (TCG_TARGET_INSN_UNIT_SIZE == 8) {
189 *s->code_ptr++ = v;
190 } else {
191 tcg_insn_unit *p = s->code_ptr;
192 memcpy(p, &v, sizeof(v));
193 s->code_ptr = p + (8 / TCG_TARGET_INSN_UNIT_SIZE);
194 }
ac26eb69
RH		 195}
196
4196dca6
PM		 197static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p,
198 uint64_t v)
5c53bb81 199{
1813e175
RH		 200 if (TCG_TARGET_INSN_UNIT_SIZE == 8) {
201 *p = v;
202 } else {
203 memcpy(p, &v, sizeof(v));
204 }
5c53bb81 205}
1813e175 206#endif
5c53bb81 207
c896fe29
FB		 208/* label relocation processing */
209
1813e175 210static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type,
2ba7fae2 211 int label_index, intptr_t addend)
c896fe29
FB		 212{
213 TCGLabel *l;
214 TCGRelocation *r;
215
216 l = &s->labels[label_index];
217 if (l->has_value) {
623e265c
PB		 218 /* FIXME: This may break relocations on RISC targets that
219 modify instruction fields in place. The caller may not have
220 written the initial value. */
f54b3f92 221 patch_reloc(code_ptr, type, l->u.value, addend);
c896fe29
FB		 222 } else {
223 /* add a new relocation entry */
224 r = tcg_malloc(sizeof(TCGRelocation));
225 r->type = type;
226 r->ptr = code_ptr;
227 r->addend = addend;
228 r->next = l->u.first_reloc;
229 l->u.first_reloc = r;
230 }
231}
232
1813e175 233static void tcg_out_label(TCGContext *s, int label_index, tcg_insn_unit *ptr)
c896fe29 234{
1813e175 235 TCGLabel *l = &s->labels[label_index];
2ba7fae2 236 intptr_t value = (intptr_t)ptr;
1813e175 237 TCGRelocation *r;
c896fe29 238
1813e175
RH		 239 assert(!l->has_value);
240
241 for (r = l->u.first_reloc; r != NULL; r = r->next) {
f54b3f92 242 patch_reloc(r->ptr, r->type, value, r->addend);
c896fe29 243 }
1813e175 244
c896fe29 245 l->has_value = 1;
1813e175 246 l->u.value_ptr = ptr;
c896fe29
FB		 247}
248
249int gen_new_label(void)
250{
251 TCGContext *s = &tcg_ctx;
252 int idx;
253 TCGLabel *l;
254
255 if (s->nb_labels >= TCG_MAX_LABELS)
256 tcg_abort();
257 idx = s->nb_labels++;
258 l = &s->labels[idx];
259 l->has_value = 0;
260 l->u.first_reloc = NULL;
261 return idx;
262}
263
264#include "tcg-target.c"
265
c896fe29
FB		 266/* pool based memory allocation */
267void *tcg_malloc_internal(TCGContext *s, int size)
268{
269 TCGPool *p;
270 int pool_size;
271
272 if (size > TCG_POOL_CHUNK_SIZE) {
273 /* big malloc: insert a new pool (XXX: could optimize) */
7267c094 274 p = g_malloc(sizeof(TCGPool) + size);
c896fe29 275 p->size = size;
4055299e
KB		 276 p->next = s->pool_first_large;
277 s->pool_first_large = p;
278 return p->data;
c896fe29
FB		 279 } else {
280 p = s->pool_current;
281 if (!p) {
282 p = s->pool_first;
283 if (!p)
284 goto new_pool;
285 } else {
286 if (!p->next) {
287 new_pool:
288 pool_size = TCG_POOL_CHUNK_SIZE;
7267c094 289 p = g_malloc(sizeof(TCGPool) + pool_size);
c896fe29
FB		 290 p->size = pool_size;
291 p->next = NULL;
292 if (s->pool_current)
293 s->pool_current->next = p;
294 else
295 s->pool_first = p;
296 } else {
297 p = p->next;
298 }
299 }
300 }
301 s->pool_current = p;
302 s->pool_cur = p->data + size;
303 s->pool_end = p->data + p->size;
304 return p->data;
305}
306
307void tcg_pool_reset(TCGContext *s)
308{
4055299e
KB		 309 TCGPool *p, *t;
310 for (p = s->pool_first_large; p; p = t) {
311 t = p->next;
312 g_free(p);
313 }
314 s->pool_first_large = NULL;
c896fe29
FB		 315 s->pool_cur = s->pool_end = NULL;
316 s->pool_current = NULL;
317}
318
100b5e01
RH		 319typedef struct TCGHelperInfo {
320 void *func;
321 const char *name;
afb49896
RH		 322 unsigned flags;
323 unsigned sizemask;
100b5e01
RH		 324} TCGHelperInfo;
325
2ef6175a
RH		 326#include "exec/helper-proto.h"
327
100b5e01 328static const TCGHelperInfo all_helpers[] = {
2ef6175a 329#include "exec/helper-tcg.h"
100b5e01
RH		 330};
331
c896fe29
FB		 332void tcg_context_init(TCGContext *s)
333{
100b5e01 334 int op, total_args, n, i;
c896fe29
FB		 335 TCGOpDef *def;
336 TCGArgConstraint *args_ct;
337 int *sorted_args;
84fd9dd3 338 GHashTable *helper_table;
c896fe29
FB		 339
340 memset(s, 0, sizeof(*s));
c896fe29
FB		 341 s->nb_globals = 0;
342
343 /* Count total number of arguments and allocate the corresponding
344 space */
345 total_args = 0;
346 for(op = 0; op < NB_OPS; op++) {
347 def = &tcg_op_defs[op];
348 n = def->nb_iargs + def->nb_oargs;
349 total_args += n;
350 }
351
7267c094
AL		 352 args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
353 sorted_args = g_malloc(sizeof(int) * total_args);
c896fe29
FB		 354
355 for(op = 0; op < NB_OPS; op++) {
356 def = &tcg_op_defs[op];
357 def->args_ct = args_ct;
358 def->sorted_args = sorted_args;
359 n = def->nb_iargs + def->nb_oargs;
360 sorted_args += n;
361 args_ct += n;
362 }
5cd8f621
RH		 363
364 /* Register helpers. */
84fd9dd3
RH		 365 /* Use g_direct_hash/equal for direct pointer comparisons on func. */
366 s->helpers = helper_table = g_hash_table_new(NULL, NULL);
367
100b5e01 368 for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) {
84fd9dd3 369 g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func,
72866e82 370 (gpointer)&all_helpers[i]);
100b5e01 371 }
5cd8f621 372
c896fe29 373 tcg_target_init(s);
9002ec79 374}
b03cce8e 375
9002ec79
RH		 376void tcg_prologue_init(TCGContext *s)
377{
b03cce8e 378 /* init global prologue and epilogue */
0b0d3320 379 s->code_buf = s->code_gen_prologue;
b03cce8e
FB		 380 s->code_ptr = s->code_buf;
381 tcg_target_qemu_prologue(s);
b93949ef 382 flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
d6b64b2b
RH		 383
384#ifdef DEBUG_DISAS
385 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
1813e175 386 size_t size = tcg_current_code_size(s);
d6b64b2b
RH		 387 qemu_log("PROLOGUE: [size=%zu]\n", size);
388 log_disas(s->code_buf, size);
389 qemu_log("\n");
390 qemu_log_flush();
391 }
392#endif
c896fe29
FB		 393}
394
e2c6d1b4 395void tcg_set_frame(TCGContext *s, int reg, intptr_t start, intptr_t size)
c896fe29
FB		 396{
397 s->frame_start = start;
398 s->frame_end = start + size;
399 s->frame_reg = reg;
400}
401
c896fe29
FB		 402void tcg_func_start(TCGContext *s)
403{
404 tcg_pool_reset(s);
405 s->nb_temps = s->nb_globals;
0ec9eabc
RH		 406
407 /* No temps have been previously allocated for size or locality. */
408 memset(s->free_temps, 0, sizeof(s->free_temps));
409
c896fe29
FB		 410 s->labels = tcg_malloc(sizeof(TCGLabel) * TCG_MAX_LABELS);
411 s->nb_labels = 0;
412 s->current_frame_offset = s->frame_start;
413
0a209d4b
RH		 414#ifdef CONFIG_DEBUG_TCG
415 s->goto_tb_issue_mask = 0;
416#endif
417
92414b31 418 s->gen_opc_ptr = s->gen_opc_buf;
1ff0a2c5 419 s->gen_opparam_ptr = s->gen_opparam_buf;
b76f0d8c 420
9ecefc84 421 s->be = tcg_malloc(sizeof(TCGBackendData));
c896fe29
FB		 422}
423
424static inline void tcg_temp_alloc(TCGContext *s, int n)
425{
426 if (n > TCG_MAX_TEMPS)
427 tcg_abort();
428}
429
a7812ae4
PB		 430static inline int tcg_global_reg_new_internal(TCGType type, int reg,
431 const char *name)
c896fe29
FB		 432{
433 TCGContext *s = &tcg_ctx;
434 TCGTemp *ts;
435 int idx;
436
437#if TCG_TARGET_REG_BITS == 32
438 if (type != TCG_TYPE_I32)
439 tcg_abort();
440#endif
441 if (tcg_regset_test_reg(s->reserved_regs, reg))
442 tcg_abort();
443 idx = s->nb_globals;
444 tcg_temp_alloc(s, s->nb_globals + 1);
445 ts = &s->temps[s->nb_globals];
446 ts->base_type = type;
447 ts->type = type;
448 ts->fixed_reg = 1;
449 ts->reg = reg;
c896fe29
FB		 450 ts->name = name;
451 s->nb_globals++;
452 tcg_regset_set_reg(s->reserved_regs, reg);
a7812ae4
PB		 453 return idx;
454}
455
456TCGv_i32 tcg_global_reg_new_i32(int reg, const char *name)
457{
458 int idx;
459
460 idx = tcg_global_reg_new_internal(TCG_TYPE_I32, reg, name);
461 return MAKE_TCGV_I32(idx);
462}
463
464TCGv_i64 tcg_global_reg_new_i64(int reg, const char *name)
465{
466 int idx;
467
468 idx = tcg_global_reg_new_internal(TCG_TYPE_I64, reg, name);
469 return MAKE_TCGV_I64(idx);
c896fe29
FB		 470}
471
a7812ae4 472static inline int tcg_global_mem_new_internal(TCGType type, int reg,
2f2f244d 473 intptr_t offset,
a7812ae4 474 const char *name)
c896fe29
FB		 475{
476 TCGContext *s = &tcg_ctx;
477 TCGTemp *ts;
478 int idx;
479
480 idx = s->nb_globals;
481#if TCG_TARGET_REG_BITS == 32
482 if (type == TCG_TYPE_I64) {
483 char buf[64];
c588979b 484 tcg_temp_alloc(s, s->nb_globals + 2);
c896fe29
FB		 485 ts = &s->temps[s->nb_globals];
486 ts->base_type = type;
487 ts->type = TCG_TYPE_I32;
488 ts->fixed_reg = 0;
489 ts->mem_allocated = 1;
490 ts->mem_reg = reg;
02eb19d0 491#ifdef HOST_WORDS_BIGENDIAN
c896fe29
FB		 492 ts->mem_offset = offset + 4;
493#else
494 ts->mem_offset = offset;
495#endif
c896fe29
FB		 496 pstrcpy(buf, sizeof(buf), name);
497 pstrcat(buf, sizeof(buf), "_0");
498 ts->name = strdup(buf);
499 ts++;
500
501 ts->base_type = type;
502 ts->type = TCG_TYPE_I32;
503 ts->fixed_reg = 0;
504 ts->mem_allocated = 1;
505 ts->mem_reg = reg;
02eb19d0 506#ifdef HOST_WORDS_BIGENDIAN
c896fe29
FB		 507 ts->mem_offset = offset;
508#else
509 ts->mem_offset = offset + 4;
510#endif
c896fe29
FB		 511 pstrcpy(buf, sizeof(buf), name);
512 pstrcat(buf, sizeof(buf), "_1");
513 ts->name = strdup(buf);
514
515 s->nb_globals += 2;
516 } else
517#endif
518 {
519 tcg_temp_alloc(s, s->nb_globals + 1);
520 ts = &s->temps[s->nb_globals];
521 ts->base_type = type;
522 ts->type = type;
523 ts->fixed_reg = 0;
524 ts->mem_allocated = 1;
525 ts->mem_reg = reg;
526 ts->mem_offset = offset;
c896fe29
FB		 527 ts->name = name;
528 s->nb_globals++;
529 }
a7812ae4
PB		 530 return idx;
531}
532
2f2f244d 533TCGv_i32 tcg_global_mem_new_i32(int reg, intptr_t offset, const char *name)
a7812ae4 534{
2f2f244d 535 int idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
a7812ae4
PB		 536 return MAKE_TCGV_I32(idx);
537}
538
2f2f244d 539TCGv_i64 tcg_global_mem_new_i64(int reg, intptr_t offset, const char *name)
a7812ae4 540{
2f2f244d 541 int idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
a7812ae4 542 return MAKE_TCGV_I64(idx);
c896fe29
FB		 543}
544
a7812ae4 545static inline int tcg_temp_new_internal(TCGType type, int temp_local)
c896fe29
FB		 546{
547 TCGContext *s = &tcg_ctx;
548 TCGTemp *ts;
641d5fbe 549 int idx, k;
c896fe29 550
0ec9eabc
RH		 551 k = type + (temp_local ? TCG_TYPE_COUNT : 0);
552 idx = find_first_bit(s->free_temps[k].l, TCG_MAX_TEMPS);
553 if (idx < TCG_MAX_TEMPS) {
554 /* There is already an available temp with the right type. */
555 clear_bit(idx, s->free_temps[k].l);
556
e8996ee0 557 ts = &s->temps[idx];
e8996ee0 558 ts->temp_allocated = 1;
0ec9eabc 559 assert(ts->base_type == type);
641d5fbe 560 assert(ts->temp_local == temp_local);
e8996ee0
FB		 561 } else {
562 idx = s->nb_temps;
c896fe29 563#if TCG_TARGET_REG_BITS == 32
e8996ee0 564 if (type == TCG_TYPE_I64) {
8df1ca4b 565 tcg_temp_alloc(s, s->nb_temps + 2);
e8996ee0
FB		 566 ts = &s->temps[s->nb_temps];
567 ts->base_type = type;
568 ts->type = TCG_TYPE_I32;
569 ts->temp_allocated = 1;
641d5fbe 570 ts->temp_local = temp_local;
e8996ee0
FB		 571 ts->name = NULL;
572 ts++;
f6aa2f7d 573 ts->base_type = type;
e8996ee0
FB		 574 ts->type = TCG_TYPE_I32;
575 ts->temp_allocated = 1;
641d5fbe 576 ts->temp_local = temp_local;
e8996ee0
FB		 577 ts->name = NULL;
578 s->nb_temps += 2;
579 } else
c896fe29 580#endif
e8996ee0
FB		 581 {
582 tcg_temp_alloc(s, s->nb_temps + 1);
583 ts = &s->temps[s->nb_temps];
584 ts->base_type = type;
585 ts->type = type;
586 ts->temp_allocated = 1;
641d5fbe 587 ts->temp_local = temp_local;
e8996ee0
FB		 588 ts->name = NULL;
589 s->nb_temps++;
590 }
c896fe29 591 }
27bfd83c
PM		 592
593#if defined(CONFIG_DEBUG_TCG)
594 s->temps_in_use++;
595#endif
a7812ae4 596 return idx;
c896fe29
FB		 597}
598
a7812ae4
PB		 599TCGv_i32 tcg_temp_new_internal_i32(int temp_local)
600{
601 int idx;
602
603 idx = tcg_temp_new_internal(TCG_TYPE_I32, temp_local);
604 return MAKE_TCGV_I32(idx);
605}
606
607TCGv_i64 tcg_temp_new_internal_i64(int temp_local)
608{
609 int idx;
610
611 idx = tcg_temp_new_internal(TCG_TYPE_I64, temp_local);
612 return MAKE_TCGV_I64(idx);
613}
614
0ec9eabc 615static void tcg_temp_free_internal(int idx)
c896fe29
FB		 616{
617 TCGContext *s = &tcg_ctx;
618 TCGTemp *ts;
641d5fbe 619 int k;
c896fe29 620
27bfd83c
PM		 621#if defined(CONFIG_DEBUG_TCG)
622 s->temps_in_use--;
623 if (s->temps_in_use < 0) {
624 fprintf(stderr, "More temporaries freed than allocated!\n");
625 }
626#endif
627
e8996ee0 628 assert(idx >= s->nb_globals && idx < s->nb_temps);
c896fe29 629 ts = &s->temps[idx];
e8996ee0
FB		 630 assert(ts->temp_allocated != 0);
631 ts->temp_allocated = 0;
0ec9eabc 632
18d13fa2 633 k = ts->base_type + (ts->temp_local ? TCG_TYPE_COUNT : 0);
0ec9eabc 634 set_bit(idx, s->free_temps[k].l);
c896fe29
FB		 635}
636
a7812ae4
PB		 637void tcg_temp_free_i32(TCGv_i32 arg)
638{
639 tcg_temp_free_internal(GET_TCGV_I32(arg));
640}
641
642void tcg_temp_free_i64(TCGv_i64 arg)
643{
644 tcg_temp_free_internal(GET_TCGV_I64(arg));
645}
e8996ee0 646
a7812ae4 647TCGv_i32 tcg_const_i32(int32_t val)
c896fe29 648{
a7812ae4
PB		 649 TCGv_i32 t0;
650 t0 = tcg_temp_new_i32();
e8996ee0
FB		 651 tcg_gen_movi_i32(t0, val);
652 return t0;
653}
c896fe29 654
a7812ae4 655TCGv_i64 tcg_const_i64(int64_t val)
e8996ee0 656{
a7812ae4
PB		 657 TCGv_i64 t0;
658 t0 = tcg_temp_new_i64();
e8996ee0
FB		 659 tcg_gen_movi_i64(t0, val);
660 return t0;
c896fe29
FB		 661}
662
a7812ae4 663TCGv_i32 tcg_const_local_i32(int32_t val)
bdffd4a9 664{
a7812ae4
PB		 665 TCGv_i32 t0;
666 t0 = tcg_temp_local_new_i32();
bdffd4a9
AJ		 667 tcg_gen_movi_i32(t0, val);
668 return t0;
669}
670
a7812ae4 671TCGv_i64 tcg_const_local_i64(int64_t val)
bdffd4a9 672{
a7812ae4
PB		 673 TCGv_i64 t0;
674 t0 = tcg_temp_local_new_i64();
bdffd4a9
AJ		 675 tcg_gen_movi_i64(t0, val);
676 return t0;
677}
678
27bfd83c
PM		 679#if defined(CONFIG_DEBUG_TCG)
680void tcg_clear_temp_count(void)
681{
682 TCGContext *s = &tcg_ctx;
683 s->temps_in_use = 0;
684}
685
686int tcg_check_temp_count(void)
687{
688 TCGContext *s = &tcg_ctx;
689 if (s->temps_in_use) {
690 /* Clear the count so that we don't give another
691 * warning immediately next time around.
692 */
693 s->temps_in_use = 0;
694 return 1;
695 }
696 return 0;
697}
698#endif
699
39cf05d3
FB		 700/* Note: we convert the 64 bit args to 32 bit and do some alignment
701 and endian swap. Maybe it would be better to do the alignment
702 and endian swap in tcg_reg_alloc_call(). */
bbb8a1b4
RH		 703void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
704 int nargs, TCGArg *args)
c896fe29 705{
bbb8a1b4
RH		 706 int i, real_args, nb_rets;
707 unsigned sizemask, flags;
a7812ae4 708 TCGArg *nparam;
afb49896
RH		 709 TCGHelperInfo *info;
710
711 info = g_hash_table_lookup(s->helpers, (gpointer)func);
bbb8a1b4
RH		 712 flags = info->flags;
713 sizemask = info->sizemask;
2bece2c8 714
34b1a49c
RH		 715#if defined(__sparc__) && !defined(__arch64__) \
716 && !defined(CONFIG_TCG_INTERPRETER)
717 /* We have 64-bit values in one register, but need to pass as two
718 separate parameters. Split them. */
719 int orig_sizemask = sizemask;
720 int orig_nargs = nargs;
721 TCGv_i64 retl, reth;
722
723 TCGV_UNUSED_I64(retl);
724 TCGV_UNUSED_I64(reth);
725 if (sizemask != 0) {
726 TCGArg *split_args = __builtin_alloca(sizeof(TCGArg) * nargs * 2);
727 for (i = real_args = 0; i < nargs; ++i) {
728 int is_64bit = sizemask & (1 << (i+1)*2);
729 if (is_64bit) {
730 TCGv_i64 orig = MAKE_TCGV_I64(args[i]);
731 TCGv_i32 h = tcg_temp_new_i32();
732 TCGv_i32 l = tcg_temp_new_i32();
733 tcg_gen_extr_i64_i32(l, h, orig);
734 split_args[real_args++] = GET_TCGV_I32(h);
735 split_args[real_args++] = GET_TCGV_I32(l);
736 } else {
737 split_args[real_args++] = args[i];
738 }
739 }
740 nargs = real_args;
741 args = split_args;
742 sizemask = 0;
743 }
744#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
2bece2c8
RH		 745 for (i = 0; i < nargs; ++i) {
746 int is_64bit = sizemask & (1 << (i+1)*2);
747 int is_signed = sizemask & (2 << (i+1)*2);
748 if (!is_64bit) {
749 TCGv_i64 temp = tcg_temp_new_i64();
750 TCGv_i64 orig = MAKE_TCGV_I64(args[i]);
751 if (is_signed) {
752 tcg_gen_ext32s_i64(temp, orig);
753 } else {
754 tcg_gen_ext32u_i64(temp, orig);
755 }
756 args[i] = GET_TCGV_I64(temp);
757 }
758 }
759#endif /* TCG_TARGET_EXTEND_ARGS */
760
efd7f486 761 *s->gen_opc_ptr++ = INDEX_op_call;
c4afe5c4 762 nparam = s->gen_opparam_ptr++;
a7812ae4 763 if (ret != TCG_CALL_DUMMY_ARG) {
34b1a49c
RH		 764#if defined(__sparc__) && !defined(__arch64__) \
765 && !defined(CONFIG_TCG_INTERPRETER)
766 if (orig_sizemask & 1) {
767 /* The 32-bit ABI is going to return the 64-bit value in
768 the %o0/%o1 register pair. Prepare for this by using
769 two return temporaries, and reassemble below. */
770 retl = tcg_temp_new_i64();
771 reth = tcg_temp_new_i64();
772 *s->gen_opparam_ptr++ = GET_TCGV_I64(reth);
773 *s->gen_opparam_ptr++ = GET_TCGV_I64(retl);
774 nb_rets = 2;
775 } else {
776 *s->gen_opparam_ptr++ = ret;
777 nb_rets = 1;
778 }
779#else
780 if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) {
02eb19d0 781#ifdef HOST_WORDS_BIGENDIAN
c4afe5c4
EV		 782 *s->gen_opparam_ptr++ = ret + 1;
783 *s->gen_opparam_ptr++ = ret;
39cf05d3 784#else
c4afe5c4
EV		 785 *s->gen_opparam_ptr++ = ret;
786 *s->gen_opparam_ptr++ = ret + 1;
39cf05d3 787#endif
a7812ae4 788 nb_rets = 2;
34b1a49c 789 } else {
c4afe5c4 790 *s->gen_opparam_ptr++ = ret;
a7812ae4 791 nb_rets = 1;
c896fe29 792 }
34b1a49c 793#endif
a7812ae4
PB		 794 } else {
795 nb_rets = 0;
c896fe29 796 }
a7812ae4
PB		 797 real_args = 0;
798 for (i = 0; i < nargs; i++) {
2bece2c8 799 int is_64bit = sizemask & (1 << (i+1)*2);
bbb8a1b4 800 if (TCG_TARGET_REG_BITS < 64 && is_64bit) {
39cf05d3
FB		 801#ifdef TCG_TARGET_CALL_ALIGN_ARGS
802 /* some targets want aligned 64 bit args */
ebd486d5 803 if (real_args & 1) {
c4afe5c4 804 *s->gen_opparam_ptr++ = TCG_CALL_DUMMY_ARG;
ebd486d5 805 real_args++;
39cf05d3
FB		 806 }
807#endif
3f90f252
RH		 808 /* If stack grows up, then we will be placing successive
809 arguments at lower addresses, which means we need to
810 reverse the order compared to how we would normally
811 treat either big or little-endian. For those arguments
812 that will wind up in registers, this still works for
813 HPPA (the only current STACK_GROWSUP target) since the
814 argument registers are *also* allocated in decreasing
815 order. If another such target is added, this logic may
816 have to get more complicated to differentiate between
817 stack arguments and register arguments. */
02eb19d0 818#if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
c4afe5c4
EV		 819 *s->gen_opparam_ptr++ = args[i] + 1;
820 *s->gen_opparam_ptr++ = args[i];
c896fe29 821#else
c4afe5c4
EV		 822 *s->gen_opparam_ptr++ = args[i];
823 *s->gen_opparam_ptr++ = args[i] + 1;
c896fe29 824#endif
a7812ae4 825 real_args += 2;
2bece2c8 826 continue;
c896fe29 827 }
2bece2c8 828
c4afe5c4 829 *s->gen_opparam_ptr++ = args[i];
2bece2c8 830 real_args++;
c896fe29 831 }
cf066674 832 *s->gen_opparam_ptr++ = (uintptr_t)func;
c4afe5c4 833 *s->gen_opparam_ptr++ = flags;
a7812ae4 834
cf066674 835 *nparam = (nb_rets << 16) | real_args;
a7812ae4
PB		 836
837 /* total parameters, needed to go backward in the instruction stream */
c4afe5c4 838 *s->gen_opparam_ptr++ = 1 + nb_rets + real_args + 3;
2bece2c8 839
34b1a49c
RH		 840#if defined(__sparc__) && !defined(__arch64__) \
841 && !defined(CONFIG_TCG_INTERPRETER)
842 /* Free all of the parts we allocated above. */
843 for (i = real_args = 0; i < orig_nargs; ++i) {
844 int is_64bit = orig_sizemask & (1 << (i+1)*2);
845 if (is_64bit) {
846 TCGv_i32 h = MAKE_TCGV_I32(args[real_args++]);
847 TCGv_i32 l = MAKE_TCGV_I32(args[real_args++]);
848 tcg_temp_free_i32(h);
849 tcg_temp_free_i32(l);
850 } else {
851 real_args++;
852 }
853 }
854 if (orig_sizemask & 1) {
855 /* The 32-bit ABI returned two 32-bit pieces. Re-assemble them.
856 Note that describing these as TCGv_i64 eliminates an unnecessary
857 zero-extension that tcg_gen_concat_i32_i64 would create. */
858 tcg_gen_concat32_i64(MAKE_TCGV_I64(ret), retl, reth);
859 tcg_temp_free_i64(retl);
860 tcg_temp_free_i64(reth);
861 }
862#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
2bece2c8
RH		 863 for (i = 0; i < nargs; ++i) {
864 int is_64bit = sizemask & (1 << (i+1)*2);
865 if (!is_64bit) {
866 TCGv_i64 temp = MAKE_TCGV_I64(args[i]);
867 tcg_temp_free_i64(temp);
868 }
869 }
870#endif /* TCG_TARGET_EXTEND_ARGS */
c896fe29 871}
c896fe29 872
ac56dd48 873#if TCG_TARGET_REG_BITS == 32
a7812ae4 874void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
c896fe29
FB		 875 int c, int right, int arith)
876{
cf60bce4 877 if (c == 0) {
a7812ae4 878 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
cf60bce4
FB		 879 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
880 } else if (c >= 32) {
c896fe29
FB		 881 c -= 32;
882 if (right) {
883 if (arith) {
a7812ae4 884 tcg_gen_sari_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), c);
ac56dd48 885 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), 31);
c896fe29 886 } else {
a7812ae4 887 tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), c);
ac56dd48 888 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
c896fe29
FB		 889 }
890 } else {
a7812ae4
PB		 891 tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c);
892 tcg_gen_movi_i32(TCGV_LOW(ret), 0);
c896fe29
FB		 893 }
894 } else {
a7812ae4 895 TCGv_i32 t0, t1;
c896fe29 896
a7812ae4
PB		 897 t0 = tcg_temp_new_i32();
898 t1 = tcg_temp_new_i32();
c896fe29 899 if (right) {
ac56dd48 900 tcg_gen_shli_i32(t0, TCGV_HIGH(arg1), 32 - c);
c896fe29 901 if (arith)
ac56dd48 902 tcg_gen_sari_i32(t1, TCGV_HIGH(arg1), c);
a7812ae4 903 else
ac56dd48 904 tcg_gen_shri_i32(t1, TCGV_HIGH(arg1), c);
a7812ae4
PB		 905 tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
906 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t0);
ac56dd48 907 tcg_gen_mov_i32(TCGV_HIGH(ret), t1);
c896fe29 908 } else {
a7812ae4 909 tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
c896fe29 910 /* Note: ret can be the same as arg1, so we use t1 */
a7812ae4 911 tcg_gen_shli_i32(t1, TCGV_LOW(arg1), c);
ac56dd48
PB		 912 tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
913 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t0);
a7812ae4 914 tcg_gen_mov_i32(TCGV_LOW(ret), t1);
c896fe29 915 }
a7812ae4
PB		 916 tcg_temp_free_i32(t0);
917 tcg_temp_free_i32(t1);
c896fe29
FB		 918 }
919}
ac56dd48 920#endif
c896fe29 921
f713d6ad
RH		 922static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)
923{
924 switch (op & MO_SIZE) {
925 case MO_8:
926 op &= ~MO_BSWAP;
927 break;
928 case MO_16:
929 break;
930 case MO_32:
931 if (!is64) {
932 op &= ~MO_SIGN;
933 }
934 break;
935 case MO_64:
936 if (!is64) {
937 tcg_abort();
938 }
939 break;
940 }
941 if (st) {
942 op &= ~MO_SIGN;
943 }
944 return op;
945}
946
f713d6ad
RH		 947void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
948{
949 memop = tcg_canonicalize_memop(memop, 0, 0);
950
3d1b2ff6
RH		 951 *tcg_ctx.gen_opc_ptr++ = INDEX_op_qemu_ld_i32;
952 tcg_add_param_i32(val);
953 tcg_add_param_tl(addr);
954 *tcg_ctx.gen_opparam_ptr++ = memop;
955 *tcg_ctx.gen_opparam_ptr++ = idx;
f713d6ad
RH		 956}
957
958void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
959{
960 memop = tcg_canonicalize_memop(memop, 0, 1);
961
3d1b2ff6
RH		 962 *tcg_ctx.gen_opc_ptr++ = INDEX_op_qemu_st_i32;
963 tcg_add_param_i32(val);
964 tcg_add_param_tl(addr);
965 *tcg_ctx.gen_opparam_ptr++ = memop;
966 *tcg_ctx.gen_opparam_ptr++ = idx;
f713d6ad
RH		 967}
968
969void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
970{
971 memop = tcg_canonicalize_memop(memop, 1, 0);
972
973#if TCG_TARGET_REG_BITS == 32
974 if ((memop & MO_SIZE) < MO_64) {
975 tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);
976 if (memop & MO_SIGN) {
977 tcg_gen_sari_i32(TCGV_HIGH(val), TCGV_LOW(val), 31);
978 } else {
979 tcg_gen_movi_i32(TCGV_HIGH(val), 0);
980 }
981 return;
982 }
983#endif
984
3d1b2ff6 985 *tcg_ctx.gen_opc_ptr++ = INDEX_op_qemu_ld_i64;
f713d6ad
RH		 986 tcg_add_param_i64(val);
987 tcg_add_param_tl(addr);
3d1b2ff6 988 *tcg_ctx.gen_opparam_ptr++ = memop;
f713d6ad
RH		 989 *tcg_ctx.gen_opparam_ptr++ = idx;
990}
991
992void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
993{
994 memop = tcg_canonicalize_memop(memop, 1, 1);
995
996#if TCG_TARGET_REG_BITS == 32
997 if ((memop & MO_SIZE) < MO_64) {
998 tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);
999 return;
1000 }
1001#endif
1002
3d1b2ff6 1003 *tcg_ctx.gen_opc_ptr++ = INDEX_op_qemu_st_i64;
f713d6ad
RH		 1004 tcg_add_param_i64(val);
1005 tcg_add_param_tl(addr);
3d1b2ff6 1006 *tcg_ctx.gen_opparam_ptr++ = memop;
f713d6ad
RH		 1007 *tcg_ctx.gen_opparam_ptr++ = idx;
1008}
be210acb 1009
8fcd3692 1010static void tcg_reg_alloc_start(TCGContext *s)
c896fe29
FB		 1011{
1012 int i;
1013 TCGTemp *ts;
1014 for(i = 0; i < s->nb_globals; i++) {
1015 ts = &s->temps[i];
1016 if (ts->fixed_reg) {
1017 ts->val_type = TEMP_VAL_REG;
1018 } else {
1019 ts->val_type = TEMP_VAL_MEM;
1020 }
1021 }
e8996ee0
FB		 1022 for(i = s->nb_globals; i < s->nb_temps; i++) {
1023 ts = &s->temps[i];
7dfd8c6a
AJ		 1024 if (ts->temp_local) {
1025 ts->val_type = TEMP_VAL_MEM;
1026 } else {
1027 ts->val_type = TEMP_VAL_DEAD;
1028 }
e8996ee0
FB		 1029 ts->mem_allocated = 0;
1030 ts->fixed_reg = 0;
1031 }
c896fe29
FB		 1032 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
1033 s->reg_to_temp[i] = -1;
1034 }
1035}
1036
ac56dd48
PB		 1037static char *tcg_get_arg_str_idx(TCGContext *s, char *buf, int buf_size,
1038 int idx)
c896fe29
FB		 1039{
1040 TCGTemp *ts;
ac56dd48 1041
7f6f0ae5 1042 assert(idx >= 0 && idx < s->nb_temps);
ac56dd48
PB		 1043 ts = &s->temps[idx];
1044 if (idx < s->nb_globals) {
1045 pstrcpy(buf, buf_size, ts->name);
c896fe29 1046 } else {
641d5fbe
FB		 1047 if (ts->temp_local)
1048 snprintf(buf, buf_size, "loc%d", idx - s->nb_globals);
1049 else
1050 snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals);
c896fe29
FB		 1051 }
1052 return buf;
1053}
1054
a7812ae4
PB		 1055char *tcg_get_arg_str_i32(TCGContext *s, char *buf, int buf_size, TCGv_i32 arg)
1056{
1057 return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I32(arg));
1058}
1059
1060char *tcg_get_arg_str_i64(TCGContext *s, char *buf, int buf_size, TCGv_i64 arg)
ac56dd48 1061{
a810a2de 1062 return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I64(arg));
ac56dd48
PB		 1063}
1064
6e085f72
RH		 1065/* Find helper name. */
1066static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val)
4dc81f28 1067{
6e085f72
RH		 1068 const char *ret = NULL;
1069 if (s->helpers) {
72866e82
RH		 1070 TCGHelperInfo *info = g_hash_table_lookup(s->helpers, (gpointer)val);
1071 if (info) {
1072 ret = info->name;
1073 }
4dc81f28 1074 }
6e085f72 1075 return ret;
4dc81f28
FB		 1076}
1077
f48f3ede
BS		 1078static const char * const cond_name[] =
1079{
0aed257f
RH		 1080 [TCG_COND_NEVER] = "never",
1081 [TCG_COND_ALWAYS] = "always",
f48f3ede
BS		 1082 [TCG_COND_EQ] = "eq",
1083 [TCG_COND_NE] = "ne",
1084 [TCG_COND_LT] = "lt",
1085 [TCG_COND_GE] = "ge",
1086 [TCG_COND_LE] = "le",
1087 [TCG_COND_GT] = "gt",
1088 [TCG_COND_LTU] = "ltu",
1089 [TCG_COND_GEU] = "geu",
1090 [TCG_COND_LEU] = "leu",
1091 [TCG_COND_GTU] = "gtu"
1092};
1093
f713d6ad
RH		 1094static const char * const ldst_name[] =
1095{
1096 [MO_UB] = "ub",
1097 [MO_SB] = "sb",
1098 [MO_LEUW] = "leuw",
1099 [MO_LESW] = "lesw",
1100 [MO_LEUL] = "leul",
1101 [MO_LESL] = "lesl",
1102 [MO_LEQ] = "leq",
1103 [MO_BEUW] = "beuw",
1104 [MO_BESW] = "besw",
1105 [MO_BEUL] = "beul",
1106 [MO_BESL] = "besl",
1107 [MO_BEQ] = "beq",
1108};
1109
eeacee4d 1110void tcg_dump_ops(TCGContext *s)
c896fe29
FB		 1111{
1112 const uint16_t *opc_ptr;
1113 const TCGArg *args;
1114 TCGArg arg;
a9751609
RH		 1115 TCGOpcode c;
1116 int i, k, nb_oargs, nb_iargs, nb_cargs, first_insn;
c896fe29
FB		 1117 const TCGOpDef *def;
1118 char buf[128];
1119
7e4597d7 1120 first_insn = 1;
92414b31 1121 opc_ptr = s->gen_opc_buf;
1ff0a2c5 1122 args = s->gen_opparam_buf;
efd7f486 1123 while (opc_ptr < s->gen_opc_ptr) {
c896fe29
FB		 1124 c = *opc_ptr++;
1125 def = &tcg_op_defs[c];
7e4597d7
FB		 1126 if (c == INDEX_op_debug_insn_start) {
1127 uint64_t pc;
1128#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1129 pc = ((uint64_t)args[1] << 32) | args[0];
1130#else
1131 pc = args[0];
1132#endif
eeacee4d
BS		 1133 if (!first_insn) {
1134 qemu_log("\n");
1135 }
1136 qemu_log(" ---- 0x%" PRIx64, pc);
7e4597d7
FB		 1137 first_insn = 0;
1138 nb_oargs = def->nb_oargs;
1139 nb_iargs = def->nb_iargs;
1140 nb_cargs = def->nb_cargs;
1141 } else if (c == INDEX_op_call) {
c896fe29 1142 TCGArg arg;
4dc81f28 1143
c896fe29
FB		 1144 /* variable number of arguments */
1145 arg = *args++;
1146 nb_oargs = arg >> 16;
1147 nb_iargs = arg & 0xffff;
1148 nb_cargs = def->nb_cargs;
c896fe29 1149
cf066674
RH		 1150 /* function name, flags, out args */
1151 qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name,
1152 tcg_find_helper(s, args[nb_oargs + nb_iargs]),
1153 args[nb_oargs + nb_iargs + 1], nb_oargs);
1154 for (i = 0; i < nb_oargs; i++) {
1155 qemu_log(",%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
eeacee4d 1156 args[i]));
b03cce8e 1157 }
cf066674
RH		 1158 for (i = 0; i < nb_iargs; i++) {
1159 TCGArg arg = args[nb_oargs + i];
1160 const char *t = "<dummy>";
1161 if (arg != TCG_CALL_DUMMY_ARG) {
1162 t = tcg_get_arg_str_idx(s, buf, sizeof(buf), arg);
eeacee4d 1163 }
cf066674 1164 qemu_log(",%s", t);
e8996ee0 1165 }
b03cce8e 1166 } else {
eeacee4d 1167 qemu_log(" %s ", def->name);
b03cce8e
FB		 1168 if (c == INDEX_op_nopn) {
1169 /* variable number of arguments */
1170 nb_cargs = *args;
1171 nb_oargs = 0;
1172 nb_iargs = 0;
1173 } else {
1174 nb_oargs = def->nb_oargs;
1175 nb_iargs = def->nb_iargs;
1176 nb_cargs = def->nb_cargs;
1177 }
1178
1179 k = 0;
1180 for(i = 0; i < nb_oargs; i++) {
eeacee4d
BS		 1181 if (k != 0) {
1182 qemu_log(",");
1183 }
1184 qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
1185 args[k++]));
b03cce8e
FB		 1186 }
1187 for(i = 0; i < nb_iargs; i++) {
eeacee4d
BS		 1188 if (k != 0) {
1189 qemu_log(",");
1190 }
1191 qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
1192 args[k++]));
b03cce8e 1193 }
be210acb
RH		 1194 switch (c) {
1195 case INDEX_op_brcond_i32:
be210acb 1196 case INDEX_op_setcond_i32:
ffc5ea09 1197 case INDEX_op_movcond_i32:
ffc5ea09 1198 case INDEX_op_brcond2_i32:
be210acb 1199 case INDEX_op_setcond2_i32:
ffc5ea09 1200 case INDEX_op_brcond_i64:
be210acb 1201 case INDEX_op_setcond_i64:
ffc5ea09 1202 case INDEX_op_movcond_i64:
eeacee4d
BS		 1203 if (args[k] < ARRAY_SIZE(cond_name) && cond_name[args[k]]) {
1204 qemu_log(",%s", cond_name[args[k++]]);
1205 } else {
1206 qemu_log(",$0x%" TCG_PRIlx, args[k++]);
1207 }
f48f3ede 1208 i = 1;
be210acb 1209 break;
f713d6ad
RH		 1210 case INDEX_op_qemu_ld_i32:
1211 case INDEX_op_qemu_st_i32:
1212 case INDEX_op_qemu_ld_i64:
1213 case INDEX_op_qemu_st_i64:
1214 if (args[k] < ARRAY_SIZE(ldst_name) && ldst_name[args[k]]) {
1215 qemu_log(",%s", ldst_name[args[k++]]);
1216 } else {
1217 qemu_log(",$0x%" TCG_PRIlx, args[k++]);
1218 }
1219 i = 1;
1220 break;
be210acb 1221 default:
f48f3ede 1222 i = 0;
be210acb
RH		 1223 break;
1224 }
f48f3ede 1225 for(; i < nb_cargs; i++) {
eeacee4d
BS		 1226 if (k != 0) {
1227 qemu_log(",");
1228 }
b03cce8e 1229 arg = args[k++];
eeacee4d 1230 qemu_log("$0x%" TCG_PRIlx, arg);
b03cce8e 1231 }
c896fe29 1232 }
eeacee4d 1233 qemu_log("\n");
c896fe29
FB		 1234 args += nb_iargs + nb_oargs + nb_cargs;
1235 }
1236}
1237
1238/* we give more priority to constraints with less registers */
1239static int get_constraint_priority(const TCGOpDef *def, int k)
1240{
1241 const TCGArgConstraint *arg_ct;
1242
1243 int i, n;
1244 arg_ct = &def->args_ct[k];
1245 if (arg_ct->ct & TCG_CT_ALIAS) {
1246 /* an alias is equivalent to a single register */
1247 n = 1;
1248 } else {
1249 if (!(arg_ct->ct & TCG_CT_REG))
1250 return 0;
1251 n = 0;
1252 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
1253 if (tcg_regset_test_reg(arg_ct->u.regs, i))
1254 n++;
1255 }
1256 }
1257 return TCG_TARGET_NB_REGS - n + 1;
1258}
1259
1260/* sort from highest priority to lowest */
1261static void sort_constraints(TCGOpDef *def, int start, int n)
1262{
1263 int i, j, p1, p2, tmp;
1264
1265 for(i = 0; i < n; i++)
1266 def->sorted_args[start + i] = start + i;
1267 if (n <= 1)
1268 return;
1269 for(i = 0; i < n - 1; i++) {
1270 for(j = i + 1; j < n; j++) {
1271 p1 = get_constraint_priority(def, def->sorted_args[start + i]);
1272 p2 = get_constraint_priority(def, def->sorted_args[start + j]);
1273 if (p1 < p2) {
1274 tmp = def->sorted_args[start + i];
1275 def->sorted_args[start + i] = def->sorted_args[start + j];
1276 def->sorted_args[start + j] = tmp;
1277 }
1278 }
1279 }
1280}
1281
1282void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs)
1283{
a9751609 1284 TCGOpcode op;
c896fe29
FB		 1285 TCGOpDef *def;
1286 const char *ct_str;
1287 int i, nb_args;
1288
1289 for(;;) {
a9751609 1290 if (tdefs->op == (TCGOpcode)-1)
c896fe29
FB		 1291 break;
1292 op = tdefs->op;
c3b08d0e 1293 assert((unsigned)op < NB_OPS);
c896fe29 1294 def = &tcg_op_defs[op];
c68aaa18
SW		 1295#if defined(CONFIG_DEBUG_TCG)
1296 /* Duplicate entry in op definitions? */
1297 assert(!def->used);
1298 def->used = 1;
1299#endif
c896fe29
FB		 1300 nb_args = def->nb_iargs + def->nb_oargs;
1301 for(i = 0; i < nb_args; i++) {
1302 ct_str = tdefs->args_ct_str[i];
c68aaa18
SW		 1303 /* Incomplete TCGTargetOpDef entry? */
1304 assert(ct_str != NULL);
c896fe29
FB		 1305 tcg_regset_clear(def->args_ct[i].u.regs);
1306 def->args_ct[i].ct = 0;
1307 if (ct_str[0] >= '0' && ct_str[0] <= '9') {
1308 int oarg;
1309 oarg = ct_str[0] - '0';
1310 assert(oarg < def->nb_oargs);
1311 assert(def->args_ct[oarg].ct & TCG_CT_REG);
1312 /* TCG_CT_ALIAS is for the output arguments. The input
5ff9d6a4 1313 argument is tagged with TCG_CT_IALIAS. */
c896fe29 1314 def->args_ct[i] = def->args_ct[oarg];
5ff9d6a4
FB		 1315 def->args_ct[oarg].ct = TCG_CT_ALIAS;
1316 def->args_ct[oarg].alias_index = i;
c896fe29 1317 def->args_ct[i].ct |= TCG_CT_IALIAS;
5ff9d6a4 1318 def->args_ct[i].alias_index = oarg;
c896fe29
FB		 1319 } else {
1320 for(;;) {
1321 if (*ct_str == '\0')
1322 break;
1323 switch(*ct_str) {
1324 case 'i':
1325 def->args_ct[i].ct |= TCG_CT_CONST;
1326 ct_str++;
1327 break;
1328 default:
1329 if (target_parse_constraint(&def->args_ct[i], &ct_str) < 0) {
1330 fprintf(stderr, "Invalid constraint '%s' for arg %d of operation '%s'\n",
1331 ct_str, i, def->name);
1332 exit(1);
1333 }
1334 }
1335 }
1336 }
1337 }
1338
c68aaa18
SW		 1339 /* TCGTargetOpDef entry with too much information? */
1340 assert(i == TCG_MAX_OP_ARGS || tdefs->args_ct_str[i] == NULL);
1341
c896fe29
FB		 1342 /* sort the constraints (XXX: this is just an heuristic) */
1343 sort_constraints(def, 0, def->nb_oargs);
1344 sort_constraints(def, def->nb_oargs, def->nb_iargs);
1345
1346#if 0
1347 {
1348 int i;
1349
1350 printf("%s: sorted=", def->name);
1351 for(i = 0; i < def->nb_oargs + def->nb_iargs; i++)
1352 printf(" %d", def->sorted_args[i]);
1353 printf("\n");
1354 }
1355#endif
1356 tdefs++;
1357 }
1358
c68aaa18 1359#if defined(CONFIG_DEBUG_TCG)
a9751609 1360 i = 0;
c68aaa18 1361 for (op = 0; op < ARRAY_SIZE(tcg_op_defs); op++) {
f412c762 1362 const TCGOpDef *def = &tcg_op_defs[op];
c1a61f6c 1363 if (def->flags & TCG_OPF_NOT_PRESENT) {
c68aaa18 1364 /* Wrong entry in op definitions? */
f412c762
RH		 1365 if (def->used) {
1366 fprintf(stderr, "Invalid op definition for %s\n", def->name);
a9751609
RH		 1367 i = 1;
1368 }
c68aaa18
SW		 1369 } else {
1370 /* Missing entry in op definitions? */
f412c762
RH		 1371 if (!def->used) {
1372 fprintf(stderr, "Missing op definition for %s\n", def->name);
a9751609
RH		 1373 i = 1;
1374 }
c68aaa18
SW		 1375 }
1376 }
a9751609
RH		 1377 if (i == 1) {
1378 tcg_abort();
1379 }
c68aaa18 1380#endif
c896fe29
FB		 1381}
1382
1383#ifdef USE_LIVENESS_ANALYSIS
1384
1385/* set a nop for an operation using 'nb_args' */
1386static inline void tcg_set_nop(TCGContext *s, uint16_t *opc_ptr,
1387 TCGArg *args, int nb_args)
1388{
1389 if (nb_args == 0) {
1390 *opc_ptr = INDEX_op_nop;
1391 } else {
1392 *opc_ptr = INDEX_op_nopn;
1393 args[0] = nb_args;
1394 args[nb_args - 1] = nb_args;
1395 }
1396}
1397
9c43b68d
AJ		 1398/* liveness analysis: end of function: all temps are dead, and globals
1399 should be in memory. */
1400static inline void tcg_la_func_end(TCGContext *s, uint8_t *dead_temps,
1401 uint8_t *mem_temps)
c896fe29 1402{
9c43b68d
AJ		 1403 memset(dead_temps, 1, s->nb_temps);
1404 memset(mem_temps, 1, s->nb_globals);
1405 memset(mem_temps + s->nb_globals, 0, s->nb_temps - s->nb_globals);
c896fe29
FB		 1406}
1407
9c43b68d
AJ		 1408/* liveness analysis: end of basic block: all temps are dead, globals
1409 and local temps should be in memory. */
1410static inline void tcg_la_bb_end(TCGContext *s, uint8_t *dead_temps,
1411 uint8_t *mem_temps)
641d5fbe
FB		 1412{
1413 int i;
641d5fbe 1414
9c43b68d
AJ		 1415 memset(dead_temps, 1, s->nb_temps);
1416 memset(mem_temps, 1, s->nb_globals);
641d5fbe 1417 for(i = s->nb_globals; i < s->nb_temps; i++) {
9c43b68d 1418 mem_temps[i] = s->temps[i].temp_local;
641d5fbe
FB		 1419 }
1420}
1421
866cb6cb 1422/* Liveness analysis : update the opc_dead_args array to tell if a
c896fe29
FB		 1423 given input arguments is dead. Instructions updating dead
1424 temporaries are removed. */
8fcd3692 1425static void tcg_liveness_analysis(TCGContext *s)
c896fe29 1426{
cf066674 1427 int i, op_index, nb_args, nb_iargs, nb_oargs, nb_ops;
03271524 1428 TCGOpcode op, op_new, op_new2;
cf066674 1429 TCGArg *args, arg;
c896fe29 1430 const TCGOpDef *def;
9c43b68d 1431 uint8_t *dead_temps, *mem_temps;
ec7a869d
AJ		 1432 uint16_t dead_args;
1433 uint8_t sync_args;
03271524 1434 bool have_op_new2;
c896fe29 1435
efd7f486 1436 s->gen_opc_ptr++; /* skip end */
c896fe29 1437
92414b31 1438 nb_ops = s->gen_opc_ptr - s->gen_opc_buf;
c896fe29 1439
866cb6cb 1440 s->op_dead_args = tcg_malloc(nb_ops * sizeof(uint16_t));
ec7a869d 1441 s->op_sync_args = tcg_malloc(nb_ops * sizeof(uint8_t));
c896fe29
FB		 1442
1443 dead_temps = tcg_malloc(s->nb_temps);
9c43b68d
AJ		 1444 mem_temps = tcg_malloc(s->nb_temps);
1445 tcg_la_func_end(s, dead_temps, mem_temps);
c896fe29 1446
c4afe5c4 1447 args = s->gen_opparam_ptr;
c896fe29
FB		 1448 op_index = nb_ops - 1;
1449 while (op_index >= 0) {
92414b31 1450 op = s->gen_opc_buf[op_index];
c896fe29
FB		 1451 def = &tcg_op_defs[op];
1452 switch(op) {
1453 case INDEX_op_call:
c6e113f5
FB		 1454 {
1455 int call_flags;
c896fe29 1456
c6e113f5
FB		 1457 nb_args = args[-1];
1458 args -= nb_args;
cf066674
RH		 1459 arg = *args++;
1460 nb_iargs = arg & 0xffff;
1461 nb_oargs = arg >> 16;
1462 call_flags = args[nb_oargs + nb_iargs + 1];
c6e113f5
FB		 1463
1464 /* pure functions can be removed if their result is not
1465 used */
78505279 1466 if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) {
cf066674 1467 for (i = 0; i < nb_oargs; i++) {
c6e113f5 1468 arg = args[i];
9c43b68d 1469 if (!dead_temps[arg] || mem_temps[arg]) {
c6e113f5 1470 goto do_not_remove_call;
9c43b68d 1471 }
c6e113f5 1472 }
92414b31 1473 tcg_set_nop(s, s->gen_opc_buf + op_index,
c6e113f5
FB		 1474 args - 1, nb_args);
1475 } else {
1476 do_not_remove_call:
c896fe29 1477
c6e113f5 1478 /* output args are dead */
6b64b624 1479 dead_args = 0;
ec7a869d 1480 sync_args = 0;
cf066674 1481 for (i = 0; i < nb_oargs; i++) {
c6e113f5 1482 arg = args[i];
6b64b624
AJ		 1483 if (dead_temps[arg]) {
1484 dead_args |= (1 << i);
1485 }
9c43b68d
AJ		 1486 if (mem_temps[arg]) {
1487 sync_args |= (1 << i);
1488 }
c6e113f5 1489 dead_temps[arg] = 1;
9c43b68d 1490 mem_temps[arg] = 0;
c6e113f5 1491 }
78505279
AJ		 1492
1493 if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) {
1494 /* globals should be synced to memory */
1495 memset(mem_temps, 1, s->nb_globals);
1496 }
1497 if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS |
1498 TCG_CALL_NO_READ_GLOBALS))) {
9c43b68d
AJ		 1499 /* globals should go back to memory */
1500 memset(dead_temps, 1, s->nb_globals);
b9c18f56
AJ		 1501 }
1502
c6e113f5 1503 /* input args are live */
cf066674 1504 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
866cb6cb 1505 arg = args[i];
39cf05d3
FB		 1506 if (arg != TCG_CALL_DUMMY_ARG) {
1507 if (dead_temps[arg]) {
866cb6cb 1508 dead_args |= (1 << i);
39cf05d3
FB		 1509 }
1510 dead_temps[arg] = 0;
c6e113f5 1511 }
c6e113f5 1512 }
866cb6cb 1513 s->op_dead_args[op_index] = dead_args;
ec7a869d 1514 s->op_sync_args[op_index] = sync_args;
c896fe29 1515 }
c6e113f5 1516 args--;
c896fe29 1517 }
c896fe29 1518 break;
7e4597d7
FB		 1519 case INDEX_op_debug_insn_start:
1520 args -= def->nb_args;
1521 break;
c896fe29
FB		 1522 case INDEX_op_nopn:
1523 nb_args = args[-1];
1524 args -= nb_args;
1525 break;
5ff9d6a4
FB		 1526 case INDEX_op_discard:
1527 args--;
1528 /* mark the temporary as dead */
1529 dead_temps[args[0]] = 1;
9c43b68d 1530 mem_temps[args[0]] = 0;
5ff9d6a4 1531 break;
c896fe29
FB		 1532 case INDEX_op_end:
1533 break;
1305c451
RH		 1534
1535 case INDEX_op_add2_i32:
f1fae40c
RH		 1536 op_new = INDEX_op_add_i32;
1537 goto do_addsub2;
1305c451 1538 case INDEX_op_sub2_i32:
f1fae40c
RH		 1539 op_new = INDEX_op_sub_i32;
1540 goto do_addsub2;
1541 case INDEX_op_add2_i64:
1542 op_new = INDEX_op_add_i64;
1543 goto do_addsub2;
1544 case INDEX_op_sub2_i64:
1545 op_new = INDEX_op_sub_i64;
1546 do_addsub2:
1305c451
RH		 1547 args -= 6;
1548 nb_iargs = 4;
1549 nb_oargs = 2;
1550 /* Test if the high part of the operation is dead, but not
1551 the low part. The result can be optimized to a simple
1552 add or sub. This happens often for x86_64 guest when the
1553 cpu mode is set to 32 bit. */
3c5645fa
KB		 1554 if (dead_temps[args[1]] && !mem_temps[args[1]]) {
1555 if (dead_temps[args[0]] && !mem_temps[args[0]]) {
1305c451
RH		 1556 goto do_remove;
1557 }
1558 /* Create the single operation plus nop. */
f1fae40c 1559 s->gen_opc_buf[op_index] = op = op_new;
1305c451
RH		 1560 args[1] = args[2];
1561 args[2] = args[4];
92414b31
EV		 1562 assert(s->gen_opc_buf[op_index + 1] == INDEX_op_nop);
1563 tcg_set_nop(s, s->gen_opc_buf + op_index + 1, args + 3, 3);
1305c451
RH		 1564 /* Fall through and mark the single-word operation live. */
1565 nb_iargs = 2;
1566 nb_oargs = 1;
1567 }
1568 goto do_not_remove;
1569
1414968a 1570 case INDEX_op_mulu2_i32:
03271524
RH		 1571 op_new = INDEX_op_mul_i32;
1572 op_new2 = INDEX_op_muluh_i32;
1573 have_op_new2 = TCG_TARGET_HAS_muluh_i32;
1574 goto do_mul2;
f1fae40c
RH		 1575 case INDEX_op_muls2_i32:
1576 op_new = INDEX_op_mul_i32;
03271524
RH		 1577 op_new2 = INDEX_op_mulsh_i32;
1578 have_op_new2 = TCG_TARGET_HAS_mulsh_i32;
f1fae40c
RH		 1579 goto do_mul2;
1580 case INDEX_op_mulu2_i64:
03271524
RH		 1581 op_new = INDEX_op_mul_i64;
1582 op_new2 = INDEX_op_muluh_i64;
1583 have_op_new2 = TCG_TARGET_HAS_muluh_i64;
1584 goto do_mul2;
f1fae40c
RH		 1585 case INDEX_op_muls2_i64:
1586 op_new = INDEX_op_mul_i64;
03271524
RH		 1587 op_new2 = INDEX_op_mulsh_i64;
1588 have_op_new2 = TCG_TARGET_HAS_mulsh_i64;
1589 goto do_mul2;
f1fae40c 1590 do_mul2:
1414968a
RH		 1591 args -= 4;
1592 nb_iargs = 2;
1593 nb_oargs = 2;
3c5645fa
KB		 1594 if (dead_temps[args[1]] && !mem_temps[args[1]]) {
1595 if (dead_temps[args[0]] && !mem_temps[args[0]]) {
03271524 1596 /* Both parts of the operation are dead. */
1414968a
RH		 1597 goto do_remove;
1598 }
03271524 1599 /* The high part of the operation is dead; generate the low. */
f1fae40c 1600 s->gen_opc_buf[op_index] = op = op_new;
1414968a
RH		 1601 args[1] = args[2];
1602 args[2] = args[3];
03271524
RH		 1603 } else if (have_op_new2 && dead_temps[args[0]]
1604 && !mem_temps[args[0]]) {
1605 /* The low part of the operation is dead; generate the high. */
1606 s->gen_opc_buf[op_index] = op = op_new2;
1607 args[0] = args[1];
1608 args[1] = args[2];
1609 args[2] = args[3];
1610 } else {
1611 goto do_not_remove;
1414968a 1612 }
03271524
RH		 1613 assert(s->gen_opc_buf[op_index + 1] == INDEX_op_nop);
1614 tcg_set_nop(s, s->gen_opc_buf + op_index + 1, args + 3, 1);
1615 /* Mark the single-word operation live. */
1616 nb_oargs = 1;
1414968a
RH		 1617 goto do_not_remove;
1618
c896fe29 1619 default:
1305c451 1620 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
49516bc0
AJ		 1621 args -= def->nb_args;
1622 nb_iargs = def->nb_iargs;
1623 nb_oargs = def->nb_oargs;
c896fe29 1624
49516bc0
AJ		 1625 /* Test if the operation can be removed because all
1626 its outputs are dead. We assume that nb_oargs == 0
1627 implies side effects */
1628 if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) {
1629 for(i = 0; i < nb_oargs; i++) {
1630 arg = args[i];
9c43b68d 1631 if (!dead_temps[arg] || mem_temps[arg]) {
49516bc0 1632 goto do_not_remove;
9c43b68d 1633 }
49516bc0 1634 }
1305c451 1635 do_remove:
92414b31 1636 tcg_set_nop(s, s->gen_opc_buf + op_index, args, def->nb_args);
c896fe29 1637#ifdef CONFIG_PROFILER
49516bc0 1638 s->del_op_count++;
c896fe29 1639#endif
49516bc0
AJ		 1640 } else {
1641 do_not_remove:
c896fe29 1642
49516bc0 1643 /* output args are dead */
6b64b624 1644 dead_args = 0;
ec7a869d 1645 sync_args = 0;
49516bc0
AJ		 1646 for(i = 0; i < nb_oargs; i++) {
1647 arg = args[i];
6b64b624
AJ		 1648 if (dead_temps[arg]) {
1649 dead_args |= (1 << i);
1650 }
9c43b68d
AJ		 1651 if (mem_temps[arg]) {
1652 sync_args |= (1 << i);
1653 }
49516bc0 1654 dead_temps[arg] = 1;
9c43b68d 1655 mem_temps[arg] = 0;
49516bc0
AJ		 1656 }
1657
1658 /* if end of basic block, update */
1659 if (def->flags & TCG_OPF_BB_END) {
9c43b68d 1660 tcg_la_bb_end(s, dead_temps, mem_temps);
3d5c5f87
AJ		 1661 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) {
1662 /* globals should be synced to memory */
9c43b68d 1663 memset(mem_temps, 1, s->nb_globals);
49516bc0
AJ		 1664 }
1665
1666 /* input args are live */
866cb6cb
AJ		 1667 for(i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
1668 arg = args[i];
49516bc0 1669 if (dead_temps[arg]) {
866cb6cb 1670 dead_args |= (1 << i);
c896fe29 1671 }
49516bc0 1672 dead_temps[arg] = 0;
c896fe29 1673 }
866cb6cb 1674 s->op_dead_args[op_index] = dead_args;
ec7a869d 1675 s->op_sync_args[op_index] = sync_args;
c896fe29
FB		 1676 }
1677 break;
1678 }
1679 op_index--;
1680 }
1681
1ff0a2c5 1682 if (args != s->gen_opparam_buf) {
c896fe29 1683 tcg_abort();
1ff0a2c5 1684 }
c896fe29
FB		 1685}
1686#else
1687/* dummy liveness analysis */
655feed5 1688static void tcg_liveness_analysis(TCGContext *s)
c896fe29
FB		 1689{
1690 int nb_ops;
92414b31 1691 nb_ops = s->gen_opc_ptr - s->gen_opc_buf;
c896fe29 1692
866cb6cb
AJ		 1693 s->op_dead_args = tcg_malloc(nb_ops * sizeof(uint16_t));
1694 memset(s->op_dead_args, 0, nb_ops * sizeof(uint16_t));
ec7a869d
AJ		 1695 s->op_sync_args = tcg_malloc(nb_ops * sizeof(uint8_t));
1696 memset(s->op_sync_args, 0, nb_ops * sizeof(uint8_t));
c896fe29
FB		 1697}
1698#endif
1699
1700#ifndef NDEBUG
1701static void dump_regs(TCGContext *s)
1702{
1703 TCGTemp *ts;
1704 int i;
1705 char buf[64];
1706
1707 for(i = 0; i < s->nb_temps; i++) {
1708 ts = &s->temps[i];
ac56dd48 1709 printf(" %10s: ", tcg_get_arg_str_idx(s, buf, sizeof(buf), i));
c896fe29
FB		 1710 switch(ts->val_type) {
1711 case TEMP_VAL_REG:
1712 printf("%s", tcg_target_reg_names[ts->reg]);
1713 break;
1714 case TEMP_VAL_MEM:
1715 printf("%d(%s)", (int)ts->mem_offset, tcg_target_reg_names[ts->mem_reg]);
1716 break;
1717 case TEMP_VAL_CONST:
1718 printf("$0x%" TCG_PRIlx, ts->val);
1719 break;
1720 case TEMP_VAL_DEAD:
1721 printf("D");
1722 break;
1723 default:
1724 printf("???");
1725 break;
1726 }
1727 printf("\n");
1728 }
1729
1730 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
1731 if (s->reg_to_temp[i] >= 0) {
1732 printf("%s: %s\n",
1733 tcg_target_reg_names[i],
ac56dd48 1734 tcg_get_arg_str_idx(s, buf, sizeof(buf), s->reg_to_temp[i]));
c896fe29
FB		 1735 }
1736 }
1737}
1738
1739static void check_regs(TCGContext *s)
1740{
1741 int reg, k;
1742 TCGTemp *ts;
1743 char buf[64];
1744
1745 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
1746 k = s->reg_to_temp[reg];
1747 if (k >= 0) {
1748 ts = &s->temps[k];
1749 if (ts->val_type != TEMP_VAL_REG ||
1750 ts->reg != reg) {
1751 printf("Inconsistency for register %s:\n",
1752 tcg_target_reg_names[reg]);
b03cce8e 1753 goto fail;
c896fe29
FB		 1754 }
1755 }
1756 }
1757 for(k = 0; k < s->nb_temps; k++) {
1758 ts = &s->temps[k];
1759 if (ts->val_type == TEMP_VAL_REG &&
1760 !ts->fixed_reg &&
1761 s->reg_to_temp[ts->reg] != k) {
1762 printf("Inconsistency for temp %s:\n",
ac56dd48 1763 tcg_get_arg_str_idx(s, buf, sizeof(buf), k));
b03cce8e 1764 fail:
c896fe29
FB		 1765 printf("reg state:\n");
1766 dump_regs(s);
1767 tcg_abort();
1768 }
1769 }
1770}
1771#endif
1772
1773static void temp_allocate_frame(TCGContext *s, int temp)
1774{
1775 TCGTemp *ts;
1776 ts = &s->temps[temp];
9b9c37c3
RH		 1777#if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64)
1778 /* Sparc64 stack is accessed with offset of 2047 */
b591dc59
BS		 1779 s->current_frame_offset = (s->current_frame_offset +
1780 (tcg_target_long)sizeof(tcg_target_long) - 1) &
1781 ~(sizeof(tcg_target_long) - 1);
f44c9960 1782#endif
b591dc59
BS		 1783 if (s->current_frame_offset + (tcg_target_long)sizeof(tcg_target_long) >
1784 s->frame_end) {
5ff9d6a4 1785 tcg_abort();
b591dc59 1786 }
c896fe29
FB		 1787 ts->mem_offset = s->current_frame_offset;
1788 ts->mem_reg = s->frame_reg;
1789 ts->mem_allocated = 1;
e2c6d1b4 1790 s->current_frame_offset += sizeof(tcg_target_long);
c896fe29
FB		 1791}
1792
7f6ceedf
AJ		 1793/* sync register 'reg' by saving it to the corresponding temporary */
1794static inline void tcg_reg_sync(TCGContext *s, int reg)
1795{
1796 TCGTemp *ts;
1797 int temp;
1798
1799 temp = s->reg_to_temp[reg];
1800 ts = &s->temps[temp];
1801 assert(ts->val_type == TEMP_VAL_REG);
1802 if (!ts->mem_coherent && !ts->fixed_reg) {
1803 if (!ts->mem_allocated) {
1804 temp_allocate_frame(s, temp);
1805 }
1806 tcg_out_st(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
1807 }
1808 ts->mem_coherent = 1;
1809}
1810
c896fe29
FB		 1811/* free register 'reg' by spilling the corresponding temporary if necessary */
1812static void tcg_reg_free(TCGContext *s, int reg)
1813{
c896fe29
FB		 1814 int temp;
1815
1816 temp = s->reg_to_temp[reg];
1817 if (temp != -1) {
7f6ceedf
AJ		 1818 tcg_reg_sync(s, reg);
1819 s->temps[temp].val_type = TEMP_VAL_MEM;
c896fe29
FB		 1820 s->reg_to_temp[reg] = -1;
1821 }
1822}
1823
1824/* Allocate a register belonging to reg1 & ~reg2 */
1825static int tcg_reg_alloc(TCGContext *s, TCGRegSet reg1, TCGRegSet reg2)
1826{
1827 int i, reg;
1828 TCGRegSet reg_ct;
1829
1830 tcg_regset_andnot(reg_ct, reg1, reg2);
1831
1832 /* first try free registers */
0954d0d9 1833 for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
c896fe29
FB		 1834 reg = tcg_target_reg_alloc_order[i];
1835 if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] == -1)
1836 return reg;
1837 }
1838
1839 /* XXX: do better spill choice */
0954d0d9 1840 for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
c896fe29
FB		 1841 reg = tcg_target_reg_alloc_order[i];
1842 if (tcg_regset_test_reg(reg_ct, reg)) {
1843 tcg_reg_free(s, reg);
1844 return reg;
1845 }
1846 }
1847
1848 tcg_abort();
1849}
1850
639368dd
AJ		 1851/* mark a temporary as dead. */
1852static inline void temp_dead(TCGContext *s, int temp)
1853{
1854 TCGTemp *ts;
1855
1856 ts = &s->temps[temp];
1857 if (!ts->fixed_reg) {
1858 if (ts->val_type == TEMP_VAL_REG) {
1859 s->reg_to_temp[ts->reg] = -1;
1860 }
e5138db5 1861 if (temp < s->nb_globals || ts->temp_local) {
639368dd
AJ		 1862 ts->val_type = TEMP_VAL_MEM;
1863 } else {
1864 ts->val_type = TEMP_VAL_DEAD;
1865 }
1866 }
1867}
1868
1ad80729 1869/* sync a temporary to memory. 'allocated_regs' is used in case a
641d5fbe 1870 temporary registers needs to be allocated to store a constant. */
1ad80729 1871static inline void temp_sync(TCGContext *s, int temp, TCGRegSet allocated_regs)
641d5fbe
FB		 1872{
1873 TCGTemp *ts;
641d5fbe
FB		 1874
1875 ts = &s->temps[temp];
1876 if (!ts->fixed_reg) {
1877 switch(ts->val_type) {
1ad80729
AJ		 1878 case TEMP_VAL_CONST:
1879 ts->reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
1880 allocated_regs);
1881 ts->val_type = TEMP_VAL_REG;
1882 s->reg_to_temp[ts->reg] = temp;
1883 ts->mem_coherent = 0;
1884 tcg_out_movi(s, ts->type, ts->reg, ts->val);
1885 /* fallthrough*/
641d5fbe 1886 case TEMP_VAL_REG:
1ad80729 1887 tcg_reg_sync(s, ts->reg);
641d5fbe
FB		 1888 break;
1889 case TEMP_VAL_DEAD:
641d5fbe
FB		 1890 case TEMP_VAL_MEM:
1891 break;
1892 default:
1893 tcg_abort();
1894 }
1895 }
1896}
1897
1ad80729
AJ		 1898/* save a temporary to memory. 'allocated_regs' is used in case a
1899 temporary registers needs to be allocated to store a constant. */
1900static inline void temp_save(TCGContext *s, int temp, TCGRegSet allocated_regs)
1901{
2c0366f0
AJ		 1902#ifdef USE_LIVENESS_ANALYSIS
1903 /* The liveness analysis already ensures that globals are back
1904 in memory. Keep an assert for safety. */
1905 assert(s->temps[temp].val_type == TEMP_VAL_MEM || s->temps[temp].fixed_reg);
1906#else
1ad80729
AJ		 1907 temp_sync(s, temp, allocated_regs);
1908 temp_dead(s, temp);
2c0366f0 1909#endif
1ad80729
AJ		 1910}
1911
9814dd27 1912/* save globals to their canonical location and assume they can be
e8996ee0
FB		 1913 modified be the following code. 'allocated_regs' is used in case a
1914 temporary registers needs to be allocated to store a constant. */
1915static void save_globals(TCGContext *s, TCGRegSet allocated_regs)
c896fe29 1916{
641d5fbe 1917 int i;
c896fe29
FB		 1918
1919 for(i = 0; i < s->nb_globals; i++) {
641d5fbe 1920 temp_save(s, i, allocated_regs);
c896fe29 1921 }
e5097dc8
FB		 1922}
1923
3d5c5f87
AJ		 1924/* sync globals to their canonical location and assume they can be
1925 read by the following code. 'allocated_regs' is used in case a
1926 temporary registers needs to be allocated to store a constant. */
1927static void sync_globals(TCGContext *s, TCGRegSet allocated_regs)
1928{
1929 int i;
1930
1931 for (i = 0; i < s->nb_globals; i++) {
1932#ifdef USE_LIVENESS_ANALYSIS
1933 assert(s->temps[i].val_type != TEMP_VAL_REG || s->temps[i].fixed_reg ||
1934 s->temps[i].mem_coherent);
1935#else
1936 temp_sync(s, i, allocated_regs);
1937#endif
1938 }
1939}
1940
e5097dc8 1941/* at the end of a basic block, we assume all temporaries are dead and
e8996ee0
FB		 1942 all globals are stored at their canonical location. */
1943static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs)
e5097dc8
FB		 1944{
1945 TCGTemp *ts;
1946 int i;
1947
c896fe29
FB		 1948 for(i = s->nb_globals; i < s->nb_temps; i++) {
1949 ts = &s->temps[i];
641d5fbe
FB		 1950 if (ts->temp_local) {
1951 temp_save(s, i, allocated_regs);
1952 } else {
2c0366f0
AJ		 1953#ifdef USE_LIVENESS_ANALYSIS
1954 /* The liveness analysis already ensures that temps are dead.
1955 Keep an assert for safety. */
1956 assert(ts->val_type == TEMP_VAL_DEAD);
1957#else
639368dd 1958 temp_dead(s, i);
2c0366f0 1959#endif
c896fe29
FB		 1960 }
1961 }
e8996ee0
FB		 1962
1963 save_globals(s, allocated_regs);
c896fe29
FB		 1964}
1965
866cb6cb 1966#define IS_DEAD_ARG(n) ((dead_args >> (n)) & 1)
ec7a869d 1967#define NEED_SYNC_ARG(n) ((sync_args >> (n)) & 1)
c896fe29 1968
ec7a869d
AJ		 1969static void tcg_reg_alloc_movi(TCGContext *s, const TCGArg *args,
1970 uint16_t dead_args, uint8_t sync_args)
e8996ee0
FB		 1971{
1972 TCGTemp *ots;
1973 tcg_target_ulong val;
1974
1975 ots = &s->temps[args[0]];
1976 val = args[1];
1977
1978 if (ots->fixed_reg) {
1979 /* for fixed registers, we do not do any constant
1980 propagation */
1981 tcg_out_movi(s, ots->type, ots->reg, val);
1982 } else {
1235fc06 1983 /* The movi is not explicitly generated here */
e8996ee0
FB		 1984 if (ots->val_type == TEMP_VAL_REG)
1985 s->reg_to_temp[ots->reg] = -1;
1986 ots->val_type = TEMP_VAL_CONST;
1987 ots->val = val;
1988 }
ec7a869d
AJ		 1989 if (NEED_SYNC_ARG(0)) {
1990 temp_sync(s, args[0], s->reserved_regs);
1991 }
4c4e1ab2
AJ		 1992 if (IS_DEAD_ARG(0)) {
1993 temp_dead(s, args[0]);
1994 }
e8996ee0
FB		 1995}
1996
c896fe29 1997static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
ec7a869d
AJ		 1998 const TCGArg *args, uint16_t dead_args,
1999 uint8_t sync_args)
c896fe29 2000{
c29c1d7e 2001 TCGRegSet allocated_regs;
c896fe29 2002 TCGTemp *ts, *ots;
450445d5 2003 TCGType otype, itype;
c896fe29 2004
c29c1d7e 2005 tcg_regset_set(allocated_regs, s->reserved_regs);
c896fe29
FB		 2006 ots = &s->temps[args[0]];
2007 ts = &s->temps[args[1]];
450445d5
RH		 2008
2009 /* Note that otype != itype for no-op truncation. */
2010 otype = ots->type;
2011 itype = ts->type;
c29c1d7e
AJ		 2012
2013 /* If the source value is not in a register, and we're going to be
2014 forced to have it in a register in order to perform the copy,
2015 then copy the SOURCE value into its own register first. That way
2016 we don't have to reload SOURCE the next time it is used. */
2017 if (((NEED_SYNC_ARG(0) || ots->fixed_reg) && ts->val_type != TEMP_VAL_REG)
2018 || ts->val_type == TEMP_VAL_MEM) {
450445d5 2019 ts->reg = tcg_reg_alloc(s, tcg_target_available_regs[itype],
af3cbfbe 2020 allocated_regs);
c29c1d7e 2021 if (ts->val_type == TEMP_VAL_MEM) {
450445d5 2022 tcg_out_ld(s, itype, ts->reg, ts->mem_reg, ts->mem_offset);
c29c1d7e
AJ		 2023 ts->mem_coherent = 1;
2024 } else if (ts->val_type == TEMP_VAL_CONST) {
450445d5 2025 tcg_out_movi(s, itype, ts->reg, ts->val);
c29c1d7e
AJ		 2026 }
2027 s->reg_to_temp[ts->reg] = args[1];
2028 ts->val_type = TEMP_VAL_REG;
2029 }
c896fe29 2030
c29c1d7e
AJ		 2031 if (IS_DEAD_ARG(0) && !ots->fixed_reg) {
2032 /* mov to a non-saved dead register makes no sense (even with
2033 liveness analysis disabled). */
2034 assert(NEED_SYNC_ARG(0));
2035 /* The code above should have moved the temp to a register. */
2036 assert(ts->val_type == TEMP_VAL_REG);
2037 if (!ots->mem_allocated) {
2038 temp_allocate_frame(s, args[0]);
2039 }
450445d5 2040 tcg_out_st(s, otype, ts->reg, ots->mem_reg, ots->mem_offset);
c29c1d7e
AJ		 2041 if (IS_DEAD_ARG(1)) {
2042 temp_dead(s, args[1]);
2043 }
2044 temp_dead(s, args[0]);
2045 } else if (ts->val_type == TEMP_VAL_CONST) {
2046 /* propagate constant */
2047 if (ots->val_type == TEMP_VAL_REG) {
2048 s->reg_to_temp[ots->reg] = -1;
2049 }
2050 ots->val_type = TEMP_VAL_CONST;
2051 ots->val = ts->val;
2052 } else {
2053 /* The code in the first if block should have moved the
2054 temp to a register. */
2055 assert(ts->val_type == TEMP_VAL_REG);
866cb6cb 2056 if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) {
c896fe29 2057 /* the mov can be suppressed */
c29c1d7e 2058 if (ots->val_type == TEMP_VAL_REG) {
c896fe29 2059 s->reg_to_temp[ots->reg] = -1;
c29c1d7e
AJ		 2060 }
2061 ots->reg = ts->reg;
639368dd 2062 temp_dead(s, args[1]);
c896fe29 2063 } else {
c29c1d7e
AJ		 2064 if (ots->val_type != TEMP_VAL_REG) {
2065 /* When allocating a new register, make sure to not spill the
2066 input one. */
2067 tcg_regset_set_reg(allocated_regs, ts->reg);
450445d5 2068 ots->reg = tcg_reg_alloc(s, tcg_target_available_regs[otype],
af3cbfbe 2069 allocated_regs);
c896fe29 2070 }
450445d5 2071 tcg_out_mov(s, otype, ots->reg, ts->reg);
c896fe29 2072 }
c29c1d7e
AJ		 2073 ots->val_type = TEMP_VAL_REG;
2074 ots->mem_coherent = 0;
2075 s->reg_to_temp[ots->reg] = args[0];
2076 if (NEED_SYNC_ARG(0)) {
2077 tcg_reg_sync(s, ots->reg);
c896fe29 2078 }
ec7a869d 2079 }
c896fe29
FB		 2080}
2081
2082static void tcg_reg_alloc_op(TCGContext *s,
a9751609 2083 const TCGOpDef *def, TCGOpcode opc,
ec7a869d
AJ		 2084 const TCGArg *args, uint16_t dead_args,
2085 uint8_t sync_args)
c896fe29
FB		 2086{
2087 TCGRegSet allocated_regs;
2088 int i, k, nb_iargs, nb_oargs, reg;
2089 TCGArg arg;
2090 const TCGArgConstraint *arg_ct;
2091 TCGTemp *ts;
2092 TCGArg new_args[TCG_MAX_OP_ARGS];
2093 int const_args[TCG_MAX_OP_ARGS];
2094
2095 nb_oargs = def->nb_oargs;
2096 nb_iargs = def->nb_iargs;
2097
2098 /* copy constants */
2099 memcpy(new_args + nb_oargs + nb_iargs,
2100 args + nb_oargs + nb_iargs,
2101 sizeof(TCGArg) * def->nb_cargs);
2102
2103 /* satisfy input constraints */
2104 tcg_regset_set(allocated_regs, s->reserved_regs);
2105 for(k = 0; k < nb_iargs; k++) {
2106 i = def->sorted_args[nb_oargs + k];
2107 arg = args[i];
2108 arg_ct = &def->args_ct[i];
2109 ts = &s->temps[arg];
2110 if (ts->val_type == TEMP_VAL_MEM) {
2111 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
e4d5434c 2112 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
c896fe29
FB		 2113 ts->val_type = TEMP_VAL_REG;
2114 ts->reg = reg;
2115 ts->mem_coherent = 1;
2116 s->reg_to_temp[reg] = arg;
2117 } else if (ts->val_type == TEMP_VAL_CONST) {
f6c6afc1 2118 if (tcg_target_const_match(ts->val, ts->type, arg_ct)) {
c896fe29
FB		 2119 /* constant is OK for instruction */
2120 const_args[i] = 1;
2121 new_args[i] = ts->val;
2122 goto iarg_end;
2123 } else {
e8996ee0 2124 /* need to move to a register */
c896fe29
FB		 2125 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
2126 tcg_out_movi(s, ts->type, reg, ts->val);
e8996ee0
FB		 2127 ts->val_type = TEMP_VAL_REG;
2128 ts->reg = reg;
2129 ts->mem_coherent = 0;
2130 s->reg_to_temp[reg] = arg;
c896fe29
FB		 2131 }
2132 }
2133 assert(ts->val_type == TEMP_VAL_REG);
5ff9d6a4
FB		 2134 if (arg_ct->ct & TCG_CT_IALIAS) {
2135 if (ts->fixed_reg) {
2136 /* if fixed register, we must allocate a new register
2137 if the alias is not the same register */
2138 if (arg != args[arg_ct->alias_index])
2139 goto allocate_in_reg;
2140 } else {
2141 /* if the input is aliased to an output and if it is
2142 not dead after the instruction, we must allocate
2143 a new register and move it */
866cb6cb 2144 if (!IS_DEAD_ARG(i)) {
5ff9d6a4 2145 goto allocate_in_reg;
866cb6cb 2146 }
5ff9d6a4 2147 }
c896fe29
FB		 2148 }
2149 reg = ts->reg;
2150 if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
2151 /* nothing to do : the constraint is satisfied */
2152 } else {
2153 allocate_in_reg:
2154 /* allocate a new register matching the constraint
2155 and move the temporary register into it */
2156 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
3b6dac34 2157 tcg_out_mov(s, ts->type, reg, ts->reg);
c896fe29 2158 }
c896fe29
FB		 2159 new_args[i] = reg;
2160 const_args[i] = 0;
2161 tcg_regset_set_reg(allocated_regs, reg);
2162 iarg_end: ;
2163 }
2164
a52ad07e
AJ		 2165 /* mark dead temporaries and free the associated registers */
2166 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
2167 if (IS_DEAD_ARG(i)) {
2168 temp_dead(s, args[i]);
2169 }
2170 }
2171
e8996ee0
FB		 2172 if (def->flags & TCG_OPF_BB_END) {
2173 tcg_reg_alloc_bb_end(s, allocated_regs);
2174 } else {
e8996ee0
FB		 2175 if (def->flags & TCG_OPF_CALL_CLOBBER) {
2176 /* XXX: permit generic clobber register list ? */
2177 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
2178 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) {
2179 tcg_reg_free(s, reg);
2180 }
c896fe29 2181 }
3d5c5f87
AJ		 2182 }
2183 if (def->flags & TCG_OPF_SIDE_EFFECTS) {
2184 /* sync globals if the op has side effects and might trigger
2185 an exception. */
2186 sync_globals(s, allocated_regs);
c896fe29 2187 }
e8996ee0
FB		 2188
2189 /* satisfy the output constraints */
2190 tcg_regset_set(allocated_regs, s->reserved_regs);
2191 for(k = 0; k < nb_oargs; k++) {
2192 i = def->sorted_args[k];
2193 arg = args[i];
2194 arg_ct = &def->args_ct[i];
2195 ts = &s->temps[arg];
2196 if (arg_ct->ct & TCG_CT_ALIAS) {
2197 reg = new_args[arg_ct->alias_index];
2198 } else {
2199 /* if fixed register, we try to use it */
2200 reg = ts->reg;
2201 if (ts->fixed_reg &&
2202 tcg_regset_test_reg(arg_ct->u.regs, reg)) {
2203 goto oarg_end;
2204 }
2205 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
c896fe29 2206 }
e8996ee0
FB		 2207 tcg_regset_set_reg(allocated_regs, reg);
2208 /* if a fixed register is used, then a move will be done afterwards */
2209 if (!ts->fixed_reg) {
ec7a869d
AJ		 2210 if (ts->val_type == TEMP_VAL_REG) {
2211 s->reg_to_temp[ts->reg] = -1;
2212 }
2213 ts->val_type = TEMP_VAL_REG;
2214 ts->reg = reg;
2215 /* temp value is modified, so the value kept in memory is
2216 potentially not the same */
2217 ts->mem_coherent = 0;
2218 s->reg_to_temp[reg] = arg;
e8996ee0
FB		 2219 }
2220 oarg_end:
2221 new_args[i] = reg;
c896fe29 2222 }
c896fe29
FB		 2223 }
2224
c896fe29
FB		 2225 /* emit instruction */
2226 tcg_out_op(s, opc, new_args, const_args);
2227
2228 /* move the outputs in the correct register if needed */
2229 for(i = 0; i < nb_oargs; i++) {
2230 ts = &s->temps[args[i]];
2231 reg = new_args[i];
2232 if (ts->fixed_reg && ts->reg != reg) {
3b6dac34 2233 tcg_out_mov(s, ts->type, ts->reg, reg);
c896fe29 2234 }
ec7a869d
AJ		 2235 if (NEED_SYNC_ARG(i)) {
2236 tcg_reg_sync(s, reg);
2237 }
2238 if (IS_DEAD_ARG(i)) {
2239 temp_dead(s, args[i]);
2240 }
c896fe29
FB		 2241 }
2242}
2243
b03cce8e
FB		 2244#ifdef TCG_TARGET_STACK_GROWSUP
2245#define STACK_DIR(x) (-(x))
2246#else
2247#define STACK_DIR(x) (x)
2248#endif
2249
c896fe29 2250static int tcg_reg_alloc_call(TCGContext *s, const TCGOpDef *def,
a9751609 2251 TCGOpcode opc, const TCGArg *args,
ec7a869d 2252 uint16_t dead_args, uint8_t sync_args)
c896fe29
FB		 2253{
2254 int nb_iargs, nb_oargs, flags, nb_regs, i, reg, nb_params;
cf066674 2255 TCGArg arg;
c896fe29 2256 TCGTemp *ts;
d3452f1f
RH		 2257 intptr_t stack_offset;
2258 size_t call_stack_size;
cf066674
RH		 2259 tcg_insn_unit *func_addr;
2260 int allocate_args;
c896fe29 2261 TCGRegSet allocated_regs;
c896fe29
FB		 2262
2263 arg = *args++;
2264
2265 nb_oargs = arg >> 16;
2266 nb_iargs = arg & 0xffff;
cf066674 2267 nb_params = nb_iargs;
c896fe29 2268
cf066674
RH		 2269 func_addr = (tcg_insn_unit *)(intptr_t)args[nb_oargs + nb_iargs];
2270 flags = args[nb_oargs + nb_iargs + 1];
c896fe29 2271
6e17d0c5 2272 nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs);
cf066674 2273 if (nb_regs > nb_params) {
c896fe29 2274 nb_regs = nb_params;
cf066674 2275 }
c896fe29
FB		 2276
2277 /* assign stack slots first */
c896fe29
FB		 2278 call_stack_size = (nb_params - nb_regs) * sizeof(tcg_target_long);
2279 call_stack_size = (call_stack_size + TCG_TARGET_STACK_ALIGN - 1) &
2280 ~(TCG_TARGET_STACK_ALIGN - 1);
b03cce8e
FB		 2281 allocate_args = (call_stack_size > TCG_STATIC_CALL_ARGS_SIZE);
2282 if (allocate_args) {
345649c0
BS		 2283 /* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed,
2284 preallocate call stack */
2285 tcg_abort();
b03cce8e 2286 }
39cf05d3
FB		 2287
2288 stack_offset = TCG_TARGET_CALL_STACK_OFFSET;
c896fe29
FB		 2289 for(i = nb_regs; i < nb_params; i++) {
2290 arg = args[nb_oargs + i];
39cf05d3
FB		 2291#ifdef TCG_TARGET_STACK_GROWSUP
2292 stack_offset -= sizeof(tcg_target_long);
2293#endif
2294 if (arg != TCG_CALL_DUMMY_ARG) {
2295 ts = &s->temps[arg];
2296 if (ts->val_type == TEMP_VAL_REG) {
2297 tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset);
2298 } else if (ts->val_type == TEMP_VAL_MEM) {
2299 reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
2300 s->reserved_regs);
2301 /* XXX: not correct if reading values from the stack */
2302 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
2303 tcg_out_st(s, ts->type, reg, TCG_REG_CALL_STACK, stack_offset);
2304 } else if (ts->val_type == TEMP_VAL_CONST) {
2305 reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
2306 s->reserved_regs);
2307 /* XXX: sign extend may be needed on some targets */
2308 tcg_out_movi(s, ts->type, reg, ts->val);
2309 tcg_out_st(s, ts->type, reg, TCG_REG_CALL_STACK, stack_offset);
2310 } else {
2311 tcg_abort();
2312 }
c896fe29 2313 }
39cf05d3
FB		 2314#ifndef TCG_TARGET_STACK_GROWSUP
2315 stack_offset += sizeof(tcg_target_long);
2316#endif
c896fe29
FB		 2317 }
2318
2319 /* assign input registers */
2320 tcg_regset_set(allocated_regs, s->reserved_regs);
2321 for(i = 0; i < nb_regs; i++) {
2322 arg = args[nb_oargs + i];
39cf05d3
FB		 2323 if (arg != TCG_CALL_DUMMY_ARG) {
2324 ts = &s->temps[arg];
2325 reg = tcg_target_call_iarg_regs[i];
2326 tcg_reg_free(s, reg);
2327 if (ts->val_type == TEMP_VAL_REG) {
2328 if (ts->reg != reg) {
3b6dac34 2329 tcg_out_mov(s, ts->type, reg, ts->reg);
39cf05d3
FB		 2330 }
2331 } else if (ts->val_type == TEMP_VAL_MEM) {
2332 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
2333 } else if (ts->val_type == TEMP_VAL_CONST) {
2334 /* XXX: sign extend ? */
2335 tcg_out_movi(s, ts->type, reg, ts->val);
2336 } else {
2337 tcg_abort();
c896fe29 2338 }
39cf05d3 2339 tcg_regset_set_reg(allocated_regs, reg);
c896fe29 2340 }
c896fe29
FB		 2341 }
2342
c896fe29 2343 /* mark dead temporaries and free the associated registers */
866cb6cb 2344 for(i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
866cb6cb 2345 if (IS_DEAD_ARG(i)) {
639368dd 2346 temp_dead(s, args[i]);
c896fe29
FB		 2347 }
2348 }
2349
2350 /* clobber call registers */
2351 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
2352 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) {
2353 tcg_reg_free(s, reg);
2354 }
2355 }
78505279
AJ		 2356
2357 /* Save globals if they might be written by the helper, sync them if
2358 they might be read. */
2359 if (flags & TCG_CALL_NO_READ_GLOBALS) {
2360 /* Nothing to do */
2361 } else if (flags & TCG_CALL_NO_WRITE_GLOBALS) {
2362 sync_globals(s, allocated_regs);
2363 } else {
b9c18f56
AJ		 2364 save_globals(s, allocated_regs);
2365 }
c896fe29 2366
cf066674 2367 tcg_out_call(s, func_addr);
c896fe29
FB		 2368
2369 /* assign output registers and emit moves if needed */
2370 for(i = 0; i < nb_oargs; i++) {
2371 arg = args[i];
2372 ts = &s->temps[arg];
2373 reg = tcg_target_call_oarg_regs[i];
e8996ee0 2374 assert(s->reg_to_temp[reg] == -1);
34b1a49c 2375
c896fe29
FB		 2376 if (ts->fixed_reg) {
2377 if (ts->reg != reg) {
3b6dac34 2378 tcg_out_mov(s, ts->type, ts->reg, reg);
c896fe29
FB		 2379 }
2380 } else {
ec7a869d
AJ		 2381 if (ts->val_type == TEMP_VAL_REG) {
2382 s->reg_to_temp[ts->reg] = -1;
2383 }
2384 ts->val_type = TEMP_VAL_REG;
2385 ts->reg = reg;
2386 ts->mem_coherent = 0;
2387 s->reg_to_temp[reg] = arg;
2388 if (NEED_SYNC_ARG(i)) {
2389 tcg_reg_sync(s, reg);
2390 }
8c11ad25 2391 if (IS_DEAD_ARG(i)) {
639368dd 2392 temp_dead(s, args[i]);
8c11ad25 2393 }
c896fe29
FB		 2394 }
2395 }
2396
2397 return nb_iargs + nb_oargs + def->nb_cargs + 1;
2398}
2399
2400#ifdef CONFIG_PROFILER
2401
54604f74 2402static int64_t tcg_table_op_count[NB_OPS];
c896fe29 2403
871e6c35 2404static void dump_op_count(void)
c896fe29
FB		 2405{
2406 int i;
2407 FILE *f;
54604f74 2408 f = fopen("/tmp/op.log", "w");
c896fe29 2409 for(i = INDEX_op_end; i < NB_OPS; i++) {
54604f74 2410 fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name, tcg_table_op_count[i]);
c896fe29
FB		 2411 }
2412 fclose(f);
2413}
2414#endif
2415
2416
1813e175
RH		 2417static inline int tcg_gen_code_common(TCGContext *s,
2418 tcg_insn_unit *gen_code_buf,
2ba1eeb6 2419 long search_pc)
c896fe29 2420{
a9751609
RH		 2421 TCGOpcode opc;
2422 int op_index;
c896fe29 2423 const TCGOpDef *def;
c896fe29
FB		 2424 const TCGArg *args;
2425
2426#ifdef DEBUG_DISAS
8fec2b8c 2427 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
93fcfe39 2428 qemu_log("OP:\n");
eeacee4d 2429 tcg_dump_ops(s);
93fcfe39 2430 qemu_log("\n");
c896fe29
FB		 2431 }
2432#endif
2433
c5cc28ff
AJ		 2434#ifdef CONFIG_PROFILER
2435 s->opt_time -= profile_getclock();
2436#endif
2437
8f2e8c07 2438#ifdef USE_TCG_OPTIMIZATIONS
c4afe5c4 2439 s->gen_opparam_ptr =
1ff0a2c5 2440 tcg_optimize(s, s->gen_opc_ptr, s->gen_opparam_buf, tcg_op_defs);
8f2e8c07
KB		 2441#endif
2442
a23a9ec6 2443#ifdef CONFIG_PROFILER
c5cc28ff 2444 s->opt_time += profile_getclock();
a23a9ec6
FB		 2445 s->la_time -= profile_getclock();
2446#endif
c5cc28ff 2447
c896fe29 2448 tcg_liveness_analysis(s);
c5cc28ff 2449
a23a9ec6
FB		 2450#ifdef CONFIG_PROFILER
2451 s->la_time += profile_getclock();
2452#endif
c896fe29
FB		 2453
2454#ifdef DEBUG_DISAS
8fec2b8c 2455 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) {
c5cc28ff 2456 qemu_log("OP after optimization and liveness analysis:\n");
eeacee4d 2457 tcg_dump_ops(s);
93fcfe39 2458 qemu_log("\n");
c896fe29
FB		 2459 }
2460#endif
2461
2462 tcg_reg_alloc_start(s);
2463
2464 s->code_buf = gen_code_buf;
2465 s->code_ptr = gen_code_buf;
2466
9ecefc84
RH		 2467 tcg_out_tb_init(s);
2468
1ff0a2c5 2469 args = s->gen_opparam_buf;
c896fe29 2470 op_index = 0;
b3db8758 2471
c896fe29 2472 for(;;) {
92414b31 2473 opc = s->gen_opc_buf[op_index];
c896fe29 2474#ifdef CONFIG_PROFILER
54604f74 2475 tcg_table_op_count[opc]++;
c896fe29
FB		 2476#endif
2477 def = &tcg_op_defs[opc];
2478#if 0
2479 printf("%s: %d %d %d\n", def->name,
2480 def->nb_oargs, def->nb_iargs, def->nb_cargs);
2481 // dump_regs(s);
2482#endif
2483 switch(opc) {
2484 case INDEX_op_mov_i32:
c896fe29 2485 case INDEX_op_mov_i64:
ec7a869d
AJ		 2486 tcg_reg_alloc_mov(s, def, args, s->op_dead_args[op_index],
2487 s->op_sync_args[op_index]);
c896fe29 2488 break;
e8996ee0 2489 case INDEX_op_movi_i32:
e8996ee0 2490 case INDEX_op_movi_i64:
ec7a869d
AJ		 2491 tcg_reg_alloc_movi(s, args, s->op_dead_args[op_index],
2492 s->op_sync_args[op_index]);
e8996ee0 2493 break;
7e4597d7
FB		 2494 case INDEX_op_debug_insn_start:
2495 /* debug instruction */
2496 break;
c896fe29
FB		 2497 case INDEX_op_nop:
2498 case INDEX_op_nop1:
2499 case INDEX_op_nop2:
2500 case INDEX_op_nop3:
2501 break;
2502 case INDEX_op_nopn:
2503 args += args[0];
2504 goto next;
5ff9d6a4 2505 case INDEX_op_discard:
639368dd 2506 temp_dead(s, args[0]);
5ff9d6a4 2507 break;
c896fe29 2508 case INDEX_op_set_label:
e8996ee0 2509 tcg_reg_alloc_bb_end(s, s->reserved_regs);
9d6fca70 2510 tcg_out_label(s, args[0], s->code_ptr);
c896fe29
FB		 2511 break;
2512 case INDEX_op_call:
ec7a869d
AJ		 2513 args += tcg_reg_alloc_call(s, def, opc, args,
2514 s->op_dead_args[op_index],
2515 s->op_sync_args[op_index]);
c896fe29
FB		 2516 goto next;
2517 case INDEX_op_end:
2518 goto the_end;
c896fe29 2519 default:
25c4d9cc
RH		 2520 /* Sanity check that we've not introduced any unhandled opcodes. */
2521 if (def->flags & TCG_OPF_NOT_PRESENT) {
2522 tcg_abort();
2523 }
c896fe29
FB		 2524 /* Note: in order to speed up the code, it would be much
2525 faster to have specialized register allocator functions for
2526 some common argument patterns */
ec7a869d
AJ		 2527 tcg_reg_alloc_op(s, def, opc, args, s->op_dead_args[op_index],
2528 s->op_sync_args[op_index]);
c896fe29
FB		 2529 break;
2530 }
2531 args += def->nb_args;
8df1ca4b 2532 next:
1813e175 2533 if (search_pc >= 0 && search_pc < tcg_current_code_size(s)) {
b314f270 2534 return op_index;
c896fe29
FB		 2535 }
2536 op_index++;
2537#ifndef NDEBUG
2538 check_regs(s);
2539#endif
2540 }
2541 the_end:
b76f0d8c
YL		 2542 /* Generate TB finalization at the end of block */
2543 tcg_out_tb_finalize(s);
c896fe29
FB		 2544 return -1;
2545}
2546
1813e175 2547int tcg_gen_code(TCGContext *s, tcg_insn_unit *gen_code_buf)
c896fe29
FB		 2548{
2549#ifdef CONFIG_PROFILER
2550 {
c896fe29 2551 int n;
92414b31 2552 n = (s->gen_opc_ptr - s->gen_opc_buf);
a23a9ec6
FB		 2553 s->op_count += n;
2554 if (n > s->op_count_max)
2555 s->op_count_max = n;
2556
2557 s->temp_count += s->nb_temps;
2558 if (s->nb_temps > s->temp_count_max)
2559 s->temp_count_max = s->nb_temps;
c896fe29
FB		 2560 }
2561#endif
2562
2ba1eeb6 2563 tcg_gen_code_common(s, gen_code_buf, -1);
c896fe29
FB		 2564
2565 /* flush instruction cache */
1813e175 2566 flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
2aeabc08 2567
1813e175 2568 return tcg_current_code_size(s);
c896fe29
FB		 2569}
2570
2ba1eeb6 2571/* Return the index of the micro operation such as the pc after is <
623e265c
PB		 2572 offset bytes from the start of the TB. The contents of gen_code_buf must
2573 not be changed, though writing the same values is ok.
2574 Return -1 if not found. */
1813e175
RH		 2575int tcg_gen_code_search_pc(TCGContext *s, tcg_insn_unit *gen_code_buf,
2576 long offset)
c896fe29 2577{
623e265c 2578 return tcg_gen_code_common(s, gen_code_buf, offset);
c896fe29 2579}
a23a9ec6
FB		 2580
2581#ifdef CONFIG_PROFILER
405cf9ff 2582void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
a23a9ec6
FB		 2583{
2584 TCGContext *s = &tcg_ctx;
2585 int64_t tot;
2586
2587 tot = s->interm_time + s->code_time;
2588 cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n",
2589 tot, tot / 2.4e9);
2590 cpu_fprintf(f, "translated TBs %" PRId64 " (aborted=%" PRId64 " %0.1f%%)\n",
2591 s->tb_count,
2592 s->tb_count1 - s->tb_count,
2593 s->tb_count1 ? (double)(s->tb_count1 - s->tb_count) / s->tb_count1 * 100.0 : 0);
2594 cpu_fprintf(f, "avg ops/TB %0.1f max=%d\n",
2595 s->tb_count ? (double)s->op_count / s->tb_count : 0, s->op_count_max);
a23a9ec6
FB		 2596 cpu_fprintf(f, "deleted ops/TB %0.2f\n",
2597 s->tb_count ?
2598 (double)s->del_op_count / s->tb_count : 0);
2599 cpu_fprintf(f, "avg temps/TB %0.2f max=%d\n",
2600 s->tb_count ?
2601 (double)s->temp_count / s->tb_count : 0,
2602 s->temp_count_max);
2603
2604 cpu_fprintf(f, "cycles/op %0.1f\n",
2605 s->op_count ? (double)tot / s->op_count : 0);
2606 cpu_fprintf(f, "cycles/in byte %0.1f\n",
2607 s->code_in_len ? (double)tot / s->code_in_len : 0);
2608 cpu_fprintf(f, "cycles/out byte %0.1f\n",
2609 s->code_out_len ? (double)tot / s->code_out_len : 0);
2610 if (tot == 0)
2611 tot = 1;
2612 cpu_fprintf(f, " gen_interm time %0.1f%%\n",
2613 (double)s->interm_time / tot * 100.0);
2614 cpu_fprintf(f, " gen_code time %0.1f%%\n",
2615 (double)s->code_time / tot * 100.0);
c5cc28ff
AJ		 2616 cpu_fprintf(f, "optim./code time %0.1f%%\n",
2617 (double)s->opt_time / (s->code_time ? s->code_time : 1)
2618 * 100.0);
a23a9ec6
FB		 2619 cpu_fprintf(f, "liveness/code time %0.1f%%\n",
2620 (double)s->la_time / (s->code_time ? s->code_time : 1) * 100.0);
2621 cpu_fprintf(f, "cpu_restore count %" PRId64 "\n",
2622 s->restore_count);
2623 cpu_fprintf(f, " avg cycles %0.1f\n",
2624 s->restore_count ? (double)s->restore_time / s->restore_count : 0);
871e6c35
BS		 2625
2626 dump_op_count();
a23a9ec6
FB		 2627}
2628#else
405cf9ff 2629void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
a23a9ec6 2630{
24bf7b3a 2631 cpu_fprintf(f, "[TCG profiler not compiled]\n");
a23a9ec6
FB		 2632}
2633#endif
813da627
RH		 2634
2635#ifdef ELF_HOST_MACHINE
5872bbf2
RH		 2636/* In order to use this feature, the backend needs to do three things:
2637
2638 (1) Define ELF_HOST_MACHINE to indicate both what value to
2639 put into the ELF image and to indicate support for the feature.
2640
2641 (2) Define tcg_register_jit. This should create a buffer containing
2642 the contents of a .debug_frame section that describes the post-
2643 prologue unwind info for the tcg machine.
2644
2645 (3) Call tcg_register_jit_int, with the constructed .debug_frame.
2646*/
813da627
RH		 2647
2648/* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */
2649typedef enum {
2650 JIT_NOACTION = 0,
2651 JIT_REGISTER_FN,
2652 JIT_UNREGISTER_FN
2653} jit_actions_t;
2654
2655struct jit_code_entry {
2656 struct jit_code_entry *next_entry;
2657 struct jit_code_entry *prev_entry;
2658 const void *symfile_addr;
2659 uint64_t symfile_size;
2660};
2661
2662struct jit_descriptor {
2663 uint32_t version;
2664 uint32_t action_flag;
2665 struct jit_code_entry *relevant_entry;
2666 struct jit_code_entry *first_entry;
2667};
2668
2669void __jit_debug_register_code(void) __attribute__((noinline));
2670void __jit_debug_register_code(void)
2671{
2672 asm("");
2673}
2674
2675/* Must statically initialize the version, because GDB may check
2676 the version before we can set it. */
2677struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 };
2678
2679/* End GDB interface. */
2680
2681static int find_string(const char *strtab, const char *str)
2682{
2683 const char *p = strtab + 1;
2684
2685 while (1) {
2686 if (strcmp(p, str) == 0) {
2687 return p - strtab;
2688 }
2689 p += strlen(p) + 1;
2690 }
2691}
2692
5872bbf2 2693static void tcg_register_jit_int(void *buf_ptr, size_t buf_size,
2c90784a
RH		 2694 const void *debug_frame,
2695 size_t debug_frame_size)
813da627 2696{
5872bbf2
RH		 2697 struct __attribute__((packed)) DebugInfo {
2698 uint32_t len;
2699 uint16_t version;
2700 uint32_t abbrev;
2701 uint8_t ptr_size;
2702 uint8_t cu_die;
2703 uint16_t cu_lang;
2704 uintptr_t cu_low_pc;
2705 uintptr_t cu_high_pc;
2706 uint8_t fn_die;
2707 char fn_name[16];
2708 uintptr_t fn_low_pc;
2709 uintptr_t fn_high_pc;
2710 uint8_t cu_eoc;
2711 };
813da627
RH		 2712
2713 struct ElfImage {
2714 ElfW(Ehdr) ehdr;
2715 ElfW(Phdr) phdr;
5872bbf2
RH		 2716 ElfW(Shdr) shdr[7];
2717 ElfW(Sym) sym[2];
2718 struct DebugInfo di;
2719 uint8_t da[24];
2720 char str[80];
2721 };
2722
2723 struct ElfImage *img;
2724
2725 static const struct ElfImage img_template = {
2726 .ehdr = {
2727 .e_ident[EI_MAG0] = ELFMAG0,
2728 .e_ident[EI_MAG1] = ELFMAG1,
2729 .e_ident[EI_MAG2] = ELFMAG2,
2730 .e_ident[EI_MAG3] = ELFMAG3,
2731 .e_ident[EI_CLASS] = ELF_CLASS,
2732 .e_ident[EI_DATA] = ELF_DATA,
2733 .e_ident[EI_VERSION] = EV_CURRENT,
2734 .e_type = ET_EXEC,
2735 .e_machine = ELF_HOST_MACHINE,
2736 .e_version = EV_CURRENT,
2737 .e_phoff = offsetof(struct ElfImage, phdr),
2738 .e_shoff = offsetof(struct ElfImage, shdr),
2739 .e_ehsize = sizeof(ElfW(Shdr)),
2740 .e_phentsize = sizeof(ElfW(Phdr)),
2741 .e_phnum = 1,
2742 .e_shentsize = sizeof(ElfW(Shdr)),
2743 .e_shnum = ARRAY_SIZE(img->shdr),
2744 .e_shstrndx = ARRAY_SIZE(img->shdr) - 1,
abbb3eae
RH		 2745#ifdef ELF_HOST_FLAGS
2746 .e_flags = ELF_HOST_FLAGS,
2747#endif
2748#ifdef ELF_OSABI
2749 .e_ident[EI_OSABI] = ELF_OSABI,
2750#endif
5872bbf2
RH		 2751 },
2752 .phdr = {
2753 .p_type = PT_LOAD,
2754 .p_flags = PF_X,
2755 },
2756 .shdr = {
2757 [0] = { .sh_type = SHT_NULL },
2758 /* Trick: The contents of code_gen_buffer are not present in
2759 this fake ELF file; that got allocated elsewhere. Therefore
2760 we mark .text as SHT_NOBITS (similar to .bss) so that readers
2761 will not look for contents. We can record any address. */
2762 [1] = { /* .text */
2763 .sh_type = SHT_NOBITS,
2764 .sh_flags = SHF_EXECINSTR | SHF_ALLOC,
2765 },
2766 [2] = { /* .debug_info */
2767 .sh_type = SHT_PROGBITS,
2768 .sh_offset = offsetof(struct ElfImage, di),
2769 .sh_size = sizeof(struct DebugInfo),
2770 },
2771 [3] = { /* .debug_abbrev */
2772 .sh_type = SHT_PROGBITS,
2773 .sh_offset = offsetof(struct ElfImage, da),
2774 .sh_size = sizeof(img->da),
2775 },
2776 [4] = { /* .debug_frame */
2777 .sh_type = SHT_PROGBITS,
2778 .sh_offset = sizeof(struct ElfImage),
2779 },
2780 [5] = { /* .symtab */
2781 .sh_type = SHT_SYMTAB,
2782 .sh_offset = offsetof(struct ElfImage, sym),
2783 .sh_size = sizeof(img->sym),
2784 .sh_info = 1,
2785 .sh_link = ARRAY_SIZE(img->shdr) - 1,
2786 .sh_entsize = sizeof(ElfW(Sym)),
2787 },
2788 [6] = { /* .strtab */
2789 .sh_type = SHT_STRTAB,
2790 .sh_offset = offsetof(struct ElfImage, str),
2791 .sh_size = sizeof(img->str),
2792 }
2793 },
2794 .sym = {
2795 [1] = { /* code_gen_buffer */
2796 .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC),
2797 .st_shndx = 1,
2798 }
2799 },
2800 .di = {
2801 .len = sizeof(struct DebugInfo) - 4,
2802 .version = 2,
2803 .ptr_size = sizeof(void *),
2804 .cu_die = 1,
2805 .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */
2806 .fn_die = 2,
2807 .fn_name = "code_gen_buffer"
2808 },
2809 .da = {
2810 1, /* abbrev number (the cu) */
2811 0x11, 1, /* DW_TAG_compile_unit, has children */
2812 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */
2813 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2814 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2815 0, 0, /* end of abbrev */
2816 2, /* abbrev number (the fn) */
2817 0x2e, 0, /* DW_TAG_subprogram, no children */
2818 0x3, 0x8, /* DW_AT_name, DW_FORM_string */
2819 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2820 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2821 0, 0, /* end of abbrev */
2822 0 /* no more abbrev */
2823 },
2824 .str = "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0"
2825 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer",
813da627
RH		 2826 };
2827
2828 /* We only need a single jit entry; statically allocate it. */
2829 static struct jit_code_entry one_entry;
2830
5872bbf2 2831 uintptr_t buf = (uintptr_t)buf_ptr;
813da627 2832 size_t img_size = sizeof(struct ElfImage) + debug_frame_size;
2c90784a 2833 DebugFrameHeader *dfh;
813da627 2834
5872bbf2
RH		 2835 img = g_malloc(img_size);
2836 *img = img_template;
813da627 2837
5872bbf2
RH		 2838 img->phdr.p_vaddr = buf;
2839 img->phdr.p_paddr = buf;
2840 img->phdr.p_memsz = buf_size;
813da627 2841
813da627 2842 img->shdr[1].sh_name = find_string(img->str, ".text");
5872bbf2 2843 img->shdr[1].sh_addr = buf;
813da627
RH		 2844 img->shdr[1].sh_size = buf_size;
2845
5872bbf2
RH		 2846 img->shdr[2].sh_name = find_string(img->str, ".debug_info");
2847 img->shdr[3].sh_name = find_string(img->str, ".debug_abbrev");
2848
2849 img->shdr[4].sh_name = find_string(img->str, ".debug_frame");
2850 img->shdr[4].sh_size = debug_frame_size;
2851
2852 img->shdr[5].sh_name = find_string(img->str, ".symtab");
2853 img->shdr[6].sh_name = find_string(img->str, ".strtab");
2854
2855 img->sym[1].st_name = find_string(img->str, "code_gen_buffer");
2856 img->sym[1].st_value = buf;
2857 img->sym[1].st_size = buf_size;
813da627 2858
5872bbf2 2859 img->di.cu_low_pc = buf;
45aba097 2860 img->di.cu_high_pc = buf + buf_size;
5872bbf2 2861 img->di.fn_low_pc = buf;
45aba097 2862 img->di.fn_high_pc = buf + buf_size;
813da627 2863
2c90784a
RH		 2864 dfh = (DebugFrameHeader *)(img + 1);
2865 memcpy(dfh, debug_frame, debug_frame_size);
2866 dfh->fde.func_start = buf;
2867 dfh->fde.func_len = buf_size;
2868
813da627
RH		 2869#ifdef DEBUG_JIT
2870 /* Enable this block to be able to debug the ELF image file creation.
2871 One can use readelf, objdump, or other inspection utilities. */
2872 {
2873 FILE *f = fopen("/tmp/qemu.jit", "w+b");
2874 if (f) {
5872bbf2 2875 if (fwrite(img, img_size, 1, f) != img_size) {
813da627
RH		 2876 /* Avoid stupid unused return value warning for fwrite. */
2877 }
2878 fclose(f);
2879 }
2880 }
2881#endif
2882
2883 one_entry.symfile_addr = img;
2884 one_entry.symfile_size = img_size;
2885
2886 __jit_debug_descriptor.action_flag = JIT_REGISTER_FN;
2887 __jit_debug_descriptor.relevant_entry = &one_entry;
2888 __jit_debug_descriptor.first_entry = &one_entry;
2889 __jit_debug_register_code();
2890}
2891#else
5872bbf2
RH		 2892/* No support for the feature. Provide the entry point expected by exec.c,
2893 and implement the internal function we declared earlier. */
813da627
RH		 2894
2895static void tcg_register_jit_int(void *buf, size_t size,
2c90784a
RH		 2896 const void *debug_frame,
2897 size_t debug_frame_size)
813da627
RH		 2898{
2899}
2900
2901void tcg_register_jit(void *buf, size_t buf_size)
2902{
2903}
2904#endif /* ELF_HOST_MACHINE */
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