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target-i386/helper: remove EDI macro
[qemu.git] / target-i386 / seg_helper.c
CommitLineData
eaa728ee 1/*
10774999
BS		 2 * x86 segmentation related helpers:
3 * TSS, interrupts, system calls, jumps and call/task gates, descriptors
eaa728ee
FB		 4 *
5 * Copyright (c) 2003 Fabrice Bellard
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
eaa728ee 19 */
83dae095 20
3e457172 21#include "cpu.h"
1de7afc9 22#include "qemu/log.h"
3e457172 23#include "helper.h"
eaa728ee 24
3e457172 25//#define DEBUG_PCALL
d12d51d5 26
92fc4b58 27#if !defined(CONFIG_USER_ONLY)
022c62cb 28#include "exec/softmmu_exec.h"
92fc4b58
BS		 29#endif /* !defined(CONFIG_USER_ONLY) */
30
d12d51d5 31#ifdef DEBUG_PCALL
20054ef0
BS		 32# define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__)
33# define LOG_PCALL_STATE(env) \
6fd2a026 34 log_cpu_state_mask(CPU_LOG_PCALL, (env), CPU_DUMP_CCOP)
d12d51d5 35#else
20054ef0
BS		 36# define LOG_PCALL(...) do { } while (0)
37# define LOG_PCALL_STATE(env) do { } while (0)
d12d51d5
AL		 38#endif
39
eaa728ee 40/* return non zero if error */
2999a0b2
BS		 41static inline int load_segment(CPUX86State *env, uint32_t *e1_ptr,
42 uint32_t *e2_ptr, int selector)
eaa728ee
FB		 43{
44 SegmentCache *dt;
45 int index;
46 target_ulong ptr;
47
20054ef0 48 if (selector & 0x4) {
eaa728ee 49 dt = &env->ldt;
20054ef0 50 } else {
eaa728ee 51 dt = &env->gdt;
20054ef0 52 }
eaa728ee 53 index = selector & ~7;
20054ef0 54 if ((index + 7) > dt->limit) {
eaa728ee 55 return -1;
20054ef0 56 }
eaa728ee 57 ptr = dt->base + index;
329e607d
BS		 58 *e1_ptr = cpu_ldl_kernel(env, ptr);
59 *e2_ptr = cpu_ldl_kernel(env, ptr + 4);
eaa728ee
FB		 60 return 0;
61}
62
63static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
64{
65 unsigned int limit;
20054ef0 66
eaa728ee 67 limit = (e1 & 0xffff) | (e2 & 0x000f0000);
20054ef0 68 if (e2 & DESC_G_MASK) {
eaa728ee 69 limit = (limit << 12) | 0xfff;
20054ef0 70 }
eaa728ee
FB		 71 return limit;
72}
73
74static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
75{
20054ef0 76 return (e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000);
eaa728ee
FB		 77}
78
20054ef0
BS		 79static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1,
80 uint32_t e2)
eaa728ee
FB		 81{
82 sc->base = get_seg_base(e1, e2);
83 sc->limit = get_seg_limit(e1, e2);
84 sc->flags = e2;
85}
86
87/* init the segment cache in vm86 mode. */
2999a0b2 88static inline void load_seg_vm(CPUX86State *env, int seg, int selector)
eaa728ee
FB		 89{
90 selector &= 0xffff;
91 cpu_x86_load_seg_cache(env, seg, selector,
92 (selector << 4), 0xffff, 0);
93}
94
2999a0b2 95static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr,
eaa728ee
FB		 96 uint32_t *esp_ptr, int dpl)
97{
98 int type, index, shift;
99
100#if 0
101 {
102 int i;
103 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
20054ef0 104 for (i = 0; i < env->tr.limit; i++) {
eaa728ee 105 printf("%02x ", env->tr.base[i]);
20054ef0
BS		 106 if ((i & 7) == 7) {
107 printf("\n");
108 }
eaa728ee
FB		 109 }
110 printf("\n");
111 }
112#endif
113
20054ef0 114 if (!(env->tr.flags & DESC_P_MASK)) {
eaa728ee 115 cpu_abort(env, "invalid tss");
20054ef0 116 }
eaa728ee 117 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
20054ef0 118 if ((type & 7) != 1) {
eaa728ee 119 cpu_abort(env, "invalid tss type");
20054ef0 120 }
eaa728ee
FB		 121 shift = type >> 3;
122 index = (dpl * 4 + 2) << shift;
20054ef0 123 if (index + (4 << shift) - 1 > env->tr.limit) {
77b2bc2c 124 raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
20054ef0 125 }
eaa728ee 126 if (shift == 0) {
329e607d
BS		 127 *esp_ptr = cpu_lduw_kernel(env, env->tr.base + index);
128 *ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 2);
eaa728ee 129 } else {
329e607d
BS		 130 *esp_ptr = cpu_ldl_kernel(env, env->tr.base + index);
131 *ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 4);
eaa728ee
FB		 132 }
133}
134
135/* XXX: merge with load_seg() */
2999a0b2 136static void tss_load_seg(CPUX86State *env, int seg_reg, int selector)
eaa728ee
FB		 137{
138 uint32_t e1, e2;
139 int rpl, dpl, cpl;
140
141 if ((selector & 0xfffc) != 0) {
2999a0b2 142 if (load_segment(env, &e1, &e2, selector) != 0) {
77b2bc2c 143 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
20054ef0
BS		 144 }
145 if (!(e2 & DESC_S_MASK)) {
77b2bc2c 146 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
20054ef0 147 }
eaa728ee
FB		 148 rpl = selector & 3;
149 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
150 cpl = env->hflags & HF_CPL_MASK;
151 if (seg_reg == R_CS) {
20054ef0 152 if (!(e2 & DESC_CS_MASK)) {
77b2bc2c 153 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
20054ef0
BS		 154 }
155 /* XXX: is it correct? */
156 if (dpl != rpl) {
77b2bc2c 157 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
20054ef0
BS		 158 }
159 if ((e2 & DESC_C_MASK) && dpl > rpl) {
77b2bc2c 160 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
20054ef0 161 }
eaa728ee
FB		 162 } else if (seg_reg == R_SS) {
163 /* SS must be writable data */
20054ef0 164 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
77b2bc2c 165 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
20054ef0
BS		 166 }
167 if (dpl != cpl || dpl != rpl) {
77b2bc2c 168 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
20054ef0 169 }
eaa728ee
FB		 170 } else {
171 /* not readable code */
20054ef0 172 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK)) {
77b2bc2c 173 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
20054ef0 174 }
eaa728ee
FB		 175 /* if data or non conforming code, checks the rights */
176 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
20054ef0 177 if (dpl < cpl || dpl < rpl) {
77b2bc2c 178 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
20054ef0 179 }
eaa728ee
FB		 180 }
181 }
20054ef0 182 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 183 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
20054ef0 184 }
eaa728ee 185 cpu_x86_load_seg_cache(env, seg_reg, selector,
20054ef0
BS		 186 get_seg_base(e1, e2),
187 get_seg_limit(e1, e2),
188 e2);
eaa728ee 189 } else {
20054ef0 190 if (seg_reg == R_SS || seg_reg == R_CS) {
77b2bc2c 191 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
20054ef0 192 }
eaa728ee
FB		 193 }
194}
195
196#define SWITCH_TSS_JMP 0
197#define SWITCH_TSS_IRET 1
198#define SWITCH_TSS_CALL 2
199
200/* XXX: restore CPU state in registers (PowerPC case) */
2999a0b2 201static void switch_tss(CPUX86State *env, int tss_selector,
eaa728ee
FB		 202 uint32_t e1, uint32_t e2, int source,
203 uint32_t next_eip)
204{
205 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
206 target_ulong tss_base;
207 uint32_t new_regs[8], new_segs[6];
208 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
209 uint32_t old_eflags, eflags_mask;
210 SegmentCache *dt;
211 int index;
212 target_ulong ptr;
213
214 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
20054ef0
BS		 215 LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type,
216 source);
eaa728ee
FB		 217
218 /* if task gate, we read the TSS segment and we load it */
219 if (type == 5) {
20054ef0 220 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 221 raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
20054ef0 222 }
eaa728ee 223 tss_selector = e1 >> 16;
20054ef0 224 if (tss_selector & 4) {
77b2bc2c 225 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
20054ef0 226 }
2999a0b2 227 if (load_segment(env, &e1, &e2, tss_selector) != 0) {
77b2bc2c 228 raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
20054ef0
BS		 229 }
230 if (e2 & DESC_S_MASK) {
77b2bc2c 231 raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
20054ef0 232 }
eaa728ee 233 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
20054ef0 234 if ((type & 7) != 1) {
77b2bc2c 235 raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
20054ef0 236 }
eaa728ee
FB		 237 }
238
20054ef0 239 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 240 raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
20054ef0 241 }
eaa728ee 242
20054ef0 243 if (type & 8) {
eaa728ee 244 tss_limit_max = 103;
20054ef0 245 } else {
eaa728ee 246 tss_limit_max = 43;
20054ef0 247 }
eaa728ee
FB		 248 tss_limit = get_seg_limit(e1, e2);
249 tss_base = get_seg_base(e1, e2);
250 if ((tss_selector & 4) != 0 ||
20054ef0 251 tss_limit < tss_limit_max) {
77b2bc2c 252 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
20054ef0 253 }
eaa728ee 254 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
20054ef0 255 if (old_type & 8) {
eaa728ee 256 old_tss_limit_max = 103;
20054ef0 257 } else {
eaa728ee 258 old_tss_limit_max = 43;
20054ef0 259 }
eaa728ee
FB		 260
261 /* read all the registers from the new TSS */
262 if (type & 8) {
263 /* 32 bit */
329e607d
BS		 264 new_cr3 = cpu_ldl_kernel(env, tss_base + 0x1c);
265 new_eip = cpu_ldl_kernel(env, tss_base + 0x20);
266 new_eflags = cpu_ldl_kernel(env, tss_base + 0x24);
20054ef0 267 for (i = 0; i < 8; i++) {
329e607d 268 new_regs[i] = cpu_ldl_kernel(env, tss_base + (0x28 + i * 4));
20054ef0
BS		 269 }
270 for (i = 0; i < 6; i++) {
329e607d 271 new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x48 + i * 4));
20054ef0 272 }
329e607d
BS		 273 new_ldt = cpu_lduw_kernel(env, tss_base + 0x60);
274 new_trap = cpu_ldl_kernel(env, tss_base + 0x64);
eaa728ee
FB		 275 } else {
276 /* 16 bit */
277 new_cr3 = 0;
329e607d
BS		 278 new_eip = cpu_lduw_kernel(env, tss_base + 0x0e);
279 new_eflags = cpu_lduw_kernel(env, tss_base + 0x10);
20054ef0 280 for (i = 0; i < 8; i++) {
329e607d
BS		 281 new_regs[i] = cpu_lduw_kernel(env, tss_base + (0x12 + i * 2)) |
282 0xffff0000;
20054ef0
BS		 283 }
284 for (i = 0; i < 4; i++) {
329e607d 285 new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x22 + i * 4));
20054ef0 286 }
329e607d 287 new_ldt = cpu_lduw_kernel(env, tss_base + 0x2a);
eaa728ee
FB		 288 new_segs[R_FS] = 0;
289 new_segs[R_GS] = 0;
290 new_trap = 0;
291 }
4581cbcd
BS		 292 /* XXX: avoid a compiler warning, see
293 http://support.amd.com/us/Processor_TechDocs/24593.pdf
294 chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */
295 (void)new_trap;
eaa728ee
FB		 296
297 /* NOTE: we must avoid memory exceptions during the task switch,
298 so we make dummy accesses before */
299 /* XXX: it can still fail in some cases, so a bigger hack is
300 necessary to valid the TLB after having done the accesses */
301
329e607d
BS		 302 v1 = cpu_ldub_kernel(env, env->tr.base);
303 v2 = cpu_ldub_kernel(env, env->tr.base + old_tss_limit_max);
304 cpu_stb_kernel(env, env->tr.base, v1);
305 cpu_stb_kernel(env, env->tr.base + old_tss_limit_max, v2);
eaa728ee
FB		 306
307 /* clear busy bit (it is restartable) */
308 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
309 target_ulong ptr;
310 uint32_t e2;
20054ef0 311
eaa728ee 312 ptr = env->gdt.base + (env->tr.selector & ~7);
329e607d 313 e2 = cpu_ldl_kernel(env, ptr + 4);
eaa728ee 314 e2 &= ~DESC_TSS_BUSY_MASK;
329e607d 315 cpu_stl_kernel(env, ptr + 4, e2);
eaa728ee 316 }
997ff0d9 317 old_eflags = cpu_compute_eflags(env);
20054ef0 318 if (source == SWITCH_TSS_IRET) {
eaa728ee 319 old_eflags &= ~NT_MASK;
20054ef0 320 }
eaa728ee
FB		 321
322 /* save the current state in the old TSS */
323 if (type & 8) {
324 /* 32 bit */
329e607d
BS		 325 cpu_stl_kernel(env, env->tr.base + 0x20, next_eip);
326 cpu_stl_kernel(env, env->tr.base + 0x24, old_eflags);
4b34e3ad 327 cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX]);
a4165610 328 cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]);
00f5e6f2 329 cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX]);
70b51365 330 cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]);
08b3ded6 331 cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), env->regs[R_ESP]);
c12dddd7 332 cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP]);
78c3c6d3 333 cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), env->regs[R_ESI]);
cf75c597 334 cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), env->regs[R_EDI]);
20054ef0 335 for (i = 0; i < 6; i++) {
329e607d
BS		 336 cpu_stw_kernel(env, env->tr.base + (0x48 + i * 4),
337 env->segs[i].selector);
20054ef0 338 }
eaa728ee
FB		 339 } else {
340 /* 16 bit */
329e607d
BS		 341 cpu_stw_kernel(env, env->tr.base + 0x0e, next_eip);
342 cpu_stw_kernel(env, env->tr.base + 0x10, old_eflags);
4b34e3ad 343 cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX]);
a4165610 344 cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]);
00f5e6f2 345 cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX]);
70b51365 346 cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]);
08b3ded6 347 cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), env->regs[R_ESP]);
c12dddd7 348 cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP]);
78c3c6d3 349 cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), env->regs[R_ESI]);
cf75c597 350 cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), env->regs[R_EDI]);
20054ef0 351 for (i = 0; i < 4; i++) {
329e607d
BS		 352 cpu_stw_kernel(env, env->tr.base + (0x22 + i * 4),
353 env->segs[i].selector);
20054ef0 354 }
eaa728ee
FB		 355 }
356
357 /* now if an exception occurs, it will occurs in the next task
358 context */
359
360 if (source == SWITCH_TSS_CALL) {
329e607d 361 cpu_stw_kernel(env, tss_base, env->tr.selector);
eaa728ee
FB		 362 new_eflags |= NT_MASK;
363 }
364
365 /* set busy bit */
366 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
367 target_ulong ptr;
368 uint32_t e2;
20054ef0 369
eaa728ee 370 ptr = env->gdt.base + (tss_selector & ~7);
329e607d 371 e2 = cpu_ldl_kernel(env, ptr + 4);
eaa728ee 372 e2 |= DESC_TSS_BUSY_MASK;
329e607d 373 cpu_stl_kernel(env, ptr + 4, e2);
eaa728ee
FB		 374 }
375
376 /* set the new CPU state */
377 /* from this point, any exception which occurs can give problems */
378 env->cr[0] |= CR0_TS_MASK;
379 env->hflags |= HF_TS_MASK;
380 env->tr.selector = tss_selector;
381 env->tr.base = tss_base;
382 env->tr.limit = tss_limit;
383 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
384
385 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
386 cpu_x86_update_cr3(env, new_cr3);
387 }
388
389 /* load all registers without an exception, then reload them with
390 possible exception */
391 env->eip = new_eip;
392 eflags_mask = TF_MASK | AC_MASK | ID_MASK |
393 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
20054ef0 394 if (!(type & 8)) {
eaa728ee 395 eflags_mask &= 0xffff;
20054ef0 396 }
997ff0d9 397 cpu_load_eflags(env, new_eflags, eflags_mask);
20054ef0 398 /* XXX: what to do in 16 bit case? */
4b34e3ad 399 env->regs[R_EAX] = new_regs[0];
a4165610 400 env->regs[R_ECX] = new_regs[1];
00f5e6f2 401 env->regs[R_EDX] = new_regs[2];
70b51365 402 env->regs[R_EBX] = new_regs[3];
08b3ded6 403 env->regs[R_ESP] = new_regs[4];
c12dddd7 404 env->regs[R_EBP] = new_regs[5];
78c3c6d3 405 env->regs[R_ESI] = new_regs[6];
cf75c597 406 env->regs[R_EDI] = new_regs[7];
eaa728ee 407 if (new_eflags & VM_MASK) {
20054ef0 408 for (i = 0; i < 6; i++) {
2999a0b2 409 load_seg_vm(env, i, new_segs[i]);
20054ef0 410 }
eaa728ee
FB		 411 /* in vm86, CPL is always 3 */
412 cpu_x86_set_cpl(env, 3);
413 } else {
414 /* CPL is set the RPL of CS */
415 cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
416 /* first just selectors as the rest may trigger exceptions */
20054ef0 417 for (i = 0; i < 6; i++) {
eaa728ee 418 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
20054ef0 419 }
eaa728ee
FB		 420 }
421
422 env->ldt.selector = new_ldt & ~4;
423 env->ldt.base = 0;
424 env->ldt.limit = 0;
425 env->ldt.flags = 0;
426
427 /* load the LDT */
20054ef0 428 if (new_ldt & 4) {
77b2bc2c 429 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
20054ef0 430 }
eaa728ee
FB		 431
432 if ((new_ldt & 0xfffc) != 0) {
433 dt = &env->gdt;
434 index = new_ldt & ~7;
20054ef0 435 if ((index + 7) > dt->limit) {
77b2bc2c 436 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
20054ef0 437 }
eaa728ee 438 ptr = dt->base + index;
329e607d
BS		 439 e1 = cpu_ldl_kernel(env, ptr);
440 e2 = cpu_ldl_kernel(env, ptr + 4);
20054ef0 441 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
77b2bc2c 442 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
20054ef0
BS		 443 }
444 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 445 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
20054ef0 446 }
eaa728ee
FB		 447 load_seg_cache_raw_dt(&env->ldt, e1, e2);
448 }
449
450 /* load the segments */
451 if (!(new_eflags & VM_MASK)) {
2999a0b2
BS		 452 tss_load_seg(env, R_CS, new_segs[R_CS]);
453 tss_load_seg(env, R_SS, new_segs[R_SS]);
454 tss_load_seg(env, R_ES, new_segs[R_ES]);
455 tss_load_seg(env, R_DS, new_segs[R_DS]);
456 tss_load_seg(env, R_FS, new_segs[R_FS]);
457 tss_load_seg(env, R_GS, new_segs[R_GS]);
eaa728ee
FB		 458 }
459
460 /* check that EIP is in the CS segment limits */
461 if (new_eip > env->segs[R_CS].limit) {
20054ef0 462 /* XXX: different exception if CALL? */
77b2bc2c 463 raise_exception_err(env, EXCP0D_GPF, 0);
eaa728ee 464 }
01df040b
AL		 465
466#ifndef CONFIG_USER_ONLY
467 /* reset local breakpoints */
428065ce
LG		 468 if (env->dr[7] & DR7_LOCAL_BP_MASK) {
469 for (i = 0; i < DR7_MAX_BP; i++) {
5902564a
LG		 470 if (hw_local_breakpoint_enabled(env->dr[7], i) &&
471 !hw_global_breakpoint_enabled(env->dr[7], i)) {
01df040b 472 hw_breakpoint_remove(env, i);
20054ef0 473 }
01df040b 474 }
428065ce 475 env->dr[7] &= ~DR7_LOCAL_BP_MASK;
01df040b
AL		 476 }
477#endif
eaa728ee
FB		 478}
479
eaa728ee
FB		 480static inline unsigned int get_sp_mask(unsigned int e2)
481{
20054ef0 482 if (e2 & DESC_B_MASK) {
eaa728ee 483 return 0xffffffff;
20054ef0 484 } else {
eaa728ee 485 return 0xffff;
20054ef0 486 }
eaa728ee
FB		 487}
488
20054ef0 489static int exception_has_error_code(int intno)
2ed51f5b 490{
20054ef0
BS		 491 switch (intno) {
492 case 8:
493 case 10:
494 case 11:
495 case 12:
496 case 13:
497 case 14:
498 case 17:
499 return 1;
500 }
501 return 0;
2ed51f5b
AL		 502}
503
eaa728ee 504#ifdef TARGET_X86_64
08b3ded6
LG		 505#define SET_ESP(val, sp_mask) \
506 do { \
507 if ((sp_mask) == 0xffff) { \
508 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | \
509 ((val) & 0xffff); \
510 } else if ((sp_mask) == 0xffffffffLL) { \
511 env->regs[R_ESP] = (uint32_t)(val); \
512 } else { \
513 env->regs[R_ESP] = (val); \
514 } \
20054ef0 515 } while (0)
eaa728ee 516#else
08b3ded6
LG		 517#define SET_ESP(val, sp_mask) \
518 do { \
519 env->regs[R_ESP] = (env->regs[R_ESP] & ~(sp_mask)) | \
520 ((val) & (sp_mask)); \
20054ef0 521 } while (0)
eaa728ee
FB		 522#endif
523
c0a04f0e
AL		 524/* in 64-bit machines, this can overflow. So this segment addition macro
525 * can be used to trim the value to 32-bit whenever needed */
526#define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask))))
527
eaa728ee 528/* XXX: add a is_user flag to have proper security support */
329e607d
BS		 529#define PUSHW(ssp, sp, sp_mask, val) \
530 { \
531 sp -= 2; \
532 cpu_stw_kernel(env, (ssp) + (sp & (sp_mask)), (val)); \
20054ef0 533 }
eaa728ee 534
20054ef0
BS		 535#define PUSHL(ssp, sp, sp_mask, val) \
536 { \
537 sp -= 4; \
329e607d 538 cpu_stl_kernel(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val)); \
20054ef0 539 }
eaa728ee 540
329e607d
BS		 541#define POPW(ssp, sp, sp_mask, val) \
542 { \
543 val = cpu_lduw_kernel(env, (ssp) + (sp & (sp_mask))); \
544 sp += 2; \
20054ef0 545 }
eaa728ee 546
329e607d
BS		 547#define POPL(ssp, sp, sp_mask, val) \
548 { \
549 val = (uint32_t)cpu_ldl_kernel(env, SEG_ADDL(ssp, sp, sp_mask)); \
550 sp += 4; \
20054ef0 551 }
eaa728ee
FB		 552
553/* protected mode interrupt */
2999a0b2
BS		 554static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
555 int error_code, unsigned int next_eip,
556 int is_hw)
eaa728ee
FB		 557{
558 SegmentCache *dt;
559 target_ulong ptr, ssp;
560 int type, dpl, selector, ss_dpl, cpl;
561 int has_error_code, new_stack, shift;
1c918eba 562 uint32_t e1, e2, offset, ss = 0, esp, ss_e1 = 0, ss_e2 = 0;
eaa728ee 563 uint32_t old_eip, sp_mask;
eaa728ee 564
eaa728ee 565 has_error_code = 0;
20054ef0
BS		 566 if (!is_int && !is_hw) {
567 has_error_code = exception_has_error_code(intno);
568 }
569 if (is_int) {
eaa728ee 570 old_eip = next_eip;
20054ef0 571 } else {
eaa728ee 572 old_eip = env->eip;
20054ef0 573 }
eaa728ee
FB		 574
575 dt = &env->idt;
20054ef0 576 if (intno * 8 + 7 > dt->limit) {
77b2bc2c 577 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
20054ef0 578 }
eaa728ee 579 ptr = dt->base + intno * 8;
329e607d
BS		 580 e1 = cpu_ldl_kernel(env, ptr);
581 e2 = cpu_ldl_kernel(env, ptr + 4);
eaa728ee
FB		 582 /* check gate type */
583 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
20054ef0 584 switch (type) {
eaa728ee
FB		 585 case 5: /* task gate */
586 /* must do that check here to return the correct error code */
20054ef0 587 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 588 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
20054ef0 589 }
2999a0b2 590 switch_tss(env, intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
eaa728ee
FB		 591 if (has_error_code) {
592 int type;
593 uint32_t mask;
20054ef0 594
eaa728ee
FB		 595 /* push the error code */
596 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
597 shift = type >> 3;
20054ef0 598 if (env->segs[R_SS].flags & DESC_B_MASK) {
eaa728ee 599 mask = 0xffffffff;
20054ef0 600 } else {
eaa728ee 601 mask = 0xffff;
20054ef0 602 }
08b3ded6 603 esp = (env->regs[R_ESP] - (2 << shift)) & mask;
eaa728ee 604 ssp = env->segs[R_SS].base + esp;
20054ef0 605 if (shift) {
329e607d 606 cpu_stl_kernel(env, ssp, error_code);
20054ef0 607 } else {
329e607d 608 cpu_stw_kernel(env, ssp, error_code);
20054ef0 609 }
eaa728ee
FB		 610 SET_ESP(esp, mask);
611 }
612 return;
613 case 6: /* 286 interrupt gate */
614 case 7: /* 286 trap gate */
615 case 14: /* 386 interrupt gate */
616 case 15: /* 386 trap gate */
617 break;
618 default:
77b2bc2c 619 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
eaa728ee
FB		 620 break;
621 }
622 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
623 cpl = env->hflags & HF_CPL_MASK;
1235fc06 624 /* check privilege if software int */
20054ef0 625 if (is_int && dpl < cpl) {
77b2bc2c 626 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
20054ef0 627 }
eaa728ee 628 /* check valid bit */
20054ef0 629 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 630 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
20054ef0 631 }
eaa728ee
FB		 632 selector = e1 >> 16;
633 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
20054ef0 634 if ((selector & 0xfffc) == 0) {
77b2bc2c 635 raise_exception_err(env, EXCP0D_GPF, 0);
20054ef0 636 }
2999a0b2 637 if (load_segment(env, &e1, &e2, selector) != 0) {
77b2bc2c 638 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0
BS		 639 }
640 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
77b2bc2c 641 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 642 }
eaa728ee 643 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
20054ef0 644 if (dpl > cpl) {
77b2bc2c 645 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0
BS		 646 }
647 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 648 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
20054ef0 649 }
eaa728ee
FB		 650 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
651 /* to inner privilege */
2999a0b2 652 get_ss_esp_from_tss(env, &ss, &esp, dpl);
20054ef0 653 if ((ss & 0xfffc) == 0) {
77b2bc2c 654 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0
BS		 655 }
656 if ((ss & 3) != dpl) {
77b2bc2c 657 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0 658 }
2999a0b2 659 if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) {
77b2bc2c 660 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0 661 }
eaa728ee 662 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
20054ef0 663 if (ss_dpl != dpl) {
77b2bc2c 664 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0 665 }
eaa728ee
FB		 666 if (!(ss_e2 & DESC_S_MASK) ||
667 (ss_e2 & DESC_CS_MASK) ||
20054ef0 668 !(ss_e2 & DESC_W_MASK)) {
77b2bc2c 669 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0
BS		 670 }
671 if (!(ss_e2 & DESC_P_MASK)) {
77b2bc2c 672 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0 673 }
eaa728ee
FB		 674 new_stack = 1;
675 sp_mask = get_sp_mask(ss_e2);
676 ssp = get_seg_base(ss_e1, ss_e2);
677 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
678 /* to same privilege */
20054ef0 679 if (env->eflags & VM_MASK) {
77b2bc2c 680 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 681 }
eaa728ee
FB		 682 new_stack = 0;
683 sp_mask = get_sp_mask(env->segs[R_SS].flags);
684 ssp = env->segs[R_SS].base;
08b3ded6 685 esp = env->regs[R_ESP];
eaa728ee
FB		 686 dpl = cpl;
687 } else {
77b2bc2c 688 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
eaa728ee
FB		 689 new_stack = 0; /* avoid warning */
690 sp_mask = 0; /* avoid warning */
691 ssp = 0; /* avoid warning */
692 esp = 0; /* avoid warning */
693 }
694
695 shift = type >> 3;
696
697#if 0
698 /* XXX: check that enough room is available */
699 push_size = 6 + (new_stack << 2) + (has_error_code << 1);
20054ef0 700 if (env->eflags & VM_MASK) {
eaa728ee 701 push_size += 8;
20054ef0 702 }
eaa728ee
FB		 703 push_size <<= shift;
704#endif
705 if (shift == 1) {
706 if (new_stack) {
707 if (env->eflags & VM_MASK) {
708 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
709 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
710 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
711 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
712 }
713 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
08b3ded6 714 PUSHL(ssp, esp, sp_mask, env->regs[R_ESP]);
eaa728ee 715 }
997ff0d9 716 PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env));
eaa728ee
FB		 717 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
718 PUSHL(ssp, esp, sp_mask, old_eip);
719 if (has_error_code) {
720 PUSHL(ssp, esp, sp_mask, error_code);
721 }
722 } else {
723 if (new_stack) {
724 if (env->eflags & VM_MASK) {
725 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
726 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
727 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
728 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
729 }
730 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
08b3ded6 731 PUSHW(ssp, esp, sp_mask, env->regs[R_ESP]);
eaa728ee 732 }
997ff0d9 733 PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env));
eaa728ee
FB		 734 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
735 PUSHW(ssp, esp, sp_mask, old_eip);
736 if (has_error_code) {
737 PUSHW(ssp, esp, sp_mask, error_code);
738 }
739 }
740
741 if (new_stack) {
742 if (env->eflags & VM_MASK) {
743 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
744 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
745 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
746 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
747 }
748 ss = (ss & ~3) | dpl;
749 cpu_x86_load_seg_cache(env, R_SS, ss,
750 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
751 }
752 SET_ESP(esp, sp_mask);
753
754 selector = (selector & ~3) | dpl;
755 cpu_x86_load_seg_cache(env, R_CS, selector,
756 get_seg_base(e1, e2),
757 get_seg_limit(e1, e2),
758 e2);
759 cpu_x86_set_cpl(env, dpl);
760 env->eip = offset;
761
762 /* interrupt gate clear IF mask */
763 if ((type & 1) == 0) {
764 env->eflags &= ~IF_MASK;
765 }
766 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
767}
768
769#ifdef TARGET_X86_64
770
20054ef0
BS		 771#define PUSHQ(sp, val) \
772 { \
773 sp -= 8; \
329e607d 774 cpu_stq_kernel(env, sp, (val)); \
20054ef0 775 }
eaa728ee 776
20054ef0
BS		 777#define POPQ(sp, val) \
778 { \
329e607d 779 val = cpu_ldq_kernel(env, sp); \
20054ef0
BS		 780 sp += 8; \
781 }
eaa728ee 782
2999a0b2 783static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level)
eaa728ee
FB		 784{
785 int index;
786
787#if 0
788 printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
789 env->tr.base, env->tr.limit);
790#endif
791
20054ef0 792 if (!(env->tr.flags & DESC_P_MASK)) {
eaa728ee 793 cpu_abort(env, "invalid tss");
20054ef0 794 }
eaa728ee 795 index = 8 * level + 4;
20054ef0 796 if ((index + 7) > env->tr.limit) {
77b2bc2c 797 raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
20054ef0 798 }
329e607d 799 return cpu_ldq_kernel(env, env->tr.base + index);
eaa728ee
FB		 800}
801
802/* 64 bit interrupt */
2999a0b2
BS		 803static void do_interrupt64(CPUX86State *env, int intno, int is_int,
804 int error_code, target_ulong next_eip, int is_hw)
eaa728ee
FB		 805{
806 SegmentCache *dt;
807 target_ulong ptr;
808 int type, dpl, selector, cpl, ist;
809 int has_error_code, new_stack;
810 uint32_t e1, e2, e3, ss;
811 target_ulong old_eip, esp, offset;
eaa728ee 812
eaa728ee 813 has_error_code = 0;
20054ef0
BS		 814 if (!is_int && !is_hw) {
815 has_error_code = exception_has_error_code(intno);
816 }
817 if (is_int) {
eaa728ee 818 old_eip = next_eip;
20054ef0 819 } else {
eaa728ee 820 old_eip = env->eip;
20054ef0 821 }
eaa728ee
FB		 822
823 dt = &env->idt;
20054ef0 824 if (intno * 16 + 15 > dt->limit) {
77b2bc2c 825 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
20054ef0 826 }
eaa728ee 827 ptr = dt->base + intno * 16;
329e607d
BS		 828 e1 = cpu_ldl_kernel(env, ptr);
829 e2 = cpu_ldl_kernel(env, ptr + 4);
830 e3 = cpu_ldl_kernel(env, ptr + 8);
eaa728ee
FB		 831 /* check gate type */
832 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
20054ef0 833 switch (type) {
eaa728ee
FB		 834 case 14: /* 386 interrupt gate */
835 case 15: /* 386 trap gate */
836 break;
837 default:
77b2bc2c 838 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
eaa728ee
FB		 839 break;
840 }
841 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
842 cpl = env->hflags & HF_CPL_MASK;
1235fc06 843 /* check privilege if software int */
20054ef0 844 if (is_int && dpl < cpl) {
77b2bc2c 845 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
20054ef0 846 }
eaa728ee 847 /* check valid bit */
20054ef0 848 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 849 raise_exception_err(env, EXCP0B_NOSEG, intno * 16 + 2);
20054ef0 850 }
eaa728ee
FB		 851 selector = e1 >> 16;
852 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
853 ist = e2 & 7;
20054ef0 854 if ((selector & 0xfffc) == 0) {
77b2bc2c 855 raise_exception_err(env, EXCP0D_GPF, 0);
20054ef0 856 }
eaa728ee 857
2999a0b2 858 if (load_segment(env, &e1, &e2, selector) != 0) {
77b2bc2c 859 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0
BS		 860 }
861 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
77b2bc2c 862 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 863 }
eaa728ee 864 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
20054ef0 865 if (dpl > cpl) {
77b2bc2c 866 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0
BS		 867 }
868 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 869 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
20054ef0
BS		 870 }
871 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK)) {
77b2bc2c 872 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 873 }
eaa728ee
FB		 874 if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) {
875 /* to inner privilege */
20054ef0 876 if (ist != 0) {
2999a0b2 877 esp = get_rsp_from_tss(env, ist + 3);
20054ef0 878 } else {
2999a0b2 879 esp = get_rsp_from_tss(env, dpl);
20054ef0 880 }
eaa728ee
FB		 881 esp &= ~0xfLL; /* align stack */
882 ss = 0;
883 new_stack = 1;
884 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
885 /* to same privilege */
20054ef0 886 if (env->eflags & VM_MASK) {
77b2bc2c 887 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 888 }
eaa728ee 889 new_stack = 0;
20054ef0 890 if (ist != 0) {
2999a0b2 891 esp = get_rsp_from_tss(env, ist + 3);
20054ef0 892 } else {
08b3ded6 893 esp = env->regs[R_ESP];
20054ef0 894 }
eaa728ee
FB		 895 esp &= ~0xfLL; /* align stack */
896 dpl = cpl;
897 } else {
77b2bc2c 898 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
eaa728ee
FB		 899 new_stack = 0; /* avoid warning */
900 esp = 0; /* avoid warning */
901 }
902
903 PUSHQ(esp, env->segs[R_SS].selector);
08b3ded6 904 PUSHQ(esp, env->regs[R_ESP]);
997ff0d9 905 PUSHQ(esp, cpu_compute_eflags(env));
eaa728ee
FB		 906 PUSHQ(esp, env->segs[R_CS].selector);
907 PUSHQ(esp, old_eip);
908 if (has_error_code) {
909 PUSHQ(esp, error_code);
910 }
911
912 if (new_stack) {
913 ss = 0 | dpl;
914 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
915 }
08b3ded6 916 env->regs[R_ESP] = esp;
eaa728ee
FB		 917
918 selector = (selector & ~3) | dpl;
919 cpu_x86_load_seg_cache(env, R_CS, selector,
920 get_seg_base(e1, e2),
921 get_seg_limit(e1, e2),
922 e2);
923 cpu_x86_set_cpl(env, dpl);
924 env->eip = offset;
925
926 /* interrupt gate clear IF mask */
927 if ((type & 1) == 0) {
928 env->eflags &= ~IF_MASK;
929 }
930 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
931}
932#endif
933
d9957a8b 934#ifdef TARGET_X86_64
eaa728ee 935#if defined(CONFIG_USER_ONLY)
2999a0b2 936void helper_syscall(CPUX86State *env, int next_eip_addend)
eaa728ee
FB		 937{
938 env->exception_index = EXCP_SYSCALL;
939 env->exception_next_eip = env->eip + next_eip_addend;
1162c041 940 cpu_loop_exit(env);
eaa728ee
FB		 941}
942#else
2999a0b2 943void helper_syscall(CPUX86State *env, int next_eip_addend)
eaa728ee
FB		 944{
945 int selector;
946
947 if (!(env->efer & MSR_EFER_SCE)) {
77b2bc2c 948 raise_exception_err(env, EXCP06_ILLOP, 0);
eaa728ee
FB		 949 }
950 selector = (env->star >> 32) & 0xffff;
eaa728ee
FB		 951 if (env->hflags & HF_LMA_MASK) {
952 int code64;
953
a4165610 954 env->regs[R_ECX] = env->eip + next_eip_addend;
997ff0d9 955 env->regs[11] = cpu_compute_eflags(env);
eaa728ee
FB		 956
957 code64 = env->hflags & HF_CS64_MASK;
958
959 cpu_x86_set_cpl(env, 0);
960 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
961 0, 0xffffffff,
962 DESC_G_MASK | DESC_P_MASK |
963 DESC_S_MASK |
20054ef0
BS		 964 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
965 DESC_L_MASK);
eaa728ee
FB		 966 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
967 0, 0xffffffff,
968 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
969 DESC_S_MASK |
970 DESC_W_MASK | DESC_A_MASK);
971 env->eflags &= ~env->fmask;
997ff0d9 972 cpu_load_eflags(env, env->eflags, 0);
20054ef0 973 if (code64) {
eaa728ee 974 env->eip = env->lstar;
20054ef0 975 } else {
eaa728ee 976 env->eip = env->cstar;
20054ef0 977 }
d9957a8b 978 } else {
a4165610 979 env->regs[R_ECX] = (uint32_t)(env->eip + next_eip_addend);
eaa728ee
FB		 980
981 cpu_x86_set_cpl(env, 0);
982 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
983 0, 0xffffffff,
984 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
985 DESC_S_MASK |
986 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
987 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
988 0, 0xffffffff,
989 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
990 DESC_S_MASK |
991 DESC_W_MASK | DESC_A_MASK);
992 env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
993 env->eip = (uint32_t)env->star;
994 }
995}
996#endif
d9957a8b 997#endif
eaa728ee 998
d9957a8b 999#ifdef TARGET_X86_64
2999a0b2 1000void helper_sysret(CPUX86State *env, int dflag)
eaa728ee
FB		 1001{
1002 int cpl, selector;
1003
1004 if (!(env->efer & MSR_EFER_SCE)) {
77b2bc2c 1005 raise_exception_err(env, EXCP06_ILLOP, 0);
eaa728ee
FB		 1006 }
1007 cpl = env->hflags & HF_CPL_MASK;
1008 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
77b2bc2c 1009 raise_exception_err(env, EXCP0D_GPF, 0);
eaa728ee
FB		 1010 }
1011 selector = (env->star >> 48) & 0xffff;
eaa728ee
FB		 1012 if (env->hflags & HF_LMA_MASK) {
1013 if (dflag == 2) {
1014 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
1015 0, 0xffffffff,
1016 DESC_G_MASK | DESC_P_MASK |
1017 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1018 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1019 DESC_L_MASK);
a4165610 1020 env->eip = env->regs[R_ECX];
eaa728ee
FB		 1021 } else {
1022 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1023 0, 0xffffffff,
1024 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1025 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1026 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
a4165610 1027 env->eip = (uint32_t)env->regs[R_ECX];
eaa728ee
FB		 1028 }
1029 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1030 0, 0xffffffff,
1031 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1032 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1033 DESC_W_MASK | DESC_A_MASK);
997ff0d9
BS		 1034 cpu_load_eflags(env, (uint32_t)(env->regs[11]), TF_MASK | AC_MASK
1035 | ID_MASK | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK |
1036 NT_MASK);
eaa728ee 1037 cpu_x86_set_cpl(env, 3);
d9957a8b 1038 } else {
eaa728ee
FB		 1039 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1040 0, 0xffffffff,
1041 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1042 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1043 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
a4165610 1044 env->eip = (uint32_t)env->regs[R_ECX];
eaa728ee
FB		 1045 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1046 0, 0xffffffff,
1047 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1048 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1049 DESC_W_MASK | DESC_A_MASK);
1050 env->eflags |= IF_MASK;
1051 cpu_x86_set_cpl(env, 3);
1052 }
eaa728ee 1053}
d9957a8b 1054#endif
eaa728ee
FB		 1055
1056/* real mode interrupt */
2999a0b2
BS		 1057static void do_interrupt_real(CPUX86State *env, int intno, int is_int,
1058 int error_code, unsigned int next_eip)
eaa728ee
FB		 1059{
1060 SegmentCache *dt;
1061 target_ulong ptr, ssp;
1062 int selector;
1063 uint32_t offset, esp;
1064 uint32_t old_cs, old_eip;
eaa728ee 1065
20054ef0 1066 /* real mode (simpler!) */
eaa728ee 1067 dt = &env->idt;
20054ef0 1068 if (intno * 4 + 3 > dt->limit) {
77b2bc2c 1069 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
20054ef0 1070 }
eaa728ee 1071 ptr = dt->base + intno * 4;
329e607d
BS		 1072 offset = cpu_lduw_kernel(env, ptr);
1073 selector = cpu_lduw_kernel(env, ptr + 2);
08b3ded6 1074 esp = env->regs[R_ESP];
eaa728ee 1075 ssp = env->segs[R_SS].base;
20054ef0 1076 if (is_int) {
eaa728ee 1077 old_eip = next_eip;
20054ef0 1078 } else {
eaa728ee 1079 old_eip = env->eip;
20054ef0 1080 }
eaa728ee 1081 old_cs = env->segs[R_CS].selector;
20054ef0 1082 /* XXX: use SS segment size? */
997ff0d9 1083 PUSHW(ssp, esp, 0xffff, cpu_compute_eflags(env));
eaa728ee
FB		 1084 PUSHW(ssp, esp, 0xffff, old_cs);
1085 PUSHW(ssp, esp, 0xffff, old_eip);
1086
1087 /* update processor state */
08b3ded6 1088 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | (esp & 0xffff);
eaa728ee
FB		 1089 env->eip = offset;
1090 env->segs[R_CS].selector = selector;
1091 env->segs[R_CS].base = (selector << 4);
1092 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1093}
1094
e694d4e2 1095#if defined(CONFIG_USER_ONLY)
eaa728ee 1096/* fake user mode interrupt */
2999a0b2
BS		 1097static void do_interrupt_user(CPUX86State *env, int intno, int is_int,
1098 int error_code, target_ulong next_eip)
eaa728ee
FB		 1099{
1100 SegmentCache *dt;
1101 target_ulong ptr;
1102 int dpl, cpl, shift;
1103 uint32_t e2;
1104
1105 dt = &env->idt;
1106 if (env->hflags & HF_LMA_MASK) {
1107 shift = 4;
1108 } else {
1109 shift = 3;
1110 }
1111 ptr = dt->base + (intno << shift);
329e607d 1112 e2 = cpu_ldl_kernel(env, ptr + 4);
eaa728ee
FB		 1113
1114 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1115 cpl = env->hflags & HF_CPL_MASK;
1235fc06 1116 /* check privilege if software int */
20054ef0 1117 if (is_int && dpl < cpl) {
77b2bc2c 1118 raise_exception_err(env, EXCP0D_GPF, (intno << shift) + 2);
20054ef0 1119 }
eaa728ee
FB		 1120
1121 /* Since we emulate only user space, we cannot do more than
1122 exiting the emulation with the suitable exception and error
1123 code */
20054ef0 1124 if (is_int) {
eaa728ee 1125 EIP = next_eip;
20054ef0 1126 }
eaa728ee
FB		 1127}
1128
e694d4e2
BS		 1129#else
1130
2999a0b2
BS		 1131static void handle_even_inj(CPUX86State *env, int intno, int is_int,
1132 int error_code, int is_hw, int rm)
2ed51f5b 1133{
20054ef0
BS		 1134 uint32_t event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
1135 control.event_inj));
1136
2ed51f5b 1137 if (!(event_inj & SVM_EVTINJ_VALID)) {
20054ef0
BS		 1138 int type;
1139
1140 if (is_int) {
1141 type = SVM_EVTINJ_TYPE_SOFT;
1142 } else {
1143 type = SVM_EVTINJ_TYPE_EXEPT;
1144 }
1145 event_inj = intno | type | SVM_EVTINJ_VALID;
1146 if (!rm && exception_has_error_code(intno)) {
1147 event_inj |= SVM_EVTINJ_VALID_ERR;
1148 stl_phys(env->vm_vmcb + offsetof(struct vmcb,
1149 control.event_inj_err),
1150 error_code);
1151 }
1152 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
1153 event_inj);
2ed51f5b
AL		 1154 }
1155}
00ea18d1 1156#endif
2ed51f5b 1157
eaa728ee
FB		 1158/*
1159 * Begin execution of an interruption. is_int is TRUE if coming from
1160 * the int instruction. next_eip is the EIP value AFTER the interrupt
1161 * instruction. It is only relevant if is_int is TRUE.
1162 */
2999a0b2
BS		 1163static void do_interrupt_all(CPUX86State *env, int intno, int is_int,
1164 int error_code, target_ulong next_eip, int is_hw)
eaa728ee 1165{
8fec2b8c 1166 if (qemu_loglevel_mask(CPU_LOG_INT)) {
eaa728ee
FB		 1167 if ((env->cr[0] & CR0_PE_MASK)) {
1168 static int count;
20054ef0
BS		 1169
1170 qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx
1171 " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1172 count, intno, error_code, is_int,
1173 env->hflags & HF_CPL_MASK,
1174 env->segs[R_CS].selector, EIP,
1175 (int)env->segs[R_CS].base + EIP,
08b3ded6 1176 env->segs[R_SS].selector, env->regs[R_ESP]);
eaa728ee 1177 if (intno == 0x0e) {
93fcfe39 1178 qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]);
eaa728ee 1179 } else {
4b34e3ad 1180 qemu_log(" env->regs[R_EAX]=" TARGET_FMT_lx, env->regs[R_EAX]);
eaa728ee 1181 }
93fcfe39 1182 qemu_log("\n");
6fd2a026 1183 log_cpu_state(env, CPU_DUMP_CCOP);
eaa728ee
FB		 1184#if 0
1185 {
1186 int i;
9bd5494e 1187 target_ulong ptr;
20054ef0 1188
93fcfe39 1189 qemu_log(" code=");
eaa728ee 1190 ptr = env->segs[R_CS].base + env->eip;
20054ef0 1191 for (i = 0; i < 16; i++) {
93fcfe39 1192 qemu_log(" %02x", ldub(ptr + i));
eaa728ee 1193 }
93fcfe39 1194 qemu_log("\n");
eaa728ee
FB		 1195 }
1196#endif
1197 count++;
1198 }
1199 }
1200 if (env->cr[0] & CR0_PE_MASK) {
00ea18d1 1201#if !defined(CONFIG_USER_ONLY)
20054ef0 1202 if (env->hflags & HF_SVMI_MASK) {
2999a0b2 1203 handle_even_inj(env, intno, is_int, error_code, is_hw, 0);
20054ef0 1204 }
00ea18d1 1205#endif
eb38c52c 1206#ifdef TARGET_X86_64
eaa728ee 1207 if (env->hflags & HF_LMA_MASK) {
2999a0b2 1208 do_interrupt64(env, intno, is_int, error_code, next_eip, is_hw);
eaa728ee
FB		 1209 } else
1210#endif
1211 {
2999a0b2
BS		 1212 do_interrupt_protected(env, intno, is_int, error_code, next_eip,
1213 is_hw);
eaa728ee
FB		 1214 }
1215 } else {
00ea18d1 1216#if !defined(CONFIG_USER_ONLY)
20054ef0 1217 if (env->hflags & HF_SVMI_MASK) {
2999a0b2 1218 handle_even_inj(env, intno, is_int, error_code, is_hw, 1);
20054ef0 1219 }
00ea18d1 1220#endif
2999a0b2 1221 do_interrupt_real(env, intno, is_int, error_code, next_eip);
eaa728ee 1222 }
2ed51f5b 1223
00ea18d1 1224#if !defined(CONFIG_USER_ONLY)
2ed51f5b 1225 if (env->hflags & HF_SVMI_MASK) {
20054ef0
BS		 1226 uint32_t event_inj = ldl_phys(env->vm_vmcb +
1227 offsetof(struct vmcb,
1228 control.event_inj));
1229
1230 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
1231 event_inj & ~SVM_EVTINJ_VALID);
2ed51f5b 1232 }
00ea18d1 1233#endif
eaa728ee
FB		 1234}
1235
97a8ea5a 1236void x86_cpu_do_interrupt(CPUState *cs)
e694d4e2 1237{
97a8ea5a
AF		 1238 X86CPU *cpu = X86_CPU(cs);
1239 CPUX86State *env = &cpu->env;
1240
e694d4e2
BS		 1241#if defined(CONFIG_USER_ONLY)
1242 /* if user mode only, we simulate a fake exception
1243 which will be handled outside the cpu execution
1244 loop */
2999a0b2 1245 do_interrupt_user(env, env->exception_index,
e694d4e2
BS		 1246 env->exception_is_int,
1247 env->error_code,
1248 env->exception_next_eip);
1249 /* successfully delivered */
1250 env->old_exception = -1;
1251#else
1252 /* simulate a real cpu exception. On i386, it can
1253 trigger new exceptions, but we do not handle
1254 double or triple faults yet. */
2999a0b2 1255 do_interrupt_all(env, env->exception_index,
e694d4e2
BS		 1256 env->exception_is_int,
1257 env->error_code,
1258 env->exception_next_eip, 0);
1259 /* successfully delivered */
1260 env->old_exception = -1;
1261#endif
e694d4e2
BS		 1262}
1263
2999a0b2 1264void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw)
e694d4e2 1265{
2999a0b2 1266 do_interrupt_all(env, intno, 0, 0, 0, is_hw);
e694d4e2
BS		 1267}
1268
2999a0b2
BS		 1269void helper_enter_level(CPUX86State *env, int level, int data32,
1270 target_ulong t1)
eaa728ee
FB		 1271{
1272 target_ulong ssp;
1273 uint32_t esp_mask, esp, ebp;
1274
1275 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1276 ssp = env->segs[R_SS].base;
c12dddd7 1277 ebp = env->regs[R_EBP];
08b3ded6 1278 esp = env->regs[R_ESP];
eaa728ee
FB		 1279 if (data32) {
1280 /* 32 bit */
1281 esp -= 4;
1282 while (--level) {
1283 esp -= 4;
1284 ebp -= 4;
329e607d
BS		 1285 cpu_stl_data(env, ssp + (esp & esp_mask),
1286 cpu_ldl_data(env, ssp + (ebp & esp_mask)));
eaa728ee
FB		 1287 }
1288 esp -= 4;
329e607d 1289 cpu_stl_data(env, ssp + (esp & esp_mask), t1);
eaa728ee
FB		 1290 } else {
1291 /* 16 bit */
1292 esp -= 2;
1293 while (--level) {
1294 esp -= 2;
1295 ebp -= 2;
329e607d
BS		 1296 cpu_stw_data(env, ssp + (esp & esp_mask),
1297 cpu_lduw_data(env, ssp + (ebp & esp_mask)));
eaa728ee
FB		 1298 }
1299 esp -= 2;
329e607d 1300 cpu_stw_data(env, ssp + (esp & esp_mask), t1);
eaa728ee
FB		 1301 }
1302}
1303
1304#ifdef TARGET_X86_64
2999a0b2
BS		 1305void helper_enter64_level(CPUX86State *env, int level, int data64,
1306 target_ulong t1)
eaa728ee
FB		 1307{
1308 target_ulong esp, ebp;
20054ef0 1309
c12dddd7 1310 ebp = env->regs[R_EBP];
08b3ded6 1311 esp = env->regs[R_ESP];
eaa728ee
FB		 1312
1313 if (data64) {
1314 /* 64 bit */
1315 esp -= 8;
1316 while (--level) {
1317 esp -= 8;
1318 ebp -= 8;
329e607d 1319 cpu_stq_data(env, esp, cpu_ldq_data(env, ebp));
eaa728ee
FB		 1320 }
1321 esp -= 8;
329e607d 1322 cpu_stq_data(env, esp, t1);
eaa728ee
FB		 1323 } else {
1324 /* 16 bit */
1325 esp -= 2;
1326 while (--level) {
1327 esp -= 2;
1328 ebp -= 2;
329e607d 1329 cpu_stw_data(env, esp, cpu_lduw_data(env, ebp));
eaa728ee
FB		 1330 }
1331 esp -= 2;
329e607d 1332 cpu_stw_data(env, esp, t1);
eaa728ee
FB		 1333 }
1334}
1335#endif
1336
2999a0b2 1337void helper_lldt(CPUX86State *env, int selector)
eaa728ee
FB		 1338{
1339 SegmentCache *dt;
1340 uint32_t e1, e2;
1341 int index, entry_limit;
1342 target_ulong ptr;
1343
1344 selector &= 0xffff;
1345 if ((selector & 0xfffc) == 0) {
1346 /* XXX: NULL selector case: invalid LDT */
1347 env->ldt.base = 0;
1348 env->ldt.limit = 0;
1349 } else {
20054ef0 1350 if (selector & 0x4) {
77b2bc2c 1351 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 1352 }
eaa728ee
FB		 1353 dt = &env->gdt;
1354 index = selector & ~7;
1355#ifdef TARGET_X86_64
20054ef0 1356 if (env->hflags & HF_LMA_MASK) {
eaa728ee 1357 entry_limit = 15;
20054ef0 1358 } else
eaa728ee 1359#endif
20054ef0 1360 {
eaa728ee 1361 entry_limit = 7;
20054ef0
BS		 1362 }
1363 if ((index + entry_limit) > dt->limit) {
77b2bc2c 1364 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 1365 }
eaa728ee 1366 ptr = dt->base + index;
329e607d
BS		 1367 e1 = cpu_ldl_kernel(env, ptr);
1368 e2 = cpu_ldl_kernel(env, ptr + 4);
20054ef0 1369 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
77b2bc2c 1370 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0
BS		 1371 }
1372 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 1373 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
20054ef0 1374 }
eaa728ee
FB		 1375#ifdef TARGET_X86_64
1376 if (env->hflags & HF_LMA_MASK) {
1377 uint32_t e3;
20054ef0 1378
329e607d 1379 e3 = cpu_ldl_kernel(env, ptr + 8);
eaa728ee
FB		 1380 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1381 env->ldt.base |= (target_ulong)e3 << 32;
1382 } else
1383#endif
1384 {
1385 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1386 }
1387 }
1388 env->ldt.selector = selector;
1389}
1390
2999a0b2 1391void helper_ltr(CPUX86State *env, int selector)
eaa728ee
FB		 1392{
1393 SegmentCache *dt;
1394 uint32_t e1, e2;
1395 int index, type, entry_limit;
1396 target_ulong ptr;
1397
1398 selector &= 0xffff;
1399 if ((selector & 0xfffc) == 0) {
1400 /* NULL selector case: invalid TR */
1401 env->tr.base = 0;
1402 env->tr.limit = 0;
1403 env->tr.flags = 0;
1404 } else {
20054ef0 1405 if (selector & 0x4) {
77b2bc2c 1406 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 1407 }
eaa728ee
FB		 1408 dt = &env->gdt;
1409 index = selector & ~7;
1410#ifdef TARGET_X86_64
20054ef0 1411 if (env->hflags & HF_LMA_MASK) {
eaa728ee 1412 entry_limit = 15;
20054ef0 1413 } else
eaa728ee 1414#endif
20054ef0 1415 {
eaa728ee 1416 entry_limit = 7;
20054ef0
BS		 1417 }
1418 if ((index + entry_limit) > dt->limit) {
77b2bc2c 1419 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 1420 }
eaa728ee 1421 ptr = dt->base + index;
329e607d
BS		 1422 e1 = cpu_ldl_kernel(env, ptr);
1423 e2 = cpu_ldl_kernel(env, ptr + 4);
eaa728ee
FB		 1424 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1425 if ((e2 & DESC_S_MASK) ||
20054ef0 1426 (type != 1 && type != 9)) {
77b2bc2c 1427 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0
BS		 1428 }
1429 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 1430 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
20054ef0 1431 }
eaa728ee
FB		 1432#ifdef TARGET_X86_64
1433 if (env->hflags & HF_LMA_MASK) {
1434 uint32_t e3, e4;
20054ef0 1435
329e607d
BS		 1436 e3 = cpu_ldl_kernel(env, ptr + 8);
1437 e4 = cpu_ldl_kernel(env, ptr + 12);
20054ef0 1438 if ((e4 >> DESC_TYPE_SHIFT) & 0xf) {
77b2bc2c 1439 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 1440 }
eaa728ee
FB		 1441 load_seg_cache_raw_dt(&env->tr, e1, e2);
1442 env->tr.base |= (target_ulong)e3 << 32;
1443 } else
1444#endif
1445 {
1446 load_seg_cache_raw_dt(&env->tr, e1, e2);
1447 }
1448 e2 |= DESC_TSS_BUSY_MASK;
329e607d 1449 cpu_stl_kernel(env, ptr + 4, e2);
eaa728ee
FB		 1450 }
1451 env->tr.selector = selector;
1452}
1453
1454/* only works if protected mode and not VM86. seg_reg must be != R_CS */
2999a0b2 1455void helper_load_seg(CPUX86State *env, int seg_reg, int selector)
eaa728ee
FB		 1456{
1457 uint32_t e1, e2;
1458 int cpl, dpl, rpl;
1459 SegmentCache *dt;
1460 int index;
1461 target_ulong ptr;
1462
1463 selector &= 0xffff;
1464 cpl = env->hflags & HF_CPL_MASK;
1465 if ((selector & 0xfffc) == 0) {
1466 /* null selector case */
1467 if (seg_reg == R_SS
1468#ifdef TARGET_X86_64
1469 && (!(env->hflags & HF_CS64_MASK) || cpl == 3)
1470#endif
20054ef0 1471 ) {
77b2bc2c 1472 raise_exception_err(env, EXCP0D_GPF, 0);
20054ef0 1473 }
eaa728ee
FB		 1474 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
1475 } else {
1476
20054ef0 1477 if (selector & 0x4) {
eaa728ee 1478 dt = &env->ldt;
20054ef0 1479 } else {
eaa728ee 1480 dt = &env->gdt;
20054ef0 1481 }
eaa728ee 1482 index = selector & ~7;
20054ef0 1483 if ((index + 7) > dt->limit) {
77b2bc2c 1484 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 1485 }
eaa728ee 1486 ptr = dt->base + index;
329e607d
BS		 1487 e1 = cpu_ldl_kernel(env, ptr);
1488 e2 = cpu_ldl_kernel(env, ptr + 4);
eaa728ee 1489
20054ef0 1490 if (!(e2 & DESC_S_MASK)) {
77b2bc2c 1491 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 1492 }
eaa728ee
FB		 1493 rpl = selector & 3;
1494 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1495 if (seg_reg == R_SS) {
1496 /* must be writable segment */
20054ef0 1497 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
77b2bc2c 1498 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0
BS		 1499 }
1500 if (rpl != cpl || dpl != cpl) {
77b2bc2c 1501 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 1502 }
eaa728ee
FB		 1503 } else {
1504 /* must be readable segment */
20054ef0 1505 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK) {
77b2bc2c 1506 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 1507 }
eaa728ee
FB		 1508
1509 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1510 /* if not conforming code, test rights */
20054ef0 1511 if (dpl < cpl || dpl < rpl) {
77b2bc2c 1512 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 1513 }
eaa728ee
FB		 1514 }
1515 }
1516
1517 if (!(e2 & DESC_P_MASK)) {
20054ef0 1518 if (seg_reg == R_SS) {
77b2bc2c 1519 raise_exception_err(env, EXCP0C_STACK, selector & 0xfffc);
20054ef0 1520 } else {
77b2bc2c 1521 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
20054ef0 1522 }
eaa728ee
FB		 1523 }
1524
1525 /* set the access bit if not already set */
1526 if (!(e2 & DESC_A_MASK)) {
1527 e2 |= DESC_A_MASK;
329e607d 1528 cpu_stl_kernel(env, ptr + 4, e2);
eaa728ee
FB		 1529 }
1530
1531 cpu_x86_load_seg_cache(env, seg_reg, selector,
1532 get_seg_base(e1, e2),
1533 get_seg_limit(e1, e2),
1534 e2);
1535#if 0
93fcfe39 1536 qemu_log("load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
eaa728ee
FB		 1537 selector, (unsigned long)sc->base, sc->limit, sc->flags);
1538#endif
1539 }
1540}
1541
1542/* protected mode jump */
2999a0b2 1543void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
eaa728ee
FB		 1544 int next_eip_addend)
1545{
1546 int gate_cs, type;
1547 uint32_t e1, e2, cpl, dpl, rpl, limit;
1548 target_ulong next_eip;
1549
20054ef0 1550 if ((new_cs & 0xfffc) == 0) {
77b2bc2c 1551 raise_exception_err(env, EXCP0D_GPF, 0);
20054ef0 1552 }
2999a0b2 1553 if (load_segment(env, &e1, &e2, new_cs) != 0) {
77b2bc2c 1554 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 1555 }
eaa728ee
FB		 1556 cpl = env->hflags & HF_CPL_MASK;
1557 if (e2 & DESC_S_MASK) {
20054ef0 1558 if (!(e2 & DESC_CS_MASK)) {
77b2bc2c 1559 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 1560 }
eaa728ee
FB		 1561 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1562 if (e2 & DESC_C_MASK) {
1563 /* conforming code segment */
20054ef0 1564 if (dpl > cpl) {
77b2bc2c 1565 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 1566 }
eaa728ee
FB		 1567 } else {
1568 /* non conforming code segment */
1569 rpl = new_cs & 3;
20054ef0 1570 if (rpl > cpl) {
77b2bc2c 1571 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0
BS		 1572 }
1573 if (dpl != cpl) {
77b2bc2c 1574 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 1575 }
eaa728ee 1576 }
20054ef0 1577 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 1578 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
20054ef0 1579 }
eaa728ee
FB		 1580 limit = get_seg_limit(e1, e2);
1581 if (new_eip > limit &&
20054ef0 1582 !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK)) {
77b2bc2c 1583 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 1584 }
eaa728ee
FB		 1585 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1586 get_seg_base(e1, e2), limit, e2);
1587 EIP = new_eip;
1588 } else {
1589 /* jump to call or task gate */
1590 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1591 rpl = new_cs & 3;
1592 cpl = env->hflags & HF_CPL_MASK;
1593 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
20054ef0 1594 switch (type) {
eaa728ee
FB		 1595 case 1: /* 286 TSS */
1596 case 9: /* 386 TSS */
1597 case 5: /* task gate */
20054ef0 1598 if (dpl < cpl || dpl < rpl) {
77b2bc2c 1599 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 1600 }
eaa728ee 1601 next_eip = env->eip + next_eip_addend;
2999a0b2 1602 switch_tss(env, new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
eaa728ee
FB		 1603 CC_OP = CC_OP_EFLAGS;
1604 break;
1605 case 4: /* 286 call gate */
1606 case 12: /* 386 call gate */
20054ef0 1607 if ((dpl < cpl) || (dpl < rpl)) {
77b2bc2c 1608 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0
BS		 1609 }
1610 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 1611 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
20054ef0 1612 }
eaa728ee
FB		 1613 gate_cs = e1 >> 16;
1614 new_eip = (e1 & 0xffff);
20054ef0 1615 if (type == 12) {
eaa728ee 1616 new_eip |= (e2 & 0xffff0000);
20054ef0 1617 }
2999a0b2 1618 if (load_segment(env, &e1, &e2, gate_cs) != 0) {
77b2bc2c 1619 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
20054ef0 1620 }
eaa728ee
FB		 1621 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1622 /* must be code segment */
1623 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
20054ef0 1624 (DESC_S_MASK | DESC_CS_MASK))) {
77b2bc2c 1625 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
20054ef0 1626 }
eaa728ee 1627 if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
20054ef0 1628 (!(e2 & DESC_C_MASK) && (dpl != cpl))) {
77b2bc2c 1629 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
20054ef0
BS		 1630 }
1631 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 1632 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
20054ef0 1633 }
eaa728ee 1634 limit = get_seg_limit(e1, e2);
20054ef0 1635 if (new_eip > limit) {
77b2bc2c 1636 raise_exception_err(env, EXCP0D_GPF, 0);
20054ef0 1637 }
eaa728ee
FB		 1638 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
1639 get_seg_base(e1, e2), limit, e2);
1640 EIP = new_eip;
1641 break;
1642 default:
77b2bc2c 1643 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
eaa728ee
FB		 1644 break;
1645 }
1646 }
1647}
1648
1649/* real mode call */
2999a0b2 1650void helper_lcall_real(CPUX86State *env, int new_cs, target_ulong new_eip1,
eaa728ee
FB		 1651 int shift, int next_eip)
1652{
1653 int new_eip;
1654 uint32_t esp, esp_mask;
1655 target_ulong ssp;
1656
1657 new_eip = new_eip1;
08b3ded6 1658 esp = env->regs[R_ESP];
eaa728ee
FB		 1659 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1660 ssp = env->segs[R_SS].base;
1661 if (shift) {
1662 PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
1663 PUSHL(ssp, esp, esp_mask, next_eip);
1664 } else {
1665 PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
1666 PUSHW(ssp, esp, esp_mask, next_eip);
1667 }
1668
1669 SET_ESP(esp, esp_mask);
1670 env->eip = new_eip;
1671 env->segs[R_CS].selector = new_cs;
1672 env->segs[R_CS].base = (new_cs << 4);
1673}
1674
1675/* protected mode call */
2999a0b2 1676void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
eaa728ee
FB		 1677 int shift, int next_eip_addend)
1678{
1679 int new_stack, i;
1680 uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
1c918eba 1681 uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, sp, type, ss_dpl, sp_mask;
eaa728ee
FB		 1682 uint32_t val, limit, old_sp_mask;
1683 target_ulong ssp, old_ssp, next_eip;
1684
1685 next_eip = env->eip + next_eip_addend;
d12d51d5
AL		 1686 LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift);
1687 LOG_PCALL_STATE(env);
20054ef0 1688 if ((new_cs & 0xfffc) == 0) {
77b2bc2c 1689 raise_exception_err(env, EXCP0D_GPF, 0);
20054ef0 1690 }
2999a0b2 1691 if (load_segment(env, &e1, &e2, new_cs) != 0) {
77b2bc2c 1692 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 1693 }
eaa728ee 1694 cpl = env->hflags & HF_CPL_MASK;
d12d51d5 1695 LOG_PCALL("desc=%08x:%08x\n", e1, e2);
eaa728ee 1696 if (e2 & DESC_S_MASK) {
20054ef0 1697 if (!(e2 & DESC_CS_MASK)) {
77b2bc2c 1698 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 1699 }
eaa728ee
FB		 1700 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1701 if (e2 & DESC_C_MASK) {
1702 /* conforming code segment */
20054ef0 1703 if (dpl > cpl) {
77b2bc2c 1704 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 1705 }
eaa728ee
FB		 1706 } else {
1707 /* non conforming code segment */
1708 rpl = new_cs & 3;
20054ef0 1709 if (rpl > cpl) {
77b2bc2c 1710 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0
BS		 1711 }
1712 if (dpl != cpl) {
77b2bc2c 1713 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 1714 }
eaa728ee 1715 }
20054ef0 1716 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 1717 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
20054ef0 1718 }
eaa728ee
FB		 1719
1720#ifdef TARGET_X86_64
1721 /* XXX: check 16/32 bit cases in long mode */
1722 if (shift == 2) {
1723 target_ulong rsp;
20054ef0 1724
eaa728ee 1725 /* 64 bit case */
08b3ded6 1726 rsp = env->regs[R_ESP];
eaa728ee
FB		 1727 PUSHQ(rsp, env->segs[R_CS].selector);
1728 PUSHQ(rsp, next_eip);
1729 /* from this point, not restartable */
08b3ded6 1730 env->regs[R_ESP] = rsp;
eaa728ee
FB		 1731 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1732 get_seg_base(e1, e2),
1733 get_seg_limit(e1, e2), e2);
1734 EIP = new_eip;
1735 } else
1736#endif
1737 {
08b3ded6 1738 sp = env->regs[R_ESP];
eaa728ee
FB		 1739 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1740 ssp = env->segs[R_SS].base;
1741 if (shift) {
1742 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1743 PUSHL(ssp, sp, sp_mask, next_eip);
1744 } else {
1745 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1746 PUSHW(ssp, sp, sp_mask, next_eip);
1747 }
1748
1749 limit = get_seg_limit(e1, e2);
20054ef0 1750 if (new_eip > limit) {
77b2bc2c 1751 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 1752 }
eaa728ee
FB		 1753 /* from this point, not restartable */
1754 SET_ESP(sp, sp_mask);
1755 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1756 get_seg_base(e1, e2), limit, e2);
1757 EIP = new_eip;
1758 }
1759 } else {
1760 /* check gate type */
1761 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1762 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1763 rpl = new_cs & 3;
20054ef0 1764 switch (type) {
eaa728ee
FB		 1765 case 1: /* available 286 TSS */
1766 case 9: /* available 386 TSS */
1767 case 5: /* task gate */
20054ef0 1768 if (dpl < cpl || dpl < rpl) {
77b2bc2c 1769 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 1770 }
2999a0b2 1771 switch_tss(env, new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
eaa728ee
FB		 1772 CC_OP = CC_OP_EFLAGS;
1773 return;
1774 case 4: /* 286 call gate */
1775 case 12: /* 386 call gate */
1776 break;
1777 default:
77b2bc2c 1778 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
eaa728ee
FB		 1779 break;
1780 }
1781 shift = type >> 3;
1782
20054ef0 1783 if (dpl < cpl || dpl < rpl) {
77b2bc2c 1784 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 1785 }
eaa728ee 1786 /* check valid bit */
20054ef0 1787 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 1788 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
20054ef0 1789 }
eaa728ee
FB		 1790 selector = e1 >> 16;
1791 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
1792 param_count = e2 & 0x1f;
20054ef0 1793 if ((selector & 0xfffc) == 0) {
77b2bc2c 1794 raise_exception_err(env, EXCP0D_GPF, 0);
20054ef0 1795 }
eaa728ee 1796
2999a0b2 1797 if (load_segment(env, &e1, &e2, selector) != 0) {
77b2bc2c 1798 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0
BS		 1799 }
1800 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
77b2bc2c 1801 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0 1802 }
eaa728ee 1803 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
20054ef0 1804 if (dpl > cpl) {
77b2bc2c 1805 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
20054ef0
BS		 1806 }
1807 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 1808 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
20054ef0 1809 }
eaa728ee
FB		 1810
1811 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
1812 /* to inner privilege */
2999a0b2 1813 get_ss_esp_from_tss(env, &ss, &sp, dpl);
08b3ded6 1814 LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]=" TARGET_FMT_lx
20054ef0 1815 "\n",
08b3ded6 1816 ss, sp, param_count, env->regs[R_ESP]);
20054ef0 1817 if ((ss & 0xfffc) == 0) {
77b2bc2c 1818 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0
BS		 1819 }
1820 if ((ss & 3) != dpl) {
77b2bc2c 1821 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0 1822 }
2999a0b2 1823 if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) {
77b2bc2c 1824 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0 1825 }
eaa728ee 1826 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
20054ef0 1827 if (ss_dpl != dpl) {
77b2bc2c 1828 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0 1829 }
eaa728ee
FB		 1830 if (!(ss_e2 & DESC_S_MASK) ||
1831 (ss_e2 & DESC_CS_MASK) ||
20054ef0 1832 !(ss_e2 & DESC_W_MASK)) {
77b2bc2c 1833 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0
BS		 1834 }
1835 if (!(ss_e2 & DESC_P_MASK)) {
77b2bc2c 1836 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
20054ef0 1837 }
eaa728ee 1838
20054ef0 1839 /* push_size = ((param_count * 2) + 8) << shift; */
eaa728ee
FB		 1840
1841 old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
1842 old_ssp = env->segs[R_SS].base;
1843
1844 sp_mask = get_sp_mask(ss_e2);
1845 ssp = get_seg_base(ss_e1, ss_e2);
1846 if (shift) {
1847 PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
08b3ded6 1848 PUSHL(ssp, sp, sp_mask, env->regs[R_ESP]);
20054ef0 1849 for (i = param_count - 1; i >= 0; i--) {
08b3ded6 1850 val = cpu_ldl_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 4) &
329e607d 1851 old_sp_mask));
eaa728ee
FB		 1852 PUSHL(ssp, sp, sp_mask, val);
1853 }
1854 } else {
1855 PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
08b3ded6 1856 PUSHW(ssp, sp, sp_mask, env->regs[R_ESP]);
20054ef0 1857 for (i = param_count - 1; i >= 0; i--) {
08b3ded6 1858 val = cpu_lduw_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 2) &
329e607d 1859 old_sp_mask));
eaa728ee
FB		 1860 PUSHW(ssp, sp, sp_mask, val);
1861 }
1862 }
1863 new_stack = 1;
1864 } else {
1865 /* to same privilege */
08b3ded6 1866 sp = env->regs[R_ESP];
eaa728ee
FB		 1867 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1868 ssp = env->segs[R_SS].base;
20054ef0 1869 /* push_size = (4 << shift); */
eaa728ee
FB		 1870 new_stack = 0;
1871 }
1872
1873 if (shift) {
1874 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1875 PUSHL(ssp, sp, sp_mask, next_eip);
1876 } else {
1877 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1878 PUSHW(ssp, sp, sp_mask, next_eip);
1879 }
1880
1881 /* from this point, not restartable */
1882
1883 if (new_stack) {
1884 ss = (ss & ~3) | dpl;
1885 cpu_x86_load_seg_cache(env, R_SS, ss,
1886 ssp,
1887 get_seg_limit(ss_e1, ss_e2),
1888 ss_e2);
1889 }
1890
1891 selector = (selector & ~3) | dpl;
1892 cpu_x86_load_seg_cache(env, R_CS, selector,
1893 get_seg_base(e1, e2),
1894 get_seg_limit(e1, e2),
1895 e2);
1896 cpu_x86_set_cpl(env, dpl);
1897 SET_ESP(sp, sp_mask);
1898 EIP = offset;
1899 }
eaa728ee
FB		 1900}
1901
1902/* real and vm86 mode iret */
2999a0b2 1903void helper_iret_real(CPUX86State *env, int shift)
eaa728ee
FB		 1904{
1905 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
1906 target_ulong ssp;
1907 int eflags_mask;
1908
20054ef0 1909 sp_mask = 0xffff; /* XXXX: use SS segment size? */
08b3ded6 1910 sp = env->regs[R_ESP];
eaa728ee
FB		 1911 ssp = env->segs[R_SS].base;
1912 if (shift == 1) {
1913 /* 32 bits */
1914 POPL(ssp, sp, sp_mask, new_eip);
1915 POPL(ssp, sp, sp_mask, new_cs);
1916 new_cs &= 0xffff;
1917 POPL(ssp, sp, sp_mask, new_eflags);
1918 } else {
1919 /* 16 bits */
1920 POPW(ssp, sp, sp_mask, new_eip);
1921 POPW(ssp, sp, sp_mask, new_cs);
1922 POPW(ssp, sp, sp_mask, new_eflags);
1923 }
08b3ded6 1924 env->regs[R_ESP] = (env->regs[R_ESP] & ~sp_mask) | (sp & sp_mask);
bdadc0b5 1925 env->segs[R_CS].selector = new_cs;
1926 env->segs[R_CS].base = (new_cs << 4);
eaa728ee 1927 env->eip = new_eip;
20054ef0
BS		 1928 if (env->eflags & VM_MASK) {
1929 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK |
1930 NT_MASK;
1931 } else {
1932 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK |
1933 RF_MASK | NT_MASK;
1934 }
1935 if (shift == 0) {
eaa728ee 1936 eflags_mask &= 0xffff;
20054ef0 1937 }
997ff0d9 1938 cpu_load_eflags(env, new_eflags, eflags_mask);
db620f46 1939 env->hflags2 &= ~HF2_NMI_MASK;
eaa728ee
FB		 1940}
1941
2999a0b2 1942static inline void validate_seg(CPUX86State *env, int seg_reg, int cpl)
eaa728ee
FB		 1943{
1944 int dpl;
1945 uint32_t e2;
1946
1947 /* XXX: on x86_64, we do not want to nullify FS and GS because
1948 they may still contain a valid base. I would be interested to
1949 know how a real x86_64 CPU behaves */
1950 if ((seg_reg == R_FS || seg_reg == R_GS) &&
20054ef0 1951 (env->segs[seg_reg].selector & 0xfffc) == 0) {
eaa728ee 1952 return;
20054ef0 1953 }
eaa728ee
FB		 1954
1955 e2 = env->segs[seg_reg].flags;
1956 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1957 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1958 /* data or non conforming code segment */
1959 if (dpl < cpl) {
1960 cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
1961 }
1962 }
1963}
1964
1965/* protected mode iret */
2999a0b2
BS		 1966static inline void helper_ret_protected(CPUX86State *env, int shift,
1967 int is_iret, int addend)
eaa728ee
FB		 1968{
1969 uint32_t new_cs, new_eflags, new_ss;
1970 uint32_t new_es, new_ds, new_fs, new_gs;
1971 uint32_t e1, e2, ss_e1, ss_e2;
1972 int cpl, dpl, rpl, eflags_mask, iopl;
1973 target_ulong ssp, sp, new_eip, new_esp, sp_mask;
1974
1975#ifdef TARGET_X86_64
20054ef0 1976 if (shift == 2) {
eaa728ee 1977 sp_mask = -1;
20054ef0 1978 } else
eaa728ee 1979#endif
20054ef0 1980 {
eaa728ee 1981 sp_mask = get_sp_mask(env->segs[R_SS].flags);
20054ef0 1982 }
08b3ded6 1983 sp = env->regs[R_ESP];
eaa728ee
FB		 1984 ssp = env->segs[R_SS].base;
1985 new_eflags = 0; /* avoid warning */
1986#ifdef TARGET_X86_64
1987 if (shift == 2) {
1988 POPQ(sp, new_eip);
1989 POPQ(sp, new_cs);
1990 new_cs &= 0xffff;
1991 if (is_iret) {
1992 POPQ(sp, new_eflags);
1993 }
1994 } else
1995#endif
20054ef0
BS		 1996 {
1997 if (shift == 1) {
1998 /* 32 bits */
1999 POPL(ssp, sp, sp_mask, new_eip);
2000 POPL(ssp, sp, sp_mask, new_cs);
2001 new_cs &= 0xffff;
2002 if (is_iret) {
2003 POPL(ssp, sp, sp_mask, new_eflags);
2004 if (new_eflags & VM_MASK) {
2005 goto return_to_vm86;
2006 }
2007 }
2008 } else {
2009 /* 16 bits */
2010 POPW(ssp, sp, sp_mask, new_eip);
2011 POPW(ssp, sp, sp_mask, new_cs);
2012 if (is_iret) {
2013 POPW(ssp, sp, sp_mask, new_eflags);
2014 }
eaa728ee 2015 }
eaa728ee 2016 }
d12d51d5
AL		 2017 LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2018 new_cs, new_eip, shift, addend);
2019 LOG_PCALL_STATE(env);
20054ef0 2020 if ((new_cs & 0xfffc) == 0) {
77b2bc2c 2021 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 2022 }
2999a0b2 2023 if (load_segment(env, &e1, &e2, new_cs) != 0) {
77b2bc2c 2024 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 2025 }
eaa728ee 2026 if (!(e2 & DESC_S_MASK) ||
20054ef0 2027 !(e2 & DESC_CS_MASK)) {
77b2bc2c 2028 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 2029 }
eaa728ee
FB		 2030 cpl = env->hflags & HF_CPL_MASK;
2031 rpl = new_cs & 3;
20054ef0 2032 if (rpl < cpl) {
77b2bc2c 2033 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 2034 }
eaa728ee
FB		 2035 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2036 if (e2 & DESC_C_MASK) {
20054ef0 2037 if (dpl > rpl) {
77b2bc2c 2038 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 2039 }
eaa728ee 2040 } else {
20054ef0 2041 if (dpl != rpl) {
77b2bc2c 2042 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
20054ef0 2043 }
eaa728ee 2044 }
20054ef0 2045 if (!(e2 & DESC_P_MASK)) {
77b2bc2c 2046 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
20054ef0 2047 }
eaa728ee
FB		 2048
2049 sp += addend;
2050 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
2051 ((env->hflags & HF_CS64_MASK) && !is_iret))) {
1235fc06 2052 /* return to same privilege level */
eaa728ee
FB		 2053 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2054 get_seg_base(e1, e2),
2055 get_seg_limit(e1, e2),
2056 e2);
2057 } else {
2058 /* return to different privilege level */
2059#ifdef TARGET_X86_64
2060 if (shift == 2) {
2061 POPQ(sp, new_esp);
2062 POPQ(sp, new_ss);
2063 new_ss &= 0xffff;
2064 } else
2065#endif
20054ef0
BS		 2066 {
2067 if (shift == 1) {
2068 /* 32 bits */
2069 POPL(ssp, sp, sp_mask, new_esp);
2070 POPL(ssp, sp, sp_mask, new_ss);
2071 new_ss &= 0xffff;
2072 } else {
2073 /* 16 bits */
2074 POPW(ssp, sp, sp_mask, new_esp);
2075 POPW(ssp, sp, sp_mask, new_ss);
2076 }
eaa728ee 2077 }
d12d51d5 2078 LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n",
20054ef0 2079 new_ss, new_esp);
eaa728ee
FB		 2080 if ((new_ss & 0xfffc) == 0) {
2081#ifdef TARGET_X86_64
20054ef0
BS		 2082 /* NULL ss is allowed in long mode if cpl != 3 */
2083 /* XXX: test CS64? */
eaa728ee
FB		 2084 if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2085 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2086 0, 0xffffffff,
2087 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2088 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
2089 DESC_W_MASK | DESC_A_MASK);
20054ef0 2090 ss_e2 = DESC_B_MASK; /* XXX: should not be needed? */
eaa728ee
FB		 2091 } else
2092#endif
2093 {
77b2bc2c 2094 raise_exception_err(env, EXCP0D_GPF, 0);
eaa728ee
FB		 2095 }
2096 } else {
20054ef0 2097 if ((new_ss & 3) != rpl) {
77b2bc2c 2098 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
20054ef0 2099 }
2999a0b2 2100 if (load_segment(env, &ss_e1, &ss_e2, new_ss) != 0) {
77b2bc2c 2101 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
20054ef0 2102 }
eaa728ee
FB		 2103 if (!(ss_e2 & DESC_S_MASK) ||
2104 (ss_e2 & DESC_CS_MASK) ||
20054ef0 2105 !(ss_e2 & DESC_W_MASK)) {
77b2bc2c 2106 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
20054ef0 2107 }
eaa728ee 2108 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
20054ef0 2109 if (dpl != rpl) {
77b2bc2c 2110 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
20054ef0
BS		 2111 }
2112 if (!(ss_e2 & DESC_P_MASK)) {
77b2bc2c 2113 raise_exception_err(env, EXCP0B_NOSEG, new_ss & 0xfffc);
20054ef0 2114 }
eaa728ee
FB		 2115 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2116 get_seg_base(ss_e1, ss_e2),
2117 get_seg_limit(ss_e1, ss_e2),
2118 ss_e2);
2119 }
2120
2121 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2122 get_seg_base(e1, e2),
2123 get_seg_limit(e1, e2),
2124 e2);
2125 cpu_x86_set_cpl(env, rpl);
2126 sp = new_esp;
2127#ifdef TARGET_X86_64
20054ef0 2128 if (env->hflags & HF_CS64_MASK) {
eaa728ee 2129 sp_mask = -1;
20054ef0 2130 } else
eaa728ee 2131#endif
20054ef0 2132 {
eaa728ee 2133 sp_mask = get_sp_mask(ss_e2);
20054ef0 2134 }
eaa728ee
FB		 2135
2136 /* validate data segments */
2999a0b2
BS		 2137 validate_seg(env, R_ES, rpl);
2138 validate_seg(env, R_DS, rpl);
2139 validate_seg(env, R_FS, rpl);
2140 validate_seg(env, R_GS, rpl);
eaa728ee
FB		 2141
2142 sp += addend;
2143 }
2144 SET_ESP(sp, sp_mask);
2145 env->eip = new_eip;
2146 if (is_iret) {
2147 /* NOTE: 'cpl' is the _old_ CPL */
2148 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
20054ef0 2149 if (cpl == 0) {
eaa728ee 2150 eflags_mask |= IOPL_MASK;
20054ef0 2151 }
eaa728ee 2152 iopl = (env->eflags >> IOPL_SHIFT) & 3;
20054ef0 2153 if (cpl <= iopl) {
eaa728ee 2154 eflags_mask |= IF_MASK;
20054ef0
BS		 2155 }
2156 if (shift == 0) {
eaa728ee 2157 eflags_mask &= 0xffff;
20054ef0 2158 }
997ff0d9 2159 cpu_load_eflags(env, new_eflags, eflags_mask);
eaa728ee
FB		 2160 }
2161 return;
2162
2163 return_to_vm86:
2164 POPL(ssp, sp, sp_mask, new_esp);
2165 POPL(ssp, sp, sp_mask, new_ss);
2166 POPL(ssp, sp, sp_mask, new_es);
2167 POPL(ssp, sp, sp_mask, new_ds);
2168 POPL(ssp, sp, sp_mask, new_fs);
2169 POPL(ssp, sp, sp_mask, new_gs);
2170
2171 /* modify processor state */
997ff0d9
BS		 2172 cpu_load_eflags(env, new_eflags, TF_MASK | AC_MASK | ID_MASK |
2173 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK |
2174 VIP_MASK);
2999a0b2 2175 load_seg_vm(env, R_CS, new_cs & 0xffff);
eaa728ee 2176 cpu_x86_set_cpl(env, 3);
2999a0b2
BS		 2177 load_seg_vm(env, R_SS, new_ss & 0xffff);
2178 load_seg_vm(env, R_ES, new_es & 0xffff);
2179 load_seg_vm(env, R_DS, new_ds & 0xffff);
2180 load_seg_vm(env, R_FS, new_fs & 0xffff);
2181 load_seg_vm(env, R_GS, new_gs & 0xffff);
eaa728ee
FB		 2182
2183 env->eip = new_eip & 0xffff;
08b3ded6 2184 env->regs[R_ESP] = new_esp;
eaa728ee
FB		 2185}
2186
2999a0b2 2187void helper_iret_protected(CPUX86State *env, int shift, int next_eip)
eaa728ee
FB		 2188{
2189 int tss_selector, type;
2190 uint32_t e1, e2;
2191
2192 /* specific case for TSS */
2193 if (env->eflags & NT_MASK) {
2194#ifdef TARGET_X86_64
20054ef0 2195 if (env->hflags & HF_LMA_MASK) {
77b2bc2c 2196 raise_exception_err(env, EXCP0D_GPF, 0);
20054ef0 2197 }
eaa728ee 2198#endif
329e607d 2199 tss_selector = cpu_lduw_kernel(env, env->tr.base + 0);
20054ef0 2200 if (tss_selector & 4) {
77b2bc2c 2201 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
20054ef0 2202 }
2999a0b2 2203 if (load_segment(env, &e1, &e2, tss_selector) != 0) {
77b2bc2c 2204 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
20054ef0 2205 }
eaa728ee
FB		 2206 type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2207 /* NOTE: we check both segment and busy TSS */
20054ef0 2208 if (type != 3) {
77b2bc2c 2209 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
20054ef0 2210 }
2999a0b2 2211 switch_tss(env, tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
eaa728ee 2212 } else {
2999a0b2 2213 helper_ret_protected(env, shift, 1, 0);
eaa728ee 2214 }
db620f46 2215 env->hflags2 &= ~HF2_NMI_MASK;
eaa728ee
FB		 2216}
2217
2999a0b2 2218void helper_lret_protected(CPUX86State *env, int shift, int addend)
eaa728ee 2219{
2999a0b2 2220 helper_ret_protected(env, shift, 0, addend);
eaa728ee
FB		 2221}
2222
2999a0b2 2223void helper_sysenter(CPUX86State *env)
eaa728ee
FB		 2224{
2225 if (env->sysenter_cs == 0) {
77b2bc2c 2226 raise_exception_err(env, EXCP0D_GPF, 0);
eaa728ee
FB		 2227 }
2228 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
2229 cpu_x86_set_cpl(env, 0);
2436b61a
AZ		 2230
2231#ifdef TARGET_X86_64
2232 if (env->hflags & HF_LMA_MASK) {
2233 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2234 0, 0xffffffff,
2235 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2236 DESC_S_MASK |
20054ef0
BS		 2237 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2238 DESC_L_MASK);
2436b61a
AZ		 2239 } else
2240#endif
2241 {
2242 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2243 0, 0xffffffff,
2244 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2245 DESC_S_MASK |
2246 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2247 }
eaa728ee
FB		 2248 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2249 0, 0xffffffff,
2250 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2251 DESC_S_MASK |
2252 DESC_W_MASK | DESC_A_MASK);
08b3ded6 2253 env->regs[R_ESP] = env->sysenter_esp;
eaa728ee
FB		 2254 EIP = env->sysenter_eip;
2255}
2256
2999a0b2 2257void helper_sysexit(CPUX86State *env, int dflag)
eaa728ee
FB		 2258{
2259 int cpl;
2260
2261 cpl = env->hflags & HF_CPL_MASK;
2262 if (env->sysenter_cs == 0 || cpl != 0) {
77b2bc2c 2263 raise_exception_err(env, EXCP0D_GPF, 0);
eaa728ee
FB		 2264 }
2265 cpu_x86_set_cpl(env, 3);
2436b61a
AZ		 2266#ifdef TARGET_X86_64
2267 if (dflag == 2) {
20054ef0
BS		 2268 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 32) & 0xfffc) |
2269 3, 0, 0xffffffff,
2436b61a
AZ		 2270 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2271 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
20054ef0
BS		 2272 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2273 DESC_L_MASK);
2274 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 40) & 0xfffc) |
2275 3, 0, 0xffffffff,
2436b61a
AZ		 2276 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2277 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2278 DESC_W_MASK | DESC_A_MASK);
2279 } else
2280#endif
2281 {
20054ef0
BS		 2282 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) |
2283 3, 0, 0xffffffff,
2436b61a
AZ		 2284 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2285 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2286 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
20054ef0
BS		 2287 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) |
2288 3, 0, 0xffffffff,
2436b61a
AZ		 2289 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2290 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2291 DESC_W_MASK | DESC_A_MASK);
2292 }
08b3ded6 2293 env->regs[R_ESP] = env->regs[R_ECX];
00f5e6f2 2294 EIP = env->regs[R_EDX];
eaa728ee
FB		 2295}
2296
2999a0b2 2297target_ulong helper_lsl(CPUX86State *env, target_ulong selector1)
eaa728ee
FB		 2298{
2299 unsigned int limit;
2300 uint32_t e1, e2, eflags, selector;
2301 int rpl, dpl, cpl, type;
2302
2303 selector = selector1 & 0xffff;
f0967a1a 2304 eflags = cpu_cc_compute_all(env, CC_OP);
20054ef0 2305 if ((selector & 0xfffc) == 0) {
dc1ded53 2306 goto fail;
20054ef0 2307 }
2999a0b2 2308 if (load_segment(env, &e1, &e2, selector) != 0) {
eaa728ee 2309 goto fail;
20054ef0 2310 }
eaa728ee
FB		 2311 rpl = selector & 3;
2312 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2313 cpl = env->hflags & HF_CPL_MASK;
2314 if (e2 & DESC_S_MASK) {
2315 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2316 /* conforming */
2317 } else {
20054ef0 2318 if (dpl < cpl || dpl < rpl) {
eaa728ee 2319 goto fail;
20054ef0 2320 }
eaa728ee
FB		 2321 }
2322 } else {
2323 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
20054ef0 2324 switch (type) {
eaa728ee
FB		 2325 case 1:
2326 case 2:
2327 case 3:
2328 case 9:
2329 case 11:
2330 break;
2331 default:
2332 goto fail;
2333 }
2334 if (dpl < cpl || dpl < rpl) {
2335 fail:
2336 CC_SRC = eflags & ~CC_Z;
2337 return 0;
2338 }
2339 }
2340 limit = get_seg_limit(e1, e2);
2341 CC_SRC = eflags | CC_Z;
2342 return limit;
2343}
2344
2999a0b2 2345target_ulong helper_lar(CPUX86State *env, target_ulong selector1)
eaa728ee
FB		 2346{
2347 uint32_t e1, e2, eflags, selector;
2348 int rpl, dpl, cpl, type;
2349
2350 selector = selector1 & 0xffff;
f0967a1a 2351 eflags = cpu_cc_compute_all(env, CC_OP);
20054ef0 2352 if ((selector & 0xfffc) == 0) {
eaa728ee 2353 goto fail;
20054ef0 2354 }
2999a0b2 2355 if (load_segment(env, &e1, &e2, selector) != 0) {
eaa728ee 2356 goto fail;
20054ef0 2357 }
eaa728ee
FB		 2358 rpl = selector & 3;
2359 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2360 cpl = env->hflags & HF_CPL_MASK;
2361 if (e2 & DESC_S_MASK) {
2362 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2363 /* conforming */
2364 } else {
20054ef0 2365 if (dpl < cpl || dpl < rpl) {
eaa728ee 2366 goto fail;
20054ef0 2367 }
eaa728ee
FB		 2368 }
2369 } else {
2370 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
20054ef0 2371 switch (type) {
eaa728ee
FB		 2372 case 1:
2373 case 2:
2374 case 3:
2375 case 4:
2376 case 5:
2377 case 9:
2378 case 11:
2379 case 12:
2380 break;
2381 default:
2382 goto fail;
2383 }
2384 if (dpl < cpl || dpl < rpl) {
2385 fail:
2386 CC_SRC = eflags & ~CC_Z;
2387 return 0;
2388 }
2389 }
2390 CC_SRC = eflags | CC_Z;
2391 return e2 & 0x00f0ff00;
2392}
2393
2999a0b2 2394void helper_verr(CPUX86State *env, target_ulong selector1)
eaa728ee
FB		 2395{
2396 uint32_t e1, e2, eflags, selector;
2397 int rpl, dpl, cpl;
2398
2399 selector = selector1 & 0xffff;
f0967a1a 2400 eflags = cpu_cc_compute_all(env, CC_OP);
20054ef0 2401 if ((selector & 0xfffc) == 0) {
eaa728ee 2402 goto fail;
20054ef0 2403 }
2999a0b2 2404 if (load_segment(env, &e1, &e2, selector) != 0) {
eaa728ee 2405 goto fail;
20054ef0
BS		 2406 }
2407 if (!(e2 & DESC_S_MASK)) {
eaa728ee 2408 goto fail;
20054ef0 2409 }
eaa728ee
FB		 2410 rpl = selector & 3;
2411 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2412 cpl = env->hflags & HF_CPL_MASK;
2413 if (e2 & DESC_CS_MASK) {
20054ef0 2414 if (!(e2 & DESC_R_MASK)) {
eaa728ee 2415 goto fail;
20054ef0 2416 }
eaa728ee 2417 if (!(e2 & DESC_C_MASK)) {
20054ef0 2418 if (dpl < cpl || dpl < rpl) {
eaa728ee 2419 goto fail;
20054ef0 2420 }
eaa728ee
FB		 2421 }
2422 } else {
2423 if (dpl < cpl || dpl < rpl) {
2424 fail:
2425 CC_SRC = eflags & ~CC_Z;
2426 return;
2427 }
2428 }
2429 CC_SRC = eflags | CC_Z;
2430}
2431
2999a0b2 2432void helper_verw(CPUX86State *env, target_ulong selector1)
eaa728ee
FB		 2433{
2434 uint32_t e1, e2, eflags, selector;
2435 int rpl, dpl, cpl;
2436
2437 selector = selector1 & 0xffff;
f0967a1a 2438 eflags = cpu_cc_compute_all(env, CC_OP);
20054ef0 2439 if ((selector & 0xfffc) == 0) {
eaa728ee 2440 goto fail;
20054ef0 2441 }
2999a0b2 2442 if (load_segment(env, &e1, &e2, selector) != 0) {
eaa728ee 2443 goto fail;
20054ef0
BS		 2444 }
2445 if (!(e2 & DESC_S_MASK)) {
eaa728ee 2446 goto fail;
20054ef0 2447 }
eaa728ee
FB		 2448 rpl = selector & 3;
2449 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2450 cpl = env->hflags & HF_CPL_MASK;
2451 if (e2 & DESC_CS_MASK) {
2452 goto fail;
2453 } else {
20054ef0 2454 if (dpl < cpl || dpl < rpl) {
eaa728ee 2455 goto fail;
20054ef0 2456 }
eaa728ee
FB		 2457 if (!(e2 & DESC_W_MASK)) {
2458 fail:
2459 CC_SRC = eflags & ~CC_Z;
2460 return;
2461 }
2462 }
2463 CC_SRC = eflags | CC_Z;
2464}
2465
f299f437 2466#if defined(CONFIG_USER_ONLY)
2999a0b2 2467void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector)
eaa728ee 2468{
f299f437
BS		 2469 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
2470 selector &= 0xffff;
2471 cpu_x86_load_seg_cache(env, seg_reg, selector,
2472 (selector << 4), 0xffff, 0);
2473 } else {
2999a0b2 2474 helper_load_seg(env, seg_reg, selector);
13822781 2475 }
eaa728ee 2476}
eaa728ee 2477#endif
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