[qemu.git] / target-microblaze / op_helper.c

/*
 *  Microblaze helper routines.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias <[email protected]>.
 *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
#include "exec/cpu_ldst.h"

#define D(x)

#if !defined(CONFIG_USER_ONLY)

/* Try to fill the TLB and return an exception if error. If retaddr is
 * NULL, it means that the function was called in C code (i.e. not
 * from generated code or from helper.c)
 */
void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
              uintptr_t retaddr)
{
    int ret;

    ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            cpu_restore_state(cs, retaddr);
        }
        cpu_loop_exit(cs);
    }
}
#endif

void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
{
    int test = ctrl & STREAM_TEST;
    int atomic = ctrl & STREAM_ATOMIC;
    int control = ctrl & STREAM_CONTROL;
    int nonblock = ctrl & STREAM_NONBLOCK;
    int exception = ctrl & STREAM_EXCEPTION;

    qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
             id, data,
             test ? "t" : "",
             nonblock ? "n" : "",
             exception ? "e" : "",
             control ? "c" : "",
             atomic ? "a" : "");
}

uint32_t helper_get(uint32_t id, uint32_t ctrl)
{
    int test = ctrl & STREAM_TEST;
    int atomic = ctrl & STREAM_ATOMIC;
    int control = ctrl & STREAM_CONTROL;
    int nonblock = ctrl & STREAM_NONBLOCK;
    int exception = ctrl & STREAM_EXCEPTION;

    qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
             id,
             test ? "t" : "",
             nonblock ? "n" : "",
             exception ? "e" : "",
             control ? "c" : "",
             atomic ? "a" : "");
    return 0xdead0000 | id;
}

void helper_raise_exception(CPUMBState *env, uint32_t index)
{
    CPUState *cs = CPU(mb_env_get_cpu(env));

    cs->exception_index = index;
    cpu_loop_exit(cs);
}

void helper_debug(CPUMBState *env)
{
    int i;

    qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
    qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
             env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
             env->debug, env->imm, env->iflags);
    qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
             env->btaken, env->btarget,
             (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_EIP),
             (env->sregs[SR_MSR] & MSR_IE));
    for (i = 0; i < 32; i++) {
        qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
        if ((i + 1) % 4 == 0)
            qemu_log("\n");
    }
    qemu_log("\n\n");
}

static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
{
    uint32_t cout = 0;

    if ((b == ~0) && cin)
        cout = 1;
    else if ((~0 - a) < (b + cin))
        cout = 1;
    return cout;
}

uint32_t helper_cmp(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (b & 0x80000000);
    return t;
}

uint32_t helper_cmpu(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (a & 0x80000000);
    return t;
}

uint32_t helper_clz(uint32_t t0)
{
    return clz32(t0);
}

uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
{
    return compute_carry(a, b, cf);
}

static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
{
    if (b == 0) {
        env->sregs[SR_MSR] |= MSR_DZ;

        if ((env->sregs[SR_MSR] & MSR_EE)
            && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DIVZERO;
            helper_raise_exception(env, EXCP_HW_EXCP);
        }
        return 0;
    }
    env->sregs[SR_MSR] &= ~MSR_DZ;
    return 1;
}

uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
{
    if (!div_prepare(env, a, b)) {
        return 0;
    }
    return (int32_t)a / (int32_t)b;
}

uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
{
    if (!div_prepare(env, a, b)) {
        return 0;
    }
    return a / b;
}

/* raise FPU exception.  */
static void raise_fpu_exception(CPUMBState *env)
{
    env->sregs[SR_ESR] = ESR_EC_FPU;
    helper_raise_exception(env, EXCP_HW_EXCP);
}

static void update_fpu_flags(CPUMBState *env, int flags)
{
    int raise = 0;

    if (flags & float_flag_invalid) {
        env->sregs[SR_FSR] |= FSR_IO;
        raise = 1;
    }
    if (flags & float_flag_divbyzero) {
        env->sregs[SR_FSR] |= FSR_DZ;
        raise = 1;
    }
    if (flags & float_flag_overflow) {
        env->sregs[SR_FSR] |= FSR_OF;
        raise = 1;
    }
    if (flags & float_flag_underflow) {
        env->sregs[SR_FSR] |= FSR_UF;
        raise = 1;
    }
    if (raise
        && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
        && (env->sregs[SR_MSR] & MSR_EE)) {
        raise_fpu_exception(env);
    }
}

uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_add(fa.f, fb.f, &env->fp_status);

    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);
    return fd.l;
}

uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);
    return fd.l;
}

uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return fd.l;
}

uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_div(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return fd.l;
}

uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    uint32_t r = 0;

    fa.l = a;
    fb.l = b;

    if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
        update_fpu_flags(env, float_flag_invalid);
        r = 1;
    }

    if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
        r = 1;
    }

    return r;
}

uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_lt(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_le(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);


    return r;
}

uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);
    return r;
}

uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_flt(CPUMBState *env, uint32_t a)
{
    CPU_FloatU fd, fa;

    fa.l = a;
    fd.f = int32_to_float32(fa.l, &env->fp_status);
    return fd.l;
}

uint32_t helper_fint(CPUMBState *env, uint32_t a)
{
    CPU_FloatU fa;
    uint32_t r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    r = float32_to_int32(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return r;
}

uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
{
    CPU_FloatU fd, fa;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fd.l = float32_sqrt(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return fd.l;
}

uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
{
    unsigned int i;
    uint32_t mask = 0xff000000;

    for (i = 0; i < 4; i++) {
        if ((a & mask) == (b & mask))
            return i + 1;
        mask >>= 8;
    }
    return 0;
}

void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
                     uint32_t mask)
{
    if (addr & mask) {
            qemu_log_mask(CPU_LOG_INT,
                          "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
                          addr, mask, wr, dr);
            env->sregs[SR_EAR] = addr;
            env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
                                 | (dr & 31) << 5;
            if (mask == 3) {
                env->sregs[SR_ESR] |= 1 << 11;
            }
            if (!(env->sregs[SR_MSR] & MSR_EE)) {
                return;
            }
            helper_raise_exception(env, EXCP_HW_EXCP);
    }
}

void helper_stackprot(CPUMBState *env, uint32_t addr)
{
    if (addr < env->slr || addr > env->shr) {
        qemu_log("Stack protector violation at %x %x %x\n",
                 addr, env->slr, env->shr);
        env->sregs[SR_EAR] = addr;
        env->sregs[SR_ESR] = ESR_EC_STACKPROT;
        helper_raise_exception(env, EXCP_HW_EXCP);
    }
}

#if !defined(CONFIG_USER_ONLY)
/* Writes/reads to the MMU's special regs end up here.  */
uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
{
    return mmu_read(env, rn);
}

void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
{
    mmu_write(env, rn, v);
}

void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
                              bool is_write, bool is_exec, int is_asi,
                              unsigned size)
{
    MicroBlazeCPU *cpu;
    CPUMBState *env;

    qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
             addr, is_write ? 1 : 0, is_exec ? 1 : 0);
    if (cs == NULL) {
        return;
    }
    cpu = MICROBLAZE_CPU(cs);
    env = &cpu->env;
    if (!(env->sregs[SR_MSR] & MSR_EE)) {
        return;
    }

    env->sregs[SR_EAR] = addr;
    if (is_exec) {
        if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
            helper_raise_exception(env, EXCP_HW_EXCP);
        }
    } else {
        if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
            helper_raise_exception(env, EXCP_HW_EXCP);
        }
    }
}
#endif
Commit	Line	Data
4acb54ba EI	1	/*
	2	* Microblaze helper routines.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias <[email protected]>.
dadc1064	5	* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
4acb54ba EI	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba EI	19	*/
4acb54ba EI	20
3e457172	21	#include "cpu.h"
2ef6175a	22	#include "exec/helper-proto.h"
1de7afc9	23	#include "qemu/host-utils.h"
f08b6170	24	#include "exec/cpu_ldst.h"
4acb54ba EI	25
	26	#define D(x)
	27
	28	#if !defined(CONFIG_USER_ONLY)
3e457172	29
4acb54ba	30	/* Try to fill the TLB and return an exception if error. If retaddr is
d5a11fef AF	31	* NULL, it means that the function was called in C code (i.e. not
	32	* from generated code or from helper.c)
	33	*/
	34	void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
20503968	35	uintptr_t retaddr)
4acb54ba	36	{
4acb54ba EI	37	int ret;
4acb54ba EI	38
d5a11fef	39	ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
4acb54ba EI	40	if (unlikely(ret)) {
	41	if (retaddr) {
	42	/* now we have a real cpu fault */
3f38f309	43	cpu_restore_state(cs, retaddr);
4acb54ba	44	}
5638d180	45	cpu_loop_exit(cs);
4acb54ba	46	}
4acb54ba EI	47	}
	48	#endif
	49
6d76d23e EI	50	void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
	51	{
	52	int test = ctrl & STREAM_TEST;
	53	int atomic = ctrl & STREAM_ATOMIC;
	54	int control = ctrl & STREAM_CONTROL;
	55	int nonblock = ctrl & STREAM_NONBLOCK;
	56	int exception = ctrl & STREAM_EXCEPTION;
	57
	58	qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
	59	id, data,
	60	test ? "t" : "",
	61	nonblock ? "n" : "",
	62	exception ? "e" : "",
	63	control ? "c" : "",
	64	atomic ? "a" : "");
	65	}
	66
	67	uint32_t helper_get(uint32_t id, uint32_t ctrl)
	68	{
	69	int test = ctrl & STREAM_TEST;
	70	int atomic = ctrl & STREAM_ATOMIC;
	71	int control = ctrl & STREAM_CONTROL;
	72	int nonblock = ctrl & STREAM_NONBLOCK;
	73	int exception = ctrl & STREAM_EXCEPTION;
	74
	75	qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
	76	id,
	77	test ? "t" : "",
	78	nonblock ? "n" : "",
	79	exception ? "e" : "",
	80	control ? "c" : "",
	81	atomic ? "a" : "");
	82	return 0xdead0000 \| id;
	83	}
	84
64254eba	85	void helper_raise_exception(CPUMBState *env, uint32_t index)
4acb54ba	86	{
27103424 AF	87	CPUState *cs = CPU(mb_env_get_cpu(env));
	88
	89	cs->exception_index = index;
5638d180	90	cpu_loop_exit(cs);
4acb54ba EI	91	}
4acb54ba EI	92
64254eba	93	void helper_debug(CPUMBState *env)
4acb54ba EI	94	{
	95	int i;
	96
	97	qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
4c24aa0a MS	98	qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
4c24aa0a MS	99	env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
17c52a43 EI	100	env->debug, env->imm, env->iflags);
	101	qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
	102	env->btaken, env->btarget,
	103	(env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
	104	(env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
	105	(env->sregs[SR_MSR] & MSR_EIP),
	106	(env->sregs[SR_MSR] & MSR_IE));
4acb54ba EI	107	for (i = 0; i < 32; i++) {
	108	qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
	109	if ((i + 1) % 4 == 0)
	110	qemu_log("\n");
	111	}
	112	qemu_log("\n\n");
	113	}
	114
	115	static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
	116	{
	117	uint32_t cout = 0;
	118
	119	if ((b == ~0) && cin)
	120	cout = 1;
	121	else if ((~0 - a) < (b + cin))
	122	cout = 1;
	123	return cout;
	124	}
	125
	126	uint32_t helper_cmp(uint32_t a, uint32_t b)
	127	{
	128	uint32_t t;
	129
	130	t = b + ~a + 1;
	131	if ((b & 0x80000000) ^ (a & 0x80000000))
	132	t = (t & 0x7fffffff) \| (b & 0x80000000);
	133	return t;
	134	}
	135
	136	uint32_t helper_cmpu(uint32_t a, uint32_t b)
	137	{
	138	uint32_t t;
	139
	140	t = b + ~a + 1;
	141	if ((b & 0x80000000) ^ (a & 0x80000000))
	142	t = (t & 0x7fffffff) \| (a & 0x80000000);
	143	return t;
	144	}
	145
48b5e96f EI	146	uint32_t helper_clz(uint32_t t0)
	147	{
	148	return clz32(t0);
	149	}
	150
5d0bb823	151	uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
4acb54ba	152	{
738c8b01	153	return compute_carry(a, b, cf);
4acb54ba EI	154	}
4acb54ba EI	155
64254eba	156	static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
4acb54ba EI	157	{
	158	if (b == 0) {
	159	env->sregs[SR_MSR] \|= MSR_DZ;
821ebb33 EI	160
	161	if ((env->sregs[SR_MSR] & MSR_EE)
	162	&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
	163	env->sregs[SR_ESR] = ESR_EC_DIVZERO;
64254eba	164	helper_raise_exception(env, EXCP_HW_EXCP);
821ebb33	165	}
4acb54ba EI	166	return 0;
	167	}
	168	env->sregs[SR_MSR] &= ~MSR_DZ;
	169	return 1;
	170	}
	171
64254eba	172	uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
4acb54ba	173	{
64254eba	174	if (!div_prepare(env, a, b)) {
4acb54ba	175	return 0;
64254eba	176	}
4acb54ba EI	177	return (int32_t)a / (int32_t)b;
	178	}
	179
64254eba	180	uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
4acb54ba	181	{
64254eba	182	if (!div_prepare(env, a, b)) {
4acb54ba	183	return 0;
64254eba	184	}
4acb54ba EI	185	return a / b;
	186	}
	187
97694c57	188	/* raise FPU exception. */
64254eba	189	static void raise_fpu_exception(CPUMBState *env)
97694c57 EI	190	{
97694c57 EI	191	env->sregs[SR_ESR] = ESR_EC_FPU;
64254eba	192	helper_raise_exception(env, EXCP_HW_EXCP);
97694c57 EI	193	}
97694c57 EI	194
64254eba	195	static void update_fpu_flags(CPUMBState *env, int flags)
97694c57 EI	196	{
	197	int raise = 0;
	198
	199	if (flags & float_flag_invalid) {
	200	env->sregs[SR_FSR] \|= FSR_IO;
	201	raise = 1;
	202	}
	203	if (flags & float_flag_divbyzero) {
	204	env->sregs[SR_FSR] \|= FSR_DZ;
	205	raise = 1;
	206	}
	207	if (flags & float_flag_overflow) {
	208	env->sregs[SR_FSR] \|= FSR_OF;
	209	raise = 1;
	210	}
	211	if (flags & float_flag_underflow) {
	212	env->sregs[SR_FSR] \|= FSR_UF;
	213	raise = 1;
	214	}
	215	if (raise
	216	&& (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
	217	&& (env->sregs[SR_MSR] & MSR_EE)) {
64254eba	218	raise_fpu_exception(env);
97694c57 EI	219	}
	220	}
	221
64254eba	222	uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	223	{
	224	CPU_FloatU fd, fa, fb;
	225	int flags;
	226
	227	set_float_exception_flags(0, &env->fp_status);
	228	fa.l = a;
	229	fb.l = b;
	230	fd.f = float32_add(fa.f, fb.f, &env->fp_status);
	231
	232	flags = get_float_exception_flags(&env->fp_status);
64254eba	233	update_fpu_flags(env, flags);
97694c57 EI	234	return fd.l;
	235	}
	236
64254eba	237	uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	238	{
	239	CPU_FloatU fd, fa, fb;
	240	int flags;
	241
	242	set_float_exception_flags(0, &env->fp_status);
	243	fa.l = a;
	244	fb.l = b;
	245	fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
	246	flags = get_float_exception_flags(&env->fp_status);
64254eba	247	update_fpu_flags(env, flags);
97694c57 EI	248	return fd.l;
	249	}
	250
64254eba	251	uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	252	{
	253	CPU_FloatU fd, fa, fb;
	254	int flags;
	255
	256	set_float_exception_flags(0, &env->fp_status);
	257	fa.l = a;
	258	fb.l = b;
	259	fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
	260	flags = get_float_exception_flags(&env->fp_status);
64254eba	261	update_fpu_flags(env, flags);
97694c57 EI	262
	263	return fd.l;
	264	}
	265
64254eba	266	uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	267	{
	268	CPU_FloatU fd, fa, fb;
	269	int flags;
	270
	271	set_float_exception_flags(0, &env->fp_status);
	272	fa.l = a;
	273	fb.l = b;
	274	fd.f = float32_div(fb.f, fa.f, &env->fp_status);
	275	flags = get_float_exception_flags(&env->fp_status);
64254eba	276	update_fpu_flags(env, flags);
97694c57 EI	277
	278	return fd.l;
	279	}
	280
64254eba	281	uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
97694c57	282	{
ef9d48da EI	283	CPU_FloatU fa, fb;
	284	uint32_t r = 0;
	285
	286	fa.l = a;
	287	fb.l = b;
	288
	289	if (float32_is_signaling_nan(fa.f) \|\| float32_is_signaling_nan(fb.f)) {
64254eba	290	update_fpu_flags(env, float_flag_invalid);
ef9d48da EI	291	r = 1;
	292	}
	293
18569871	294	if (float32_is_quiet_nan(fa.f) \|\| float32_is_quiet_nan(fb.f)) {
ef9d48da EI	295	r = 1;
	296	}
	297
	298	return r;
97694c57 EI	299	}
97694c57 EI	300
64254eba	301	uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	302	{
	303	CPU_FloatU fa, fb;
	304	int r;
	305	int flags;
	306
	307	set_float_exception_flags(0, &env->fp_status);
	308	fa.l = a;
	309	fb.l = b;
	310	r = float32_lt(fb.f, fa.f, &env->fp_status);
	311	flags = get_float_exception_flags(&env->fp_status);
64254eba	312	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	313
	314	return r;
	315	}
	316
64254eba	317	uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	318	{
	319	CPU_FloatU fa, fb;
	320	int flags;
	321	int r;
	322
	323	set_float_exception_flags(0, &env->fp_status);
	324	fa.l = a;
	325	fb.l = b;
211315fb	326	r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
97694c57	327	flags = get_float_exception_flags(&env->fp_status);
64254eba	328	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	329
	330	return r;
	331	}
	332
64254eba	333	uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	334	{
	335	CPU_FloatU fa, fb;
	336	int flags;
	337	int r;
	338
	339	fa.l = a;
	340	fb.l = b;
	341	set_float_exception_flags(0, &env->fp_status);
	342	r = float32_le(fa.f, fb.f, &env->fp_status);
	343	flags = get_float_exception_flags(&env->fp_status);
64254eba	344	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	345
	346
	347	return r;
	348	}
	349
64254eba	350	uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	351	{
	352	CPU_FloatU fa, fb;
	353	int flags, r;
	354
	355	fa.l = a;
	356	fb.l = b;
	357	set_float_exception_flags(0, &env->fp_status);
	358	r = float32_lt(fa.f, fb.f, &env->fp_status);
	359	flags = get_float_exception_flags(&env->fp_status);
64254eba	360	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	361	return r;
	362	}
	363
64254eba	364	uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	365	{
	366	CPU_FloatU fa, fb;
	367	int flags, r;
	368
	369	fa.l = a;
	370	fb.l = b;
	371	set_float_exception_flags(0, &env->fp_status);
211315fb	372	r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
97694c57	373	flags = get_float_exception_flags(&env->fp_status);
64254eba	374	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	375
	376	return r;
	377	}
	378
64254eba	379	uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	380	{
	381	CPU_FloatU fa, fb;
	382	int flags, r;
	383
	384	fa.l = a;
	385	fb.l = b;
	386	set_float_exception_flags(0, &env->fp_status);
	387	r = !float32_lt(fa.f, fb.f, &env->fp_status);
	388	flags = get_float_exception_flags(&env->fp_status);
64254eba	389	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	390
	391	return r;
	392	}
	393
64254eba	394	uint32_t helper_flt(CPUMBState *env, uint32_t a)
97694c57 EI	395	{
	396	CPU_FloatU fd, fa;
	397
	398	fa.l = a;
	399	fd.f = int32_to_float32(fa.l, &env->fp_status);
	400	return fd.l;
	401	}
	402
64254eba	403	uint32_t helper_fint(CPUMBState *env, uint32_t a)
97694c57 EI	404	{
	405	CPU_FloatU fa;
	406	uint32_t r;
	407	int flags;
	408
	409	set_float_exception_flags(0, &env->fp_status);
	410	fa.l = a;
	411	r = float32_to_int32(fa.f, &env->fp_status);
	412	flags = get_float_exception_flags(&env->fp_status);
64254eba	413	update_fpu_flags(env, flags);
97694c57 EI	414
	415	return r;
	416	}
	417
64254eba	418	uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
97694c57 EI	419	{
	420	CPU_FloatU fd, fa;
	421	int flags;
	422
	423	set_float_exception_flags(0, &env->fp_status);
	424	fa.l = a;
	425	fd.l = float32_sqrt(fa.f, &env->fp_status);
	426	flags = get_float_exception_flags(&env->fp_status);
64254eba	427	update_fpu_flags(env, flags);
97694c57 EI	428
	429	return fd.l;
	430	}
	431
4acb54ba EI	432	uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
	433	{
	434	unsigned int i;
	435	uint32_t mask = 0xff000000;
	436
	437	for (i = 0; i < 4; i++) {
	438	if ((a & mask) == (b & mask))
	439	return i + 1;
	440	mask >>= 8;
	441	}
	442	return 0;
	443	}
	444
64254eba BS	445	void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
64254eba BS	446	uint32_t mask)
968a40f6	447	{
968a40f6	448	if (addr & mask) {
97f90cbf EI	449	qemu_log_mask(CPU_LOG_INT,
	450	"unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
	451	addr, mask, wr, dr);
	452	env->sregs[SR_EAR] = addr;
968a40f6 EI	453	env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA \| (wr << 10) \
968a40f6 EI	454	\| (dr & 31) << 5;
3aa80988	455	if (mask == 3) {
968a40f6 EI	456	env->sregs[SR_ESR] \|= 1 << 11;
968a40f6 EI	457	}
97f90cbf EI	458	if (!(env->sregs[SR_MSR] & MSR_EE)) {
	459	return;
	460	}
64254eba	461	helper_raise_exception(env, EXCP_HW_EXCP);
968a40f6 EI	462	}
	463	}
	464
64254eba	465	void helper_stackprot(CPUMBState *env, uint32_t addr)
5818dee5 EI	466	{
5818dee5 EI	467	if (addr < env->slr \|\| addr > env->shr) {
53432dc9 AF	468	qemu_log("Stack protector violation at %x %x %x\n",
	469	addr, env->slr, env->shr);
	470	env->sregs[SR_EAR] = addr;
	471	env->sregs[SR_ESR] = ESR_EC_STACKPROT;
	472	helper_raise_exception(env, EXCP_HW_EXCP);
5818dee5 EI	473	}
	474	}
	475
4acb54ba EI	476	#if !defined(CONFIG_USER_ONLY)
4acb54ba EI	477	/* Writes/reads to the MMU's special regs end up here. */
64254eba	478	uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
4acb54ba EI	479	{
	480	return mmu_read(env, rn);
	481	}
	482
64254eba	483	void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
4acb54ba EI	484	{
	485	mmu_write(env, rn, v);
	486	}
faed1c2a	487
c658b94f AF	488	void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
	489	bool is_write, bool is_exec, int is_asi,
	490	unsigned size)
faed1c2a	491	{
c658b94f AF	492	MicroBlazeCPU *cpu;
	493	CPUMBState *env;
	494
97f90cbf	495	qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
c658b94f AF	496	addr, is_write ? 1 : 0, is_exec ? 1 : 0);
	497	if (cs == NULL) {
	498	return;
	499	}
	500	cpu = MICROBLAZE_CPU(cs);
	501	env = &cpu->env;
	502	if (!(env->sregs[SR_MSR] & MSR_EE)) {
faed1c2a EI	503	return;
	504	}
	505
97f90cbf	506	env->sregs[SR_EAR] = addr;
faed1c2a	507	if (is_exec) {
97f90cbf	508	if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
faed1c2a	509	env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
64254eba	510	helper_raise_exception(env, EXCP_HW_EXCP);
faed1c2a EI	511	}
faed1c2a EI	512	} else {
97f90cbf	513	if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
faed1c2a	514	env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
64254eba	515	helper_raise_exception(env, EXCP_HW_EXCP);
faed1c2a EI	516	}
	517	}
	518	}
3c7b48b7	519	#endif