[qemu.git] / target-microblaze / op_helper.c

/*
 *  Microblaze helper routines.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias <[email protected]>.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <assert.h>
#include "exec.h"
#include "helper.h"
#include "host-utils.h"

#define D(x)

#if !defined(CONFIG_USER_ONLY)
#define MMUSUFFIX _mmu
#define SHIFT 0
#include "softmmu_template.h"
#define SHIFT 1
#include "softmmu_template.h"
#define SHIFT 2
#include "softmmu_template.h"
#define SHIFT 3
#include "softmmu_template.h"

/* Try to fill the TLB and return an exception if error. If retaddr is
   NULL, it means that the function was called in C code (i.e. not
   from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
{
    TranslationBlock *tb;
    CPUState *saved_env;
    unsigned long pc;
    int ret;

    /* XXX: hack to restore env in all cases, even if not called from
       generated code */
    saved_env = env;
    env = cpu_single_env;

    ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            pc = (unsigned long)retaddr;
            tb = tb_find_pc(pc);
            if (tb) {
                /* the PC is inside the translated code. It means that we have
                   a virtual CPU fault */
                cpu_restore_state(tb, env, pc, NULL);
            }
        }
        cpu_loop_exit();
    }
    env = saved_env;
}
#endif

void helper_raise_exception(uint32_t index)
{
    env->exception_index = index;
    cpu_loop_exit();
}

void helper_debug(void)
{
    int i;

    qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
    qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
             env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
             env->debug, env->imm, env->iflags);
    qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
             env->btaken, env->btarget,
             (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_EIP),
             (env->sregs[SR_MSR] & MSR_IE));
    for (i = 0; i < 32; i++) {
        qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
        if ((i + 1) % 4 == 0)
            qemu_log("\n");
    }
    qemu_log("\n\n");
}

static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
{
    uint32_t cout = 0;

    if ((b == ~0) && cin)
        cout = 1;
    else if ((~0 - a) < (b + cin))
        cout = 1;
    return cout;
}

uint32_t helper_cmp(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (b & 0x80000000);
    return t;
}

uint32_t helper_cmpu(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (a & 0x80000000);
    return t;
}

uint32_t helper_addkc(uint32_t a, uint32_t b, uint32_t cf)
{
    uint32_t d, ncf;

    d = a + b + cf;

    ncf = compute_carry(a, b, cf);
    return ncf;
}

static inline int div_prepare(uint32_t a, uint32_t b)
{
    if (b == 0) {
        env->sregs[SR_MSR] |= MSR_DZ;

        if ((env->sregs[SR_MSR] & MSR_EE)
            && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DIVZERO;
            helper_raise_exception(EXCP_HW_EXCP);
        }
        return 0;
    }
    env->sregs[SR_MSR] &= ~MSR_DZ;
    return 1;
}

uint32_t helper_divs(uint32_t a, uint32_t b)
{
    if (!div_prepare(a, b))
        return 0;
    return (int32_t)a / (int32_t)b;
}

uint32_t helper_divu(uint32_t a, uint32_t b)
{
    if (!div_prepare(a, b))
        return 0;
    return a / b;
}

/* raise FPU exception.  */
static void raise_fpu_exception(void)
{
    env->sregs[SR_ESR] = ESR_EC_FPU;
    helper_raise_exception(EXCP_HW_EXCP);
}

static void update_fpu_flags(int flags)
{
    int raise = 0;

    if (flags & float_flag_invalid) {
        env->sregs[SR_FSR] |= FSR_IO;
        raise = 1;
    }
    if (flags & float_flag_divbyzero) {
        env->sregs[SR_FSR] |= FSR_DZ;
        raise = 1;
    }
    if (flags & float_flag_overflow) {
        env->sregs[SR_FSR] |= FSR_OF;
        raise = 1;
    }
    if (flags & float_flag_underflow) {
        env->sregs[SR_FSR] |= FSR_UF;
        raise = 1;
    }
    if (raise
        && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
        && (env->sregs[SR_MSR] & MSR_EE)) {
        raise_fpu_exception();
    }
}

uint32_t helper_fadd(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_add(fa.f, fb.f, &env->fp_status);

    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);
    return fd.l;
}

uint32_t helper_frsub(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);
    return fd.l;
}

uint32_t helper_fmul(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return fd.l;
}

uint32_t helper_fdiv(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_div(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return fd.l;
}

uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    uint32_t r = 0;

    fa.l = a;
    fb.l = b;

    if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
        update_fpu_flags(float_flag_invalid);
        r = 1;
    }

    if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
        r = 1;
    }

    return r;
}

uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_lt(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_eq(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_le(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);


    return r;
}

uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);
    return r;
}

uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_eq(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_flt(uint32_t a)
{
    CPU_FloatU fd, fa;

    fa.l = a;
    fd.f = int32_to_float32(fa.l, &env->fp_status);
    return fd.l;
}

uint32_t helper_fint(uint32_t a)
{
    CPU_FloatU fa;
    uint32_t r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    r = float32_to_int32(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return r;
}

uint32_t helper_fsqrt(uint32_t a)
{
    CPU_FloatU fd, fa;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fd.l = float32_sqrt(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return fd.l;
}

uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
{
    unsigned int i;
    uint32_t mask = 0xff000000;

    for (i = 0; i < 4; i++) {
        if ((a & mask) == (b & mask))
            return i + 1;
        mask >>= 8;
    }
    return 0;
}

void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
{
    if (addr & mask) {
            qemu_log_mask(CPU_LOG_INT,
                          "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
                          addr, mask, wr, dr);
            env->sregs[SR_EAR] = addr;
            env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
                                 | (dr & 31) << 5;
            if (mask == 3) {
                env->sregs[SR_ESR] |= 1 << 11;
            }
            if (!(env->sregs[SR_MSR] & MSR_EE)) {
                return;
            }
            helper_raise_exception(EXCP_HW_EXCP);
    }
}

#if !defined(CONFIG_USER_ONLY)
/* Writes/reads to the MMU's special regs end up here.  */
uint32_t helper_mmu_read(uint32_t rn)
{
    return mmu_read(env, rn);
}

void helper_mmu_write(uint32_t rn, uint32_t v)
{
    mmu_write(env, rn, v);
}

void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                          int is_asi, int size)
{
    CPUState *saved_env;

    if (!cpu_single_env) {
        /* XXX: ???   */
        return;
    }

    /* XXX: hack to restore env in all cases, even if not called from
       generated code */
    saved_env = env;
    env = cpu_single_env;
    qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
             addr, is_write, is_exec);
    if (!(env->sregs[SR_MSR] & MSR_EE)) {
        env = saved_env;
        return;
    }

    env->sregs[SR_EAR] = addr;
    if (is_exec) {
        if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
            helper_raise_exception(EXCP_HW_EXCP);
        }
    } else {
        if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
            helper_raise_exception(EXCP_HW_EXCP);
        }
    }
    env = saved_env;
}
#endif
Commit	Line	Data
4acb54ba EI	1	/*
	2	* Microblaze helper routines.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias <[email protected]>.
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba EI	18	*/
	19
	20	#include <assert.h>
	21	#include "exec.h"
	22	#include "helper.h"
	23	#include "host-utils.h"
	24
	25	#define D(x)
	26
	27	#if !defined(CONFIG_USER_ONLY)
	28	#define MMUSUFFIX _mmu
	29	#define SHIFT 0
	30	#include "softmmu_template.h"
	31	#define SHIFT 1
	32	#include "softmmu_template.h"
	33	#define SHIFT 2
	34	#include "softmmu_template.h"
	35	#define SHIFT 3
	36	#include "softmmu_template.h"
	37
	38	/* Try to fill the TLB and return an exception if error. If retaddr is
	39	NULL, it means that the function was called in C code (i.e. not
	40	from generated code or from helper.c) */
	41	/* XXX: fix it to restore all registers */
	42	void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
	43	{
	44	TranslationBlock *tb;
	45	CPUState *saved_env;
	46	unsigned long pc;
	47	int ret;
	48
	49	/* XXX: hack to restore env in all cases, even if not called from
	50	generated code */
	51	saved_env = env;
	52	env = cpu_single_env;
	53
	54	ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
	55	if (unlikely(ret)) {
	56	if (retaddr) {
	57	/* now we have a real cpu fault */
	58	pc = (unsigned long)retaddr;
	59	tb = tb_find_pc(pc);
	60	if (tb) {
	61	/* the PC is inside the translated code. It means that we have
	62	a virtual CPU fault */
	63	cpu_restore_state(tb, env, pc, NULL);
	64	}
	65	}
	66	cpu_loop_exit();
	67	}
	68	env = saved_env;
	69	}
	70	#endif
	71
	72	void helper_raise_exception(uint32_t index)
	73	{
	74	env->exception_index = index;
	75	cpu_loop_exit();
	76	}
	77
	78	void helper_debug(void)
	79	{
	80	int i;
	81
82	qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
4c24aa0a MS	83	qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
4c24aa0a MS	84	env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
17c52a43 EI	85	env->debug, env->imm, env->iflags);
	86	qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
	87	env->btaken, env->btarget,
	88	(env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
	89	(env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
	90	(env->sregs[SR_MSR] & MSR_EIP),
	91	(env->sregs[SR_MSR] & MSR_IE));
4acb54ba EI	92	for (i = 0; i < 32; i++) {
	93	qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
	94	if ((i + 1) % 4 == 0)
	95	qemu_log("\n");
	96	}
	97	qemu_log("\n\n");
	98	}
	99
	100	static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
	101	{
	102	uint32_t cout = 0;
	103
	104	if ((b == ~0) && cin)
	105	cout = 1;
	106	else if ((~0 - a) < (b + cin))
	107	cout = 1;
	108	return cout;
	109	}
	110
	111	uint32_t helper_cmp(uint32_t a, uint32_t b)
	112	{
	113	uint32_t t;
	114
	115	t = b + ~a + 1;
	116	if ((b & 0x80000000) ^ (a & 0x80000000))
	117	t = (t & 0x7fffffff) \| (b & 0x80000000);
	118	return t;
	119	}
	120
	121	uint32_t helper_cmpu(uint32_t a, uint32_t b)
	122	{
	123	uint32_t t;
	124
	125	t = b + ~a + 1;
	126	if ((b & 0x80000000) ^ (a & 0x80000000))
	127	t = (t & 0x7fffffff) \| (a & 0x80000000);
	128	return t;
	129	}
	130
40cbf5b7	131	uint32_t helper_addkc(uint32_t a, uint32_t b, uint32_t cf)
4acb54ba	132	{
40cbf5b7	133	uint32_t d, ncf;
4acb54ba	134
4acb54ba EI	135	d = a + b + cf;
4acb54ba EI	136
40cbf5b7 EI	137	ncf = compute_carry(a, b, cf);
40cbf5b7 EI	138	return ncf;
4acb54ba EI	139	}
4acb54ba EI	140
4acb54ba EI	141	static inline int div_prepare(uint32_t a, uint32_t b)
	142	{
	143	if (b == 0) {
	144	env->sregs[SR_MSR] \|= MSR_DZ;
821ebb33 EI	145
	146	if ((env->sregs[SR_MSR] & MSR_EE)
	147	&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
	148	env->sregs[SR_ESR] = ESR_EC_DIVZERO;
	149	helper_raise_exception(EXCP_HW_EXCP);
	150	}
4acb54ba EI	151	return 0;
	152	}
	153	env->sregs[SR_MSR] &= ~MSR_DZ;
	154	return 1;
	155	}
	156
	157	uint32_t helper_divs(uint32_t a, uint32_t b)
	158	{
	159	if (!div_prepare(a, b))
	160	return 0;
	161	return (int32_t)a / (int32_t)b;
	162	}
	163
	164	uint32_t helper_divu(uint32_t a, uint32_t b)
	165	{
	166	if (!div_prepare(a, b))
	167	return 0;
	168	return a / b;
	169	}
	170
97694c57 EI	171	/* raise FPU exception. */
	172	static void raise_fpu_exception(void)
	173	{
	174	env->sregs[SR_ESR] = ESR_EC_FPU;
	175	helper_raise_exception(EXCP_HW_EXCP);
	176	}
	177
	178	static void update_fpu_flags(int flags)
	179	{
	180	int raise = 0;
	181
	182	if (flags & float_flag_invalid) {
	183	env->sregs[SR_FSR] \|= FSR_IO;
	184	raise = 1;
	185	}
	186	if (flags & float_flag_divbyzero) {
	187	env->sregs[SR_FSR] \|= FSR_DZ;
	188	raise = 1;
	189	}
	190	if (flags & float_flag_overflow) {
	191	env->sregs[SR_FSR] \|= FSR_OF;
	192	raise = 1;
	193	}
	194	if (flags & float_flag_underflow) {
	195	env->sregs[SR_FSR] \|= FSR_UF;
	196	raise = 1;
	197	}
	198	if (raise
	199	&& (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
	200	&& (env->sregs[SR_MSR] & MSR_EE)) {
	201	raise_fpu_exception();
	202	}
	203	}
	204
	205	uint32_t helper_fadd(uint32_t a, uint32_t b)
	206	{
	207	CPU_FloatU fd, fa, fb;
	208	int flags;
	209
	210	set_float_exception_flags(0, &env->fp_status);
	211	fa.l = a;
	212	fb.l = b;
	213	fd.f = float32_add(fa.f, fb.f, &env->fp_status);
	214
	215	flags = get_float_exception_flags(&env->fp_status);
	216	update_fpu_flags(flags);
	217	return fd.l;
	218	}
	219
	220	uint32_t helper_frsub(uint32_t a, uint32_t b)
	221	{
	222	CPU_FloatU fd, fa, fb;
	223	int flags;
	224
	225	set_float_exception_flags(0, &env->fp_status);
	226	fa.l = a;
	227	fb.l = b;
	228	fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
	229	flags = get_float_exception_flags(&env->fp_status);
	230	update_fpu_flags(flags);
	231	return fd.l;
	232	}
	233
	234	uint32_t helper_fmul(uint32_t a, uint32_t b)
235	{
236	CPU_FloatU fd, fa, fb;
237	int flags;
238
239	set_float_exception_flags(0, &env->fp_status);
240	fa.l = a;
241	fb.l = b;
242	fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
243	flags = get_float_exception_flags(&env->fp_status);
244	update_fpu_flags(flags);
245
246	return fd.l;
247	}
248
249	uint32_t helper_fdiv(uint32_t a, uint32_t b)
250	{
251	CPU_FloatU fd, fa, fb;
252	int flags;
253
254	set_float_exception_flags(0, &env->fp_status);
255	fa.l = a;
256	fb.l = b;
257	fd.f = float32_div(fb.f, fa.f, &env->fp_status);
258	flags = get_float_exception_flags(&env->fp_status);
259	update_fpu_flags(flags);
260
261	return fd.l;
262	}
263
264	uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
265	{
ef9d48da EI	266	CPU_FloatU fa, fb;
	267	uint32_t r = 0;
	268
	269	fa.l = a;
	270	fb.l = b;
	271
	272	if (float32_is_signaling_nan(fa.f) \|\| float32_is_signaling_nan(fb.f)) {
	273	update_fpu_flags(float_flag_invalid);
	274	r = 1;
	275	}
	276
18569871	277	if (float32_is_quiet_nan(fa.f) \|\| float32_is_quiet_nan(fb.f)) {
ef9d48da EI	278	r = 1;
	279	}
	280
	281	return r;
97694c57 EI	282	}
	283
	284	uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
	285	{
	286	CPU_FloatU fa, fb;
	287	int r;
	288	int flags;
	289
	290	set_float_exception_flags(0, &env->fp_status);
	291	fa.l = a;
	292	fb.l = b;
	293	r = float32_lt(fb.f, fa.f, &env->fp_status);
	294	flags = get_float_exception_flags(&env->fp_status);
	295	update_fpu_flags(flags & float_flag_invalid);
	296
	297	return r;
	298	}
	299
	300	uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
	301	{
	302	CPU_FloatU fa, fb;
	303	int flags;
	304	int r;
	305
	306	set_float_exception_flags(0, &env->fp_status);
	307	fa.l = a;
	308	fb.l = b;
	309	r = float32_eq(fa.f, fb.f, &env->fp_status);
	310	flags = get_float_exception_flags(&env->fp_status);
	311	update_fpu_flags(flags & float_flag_invalid);
	312
	313	return r;
	314	}
	315
	316	uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
	317	{
	318	CPU_FloatU fa, fb;
	319	int flags;
	320	int r;
	321
	322	fa.l = a;
	323	fb.l = b;
	324	set_float_exception_flags(0, &env->fp_status);
	325	r = float32_le(fa.f, fb.f, &env->fp_status);
	326	flags = get_float_exception_flags(&env->fp_status);
	327	update_fpu_flags(flags & float_flag_invalid);
	328
	329
	330	return r;
	331	}
	332
	333	uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
	334	{
	335	CPU_FloatU fa, fb;
	336	int flags, r;
	337
	338	fa.l = a;
	339	fb.l = b;
	340	set_float_exception_flags(0, &env->fp_status);
	341	r = float32_lt(fa.f, fb.f, &env->fp_status);
	342	flags = get_float_exception_flags(&env->fp_status);
	343	update_fpu_flags(flags & float_flag_invalid);
	344	return r;
	345	}
346
347	uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
348	{
349	CPU_FloatU fa, fb;
350	int flags, r;
351
352	fa.l = a;
353	fb.l = b;
354	set_float_exception_flags(0, &env->fp_status);
355	r = !float32_eq(fa.f, fb.f, &env->fp_status);
356	flags = get_float_exception_flags(&env->fp_status);
357	update_fpu_flags(flags & float_flag_invalid);
358
359	return r;
360	}
361
362	uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
363	{
364	CPU_FloatU fa, fb;
365	int flags, r;
366
367	fa.l = a;
368	fb.l = b;
369	set_float_exception_flags(0, &env->fp_status);
370	r = !float32_lt(fa.f, fb.f, &env->fp_status);
371	flags = get_float_exception_flags(&env->fp_status);
372	update_fpu_flags(flags & float_flag_invalid);
373
374	return r;
375	}
376
377	uint32_t helper_flt(uint32_t a)
378	{
379	CPU_FloatU fd, fa;
380
381	fa.l = a;
382	fd.f = int32_to_float32(fa.l, &env->fp_status);
383	return fd.l;
384	}
385
386	uint32_t helper_fint(uint32_t a)
387	{
388	CPU_FloatU fa;
389	uint32_t r;
390	int flags;
391
392	set_float_exception_flags(0, &env->fp_status);
393	fa.l = a;
394	r = float32_to_int32(fa.f, &env->fp_status);
395	flags = get_float_exception_flags(&env->fp_status);
396	update_fpu_flags(flags);
397
398	return r;
399	}
400
401	uint32_t helper_fsqrt(uint32_t a)
402	{
403	CPU_FloatU fd, fa;
404	int flags;
405
406	set_float_exception_flags(0, &env->fp_status);
407	fa.l = a;
408	fd.l = float32_sqrt(fa.f, &env->fp_status);
409	flags = get_float_exception_flags(&env->fp_status);
410	update_fpu_flags(flags);
411
412	return fd.l;
413	}
414
4acb54ba EI	415	uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
	416	{
	417	unsigned int i;
	418	uint32_t mask = 0xff000000;
	419
	420	for (i = 0; i < 4; i++) {
	421	if ((a & mask) == (b & mask))
	422	return i + 1;
	423	mask >>= 8;
	424	}
	425	return 0;
	426	}
	427
3aa80988	428	void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
968a40f6	429	{
968a40f6	430	if (addr & mask) {
97f90cbf EI	431	qemu_log_mask(CPU_LOG_INT,
	432	"unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
	433	addr, mask, wr, dr);
	434	env->sregs[SR_EAR] = addr;
968a40f6 EI	435	env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA \| (wr << 10) \
968a40f6 EI	436	\| (dr & 31) << 5;
3aa80988	437	if (mask == 3) {
968a40f6 EI	438	env->sregs[SR_ESR] \|= 1 << 11;
968a40f6 EI	439	}
97f90cbf EI	440	if (!(env->sregs[SR_MSR] & MSR_EE)) {
	441	return;
	442	}
968a40f6 EI	443	helper_raise_exception(EXCP_HW_EXCP);
	444	}
	445	}
	446
4acb54ba EI	447	#if !defined(CONFIG_USER_ONLY)
	448	/* Writes/reads to the MMU's special regs end up here. */
	449	uint32_t helper_mmu_read(uint32_t rn)
	450	{
	451	return mmu_read(env, rn);
	452	}
	453
	454	void helper_mmu_write(uint32_t rn, uint32_t v)
	455	{
	456	mmu_write(env, rn, v);
	457	}
faed1c2a	458
c227f099	459	void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
faed1c2a EI	460	int is_asi, int size)
	461	{
	462	CPUState *saved_env;
e1aa3254 EI	463
	464	if (!cpu_single_env) {
	465	/* XXX: ??? */
	466	return;
	467	}
	468
faed1c2a EI	469	/* XXX: hack to restore env in all cases, even if not called from
	470	generated code */
	471	saved_env = env;
	472	env = cpu_single_env;
97f90cbf	473	qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
faed1c2a EI	474	addr, is_write, is_exec);
faed1c2a EI	475	if (!(env->sregs[SR_MSR] & MSR_EE)) {
95b279de	476	env = saved_env;
faed1c2a EI	477	return;
	478	}
	479
97f90cbf	480	env->sregs[SR_EAR] = addr;
faed1c2a	481	if (is_exec) {
97f90cbf	482	if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
faed1c2a EI	483	env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
	484	helper_raise_exception(EXCP_HW_EXCP);
	485	}
	486	} else {
97f90cbf	487	if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
faed1c2a EI	488	env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
	489	helper_raise_exception(EXCP_HW_EXCP);
	490	}
	491	}
95b279de	492	env = saved_env;
faed1c2a	493	}
3c7b48b7	494	#endif