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Make tb_invalidate_phys_addr() take a MemTxAttrs argument
[qemu.git] / target / arm / kvm.c
CommitLineData
494b00c7
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1/*
2 * ARM implementation of KVM hooks
3 *
4 * Copyright Christoffer Dall 2009-2010
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 *
9 */
10
74c21bd0 11#include "qemu/osdep.h"
494b00c7 12#include <sys/ioctl.h>
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13
14#include <linux/kvm.h>
15
16#include "qemu-common.h"
17#include "qemu/timer.h"
2ecb2027 18#include "qemu/error-report.h"
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19#include "sysemu/sysemu.h"
20#include "sysemu/kvm.h"
eb035b48 21#include "kvm_arm.h"
494b00c7 22#include "cpu.h"
b05c81d2 23#include "trace.h"
38df27c8 24#include "internals.h"
bd2be150 25#include "hw/arm/arm.h"
b05c81d2 26#include "hw/pci/pci.h"
4c663752 27#include "exec/memattrs.h"
4344af65 28#include "exec/address-spaces.h"
15eafc2e 29#include "hw/boards.h"
03dd024f 30#include "qemu/log.h"
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31
32const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
33 KVM_CAP_LAST_INFO
34};
35
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36static bool cap_has_mp_state;
37
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38static ARMHostCPUFeatures arm_host_cpu_features;
39
228d5e04
PS
40int kvm_arm_vcpu_init(CPUState *cs)
41{
42 ARMCPU *cpu = ARM_CPU(cs);
43 struct kvm_vcpu_init init;
44
45 init.target = cpu->kvm_target;
46 memcpy(init.features, cpu->kvm_init_features, sizeof(init.features));
47
48 return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
49}
50
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51bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
52 int *fdarray,
53 struct kvm_vcpu_init *init)
54{
55 int ret, kvmfd = -1, vmfd = -1, cpufd = -1;
56
57 kvmfd = qemu_open("/dev/kvm", O_RDWR);
58 if (kvmfd < 0) {
59 goto err;
60 }
61 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0);
62 if (vmfd < 0) {
63 goto err;
64 }
65 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0);
66 if (cpufd < 0) {
67 goto err;
68 }
69
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70 if (!init) {
71 /* Caller doesn't want the VCPU to be initialized, so skip it */
72 goto finish;
73 }
74
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75 ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, init);
76 if (ret >= 0) {
77 ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
78 if (ret < 0) {
79 goto err;
80 }
2f340e9c 81 } else if (cpus_to_try) {
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82 /* Old kernel which doesn't know about the
83 * PREFERRED_TARGET ioctl: we know it will only support
84 * creating one kind of guest CPU which is its preferred
85 * CPU type.
86 */
87 while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) {
88 init->target = *cpus_to_try++;
89 memset(init->features, 0, sizeof(init->features));
90 ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
91 if (ret >= 0) {
92 break;
93 }
94 }
95 if (ret < 0) {
96 goto err;
97 }
2f340e9c
PX
98 } else {
99 /* Treat a NULL cpus_to_try argument the same as an empty
100 * list, which means we will fail the call since this must
101 * be an old kernel which doesn't support PREFERRED_TARGET.
102 */
103 goto err;
a96c0514
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104 }
105
2f340e9c 106finish:
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107 fdarray[0] = kvmfd;
108 fdarray[1] = vmfd;
109 fdarray[2] = cpufd;
110
111 return true;
112
113err:
114 if (cpufd >= 0) {
115 close(cpufd);
116 }
117 if (vmfd >= 0) {
118 close(vmfd);
119 }
120 if (kvmfd >= 0) {
121 close(kvmfd);
122 }
123
124 return false;
125}
126
127void kvm_arm_destroy_scratch_host_vcpu(int *fdarray)
128{
129 int i;
130
131 for (i = 2; i >= 0; i--) {
132 close(fdarray[i]);
133 }
134}
135
c4487d76 136void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
a96c0514 137{
c4487d76 138 CPUARMState *env = &cpu->env;
a96c0514 139
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140 if (!arm_host_cpu_features.dtb_compatible) {
141 if (!kvm_enabled() ||
142 !kvm_arm_get_host_cpu_features(&arm_host_cpu_features)) {
143 /* We can't report this error yet, so flag that we need to
144 * in arm_cpu_realizefn().
145 */
146 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
147 cpu->host_cpu_probe_failed = true;
148 return;
149 }
a96c0514 150 }
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151
152 cpu->kvm_target = arm_host_cpu_features.target;
153 cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;
154 env->features = arm_host_cpu_features.features;
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155}
156
b16565b3 157int kvm_arch_init(MachineState *ms, KVMState *s)
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158{
159 /* For ARM interrupt delivery is always asynchronous,
160 * whether we are using an in-kernel VGIC or not.
161 */
162 kvm_async_interrupts_allowed = true;
a96c0514 163
5d721b78
AG
164 /*
165 * PSCI wakes up secondary cores, so we always need to
166 * have vCPUs waiting in kernel space
167 */
168 kvm_halt_in_kernel_allowed = true;
169
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170 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
171
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172 return 0;
173}
174
175unsigned long kvm_arch_vcpu_id(CPUState *cpu)
176{
177 return cpu->cpu_index;
178}
179
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180/* We track all the KVM devices which need their memory addresses
181 * passing to the kernel in a list of these structures.
182 * When board init is complete we run through the list and
183 * tell the kernel the base addresses of the memory regions.
184 * We use a MemoryListener to track mapping and unmapping of
185 * the regions during board creation, so the board models don't
186 * need to do anything special for the KVM case.
187 */
188typedef struct KVMDevice {
189 struct kvm_arm_device_addr kda;
1da41cc1 190 struct kvm_device_attr kdattr;
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191 MemoryRegion *mr;
192 QSLIST_ENTRY(KVMDevice) entries;
1da41cc1 193 int dev_fd;
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194} KVMDevice;
195
196static QSLIST_HEAD(kvm_devices_head, KVMDevice) kvm_devices_head;
197
198static void kvm_arm_devlistener_add(MemoryListener *listener,
199 MemoryRegionSection *section)
200{
201 KVMDevice *kd;
202
203 QSLIST_FOREACH(kd, &kvm_devices_head, entries) {
204 if (section->mr == kd->mr) {
205 kd->kda.addr = section->offset_within_address_space;
206 }
207 }
208}
209
210static void kvm_arm_devlistener_del(MemoryListener *listener,
211 MemoryRegionSection *section)
212{
213 KVMDevice *kd;
214
215 QSLIST_FOREACH(kd, &kvm_devices_head, entries) {
216 if (section->mr == kd->mr) {
217 kd->kda.addr = -1;
218 }
219 }
220}
221
222static MemoryListener devlistener = {
223 .region_add = kvm_arm_devlistener_add,
224 .region_del = kvm_arm_devlistener_del,
225};
226
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227static void kvm_arm_set_device_addr(KVMDevice *kd)
228{
229 struct kvm_device_attr *attr = &kd->kdattr;
230 int ret;
231
232 /* If the device control API is available and we have a device fd on the
233 * KVMDevice struct, let's use the newer API
234 */
235 if (kd->dev_fd >= 0) {
236 uint64_t addr = kd->kda.addr;
237 attr->addr = (uintptr_t)&addr;
238 ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr);
239 } else {
240 ret = kvm_vm_ioctl(kvm_state, KVM_ARM_SET_DEVICE_ADDR, &kd->kda);
241 }
242
243 if (ret < 0) {
244 fprintf(stderr, "Failed to set device address: %s\n",
245 strerror(-ret));
246 abort();
247 }
248}
249
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250static void kvm_arm_machine_init_done(Notifier *notifier, void *data)
251{
252 KVMDevice *kd, *tkd;
253
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254 QSLIST_FOREACH_SAFE(kd, &kvm_devices_head, entries, tkd) {
255 if (kd->kda.addr != -1) {
1da41cc1 256 kvm_arm_set_device_addr(kd);
eb035b48 257 }
dfde4e6e 258 memory_region_unref(kd->mr);
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259 g_free(kd);
260 }
0bbe4354 261 memory_listener_unregister(&devlistener);
eb035b48
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262}
263
264static Notifier notify = {
265 .notify = kvm_arm_machine_init_done,
266};
267
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268void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group,
269 uint64_t attr, int dev_fd)
eb035b48
PM
270{
271 KVMDevice *kd;
272
273 if (!kvm_irqchip_in_kernel()) {
274 return;
275 }
276
277 if (QSLIST_EMPTY(&kvm_devices_head)) {
4344af65 278 memory_listener_register(&devlistener, &address_space_memory);
eb035b48
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279 qemu_add_machine_init_done_notifier(&notify);
280 }
281 kd = g_new0(KVMDevice, 1);
282 kd->mr = mr;
283 kd->kda.id = devid;
284 kd->kda.addr = -1;
1da41cc1
CD
285 kd->kdattr.flags = 0;
286 kd->kdattr.group = group;
287 kd->kdattr.attr = attr;
288 kd->dev_fd = dev_fd;
eb035b48 289 QSLIST_INSERT_HEAD(&kvm_devices_head, kd, entries);
dfde4e6e 290 memory_region_ref(kd->mr);
eb035b48
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291}
292
38df27c8
AB
293static int compare_u64(const void *a, const void *b)
294{
295 if (*(uint64_t *)a > *(uint64_t *)b) {
296 return 1;
297 }
298 if (*(uint64_t *)a < *(uint64_t *)b) {
299 return -1;
300 }
301 return 0;
302}
303
304/* Initialize the CPUState's cpreg list according to the kernel's
305 * definition of what CPU registers it knows about (and throw away
306 * the previous TCG-created cpreg list).
307 */
308int kvm_arm_init_cpreg_list(ARMCPU *cpu)
309{
310 struct kvm_reg_list rl;
311 struct kvm_reg_list *rlp;
312 int i, ret, arraylen;
313 CPUState *cs = CPU(cpu);
314
315 rl.n = 0;
316 ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl);
317 if (ret != -E2BIG) {
318 return ret;
319 }
320 rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t));
321 rlp->n = rl.n;
322 ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp);
323 if (ret) {
324 goto out;
325 }
326 /* Sort the list we get back from the kernel, since cpreg_tuples
327 * must be in strictly ascending order.
328 */
329 qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64);
330
331 for (i = 0, arraylen = 0; i < rlp->n; i++) {
332 if (!kvm_arm_reg_syncs_via_cpreg_list(rlp->reg[i])) {
333 continue;
334 }
335 switch (rlp->reg[i] & KVM_REG_SIZE_MASK) {
336 case KVM_REG_SIZE_U32:
337 case KVM_REG_SIZE_U64:
338 break;
339 default:
340 fprintf(stderr, "Can't handle size of register in kernel list\n");
341 ret = -EINVAL;
342 goto out;
343 }
344
345 arraylen++;
346 }
347
348 cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen);
349 cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen);
350 cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes,
351 arraylen);
352 cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values,
353 arraylen);
354 cpu->cpreg_array_len = arraylen;
355 cpu->cpreg_vmstate_array_len = arraylen;
356
357 for (i = 0, arraylen = 0; i < rlp->n; i++) {
358 uint64_t regidx = rlp->reg[i];
359 if (!kvm_arm_reg_syncs_via_cpreg_list(regidx)) {
360 continue;
361 }
362 cpu->cpreg_indexes[arraylen] = regidx;
363 arraylen++;
364 }
365 assert(cpu->cpreg_array_len == arraylen);
366
367 if (!write_kvmstate_to_list(cpu)) {
368 /* Shouldn't happen unless kernel is inconsistent about
369 * what registers exist.
370 */
371 fprintf(stderr, "Initial read of kernel register state failed\n");
372 ret = -EINVAL;
373 goto out;
374 }
375
376out:
377 g_free(rlp);
378 return ret;
379}
380
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381bool write_kvmstate_to_list(ARMCPU *cpu)
382{
383 CPUState *cs = CPU(cpu);
384 int i;
385 bool ok = true;
386
387 for (i = 0; i < cpu->cpreg_array_len; i++) {
388 struct kvm_one_reg r;
389 uint64_t regidx = cpu->cpreg_indexes[i];
390 uint32_t v32;
391 int ret;
392
393 r.id = regidx;
394
395 switch (regidx & KVM_REG_SIZE_MASK) {
396 case KVM_REG_SIZE_U32:
397 r.addr = (uintptr_t)&v32;
398 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
399 if (!ret) {
400 cpu->cpreg_values[i] = v32;
401 }
402 break;
403 case KVM_REG_SIZE_U64:
404 r.addr = (uintptr_t)(cpu->cpreg_values + i);
405 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
406 break;
407 default:
408 abort();
409 }
410 if (ret) {
411 ok = false;
412 }
413 }
414 return ok;
415}
416
4b7a6bf4 417bool write_list_to_kvmstate(ARMCPU *cpu, int level)
ff047453
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418{
419 CPUState *cs = CPU(cpu);
420 int i;
421 bool ok = true;
422
423 for (i = 0; i < cpu->cpreg_array_len; i++) {
424 struct kvm_one_reg r;
425 uint64_t regidx = cpu->cpreg_indexes[i];
426 uint32_t v32;
427 int ret;
428
4b7a6bf4
CD
429 if (kvm_arm_cpreg_level(regidx) > level) {
430 continue;
431 }
432
ff047453
PM
433 r.id = regidx;
434 switch (regidx & KVM_REG_SIZE_MASK) {
435 case KVM_REG_SIZE_U32:
436 v32 = cpu->cpreg_values[i];
437 r.addr = (uintptr_t)&v32;
438 break;
439 case KVM_REG_SIZE_U64:
440 r.addr = (uintptr_t)(cpu->cpreg_values + i);
441 break;
442 default:
443 abort();
444 }
445 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
446 if (ret) {
447 /* We might fail for "unknown register" and also for
448 * "you tried to set a register which is constant with
449 * a different value from what it actually contains".
450 */
451 ok = false;
452 }
453 }
454 return ok;
455}
456
38df27c8
AB
457void kvm_arm_reset_vcpu(ARMCPU *cpu)
458{
25f2895e
CD
459 int ret;
460
38df27c8
AB
461 /* Re-init VCPU so that all registers are set to
462 * their respective reset values.
463 */
25f2895e
CD
464 ret = kvm_arm_vcpu_init(CPU(cpu));
465 if (ret < 0) {
466 fprintf(stderr, "kvm_arm_vcpu_init failed: %s\n", strerror(-ret));
467 abort();
468 }
469 if (!write_kvmstate_to_list(cpu)) {
470 fprintf(stderr, "write_kvmstate_to_list failed\n");
471 abort();
472 }
38df27c8
AB
473}
474
1a1753f7
AB
475/*
476 * Update KVM's MP_STATE based on what QEMU thinks it is
477 */
478int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu)
479{
480 if (cap_has_mp_state) {
481 struct kvm_mp_state mp_state = {
062ba099
AB
482 .mp_state = (cpu->power_state == PSCI_OFF) ?
483 KVM_MP_STATE_STOPPED : KVM_MP_STATE_RUNNABLE
1a1753f7
AB
484 };
485 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
486 if (ret) {
487 fprintf(stderr, "%s: failed to set MP_STATE %d/%s\n",
488 __func__, ret, strerror(-ret));
489 return -1;
490 }
491 }
492
493 return 0;
494}
495
496/*
497 * Sync the KVM MP_STATE into QEMU
498 */
499int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu)
500{
501 if (cap_has_mp_state) {
502 struct kvm_mp_state mp_state;
503 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state);
504 if (ret) {
505 fprintf(stderr, "%s: failed to get MP_STATE %d/%s\n",
506 __func__, ret, strerror(-ret));
507 abort();
508 }
062ba099
AB
509 cpu->power_state = (mp_state.mp_state == KVM_MP_STATE_STOPPED) ?
510 PSCI_OFF : PSCI_ON;
1a1753f7
AB
511 }
512
513 return 0;
514}
515
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CD
516void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
517{
518}
519
4c663752 520MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
494b00c7 521{
5d721b78
AG
522 ARMCPU *cpu;
523 uint32_t switched_level;
524
525 if (kvm_irqchip_in_kernel()) {
526 /*
527 * We only need to sync timer states with user-space interrupt
528 * controllers, so return early and save cycles if we don't.
529 */
530 return MEMTXATTRS_UNSPECIFIED;
531 }
532
533 cpu = ARM_CPU(cs);
534
535 /* Synchronize our shadowed in-kernel device irq lines with the kvm ones */
536 if (run->s.regs.device_irq_level != cpu->device_irq_level) {
537 switched_level = cpu->device_irq_level ^ run->s.regs.device_irq_level;
538
539 qemu_mutex_lock_iothread();
540
541 if (switched_level & KVM_ARM_DEV_EL1_VTIMER) {
542 qemu_set_irq(cpu->gt_timer_outputs[GTIMER_VIRT],
543 !!(run->s.regs.device_irq_level &
544 KVM_ARM_DEV_EL1_VTIMER));
545 switched_level &= ~KVM_ARM_DEV_EL1_VTIMER;
546 }
547
548 if (switched_level & KVM_ARM_DEV_EL1_PTIMER) {
549 qemu_set_irq(cpu->gt_timer_outputs[GTIMER_PHYS],
550 !!(run->s.regs.device_irq_level &
551 KVM_ARM_DEV_EL1_PTIMER));
552 switched_level &= ~KVM_ARM_DEV_EL1_PTIMER;
553 }
554
b1659527
AJ
555 if (switched_level & KVM_ARM_DEV_PMU) {
556 qemu_set_irq(cpu->pmu_interrupt,
557 !!(run->s.regs.device_irq_level & KVM_ARM_DEV_PMU));
558 switched_level &= ~KVM_ARM_DEV_PMU;
559 }
5d721b78
AG
560
561 if (switched_level) {
562 qemu_log_mask(LOG_UNIMP, "%s: unhandled in-kernel device IRQ %x\n",
563 __func__, switched_level);
564 }
565
566 /* We also mark unknown levels as processed to not waste cycles */
567 cpu->device_irq_level = run->s.regs.device_irq_level;
568 qemu_mutex_unlock_iothread();
569 }
570
4c663752 571 return MEMTXATTRS_UNSPECIFIED;
494b00c7
CD
572}
573
2ecb2027 574
494b00c7
CD
575int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
576{
2ecb2027
AB
577 int ret = 0;
578
579 switch (run->exit_reason) {
580 case KVM_EXIT_DEBUG:
581 if (kvm_arm_handle_debug(cs, &run->debug.arch)) {
582 ret = EXCP_DEBUG;
583 } /* otherwise return to guest */
584 break;
585 default:
586 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
587 __func__, run->exit_reason);
588 break;
589 }
590 return ret;
494b00c7
CD
591}
592
494b00c7
CD
593bool kvm_arch_stop_on_emulation_error(CPUState *cs)
594{
595 return true;
596}
597
598int kvm_arch_process_async_events(CPUState *cs)
599{
600 return 0;
601}
602
2ecb2027
AB
603/* The #ifdef protections are until 32bit headers are imported and can
604 * be removed once both 32 and 64 bit reach feature parity.
605 */
494b00c7
CD
606void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
607{
2ecb2027
AB
608#ifdef KVM_GUESTDBG_USE_SW_BP
609 if (kvm_sw_breakpoints_active(cs)) {
610 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
611 }
612#endif
e4482ab7
AB
613#ifdef KVM_GUESTDBG_USE_HW
614 if (kvm_arm_hw_debug_active(cs)) {
615 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW;
616 kvm_arm_copy_hw_debug_data(&dbg->arch);
617 }
618#endif
494b00c7 619}
b3a1c626
AK
620
621void kvm_arch_init_irq_routing(KVMState *s)
622{
623}
1da41cc1 624
15eafc2e 625int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
1da41cc1 626{
15eafc2e
PB
627 if (machine_kernel_irqchip_split(ms)) {
628 perror("-machine kernel_irqchip=split is not supported on ARM.");
629 exit(1);
630 }
631
1da41cc1
CD
632 /* If we can create the VGIC using the newer device control API, we
633 * let the device do this when it initializes itself, otherwise we
634 * fall back to the old API */
34e85cd9
PF
635 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL);
636}
1da41cc1 637
34e85cd9
PF
638int kvm_arm_vgic_probe(void)
639{
640 if (kvm_create_device(kvm_state,
641 KVM_DEV_TYPE_ARM_VGIC_V3, true) == 0) {
642 return 3;
643 } else if (kvm_create_device(kvm_state,
644 KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) {
645 return 2;
646 } else {
647 return 0;
1da41cc1 648 }
1da41cc1 649}
9e03a040
FB
650
651int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 652 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 653{
b05c81d2
EA
654 AddressSpace *as = pci_device_iommu_address_space(dev);
655 hwaddr xlat, len, doorbell_gpa;
656 MemoryRegionSection mrs;
657 MemoryRegion *mr;
658 int ret = 1;
659
660 if (as == &address_space_memory) {
661 return 0;
662 }
663
664 /* MSI doorbell address is translated by an IOMMU */
665
666 rcu_read_lock();
667 mr = address_space_translate(as, address, &xlat, &len, true);
668 if (!mr) {
669 goto unlock;
670 }
671 mrs = memory_region_find(mr, xlat, 1);
672 if (!mrs.mr) {
673 goto unlock;
674 }
675
676 doorbell_gpa = mrs.offset_within_address_space;
677 memory_region_unref(mrs.mr);
678
679 route->u.msi.address_lo = doorbell_gpa;
680 route->u.msi.address_hi = doorbell_gpa >> 32;
681
682 trace_kvm_arm_fixup_msi_route(address, doorbell_gpa);
683
684 ret = 0;
685
686unlock:
687 rcu_read_unlock();
688 return ret;
9e03a040 689}
1850b6b7 690
38d87493
PX
691int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
692 int vector, PCIDevice *dev)
693{
694 return 0;
695}
696
697int kvm_arch_release_virq_post(int virq)
698{
699 return 0;
700}
701
1850b6b7
EA
702int kvm_arch_msi_data_to_gsi(uint32_t data)
703{
704 return (data - 32) & 0xffff;
705}
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