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hw/m68k: add a dummy SWIM floppy controller
[qemu.git] / hw / block / fdc.c
CommitLineData
8977f3c1 1/*
890fa6be 2 * QEMU Floppy disk emulator (Intel 82078)
5fafdf24 3 *
3ccacc4a 4 * Copyright (c) 2003, 2007 Jocelyn Mayer
bcc4e41f 5 * Copyright (c) 2008 Hervé Poussineau
5fafdf24 6 *
8977f3c1
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
e80cfcfc
FB		 25/*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
f64ab228 29
80c71a24 30#include "qemu/osdep.h"
0d09e41a 31#include "hw/block/fdc.h"
da34e65c 32#include "qapi/error.h"
1de7afc9
PB		 33#include "qemu/error-report.h"
34#include "qemu/timer.h"
64552b6b 35#include "hw/irq.h"
0d09e41a 36#include "hw/isa/isa.h"
a27bd6c7 37#include "hw/qdev-properties.h"
83c9f4ca 38#include "hw/sysbus.h"
d6454270 39#include "migration/vmstate.h"
a92bd191 40#include "hw/block/block.h"
fa1d36df 41#include "sysemu/block-backend.h"
9c17d615
PB		 42#include "sysemu/blockdev.h"
43#include "sysemu/sysemu.h"
1de7afc9 44#include "qemu/log.h"
db725815 45#include "qemu/main-loop.h"
0b8fa32f 46#include "qemu/module.h"
1a5396d9 47#include "trace.h"
8977f3c1
FB		 48
49/********************************************************/
50/* debug Floppy devices */
8977f3c1 51
c691320f
JS		 52#define DEBUG_FLOPPY 0
53
001faf32 54#define FLOPPY_DPRINTF(fmt, ...) \
c691320f
JS		 55 do { \
56 if (DEBUG_FLOPPY) { \
57 fprintf(stderr, "FLOPPY: " fmt , ## __VA_ARGS__); \
58 } \
59 } while (0)
8977f3c1 60
51e6e90e
KW		 61
62/********************************************************/
63/* qdev floppy bus */
64
65#define TYPE_FLOPPY_BUS "floppy-bus"
66#define FLOPPY_BUS(obj) OBJECT_CHECK(FloppyBus, (obj), TYPE_FLOPPY_BUS)
67
68typedef struct FDCtrl FDCtrl;
394ea2ca
KW		 69typedef struct FDrive FDrive;
70static FDrive *get_drv(FDCtrl *fdctrl, int unit);
51e6e90e
KW		 71
72typedef struct FloppyBus {
73 BusState bus;
74 FDCtrl *fdc;
75} FloppyBus;
76
77static const TypeInfo floppy_bus_info = {
78 .name = TYPE_FLOPPY_BUS,
79 .parent = TYPE_BUS,
80 .instance_size = sizeof(FloppyBus),
81};
82
83static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev)
84{
85 qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
86 bus->fdc = fdc;
87}
88
89
8977f3c1
FB		 90/********************************************************/
91/* Floppy drive emulation */
92
61a8d649
MA		 93typedef enum FDriveRate {
94 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
95 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
96 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
97 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
98} FDriveRate;
99
109c17bc
JS		 100typedef enum FDriveSize {
101 FDRIVE_SIZE_UNKNOWN,
102 FDRIVE_SIZE_350,
103 FDRIVE_SIZE_525,
104} FDriveSize;
105
61a8d649 106typedef struct FDFormat {
2da44dd0 107 FloppyDriveType drive;
61a8d649
MA		 108 uint8_t last_sect;
109 uint8_t max_track;
110 uint8_t max_head;
111 FDriveRate rate;
112} FDFormat;
113
109c17bc
JS		 114/* In many cases, the total sector size of a format is enough to uniquely
115 * identify it. However, there are some total sector collisions between
116 * formats of different physical size, and these are noted below by
117 * highlighting the total sector size for entries with collisions. */
61a8d649
MA		 118static const FDFormat fd_formats[] = {
119 /* First entry is default format */
120 /* 1.44 MB 3"1/2 floppy disks */
109c17bc
JS		 121 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */
122 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */
2da44dd0
JS		 123 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, },
124 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, },
125 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, },
126 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, },
127 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, },
128 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, },
61a8d649 129 /* 2.88 MB 3"1/2 floppy disks */
2da44dd0
JS		 130 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, },
131 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, },
132 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, },
133 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, },
134 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, },
61a8d649 135 /* 720 kB 3"1/2 floppy disks */
109c17bc 136 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */
2da44dd0
JS		 137 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, },
138 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, },
139 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, },
140 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, },
141 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, },
61a8d649 142 /* 1.2 MB 5"1/4 floppy disks */
2da44dd0 143 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, },
109c17bc 144 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */
2da44dd0
JS		 145 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, },
146 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, },
109c17bc 147 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */
61a8d649 148 /* 720 kB 5"1/4 floppy disks */
109c17bc 149 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */
2da44dd0 150 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, },
61a8d649 151 /* 360 kB 5"1/4 floppy disks */
109c17bc 152 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */
2da44dd0
JS		 153 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, },
154 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, },
155 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, },
61a8d649 156 /* 320 kB 5"1/4 floppy disks */
2da44dd0
JS		 157 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, },
158 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, },
61a8d649 159 /* 360 kB must match 5"1/4 better than 3"1/2... */
109c17bc 160 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */
61a8d649 161 /* end */
2da44dd0 162 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, },
61a8d649
MA		 163};
164
109c17bc
JS		 165static FDriveSize drive_size(FloppyDriveType drive)
166{
167 switch (drive) {
168 case FLOPPY_DRIVE_TYPE_120:
169 return FDRIVE_SIZE_525;
170 case FLOPPY_DRIVE_TYPE_144:
171 case FLOPPY_DRIVE_TYPE_288:
172 return FDRIVE_SIZE_350;
173 default:
174 return FDRIVE_SIZE_UNKNOWN;
175 }
176}
177
cefec4f5
BS		 178#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
179#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
180
8977f3c1 181/* Will always be a fixed parameter for us */
f2d81b33
BS		 182#define FD_SECTOR_LEN 512
183#define FD_SECTOR_SC 2 /* Sector size code */
184#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
8977f3c1
FB		 185
186/* Floppy disk drive emulation */
5c02c033 187typedef enum FDiskFlags {
baca51fa 188 FDISK_DBL_SIDES = 0x01,
5c02c033 189} FDiskFlags;
baca51fa 190
394ea2ca 191struct FDrive {
844f65d6 192 FDCtrl *fdctrl;
4be74634 193 BlockBackend *blk;
a17c17a2 194 BlockConf *conf;
8977f3c1 195 /* Drive status */
2da44dd0 196 FloppyDriveType drive; /* CMOS drive type */
8977f3c1 197 uint8_t perpendicular; /* 2.88 MB access mode */
8977f3c1
FB		 198 /* Position */
199 uint8_t head;
200 uint8_t track;
201 uint8_t sect;
8977f3c1 202 /* Media */
16c1e3ec 203 FloppyDriveType disk; /* Current disk type */
5c02c033 204 FDiskFlags flags;
8977f3c1
FB		 205 uint8_t last_sect; /* Nb sector per track */
206 uint8_t max_track; /* Nb of tracks */
baca51fa 207 uint16_t bps; /* Bytes per sector */
8977f3c1 208 uint8_t ro; /* Is read-only */
7d905f71 209 uint8_t media_changed; /* Is media changed */
844f65d6 210 uint8_t media_rate; /* Data rate of medium */
2e1280e8 211
d5d47efc 212 bool media_validated; /* Have we validated the media? */
394ea2ca 213};
8977f3c1 214
a73275dd
JS		 215
216static FloppyDriveType get_fallback_drive_type(FDrive *drv);
217
fd9bdbd3
JS		 218/* Hack: FD_SEEK is expected to work on empty drives. However, QEMU
219 * currently goes through some pains to keep seeks within the bounds
220 * established by last_sect and max_track. Correcting this is difficult,
221 * as refactoring FDC code tends to expose nasty bugs in the Linux kernel.
222 *
223 * For now: allow empty drives to have large bounds so we can seek around,
224 * with the understanding that when a diskette is inserted, the bounds will
225 * properly tighten to match the geometry of that inserted medium.
226 */
227static void fd_empty_seek_hack(FDrive *drv)
228{
229 drv->last_sect = 0xFF;
230 drv->max_track = 0xFF;
231}
232
5c02c033 233static void fd_init(FDrive *drv)
8977f3c1
FB		 234{
235 /* Drive */
8977f3c1 236 drv->perpendicular = 0;
8977f3c1 237 /* Disk */
16c1e3ec 238 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
baca51fa 239 drv->last_sect = 0;
8977f3c1 240 drv->max_track = 0;
d5d47efc
JS		 241 drv->ro = true;
242 drv->media_changed = 1;
8977f3c1
FB		 243}
244
08388273
HP		 245#define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
246
7859cb98 247static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
08388273 248 uint8_t last_sect, uint8_t num_sides)
8977f3c1 249{
08388273 250 return (((track * num_sides) + head) * last_sect) + sect - 1;
8977f3c1
FB		 251}
252
253/* Returns current position, in sectors, for given drive */
5c02c033 254static int fd_sector(FDrive *drv)
8977f3c1 255{
08388273
HP		 256 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
257 NUM_SIDES(drv));
8977f3c1
FB		 258}
259
a7a5b7c0
EB		 260/* Returns current position, in bytes, for given drive */
261static int fd_offset(FDrive *drv)
262{
263 g_assert(fd_sector(drv) < INT_MAX >> BDRV_SECTOR_BITS);
264 return fd_sector(drv) << BDRV_SECTOR_BITS;
265}
266
77370520
BS		 267/* Seek to a new position:
268 * returns 0 if already on right track
269 * returns 1 if track changed
270 * returns 2 if track is invalid
271 * returns 3 if sector is invalid
272 * returns 4 if seek is disabled
273 */
5c02c033
BS		 274static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
275 int enable_seek)
8977f3c1
FB		 276{
277 uint32_t sector;
baca51fa
FB		 278 int ret;
279
280 if (track > drv->max_track ||
4f431960 281 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
ed5fd2cc
FB		 282 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
283 head, track, sect, 1,
284 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
285 drv->max_track, drv->last_sect);
8977f3c1
FB		 286 return 2;
287 }
288 if (sect > drv->last_sect) {
ed5fd2cc
FB		 289 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
290 head, track, sect, 1,
291 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
292 drv->max_track, drv->last_sect);
8977f3c1
FB		 293 return 3;
294 }
08388273 295 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
baca51fa 296 ret = 0;
8977f3c1
FB		 297 if (sector != fd_sector(drv)) {
298#if 0
299 if (!enable_seek) {
cced7a13
BS		 300 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
301 " (max=%d %02x %02x)\n",
302 head, track, sect, 1, drv->max_track,
303 drv->last_sect);
8977f3c1
FB		 304 return 4;
305 }
306#endif
307 drv->head = head;
6be01b1e 308 if (drv->track != track) {
abb3e55b 309 if (drv->blk != NULL && blk_is_inserted(drv->blk)) {
6be01b1e
PH		 310 drv->media_changed = 0;
311 }
4f431960 312 ret = 1;
6be01b1e 313 }
8977f3c1
FB		 314 drv->track = track;
315 drv->sect = sect;
8977f3c1
FB		 316 }
317
abb3e55b 318 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) {
c52acf60
PH		 319 ret = 2;
320 }
321
baca51fa 322 return ret;
8977f3c1
FB		 323}
324
325/* Set drive back to track 0 */
5c02c033 326static void fd_recalibrate(FDrive *drv)
8977f3c1
FB		 327{
328 FLOPPY_DPRINTF("recalibrate\n");
6be01b1e 329 fd_seek(drv, 0, 0, 1, 1);
8977f3c1
FB		 330}
331
d5d47efc
JS		 332/**
333 * Determine geometry based on inserted diskette.
334 * Will not operate on an empty drive.
335 *
336 * @return: 0 on success, -1 if the drive is empty.
337 */
338static int pick_geometry(FDrive *drv)
9a972233 339{
21862658 340 BlockBackend *blk = drv->blk;
9a972233
JS		 341 const FDFormat *parse;
342 uint64_t nb_sectors, size;
f31937aa
JS		 343 int i;
344 int match, size_match, type_match;
345 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO;
9a972233 346
d5d47efc 347 /* We can only pick a geometry if we have a diskette. */
abb3e55b
HR		 348 if (!drv->blk || !blk_is_inserted(drv->blk) ||
349 drv->drive == FLOPPY_DRIVE_TYPE_NONE)
350 {
d5d47efc
JS		 351 return -1;
352 }
353
f31937aa
JS		 354 /* We need to determine the likely geometry of the inserted medium.
355 * In order of preference, we look for:
356 * (1) The same drive type and number of sectors,
357 * (2) The same diskette size and number of sectors,
358 * (3) The same drive type.
359 *
360 * In all cases, matches that occur higher in the drive table will take
361 * precedence over matches that occur later in the table.
362 */
9a972233 363 blk_get_geometry(blk, &nb_sectors);
f31937aa 364 match = size_match = type_match = -1;
9a972233
JS		 365 for (i = 0; ; i++) {
366 parse = &fd_formats[i];
2da44dd0 367 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) {
9a972233
JS		 368 break;
369 }
f31937aa
JS		 370 size = (parse->max_head + 1) * parse->max_track * parse->last_sect;
371 if (nb_sectors == size) {
372 if (magic || parse->drive == drv->drive) {
373 /* (1) perfect match -- nb_sectors and drive type */
374 goto out;
375 } else if (drive_size(parse->drive) == drive_size(drv->drive)) {
376 /* (2) size match -- nb_sectors and physical medium size */
377 match = (match == -1) ? i : match;
378 } else {
379 /* This is suspicious -- Did the user misconfigure? */
380 size_match = (size_match == -1) ? i : size_match;
9a972233 381 }
f31937aa
JS		 382 } else if (type_match == -1) {
383 if ((parse->drive == drv->drive) ||
384 (magic && (parse->drive == get_fallback_drive_type(drv)))) {
385 /* (3) type match -- nb_sectors mismatch, but matches the type
386 * specified explicitly by the user, or matches the fallback
387 * default type when using the drive autodetect mechanism */
388 type_match = i;
9a972233
JS		 389 }
390 }
391 }
f31937aa
JS		 392
393 /* No exact match found */
9a972233 394 if (match == -1) {
f31937aa
JS		 395 if (size_match != -1) {
396 parse = &fd_formats[size_match];
397 FLOPPY_DPRINTF("User requested floppy drive type '%s', "
398 "but inserted medium appears to be a "
c691320f 399 "%"PRId64" sector '%s' type\n",
977c736f 400 FloppyDriveType_str(drv->drive),
f31937aa 401 nb_sectors,
977c736f 402 FloppyDriveType_str(parse->drive));
9a972233 403 }
329b7291 404 assert(type_match != -1 && "misconfigured fd_format");
f31937aa 405 match = type_match;
9a972233 406 }
f31937aa
JS		 407 parse = &(fd_formats[match]);
408
409 out:
21862658
JS		 410 if (parse->max_head == 0) {
411 drv->flags &= ~FDISK_DBL_SIDES;
412 } else {
413 drv->flags |= FDISK_DBL_SIDES;
414 }
415 drv->max_track = parse->max_track;
416 drv->last_sect = parse->last_sect;
d5d47efc 417 drv->disk = parse->drive;
21862658 418 drv->media_rate = parse->rate;
d5d47efc
JS		 419 return 0;
420}
421
422static void pick_drive_type(FDrive *drv)
423{
fff4687b
JS		 424 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) {
425 return;
426 }
427
d5d47efc
JS		 428 if (pick_geometry(drv) == 0) {
429 drv->drive = drv->disk;
430 } else {
a73275dd 431 drv->drive = get_fallback_drive_type(drv);
d5d47efc 432 }
fff4687b
JS		 433
434 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO);
9a972233
JS		 435}
436
8977f3c1 437/* Revalidate a disk drive after a disk change */
5c02c033 438static void fd_revalidate(FDrive *drv)
8977f3c1 439{
d5d47efc
JS		 440 int rc;
441
8977f3c1 442 FLOPPY_DPRINTF("revalidate\n");
4be74634 443 if (drv->blk != NULL) {
21862658 444 drv->ro = blk_is_read_only(drv->blk);
abb3e55b 445 if (!blk_is_inserted(drv->blk)) {
cfb08fba 446 FLOPPY_DPRINTF("No disk in drive\n");
d5d47efc 447 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
fd9bdbd3 448 fd_empty_seek_hack(drv);
d5d47efc
JS		 449 } else if (!drv->media_validated) {
450 rc = pick_geometry(drv);
451 if (rc) {
452 FLOPPY_DPRINTF("Could not validate floppy drive media");
453 } else {
454 drv->media_validated = true;
455 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n",
456 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1,
457 drv->max_track, drv->last_sect,
458 drv->ro ? "ro" : "rw");
459 }
4f431960 460 }
8977f3c1 461 } else {
cfb08fba 462 FLOPPY_DPRINTF("No drive connected\n");
baca51fa 463 drv->last_sect = 0;
4f431960
JM		 464 drv->max_track = 0;
465 drv->flags &= ~FDISK_DBL_SIDES;
d5d47efc
JS		 466 drv->drive = FLOPPY_DRIVE_TYPE_NONE;
467 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
8977f3c1 468 }
caed8802
FB		 469}
470
39829a01 471static void fd_change_cb(void *opaque, bool load, Error **errp)
394ea2ca
KW		 472{
473 FDrive *drive = opaque;
a17c17a2
KW		 474
475 if (!load) {
476 blk_set_perm(drive->blk, 0, BLK_PERM_ALL, &error_abort);
477 } else {
ceff3e1f
MZ		 478 if (!blkconf_apply_backend_options(drive->conf,
479 blk_is_read_only(drive->blk), false,
480 errp)) {
a17c17a2
KW		 481 return;
482 }
483 }
394ea2ca
KW		 484
485 drive->media_changed = 1;
486 drive->media_validated = false;
487 fd_revalidate(drive);
488}
489
490static const BlockDevOps fd_block_ops = {
491 .change_media_cb = fd_change_cb,
492};
493
494
495#define TYPE_FLOPPY_DRIVE "floppy"
496#define FLOPPY_DRIVE(obj) \
497 OBJECT_CHECK(FloppyDrive, (obj), TYPE_FLOPPY_DRIVE)
498
499typedef struct FloppyDrive {
a92bd191
KW		 500 DeviceState qdev;
501 uint32_t unit;
502 BlockConf conf;
503 FloppyDriveType type;
394ea2ca
KW		 504} FloppyDrive;
505
506static Property floppy_drive_properties[] = {
507 DEFINE_PROP_UINT32("unit", FloppyDrive, unit, -1),
a92bd191 508 DEFINE_BLOCK_PROPERTIES(FloppyDrive, conf),
85bbd1e7 509 DEFINE_PROP_SIGNED("drive-type", FloppyDrive, type,
a92bd191
KW		 510 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
511 FloppyDriveType),
394ea2ca
KW		 512 DEFINE_PROP_END_OF_LIST(),
513};
514
ae34fce5 515static void floppy_drive_realize(DeviceState *qdev, Error **errp)
394ea2ca
KW		 516{
517 FloppyDrive *dev = FLOPPY_DRIVE(qdev);
518 FloppyBus *bus = FLOPPY_BUS(qdev->parent_bus);
519 FDrive *drive;
0b9e918f 520 bool read_only;
a92bd191 521 int ret;
394ea2ca
KW		 522
523 if (dev->unit == -1) {
524 for (dev->unit = 0; dev->unit < MAX_FD; dev->unit++) {
525 drive = get_drv(bus->fdc, dev->unit);
526 if (!drive->blk) {
527 break;
528 }
529 }
530 }
531
532 if (dev->unit >= MAX_FD) {
ae34fce5
MZ		 533 error_setg(errp, "Can't create floppy unit %d, bus supports "
534 "only %d units", dev->unit, MAX_FD);
535 return;
394ea2ca
KW		 536 }
537
394ea2ca 538 drive = get_drv(bus->fdc, dev->unit);
394ea2ca 539 if (drive->blk) {
ae34fce5
MZ		 540 error_setg(errp, "Floppy unit %d is in use", dev->unit);
541 return;
a92bd191
KW		 542 }
543
544 if (!dev->conf.blk) {
394ea2ca 545 /* Anonymous BlockBackend for an empty drive */
d861ab3a 546 dev->conf.blk = blk_new(qemu_get_aio_context(), 0, BLK_PERM_ALL);
a92bd191
KW		 547 ret = blk_attach_dev(dev->conf.blk, qdev);
548 assert(ret == 0);
0b9e918f
KW		 549
550 /* Don't take write permissions on an empty drive to allow attaching a
551 * read-only node later */
552 read_only = true;
553 } else {
554 read_only = !blk_bs(dev->conf.blk) || blk_is_read_only(dev->conf.blk);
394ea2ca
KW		 555 }
556
a92bd191
KW		 557 blkconf_blocksizes(&dev->conf);
558 if (dev->conf.logical_block_size != 512 ||
559 dev->conf.physical_block_size != 512)
560 {
ae34fce5
MZ		 561 error_setg(errp, "Physical and logical block size must "
562 "be 512 for floppy");
563 return;
a92bd191
KW		 564 }
565
566 /* rerror/werror aren't supported by fdc and therefore not even registered
567 * with qdev. So set the defaults manually before they are used in
568 * blkconf_apply_backend_options(). */
569 dev->conf.rerror = BLOCKDEV_ON_ERROR_AUTO;
570 dev->conf.werror = BLOCKDEV_ON_ERROR_AUTO;
a17c17a2 571
0b9e918f 572 if (!blkconf_apply_backend_options(&dev->conf, read_only, false, errp)) {
ae34fce5 573 return;
a17c17a2 574 }
a92bd191
KW		 575
576 /* 'enospc' is the default for -drive, 'report' is what blk_new() gives us
577 * for empty drives. */
578 if (blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC &&
579 blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_REPORT) {
ae34fce5
MZ		 580 error_setg(errp, "fdc doesn't support drive option werror");
581 return;
394ea2ca 582 }
a92bd191 583 if (blk_get_on_error(dev->conf.blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
ae34fce5
MZ		 584 error_setg(errp, "fdc doesn't support drive option rerror");
585 return;
a92bd191
KW		 586 }
587
a17c17a2 588 drive->conf = &dev->conf;
a92bd191
KW		 589 drive->blk = dev->conf.blk;
590 drive->fdctrl = bus->fdc;
591
592 fd_init(drive);
593 blk_set_dev_ops(drive->blk, &fd_block_ops, drive);
594
595 /* Keep 'type' qdev property and FDrive->drive in sync */
596 drive->drive = dev->type;
597 pick_drive_type(drive);
598 dev->type = drive->drive;
599
394ea2ca 600 fd_revalidate(drive);
394ea2ca
KW		 601}
602
603static void floppy_drive_class_init(ObjectClass *klass, void *data)
604{
605 DeviceClass *k = DEVICE_CLASS(klass);
ae34fce5 606 k->realize = floppy_drive_realize;
394ea2ca
KW		 607 set_bit(DEVICE_CATEGORY_STORAGE, k->categories);
608 k->bus_type = TYPE_FLOPPY_BUS;
609 k->props = floppy_drive_properties;
610 k->desc = "virtual floppy drive";
611}
612
613static const TypeInfo floppy_drive_info = {
614 .name = TYPE_FLOPPY_DRIVE,
615 .parent = TYPE_DEVICE,
616 .instance_size = sizeof(FloppyDrive),
617 .class_init = floppy_drive_class_init,
618};
619
8977f3c1 620/********************************************************/
4b19ec0c 621/* Intel 82078 floppy disk controller emulation */
8977f3c1 622
5c02c033 623static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
07e415f2 624static void fdctrl_to_command_phase(FDCtrl *fdctrl);
85571bc7 625static int fdctrl_transfer_handler (void *opaque, int nchan,
c227f099 626 int dma_pos, int dma_len);
d497d534 627static void fdctrl_raise_irq(FDCtrl *fdctrl);
a2df5fa3 628static FDrive *get_cur_drv(FDCtrl *fdctrl);
5c02c033
BS		 629
630static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
631static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
632static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
633static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
634static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
635static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
636static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
637static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
638static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
639static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
640static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
a758f8f4 641static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
8977f3c1 642
8977f3c1
FB		 643enum {
644 FD_DIR_WRITE = 0,
645 FD_DIR_READ = 1,
646 FD_DIR_SCANE = 2,
647 FD_DIR_SCANL = 3,
648 FD_DIR_SCANH = 4,
7ea004ed 649 FD_DIR_VERIFY = 5,
8977f3c1
FB		 650};
651
652enum {
b9b3d225
BS		 653 FD_STATE_MULTI = 0x01, /* multi track flag */
654 FD_STATE_FORMAT = 0x02, /* format flag */
8977f3c1
FB		 655};
656
9fea808a 657enum {
8c6a4d77
BS		 658 FD_REG_SRA = 0x00,
659 FD_REG_SRB = 0x01,
9fea808a
BS		 660 FD_REG_DOR = 0x02,
661 FD_REG_TDR = 0x03,
662 FD_REG_MSR = 0x04,
663 FD_REG_DSR = 0x04,
664 FD_REG_FIFO = 0x05,
665 FD_REG_DIR = 0x07,
a758f8f4 666 FD_REG_CCR = 0x07,
9fea808a
BS		 667};
668
669enum {
65cef780 670 FD_CMD_READ_TRACK = 0x02,
9fea808a
BS		 671 FD_CMD_SPECIFY = 0x03,
672 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
65cef780
BS		 673 FD_CMD_WRITE = 0x05,
674 FD_CMD_READ = 0x06,
9fea808a
BS		 675 FD_CMD_RECALIBRATE = 0x07,
676 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
65cef780
BS		 677 FD_CMD_WRITE_DELETED = 0x09,
678 FD_CMD_READ_ID = 0x0a,
679 FD_CMD_READ_DELETED = 0x0c,
680 FD_CMD_FORMAT_TRACK = 0x0d,
9fea808a
BS		 681 FD_CMD_DUMPREG = 0x0e,
682 FD_CMD_SEEK = 0x0f,
683 FD_CMD_VERSION = 0x10,
65cef780 684 FD_CMD_SCAN_EQUAL = 0x11,
9fea808a
BS		 685 FD_CMD_PERPENDICULAR_MODE = 0x12,
686 FD_CMD_CONFIGURE = 0x13,
65cef780
BS		 687 FD_CMD_LOCK = 0x14,
688 FD_CMD_VERIFY = 0x16,
9fea808a
BS		 689 FD_CMD_POWERDOWN_MODE = 0x17,
690 FD_CMD_PART_ID = 0x18,
65cef780
BS		 691 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
692 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
bb350a5e 693 FD_CMD_SAVE = 0x2e,
9fea808a 694 FD_CMD_OPTION = 0x33,
bb350a5e 695 FD_CMD_RESTORE = 0x4e,
9fea808a
BS		 696 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
697 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
9fea808a
BS		 698 FD_CMD_FORMAT_AND_WRITE = 0xcd,
699 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
700};
701
702enum {
703 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
704 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
705 FD_CONFIG_POLL = 0x10, /* Poll enabled */
706 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
707 FD_CONFIG_EIS = 0x40, /* No implied seeks */
708};
709
710enum {
2fee0088
PH		 711 FD_SR0_DS0 = 0x01,
712 FD_SR0_DS1 = 0x02,
713 FD_SR0_HEAD = 0x04,
9fea808a
BS		 714 FD_SR0_EQPMT = 0x10,
715 FD_SR0_SEEK = 0x20,
716 FD_SR0_ABNTERM = 0x40,
717 FD_SR0_INVCMD = 0x80,
718 FD_SR0_RDYCHG = 0xc0,
719};
720
77370520 721enum {
844f65d6 722 FD_SR1_MA = 0x01, /* Missing address mark */
8510854e 723 FD_SR1_NW = 0x02, /* Not writable */
77370520
BS		 724 FD_SR1_EC = 0x80, /* End of cylinder */
725};
726
727enum {
728 FD_SR2_SNS = 0x04, /* Scan not satisfied */
729 FD_SR2_SEH = 0x08, /* Scan equal hit */
730};
731
8c6a4d77
BS		 732enum {
733 FD_SRA_DIR = 0x01,
734 FD_SRA_nWP = 0x02,
735 FD_SRA_nINDX = 0x04,
736 FD_SRA_HDSEL = 0x08,
737 FD_SRA_nTRK0 = 0x10,
738 FD_SRA_STEP = 0x20,
739 FD_SRA_nDRV2 = 0x40,
740 FD_SRA_INTPEND = 0x80,
741};
742
743enum {
744 FD_SRB_MTR0 = 0x01,
745 FD_SRB_MTR1 = 0x02,
746 FD_SRB_WGATE = 0x04,
747 FD_SRB_RDATA = 0x08,
748 FD_SRB_WDATA = 0x10,
749 FD_SRB_DR0 = 0x20,
750};
751
9fea808a 752enum {
78ae820c
BS		 753#if MAX_FD == 4
754 FD_DOR_SELMASK = 0x03,
755#else
9fea808a 756 FD_DOR_SELMASK = 0x01,
78ae820c 757#endif
9fea808a
BS		 758 FD_DOR_nRESET = 0x04,
759 FD_DOR_DMAEN = 0x08,
760 FD_DOR_MOTEN0 = 0x10,
761 FD_DOR_MOTEN1 = 0x20,
762 FD_DOR_MOTEN2 = 0x40,
763 FD_DOR_MOTEN3 = 0x80,
764};
765
766enum {
78ae820c 767#if MAX_FD == 4
9fea808a 768 FD_TDR_BOOTSEL = 0x0c,
78ae820c
BS		 769#else
770 FD_TDR_BOOTSEL = 0x04,
771#endif
9fea808a
BS		 772};
773
774enum {
775 FD_DSR_DRATEMASK= 0x03,
776 FD_DSR_PWRDOWN = 0x40,
777 FD_DSR_SWRESET = 0x80,
778};
779
780enum {
781 FD_MSR_DRV0BUSY = 0x01,
782 FD_MSR_DRV1BUSY = 0x02,
783 FD_MSR_DRV2BUSY = 0x04,
784 FD_MSR_DRV3BUSY = 0x08,
785 FD_MSR_CMDBUSY = 0x10,
786 FD_MSR_NONDMA = 0x20,
787 FD_MSR_DIO = 0x40,
788 FD_MSR_RQM = 0x80,
789};
790
791enum {
792 FD_DIR_DSKCHG = 0x80,
793};
794
85d291a0
KW		 795/*
796 * See chapter 5.0 "Controller phases" of the spec:
797 *
798 * Command phase:
799 * The host writes a command and its parameters into the FIFO. The command
800 * phase is completed when all parameters for the command have been supplied,
801 * and execution phase is entered.
802 *
803 * Execution phase:
804 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
805 * contains the payload now, otherwise it's unused. When all bytes of the
806 * required data have been transferred, the state is switched to either result
807 * phase (if the command produces status bytes) or directly back into the
808 * command phase for the next command.
809 *
810 * Result phase:
811 * The host reads out the FIFO, which contains one or more result bytes now.
812 */
813enum {
814 /* Only for migration: reconstruct phase from registers like qemu 2.3 */
815 FD_PHASE_RECONSTRUCT = 0,
816
817 FD_PHASE_COMMAND = 1,
818 FD_PHASE_EXECUTION = 2,
819 FD_PHASE_RESULT = 3,
820};
821
8977f3c1 822#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
baca51fa 823#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
8977f3c1 824
5c02c033 825struct FDCtrl {
dc6c1b37 826 MemoryRegion iomem;
d537cf6c 827 qemu_irq irq;
4b19ec0c 828 /* Controller state */
ed5fd2cc 829 QEMUTimer *result_timer;
242cca4f 830 int dma_chann;
85d291a0 831 uint8_t phase;
c8a35f1c 832 IsaDma *dma;
242cca4f
BS		 833 /* Controller's identification */
834 uint8_t version;
835 /* HW */
8c6a4d77
BS		 836 uint8_t sra;
837 uint8_t srb;
368df94d 838 uint8_t dor;
d7a6c270 839 uint8_t dor_vmstate; /* only used as temp during vmstate */
46d3233b 840 uint8_t tdr;
b9b3d225 841 uint8_t dsr;
368df94d 842 uint8_t msr;
8977f3c1 843 uint8_t cur_drv;
77370520
BS		 844 uint8_t status0;
845 uint8_t status1;
846 uint8_t status2;
8977f3c1 847 /* Command FIFO */
33f00271 848 uint8_t *fifo;
d7a6c270 849 int32_t fifo_size;
8977f3c1
FB		 850 uint32_t data_pos;
851 uint32_t data_len;
852 uint8_t data_state;
853 uint8_t data_dir;
890fa6be 854 uint8_t eot; /* last wanted sector */
8977f3c1 855 /* States kept only to be returned back */
8977f3c1
FB		 856 /* precompensation */
857 uint8_t precomp_trk;
858 uint8_t config;
859 uint8_t lock;
860 /* Power down config (also with status regB access mode */
861 uint8_t pwrd;
862 /* Floppy drives */
51e6e90e 863 FloppyBus bus;
d7a6c270 864 uint8_t num_floppies;
5c02c033 865 FDrive drives[MAX_FD];
a92bd191
KW		 866 struct {
867 BlockBackend *blk;
868 FloppyDriveType type;
869 } qdev_for_drives[MAX_FD];
f2d81b33 870 int reset_sensei;
09c6d585 871 uint32_t check_media_rate;
a73275dd 872 FloppyDriveType fallback; /* type=auto failure fallback */
242cca4f
BS		 873 /* Timers state */
874 uint8_t timer0;
875 uint8_t timer1;
e305a165 876 PortioList portio_list;
baca51fa
FB		 877};
878
a73275dd
JS		 879static FloppyDriveType get_fallback_drive_type(FDrive *drv)
880{
881 return drv->fdctrl->fallback;
882}
883
19d46d71 884#define TYPE_SYSBUS_FDC "base-sysbus-fdc"
dd3be742
HT		 885#define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
886
5c02c033 887typedef struct FDCtrlSysBus {
dd3be742
HT		 888 /*< private >*/
889 SysBusDevice parent_obj;
890 /*< public >*/
891
5c02c033
BS		 892 struct FDCtrl state;
893} FDCtrlSysBus;
8baf73ad 894
020c8e76
AF		 895#define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
896
5c02c033 897typedef struct FDCtrlISABus {
020c8e76
AF		 898 ISADevice parent_obj;
899
c9ae703d
HP		 900 uint32_t iobase;
901 uint32_t irq;
902 uint32_t dma;
5c02c033 903 struct FDCtrl state;
1ca4d09a
GN		 904 int32_t bootindexA;
905 int32_t bootindexB;
5c02c033 906} FDCtrlISABus;
8baf73ad 907
baca51fa
FB		 908static uint32_t fdctrl_read (void *opaque, uint32_t reg)
909{
5c02c033 910 FDCtrl *fdctrl = opaque;
baca51fa
FB		 911 uint32_t retval;
912
a18e67f5 913 reg &= 7;
e64d7d59 914 switch (reg) {
8c6a4d77
BS		 915 case FD_REG_SRA:
916 retval = fdctrl_read_statusA(fdctrl);
4f431960 917 break;
8c6a4d77 918 case FD_REG_SRB:
4f431960
JM		 919 retval = fdctrl_read_statusB(fdctrl);
920 break;
9fea808a 921 case FD_REG_DOR:
4f431960
JM		 922 retval = fdctrl_read_dor(fdctrl);
923 break;
9fea808a 924 case FD_REG_TDR:
baca51fa 925 retval = fdctrl_read_tape(fdctrl);
4f431960 926 break;
9fea808a 927 case FD_REG_MSR:
baca51fa 928 retval = fdctrl_read_main_status(fdctrl);
4f431960 929 break;
9fea808a 930 case FD_REG_FIFO:
baca51fa 931 retval = fdctrl_read_data(fdctrl);
4f431960 932 break;
9fea808a 933 case FD_REG_DIR:
baca51fa 934 retval = fdctrl_read_dir(fdctrl);
4f431960 935 break;
a541f297 936 default:
4f431960
JM		 937 retval = (uint32_t)(-1);
938 break;
a541f297 939 }
1a5396d9 940 trace_fdc_ioport_read(reg, retval);
baca51fa
FB		 941
942 return retval;
943}
944
945static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
946{
5c02c033 947 FDCtrl *fdctrl = opaque;
baca51fa 948
a18e67f5 949 reg &= 7;
1a5396d9 950 trace_fdc_ioport_write(reg, value);
e64d7d59 951 switch (reg) {
9fea808a 952 case FD_REG_DOR:
4f431960
JM		 953 fdctrl_write_dor(fdctrl, value);
954 break;
9fea808a 955 case FD_REG_TDR:
baca51fa 956 fdctrl_write_tape(fdctrl, value);
4f431960 957 break;
9fea808a 958 case FD_REG_DSR:
baca51fa 959 fdctrl_write_rate(fdctrl, value);
4f431960 960 break;
9fea808a 961 case FD_REG_FIFO:
baca51fa 962 fdctrl_write_data(fdctrl, value);
4f431960 963 break;
a758f8f4
HP		 964 case FD_REG_CCR:
965 fdctrl_write_ccr(fdctrl, value);
966 break;
a541f297 967 default:
4f431960 968 break;
a541f297 969 }
baca51fa
FB		 970}
971
a8170e5e 972static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
dc6c1b37 973 unsigned ize)
62a46c61 974{
5dcb6b91 975 return fdctrl_read(opaque, (uint32_t)reg);
62a46c61
FB		 976}
977
a8170e5e 978static void fdctrl_write_mem (void *opaque, hwaddr reg,
dc6c1b37 979 uint64_t value, unsigned size)
62a46c61 980{
5dcb6b91 981 fdctrl_write(opaque, (uint32_t)reg, value);
62a46c61
FB		 982}
983
dc6c1b37
AK		 984static const MemoryRegionOps fdctrl_mem_ops = {
985 .read = fdctrl_read_mem,
986 .write = fdctrl_write_mem,
987 .endianness = DEVICE_NATIVE_ENDIAN,
e80cfcfc
FB		 988};
989
dc6c1b37
AK		 990static const MemoryRegionOps fdctrl_mem_strict_ops = {
991 .read = fdctrl_read_mem,
992 .write = fdctrl_write_mem,
993 .endianness = DEVICE_NATIVE_ENDIAN,
994 .valid = {
995 .min_access_size = 1,
996 .max_access_size = 1,
997 },
7c560456
BS		 998};
999
7d905f71
JW		 1000static bool fdrive_media_changed_needed(void *opaque)
1001{
1002 FDrive *drive = opaque;
1003
abb3e55b 1004 return (drive->blk != NULL && drive->media_changed != 1);
7d905f71
JW		 1005}
1006
1007static const VMStateDescription vmstate_fdrive_media_changed = {
1008 .name = "fdrive/media_changed",
1009 .version_id = 1,
1010 .minimum_version_id = 1,
5cd8cada 1011 .needed = fdrive_media_changed_needed,
d49805ae 1012 .fields = (VMStateField[]) {
7d905f71
JW		 1013 VMSTATE_UINT8(media_changed, FDrive),
1014 VMSTATE_END_OF_LIST()
1015 }
1016};
1017
844f65d6
HP		 1018static bool fdrive_media_rate_needed(void *opaque)
1019{
1020 FDrive *drive = opaque;
1021
1022 return drive->fdctrl->check_media_rate;
1023}
1024
1025static const VMStateDescription vmstate_fdrive_media_rate = {
1026 .name = "fdrive/media_rate",
1027 .version_id = 1,
1028 .minimum_version_id = 1,
5cd8cada 1029 .needed = fdrive_media_rate_needed,
d49805ae 1030 .fields = (VMStateField[]) {
844f65d6
HP		 1031 VMSTATE_UINT8(media_rate, FDrive),
1032 VMSTATE_END_OF_LIST()
1033 }
1034};
1035
c0b92f30
PD		 1036static bool fdrive_perpendicular_needed(void *opaque)
1037{
1038 FDrive *drive = opaque;
1039
1040 return drive->perpendicular != 0;
1041}
1042
1043static const VMStateDescription vmstate_fdrive_perpendicular = {
1044 .name = "fdrive/perpendicular",
1045 .version_id = 1,
1046 .minimum_version_id = 1,
5cd8cada 1047 .needed = fdrive_perpendicular_needed,
c0b92f30
PD		 1048 .fields = (VMStateField[]) {
1049 VMSTATE_UINT8(perpendicular, FDrive),
1050 VMSTATE_END_OF_LIST()
1051 }
1052};
1053
1054static int fdrive_post_load(void *opaque, int version_id)
1055{
1056 fd_revalidate(opaque);
1057 return 0;
1058}
1059
d7a6c270
JQ		 1060static const VMStateDescription vmstate_fdrive = {
1061 .name = "fdrive",
1062 .version_id = 1,
1063 .minimum_version_id = 1,
c0b92f30 1064 .post_load = fdrive_post_load,
d49805ae 1065 .fields = (VMStateField[]) {
5c02c033
BS		 1066 VMSTATE_UINT8(head, FDrive),
1067 VMSTATE_UINT8(track, FDrive),
1068 VMSTATE_UINT8(sect, FDrive),
d7a6c270 1069 VMSTATE_END_OF_LIST()
7d905f71 1070 },
5cd8cada
JQ		 1071 .subsections = (const VMStateDescription*[]) {
1072 &vmstate_fdrive_media_changed,
1073 &vmstate_fdrive_media_rate,
1074 &vmstate_fdrive_perpendicular,
1075 NULL
d7a6c270
JQ		 1076 }
1077};
3ccacc4a 1078
85d291a0
KW		 1079/*
1080 * Reconstructs the phase from register values according to the logic that was
1081 * implemented in qemu 2.3. This is the default value that is used if the phase
1082 * subsection is not present on migration.
1083 *
1084 * Don't change this function to reflect newer qemu versions, it is part of
1085 * the migration ABI.
1086 */
1087static int reconstruct_phase(FDCtrl *fdctrl)
1088{
1089 if (fdctrl->msr & FD_MSR_NONDMA) {
1090 return FD_PHASE_EXECUTION;
1091 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
1092 /* qemu 2.3 disabled RQM only during DMA transfers */
1093 return FD_PHASE_EXECUTION;
1094 } else if (fdctrl->msr & FD_MSR_DIO) {
1095 return FD_PHASE_RESULT;
1096 } else {
1097 return FD_PHASE_COMMAND;
1098 }
1099}
1100
44b1ff31 1101static int fdc_pre_save(void *opaque)
3ccacc4a 1102{
5c02c033 1103 FDCtrl *s = opaque;
3ccacc4a 1104
d7a6c270 1105 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
44b1ff31
DDAG		 1106
1107 return 0;
3ccacc4a
BS		 1108}
1109
85d291a0
KW		 1110static int fdc_pre_load(void *opaque)
1111{
1112 FDCtrl *s = opaque;
1113 s->phase = FD_PHASE_RECONSTRUCT;
1114 return 0;
1115}
1116
e59fb374 1117static int fdc_post_load(void *opaque, int version_id)
3ccacc4a 1118{
5c02c033 1119 FDCtrl *s = opaque;
3ccacc4a 1120
d7a6c270
JQ		 1121 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
1122 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
85d291a0
KW		 1123
1124 if (s->phase == FD_PHASE_RECONSTRUCT) {
1125 s->phase = reconstruct_phase(s);
1126 }
1127
3ccacc4a
BS		 1128 return 0;
1129}
1130
c0b92f30
PD		 1131static bool fdc_reset_sensei_needed(void *opaque)
1132{
1133 FDCtrl *s = opaque;
1134
1135 return s->reset_sensei != 0;
1136}
1137
1138static const VMStateDescription vmstate_fdc_reset_sensei = {
1139 .name = "fdc/reset_sensei",
1140 .version_id = 1,
1141 .minimum_version_id = 1,
5cd8cada 1142 .needed = fdc_reset_sensei_needed,
c0b92f30
PD		 1143 .fields = (VMStateField[]) {
1144 VMSTATE_INT32(reset_sensei, FDCtrl),
1145 VMSTATE_END_OF_LIST()
1146 }
1147};
1148
1149static bool fdc_result_timer_needed(void *opaque)
1150{
1151 FDCtrl *s = opaque;
1152
1153 return timer_pending(s->result_timer);
1154}
1155
1156static const VMStateDescription vmstate_fdc_result_timer = {
1157 .name = "fdc/result_timer",
1158 .version_id = 1,
1159 .minimum_version_id = 1,
5cd8cada 1160 .needed = fdc_result_timer_needed,
c0b92f30 1161 .fields = (VMStateField[]) {
e720677e 1162 VMSTATE_TIMER_PTR(result_timer, FDCtrl),
c0b92f30
PD		 1163 VMSTATE_END_OF_LIST()
1164 }
1165};
1166
85d291a0
KW		 1167static bool fdc_phase_needed(void *opaque)
1168{
1169 FDCtrl *fdctrl = opaque;
1170
1171 return reconstruct_phase(fdctrl) != fdctrl->phase;
1172}
1173
1174static const VMStateDescription vmstate_fdc_phase = {
1175 .name = "fdc/phase",
1176 .version_id = 1,
1177 .minimum_version_id = 1,
5cd8cada 1178 .needed = fdc_phase_needed,
85d291a0
KW		 1179 .fields = (VMStateField[]) {
1180 VMSTATE_UINT8(phase, FDCtrl),
1181 VMSTATE_END_OF_LIST()
1182 }
1183};
1184
d7a6c270 1185static const VMStateDescription vmstate_fdc = {
aef30c3c 1186 .name = "fdc",
d7a6c270
JQ		 1187 .version_id = 2,
1188 .minimum_version_id = 2,
d7a6c270 1189 .pre_save = fdc_pre_save,
85d291a0 1190 .pre_load = fdc_pre_load,
d7a6c270 1191 .post_load = fdc_post_load,
d49805ae 1192 .fields = (VMStateField[]) {
d7a6c270 1193 /* Controller State */
5c02c033
BS		 1194 VMSTATE_UINT8(sra, FDCtrl),
1195 VMSTATE_UINT8(srb, FDCtrl),
1196 VMSTATE_UINT8(dor_vmstate, FDCtrl),
1197 VMSTATE_UINT8(tdr, FDCtrl),
1198 VMSTATE_UINT8(dsr, FDCtrl),
1199 VMSTATE_UINT8(msr, FDCtrl),
1200 VMSTATE_UINT8(status0, FDCtrl),
1201 VMSTATE_UINT8(status1, FDCtrl),
1202 VMSTATE_UINT8(status2, FDCtrl),
d7a6c270 1203 /* Command FIFO */
8ec68b06
BS		 1204 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
1205 uint8_t),
5c02c033
BS		 1206 VMSTATE_UINT32(data_pos, FDCtrl),
1207 VMSTATE_UINT32(data_len, FDCtrl),
1208 VMSTATE_UINT8(data_state, FDCtrl),
1209 VMSTATE_UINT8(data_dir, FDCtrl),
1210 VMSTATE_UINT8(eot, FDCtrl),
d7a6c270 1211 /* States kept only to be returned back */
5c02c033
BS		 1212 VMSTATE_UINT8(timer0, FDCtrl),
1213 VMSTATE_UINT8(timer1, FDCtrl),
1214 VMSTATE_UINT8(precomp_trk, FDCtrl),
1215 VMSTATE_UINT8(config, FDCtrl),
1216 VMSTATE_UINT8(lock, FDCtrl),
1217 VMSTATE_UINT8(pwrd, FDCtrl),
d2164ad3 1218 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl, NULL),
5c02c033
BS		 1219 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
1220 vmstate_fdrive, FDrive),
d7a6c270 1221 VMSTATE_END_OF_LIST()
c0b92f30 1222 },
5cd8cada
JQ		 1223 .subsections = (const VMStateDescription*[]) {
1224 &vmstate_fdc_reset_sensei,
1225 &vmstate_fdc_result_timer,
1226 &vmstate_fdc_phase,
1227 NULL
78ae820c 1228 }
d7a6c270 1229};
3ccacc4a 1230
2be37833 1231static void fdctrl_external_reset_sysbus(DeviceState *d)
3ccacc4a 1232{
dd3be742 1233 FDCtrlSysBus *sys = SYSBUS_FDC(d);
5c02c033 1234 FDCtrl *s = &sys->state;
2be37833
BS		 1235
1236 fdctrl_reset(s, 0);
1237}
1238
1239static void fdctrl_external_reset_isa(DeviceState *d)
1240{
020c8e76 1241 FDCtrlISABus *isa = ISA_FDC(d);
5c02c033 1242 FDCtrl *s = &isa->state;
3ccacc4a
BS		 1243
1244 fdctrl_reset(s, 0);
1245}
1246
2be17ebd
BS		 1247static void fdctrl_handle_tc(void *opaque, int irq, int level)
1248{
5c02c033 1249 //FDCtrl *s = opaque;
2be17ebd
BS		 1250
1251 if (level) {
1252 // XXX
1253 FLOPPY_DPRINTF("TC pulsed\n");
1254 }
1255}
1256
8977f3c1 1257/* Change IRQ state */
5c02c033 1258static void fdctrl_reset_irq(FDCtrl *fdctrl)
8977f3c1 1259{
d497d534 1260 fdctrl->status0 = 0;
8c6a4d77
BS		 1261 if (!(fdctrl->sra & FD_SRA_INTPEND))
1262 return;
ed5fd2cc 1263 FLOPPY_DPRINTF("Reset interrupt\n");
d537cf6c 1264 qemu_set_irq(fdctrl->irq, 0);
8c6a4d77 1265 fdctrl->sra &= ~FD_SRA_INTPEND;
8977f3c1
FB		 1266}
1267
d497d534 1268static void fdctrl_raise_irq(FDCtrl *fdctrl)
8977f3c1 1269{
8c6a4d77 1270 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
d537cf6c 1271 qemu_set_irq(fdctrl->irq, 1);
8c6a4d77 1272 fdctrl->sra |= FD_SRA_INTPEND;
8977f3c1 1273 }
21fcf360 1274
f2d81b33 1275 fdctrl->reset_sensei = 0;
77370520 1276 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
8977f3c1
FB		 1277}
1278
4b19ec0c 1279/* Reset controller */
5c02c033 1280static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
8977f3c1
FB		 1281{
1282 int i;
1283
4b19ec0c 1284 FLOPPY_DPRINTF("reset controller\n");
baca51fa 1285 fdctrl_reset_irq(fdctrl);
4b19ec0c 1286 /* Initialise controller */
8c6a4d77
BS		 1287 fdctrl->sra = 0;
1288 fdctrl->srb = 0xc0;
4be74634 1289 if (!fdctrl->drives[1].blk) {
8c6a4d77 1290 fdctrl->sra |= FD_SRA_nDRV2;
4be74634 1291 }
baca51fa 1292 fdctrl->cur_drv = 0;
1c346df2 1293 fdctrl->dor = FD_DOR_nRESET;
368df94d 1294 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
b9b3d225 1295 fdctrl->msr = FD_MSR_RQM;
c0b92f30
PD		 1296 fdctrl->reset_sensei = 0;
1297 timer_del(fdctrl->result_timer);
8977f3c1 1298 /* FIFO state */
baca51fa
FB		 1299 fdctrl->data_pos = 0;
1300 fdctrl->data_len = 0;
b9b3d225 1301 fdctrl->data_state = 0;
baca51fa 1302 fdctrl->data_dir = FD_DIR_WRITE;
8977f3c1 1303 for (i = 0; i < MAX_FD; i++)
1c346df2 1304 fd_recalibrate(&fdctrl->drives[i]);
07e415f2 1305 fdctrl_to_command_phase(fdctrl);
77370520 1306 if (do_irq) {
d497d534
HP		 1307 fdctrl->status0 |= FD_SR0_RDYCHG;
1308 fdctrl_raise_irq(fdctrl);
f2d81b33 1309 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
77370520 1310 }
baca51fa
FB		 1311}
1312
5c02c033 1313static inline FDrive *drv0(FDCtrl *fdctrl)
baca51fa 1314{
46d3233b 1315 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
baca51fa
FB		 1316}
1317
5c02c033 1318static inline FDrive *drv1(FDCtrl *fdctrl)
baca51fa 1319{
46d3233b
BS		 1320 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
1321 return &fdctrl->drives[1];
1322 else
1323 return &fdctrl->drives[0];
baca51fa
FB		 1324}
1325
78ae820c 1326#if MAX_FD == 4
5c02c033 1327static inline FDrive *drv2(FDCtrl *fdctrl)
78ae820c
BS		 1328{
1329 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
1330 return &fdctrl->drives[2];
1331 else
1332 return &fdctrl->drives[1];
1333}
1334
5c02c033 1335static inline FDrive *drv3(FDCtrl *fdctrl)
78ae820c
BS		 1336{
1337 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
1338 return &fdctrl->drives[3];
1339 else
1340 return &fdctrl->drives[2];
1341}
1342#endif
1343
394ea2ca 1344static FDrive *get_drv(FDCtrl *fdctrl, int unit)
baca51fa 1345{
394ea2ca 1346 switch (unit) {
78ae820c
BS		 1347 case 0: return drv0(fdctrl);
1348 case 1: return drv1(fdctrl);
1349#if MAX_FD == 4
1350 case 2: return drv2(fdctrl);
1351 case 3: return drv3(fdctrl);
1352#endif
1353 default: return NULL;
1354 }
8977f3c1
FB		 1355}
1356
394ea2ca
KW		 1357static FDrive *get_cur_drv(FDCtrl *fdctrl)
1358{
1359 return get_drv(fdctrl, fdctrl->cur_drv);
1360}
1361
8c6a4d77 1362/* Status A register : 0x00 (read-only) */
5c02c033 1363static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
8c6a4d77
BS		 1364{
1365 uint32_t retval = fdctrl->sra;
1366
1367 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
1368
1369 return retval;
1370}
1371
8977f3c1 1372/* Status B register : 0x01 (read-only) */
5c02c033 1373static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
8977f3c1 1374{
8c6a4d77
BS		 1375 uint32_t retval = fdctrl->srb;
1376
1377 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
1378
1379 return retval;
8977f3c1
FB		 1380}
1381
1382/* Digital output register : 0x02 */
5c02c033 1383static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
8977f3c1 1384{
1c346df2 1385 uint32_t retval = fdctrl->dor;
8977f3c1 1386
8977f3c1 1387 /* Selected drive */
baca51fa 1388 retval |= fdctrl->cur_drv;
8977f3c1
FB		 1389 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1390
1391 return retval;
1392}
1393
5c02c033 1394static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1395{
8977f3c1 1396 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
8c6a4d77
BS		 1397
1398 /* Motors */
1399 if (value & FD_DOR_MOTEN0)
1400 fdctrl->srb |= FD_SRB_MTR0;
1401 else
1402 fdctrl->srb &= ~FD_SRB_MTR0;
1403 if (value & FD_DOR_MOTEN1)
1404 fdctrl->srb |= FD_SRB_MTR1;
1405 else
1406 fdctrl->srb &= ~FD_SRB_MTR1;
1407
1408 /* Drive */
1409 if (value & 1)
1410 fdctrl->srb |= FD_SRB_DR0;
1411 else
1412 fdctrl->srb &= ~FD_SRB_DR0;
1413
8977f3c1 1414 /* Reset */
9fea808a 1415 if (!(value & FD_DOR_nRESET)) {
1c346df2 1416 if (fdctrl->dor & FD_DOR_nRESET) {
4b19ec0c 1417 FLOPPY_DPRINTF("controller enter RESET state\n");
8977f3c1
FB		 1418 }
1419 } else {
1c346df2 1420 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 1421 FLOPPY_DPRINTF("controller out of RESET state\n");
fb6cf1d0 1422 fdctrl_reset(fdctrl, 1);
b9b3d225 1423 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
8977f3c1
FB		 1424 }
1425 }
1426 /* Selected drive */
9fea808a 1427 fdctrl->cur_drv = value & FD_DOR_SELMASK;
368df94d
BS		 1428
1429 fdctrl->dor = value;
8977f3c1
FB		 1430}
1431
1432/* Tape drive register : 0x03 */
5c02c033 1433static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
8977f3c1 1434{
46d3233b 1435 uint32_t retval = fdctrl->tdr;
8977f3c1 1436
8977f3c1
FB		 1437 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1438
1439 return retval;
1440}
1441
5c02c033 1442static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1443{
8977f3c1 1444 /* Reset mode */
1c346df2 1445 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 1446 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB		 1447 return;
1448 }
1449 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1450 /* Disk boot selection indicator */
46d3233b 1451 fdctrl->tdr = value & FD_TDR_BOOTSEL;
8977f3c1
FB		 1452 /* Tape indicators: never allow */
1453}
1454
1455/* Main status register : 0x04 (read) */
5c02c033 1456static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
8977f3c1 1457{
b9b3d225 1458 uint32_t retval = fdctrl->msr;
8977f3c1 1459
b9b3d225 1460 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1c346df2 1461 fdctrl->dor |= FD_DOR_nRESET;
b9b3d225 1462
8977f3c1
FB		 1463 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1464
1465 return retval;
1466}
1467
1468/* Data select rate register : 0x04 (write) */
5c02c033 1469static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1470{
8977f3c1 1471 /* Reset mode */
1c346df2 1472 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4f431960
JM		 1473 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1474 return;
1475 }
8977f3c1
FB		 1476 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1477 /* Reset: autoclear */
9fea808a 1478 if (value & FD_DSR_SWRESET) {
1c346df2 1479 fdctrl->dor &= ~FD_DOR_nRESET;
baca51fa 1480 fdctrl_reset(fdctrl, 1);
1c346df2 1481 fdctrl->dor |= FD_DOR_nRESET;
8977f3c1 1482 }
9fea808a 1483 if (value & FD_DSR_PWRDOWN) {
baca51fa 1484 fdctrl_reset(fdctrl, 1);
8977f3c1 1485 }
b9b3d225 1486 fdctrl->dsr = value;
8977f3c1
FB		 1487}
1488
a758f8f4
HP		 1489/* Configuration control register: 0x07 (write) */
1490static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1491{
1492 /* Reset mode */
1493 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1494 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1495 return;
1496 }
1497 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1498
1499 /* Only the rate selection bits used in AT mode, and we
1500 * store those in the DSR.
1501 */
1502 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1503 (value & FD_DSR_DRATEMASK);
1504}
1505
5c02c033 1506static int fdctrl_media_changed(FDrive *drv)
ea185bbd 1507{
21fcf360 1508 return drv->media_changed;
ea185bbd
FB		 1509}
1510
8977f3c1 1511/* Digital input register : 0x07 (read-only) */
5c02c033 1512static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
8977f3c1 1513{
8977f3c1
FB		 1514 uint32_t retval = 0;
1515
a2df5fa3 1516 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
9fea808a 1517 retval |= FD_DIR_DSKCHG;
a2df5fa3 1518 }
3c83eb4f 1519 if (retval != 0) {
baca51fa 1520 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
3c83eb4f 1521 }
8977f3c1
FB		 1522
1523 return retval;
1524}
1525
07e415f2
KW		 1526/* Clear the FIFO and update the state for receiving the next command */
1527static void fdctrl_to_command_phase(FDCtrl *fdctrl)
8977f3c1 1528{
85d291a0 1529 fdctrl->phase = FD_PHASE_COMMAND;
baca51fa
FB		 1530 fdctrl->data_dir = FD_DIR_WRITE;
1531 fdctrl->data_pos = 0;
6cc8a11c 1532 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */
b9b3d225 1533 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
6cc8a11c 1534 fdctrl->msr |= FD_MSR_RQM;
8977f3c1
FB		 1535}
1536
83a26013
KW		 1537/* Update the state to allow the guest to read out the command status.
1538 * @fifo_len is the number of result bytes to be read out. */
1539static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
8977f3c1 1540{
85d291a0 1541 fdctrl->phase = FD_PHASE_RESULT;
baca51fa
FB		 1542 fdctrl->data_dir = FD_DIR_READ;
1543 fdctrl->data_len = fifo_len;
1544 fdctrl->data_pos = 0;
b9b3d225 1545 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
8977f3c1
FB		 1546}
1547
1548/* Set an error: unimplemented/unknown command */
5c02c033 1549static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
8977f3c1 1550{
cced7a13
BS		 1551 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1552 fdctrl->fifo[0]);
9fea808a 1553 fdctrl->fifo[0] = FD_SR0_INVCMD;
83a26013 1554 fdctrl_to_result_phase(fdctrl, 1);
8977f3c1
FB		 1555}
1556
6be01b1e
PH		 1557/* Seek to next sector
1558 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1559 * otherwise returns 1
1560 */
5c02c033 1561static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
746d6de7
BS		 1562{
1563 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1564 cur_drv->head, cur_drv->track, cur_drv->sect,
1565 fd_sector(cur_drv));
1566 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1567 error in fact */
6be01b1e
PH		 1568 uint8_t new_head = cur_drv->head;
1569 uint8_t new_track = cur_drv->track;
1570 uint8_t new_sect = cur_drv->sect;
1571
1572 int ret = 1;
1573
1574 if (new_sect >= cur_drv->last_sect ||
1575 new_sect == fdctrl->eot) {
1576 new_sect = 1;
746d6de7 1577 if (FD_MULTI_TRACK(fdctrl->data_state)) {
6be01b1e 1578 if (new_head == 0 &&
746d6de7 1579 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
6be01b1e 1580 new_head = 1;
746d6de7 1581 } else {
6be01b1e
PH		 1582 new_head = 0;
1583 new_track++;
c5139bd9 1584 fdctrl->status0 |= FD_SR0_SEEK;
6be01b1e
PH		 1585 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1586 ret = 0;
1587 }
746d6de7
BS		 1588 }
1589 } else {
c5139bd9 1590 fdctrl->status0 |= FD_SR0_SEEK;
6be01b1e
PH		 1591 new_track++;
1592 ret = 0;
1593 }
1594 if (ret == 1) {
1595 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1596 new_head, new_track, new_sect, fd_sector(cur_drv));
746d6de7 1597 }
746d6de7 1598 } else {
6be01b1e 1599 new_sect++;
746d6de7 1600 }
6be01b1e
PH		 1601 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1602 return ret;
746d6de7
BS		 1603}
1604
8977f3c1 1605/* Callback for transfer end (stop or abort) */
5c02c033
BS		 1606static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1607 uint8_t status1, uint8_t status2)
8977f3c1 1608{
5c02c033 1609 FDrive *cur_drv;
baca51fa 1610 cur_drv = get_cur_drv(fdctrl);
075f5532
HP		 1611
1612 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1613 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1614 if (cur_drv->head) {
1615 fdctrl->status0 |= FD_SR0_HEAD;
1616 }
1617 fdctrl->status0 |= status0;
2fee0088 1618
8977f3c1 1619 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
2fee0088
PH		 1620 status0, status1, status2, fdctrl->status0);
1621 fdctrl->fifo[0] = fdctrl->status0;
baca51fa
FB		 1622 fdctrl->fifo[1] = status1;
1623 fdctrl->fifo[2] = status2;
1624 fdctrl->fifo[3] = cur_drv->track;
1625 fdctrl->fifo[4] = cur_drv->head;
1626 fdctrl->fifo[5] = cur_drv->sect;
1627 fdctrl->fifo[6] = FD_SECTOR_SC;
1628 fdctrl->data_dir = FD_DIR_READ;
441f6692 1629 if (fdctrl->dma_chann != -1 && !(fdctrl->msr & FD_MSR_NONDMA)) {
c8a35f1c
HP		 1630 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1631 k->release_DREQ(fdctrl->dma, fdctrl->dma_chann);
ed5fd2cc 1632 }
b9b3d225 1633 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
368df94d 1634 fdctrl->msr &= ~FD_MSR_NONDMA;
34abf9a7 1635
83a26013 1636 fdctrl_to_result_phase(fdctrl, 7);
d497d534 1637 fdctrl_raise_irq(fdctrl);
8977f3c1
FB		 1638}
1639
1640/* Prepare a data transfer (either DMA or FIFO) */
5c02c033 1641static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
8977f3c1 1642{
5c02c033 1643 FDrive *cur_drv;
8977f3c1 1644 uint8_t kh, kt, ks;
8977f3c1 1645
cefec4f5 1646 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB		 1647 cur_drv = get_cur_drv(fdctrl);
1648 kt = fdctrl->fifo[2];
1649 kh = fdctrl->fifo[3];
1650 ks = fdctrl->fifo[4];
4b19ec0c 1651 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
cefec4f5 1652 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP		 1653 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1654 NUM_SIDES(cur_drv)));
77370520 1655 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
8977f3c1
FB		 1656 case 2:
1657 /* sect too big */
9fea808a 1658 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1659 fdctrl->fifo[3] = kt;
1660 fdctrl->fifo[4] = kh;
1661 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1662 return;
1663 case 3:
1664 /* track too big */
77370520 1665 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB		 1666 fdctrl->fifo[3] = kt;
1667 fdctrl->fifo[4] = kh;
1668 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1669 return;
1670 case 4:
1671 /* No seek enabled */
9fea808a 1672 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1673 fdctrl->fifo[3] = kt;
1674 fdctrl->fifo[4] = kh;
1675 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1676 return;
1677 case 1:
d6ed4e21 1678 fdctrl->status0 |= FD_SR0_SEEK;
8977f3c1
FB		 1679 break;
1680 default:
1681 break;
1682 }
b9b3d225 1683
844f65d6
HP		 1684 /* Check the data rate. If the programmed data rate does not match
1685 * the currently inserted medium, the operation has to fail. */
1686 if (fdctrl->check_media_rate &&
1687 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1688 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1689 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1690 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1691 fdctrl->fifo[3] = kt;
1692 fdctrl->fifo[4] = kh;
1693 fdctrl->fifo[5] = ks;
1694 return;
1695 }
1696
8977f3c1 1697 /* Set the FIFO state */
baca51fa
FB		 1698 fdctrl->data_dir = direction;
1699 fdctrl->data_pos = 0;
27c86e24 1700 assert(fdctrl->msr & FD_MSR_CMDBUSY);
baca51fa
FB		 1701 if (fdctrl->fifo[0] & 0x80)
1702 fdctrl->data_state |= FD_STATE_MULTI;
1703 else
1704 fdctrl->data_state &= ~FD_STATE_MULTI;
c83f97b5 1705 if (fdctrl->fifo[5] == 0) {
baca51fa
FB		 1706 fdctrl->data_len = fdctrl->fifo[8];
1707 } else {
4f431960 1708 int tmp;
3bcb80f1 1709 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
771effeb 1710 tmp = (fdctrl->fifo[6] - ks + 1);
baca51fa 1711 if (fdctrl->fifo[0] & 0x80)
771effeb 1712 tmp += fdctrl->fifo[6];
4f431960 1713 fdctrl->data_len *= tmp;
baca51fa 1714 }
890fa6be 1715 fdctrl->eot = fdctrl->fifo[6];
368df94d 1716 if (fdctrl->dor & FD_DOR_DMAEN) {
c8a35f1c
HP		 1717 IsaDmaTransferMode dma_mode;
1718 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1719 bool dma_mode_ok;
8977f3c1 1720 /* DMA transfer are enabled. Check if DMA channel is well programmed */
c8a35f1c 1721 dma_mode = k->get_transfer_mode(fdctrl->dma, fdctrl->dma_chann);
baca51fa 1722 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
4f431960 1723 dma_mode, direction,
baca51fa 1724 (128 << fdctrl->fifo[5]) *
4f431960 1725 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
c8a35f1c
HP		 1726 switch (direction) {
1727 case FD_DIR_SCANE:
1728 case FD_DIR_SCANL:
1729 case FD_DIR_SCANH:
1730 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_VERIFY);
1731 break;
1732 case FD_DIR_WRITE:
1733 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_WRITE);
1734 break;
1735 case FD_DIR_READ:
1736 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_READ);
1737 break;
1738 case FD_DIR_VERIFY:
1739 dma_mode_ok = true;
1740 break;
1741 default:
1742 dma_mode_ok = false;
1743 break;
1744 }
1745 if (dma_mode_ok) {
8977f3c1 1746 /* No access is allowed until DMA transfer has completed */
b9b3d225 1747 fdctrl->msr &= ~FD_MSR_RQM;
7ea004ed
HP		 1748 if (direction != FD_DIR_VERIFY) {
1749 /* Now, we just have to wait for the DMA controller to
1750 * recall us...
1751 */
c8a35f1c
HP		 1752 k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann);
1753 k->schedule(fdctrl->dma);
7ea004ed
HP		 1754 } else {
1755 /* Start transfer */
1756 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1757 fdctrl->data_len);
1758 }
8977f3c1 1759 return;
baca51fa 1760 } else {
cced7a13
BS		 1761 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1762 direction);
8977f3c1
FB		 1763 }
1764 }
1765 FLOPPY_DPRINTF("start non-DMA transfer\n");
6cc8a11c 1766 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM;
b9b3d225
BS		 1767 if (direction != FD_DIR_WRITE)
1768 fdctrl->msr |= FD_MSR_DIO;
8977f3c1 1769 /* IO based transfer: calculate len */
d497d534 1770 fdctrl_raise_irq(fdctrl);
8977f3c1
FB		 1771}
1772
1773/* Prepare a transfer of deleted data */
5c02c033 1774static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
8977f3c1 1775{
cced7a13 1776 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
77370520 1777
8977f3c1
FB		 1778 /* We don't handle deleted data,
1779 * so we don't return *ANYTHING*
1780 */
9fea808a 1781 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
8977f3c1
FB		 1782}
1783
1784/* handlers for DMA transfers */
85571bc7
FB		 1785static int fdctrl_transfer_handler (void *opaque, int nchan,
1786 int dma_pos, int dma_len)
8977f3c1 1787{
5c02c033
BS		 1788 FDCtrl *fdctrl;
1789 FDrive *cur_drv;
baca51fa 1790 int len, start_pos, rel_pos;
8977f3c1 1791 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
c8a35f1c 1792 IsaDmaClass *k;
8977f3c1 1793
baca51fa 1794 fdctrl = opaque;
b9b3d225 1795 if (fdctrl->msr & FD_MSR_RQM) {
8977f3c1
FB		 1796 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1797 return 0;
1798 }
c8a35f1c 1799 k = ISADMA_GET_CLASS(fdctrl->dma);
baca51fa
FB		 1800 cur_drv = get_cur_drv(fdctrl);
1801 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1802 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1803 status2 = FD_SR2_SNS;
85571bc7
FB		 1804 if (dma_len > fdctrl->data_len)
1805 dma_len = fdctrl->data_len;
4be74634 1806 if (cur_drv->blk == NULL) {
4f431960 1807 if (fdctrl->data_dir == FD_DIR_WRITE)
9fea808a 1808 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
4f431960 1809 else
9fea808a 1810 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
4f431960 1811 len = 0;
890fa6be
FB		 1812 goto transfer_error;
1813 }
baca51fa 1814 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
85571bc7
FB		 1815 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1816 len = dma_len - fdctrl->data_pos;
baca51fa
FB		 1817 if (len + rel_pos > FD_SECTOR_LEN)
1818 len = FD_SECTOR_LEN - rel_pos;
6f7e9aec
FB		 1819 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1820 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
cefec4f5 1821 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
baca51fa 1822 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
9fea808a 1823 fd_sector(cur_drv) * FD_SECTOR_LEN);
baca51fa 1824 if (fdctrl->data_dir != FD_DIR_WRITE ||
4f431960 1825 len < FD_SECTOR_LEN || rel_pos != 0) {
baca51fa 1826 /* READ & SCAN commands and realign to a sector for WRITE */
a7a5b7c0
EB		 1827 if (blk_pread(cur_drv->blk, fd_offset(cur_drv),
1828 fdctrl->fifo, BDRV_SECTOR_SIZE) < 0) {
8977f3c1
FB		 1829 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1830 fd_sector(cur_drv));
1831 /* Sure, image size is too small... */
baca51fa 1832 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
8977f3c1 1833 }
890fa6be 1834 }
4f431960
JM		 1835 switch (fdctrl->data_dir) {
1836 case FD_DIR_READ:
1837 /* READ commands */
c8a35f1c
HP		 1838 k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1839 fdctrl->data_pos, len);
4f431960
JM		 1840 break;
1841 case FD_DIR_WRITE:
baca51fa 1842 /* WRITE commands */
8510854e
HP		 1843 if (cur_drv->ro) {
1844 /* Handle readonly medium early, no need to do DMA, touch the
1845 * LED or attempt any writes. A real floppy doesn't attempt
1846 * to write to readonly media either. */
1847 fdctrl_stop_transfer(fdctrl,
1848 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1849 0x00);
1850 goto transfer_error;
1851 }
1852
c8a35f1c
HP		 1853 k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1854 fdctrl->data_pos, len);
a7a5b7c0
EB		 1855 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv),
1856 fdctrl->fifo, BDRV_SECTOR_SIZE, 0) < 0) {
cced7a13
BS		 1857 FLOPPY_DPRINTF("error writing sector %d\n",
1858 fd_sector(cur_drv));
9fea808a 1859 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 1860 goto transfer_error;
890fa6be 1861 }
4f431960 1862 break;
7ea004ed
HP		 1863 case FD_DIR_VERIFY:
1864 /* VERIFY commands */
1865 break;
4f431960
JM		 1866 default:
1867 /* SCAN commands */
baca51fa 1868 {
4f431960 1869 uint8_t tmpbuf[FD_SECTOR_LEN];
baca51fa 1870 int ret;
c8a35f1c
HP		 1871 k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos,
1872 len);
baca51fa 1873 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
8977f3c1 1874 if (ret == 0) {
77370520 1875 status2 = FD_SR2_SEH;
8977f3c1
FB		 1876 goto end_transfer;
1877 }
baca51fa
FB		 1878 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1879 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
8977f3c1
FB		 1880 status2 = 0x00;
1881 goto end_transfer;
1882 }
1883 }
4f431960 1884 break;
8977f3c1 1885 }
4f431960
JM		 1886 fdctrl->data_pos += len;
1887 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
baca51fa 1888 if (rel_pos == 0) {
8977f3c1 1889 /* Seek to next sector */
746d6de7
BS		 1890 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1891 break;
8977f3c1
FB		 1892 }
1893 }
4f431960 1894 end_transfer:
baca51fa
FB		 1895 len = fdctrl->data_pos - start_pos;
1896 FLOPPY_DPRINTF("end transfer %d %d %d\n",
4f431960 1897 fdctrl->data_pos, len, fdctrl->data_len);
baca51fa
FB		 1898 if (fdctrl->data_dir == FD_DIR_SCANE ||
1899 fdctrl->data_dir == FD_DIR_SCANL ||
1900 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1901 status2 = FD_SR2_SEH;
baca51fa 1902 fdctrl->data_len -= len;
890fa6be 1903 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
4f431960 1904 transfer_error:
8977f3c1 1905
baca51fa 1906 return len;
8977f3c1
FB		 1907}
1908
8977f3c1 1909/* Data register : 0x05 */
5c02c033 1910static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
8977f3c1 1911{
5c02c033 1912 FDrive *cur_drv;
8977f3c1 1913 uint32_t retval = 0;
e9077462 1914 uint32_t pos;
8977f3c1 1915
baca51fa 1916 cur_drv = get_cur_drv(fdctrl);
b9b3d225
BS		 1917 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1918 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
cced7a13 1919 FLOPPY_DPRINTF("error: controller not ready for reading\n");
8977f3c1
FB		 1920 return 0;
1921 }
f6c2d1d8
KW		 1922
1923 /* If data_len spans multiple sectors, the current position in the FIFO
1924 * wraps around while fdctrl->data_pos is the real position in the whole
1925 * request. */
baca51fa 1926 pos = fdctrl->data_pos;
e9077462 1927 pos %= FD_SECTOR_LEN;
f6c2d1d8
KW		 1928
1929 switch (fdctrl->phase) {
1930 case FD_PHASE_EXECUTION:
1931 assert(fdctrl->msr & FD_MSR_NONDMA);
8977f3c1 1932 if (pos == 0) {
746d6de7
BS		 1933 if (fdctrl->data_pos != 0)
1934 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1935 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1936 fd_sector(cur_drv));
1937 return 0;
1938 }
a7a5b7c0
EB		 1939 if (blk_pread(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
1940 BDRV_SECTOR_SIZE)
4be74634 1941 < 0) {
77370520
BS		 1942 FLOPPY_DPRINTF("error getting sector %d\n",
1943 fd_sector(cur_drv));
1944 /* Sure, image size is too small... */
1945 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1946 }
8977f3c1 1947 }
f6c2d1d8
KW		 1948
1949 if (++fdctrl->data_pos == fdctrl->data_len) {
6cc8a11c 1950 fdctrl->msr &= ~FD_MSR_RQM;
c5139bd9 1951 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
f6c2d1d8
KW		 1952 }
1953 break;
1954
1955 case FD_PHASE_RESULT:
1956 assert(!(fdctrl->msr & FD_MSR_NONDMA));
1957 if (++fdctrl->data_pos == fdctrl->data_len) {
6cc8a11c 1958 fdctrl->msr &= ~FD_MSR_RQM;
07e415f2 1959 fdctrl_to_command_phase(fdctrl);
ed5fd2cc
FB		 1960 fdctrl_reset_irq(fdctrl);
1961 }
f6c2d1d8
KW		 1962 break;
1963
1964 case FD_PHASE_COMMAND:
1965 default:
1966 abort();
8977f3c1 1967 }
f6c2d1d8
KW		 1968
1969 retval = fdctrl->fifo[pos];
8977f3c1
FB		 1970 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1971
1972 return retval;
1973}
1974
5c02c033 1975static void fdctrl_format_sector(FDCtrl *fdctrl)
8977f3c1 1976{
5c02c033 1977 FDrive *cur_drv;
baca51fa 1978 uint8_t kh, kt, ks;
8977f3c1 1979
cefec4f5 1980 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB		 1981 cur_drv = get_cur_drv(fdctrl);
1982 kt = fdctrl->fifo[6];
1983 kh = fdctrl->fifo[7];
1984 ks = fdctrl->fifo[8];
1985 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
cefec4f5 1986 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP		 1987 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1988 NUM_SIDES(cur_drv)));
9fea808a 1989 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
baca51fa
FB		 1990 case 2:
1991 /* sect too big */
9fea808a 1992 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1993 fdctrl->fifo[3] = kt;
1994 fdctrl->fifo[4] = kh;
1995 fdctrl->fifo[5] = ks;
1996 return;
1997 case 3:
1998 /* track too big */
77370520 1999 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB		 2000 fdctrl->fifo[3] = kt;
2001 fdctrl->fifo[4] = kh;
2002 fdctrl->fifo[5] = ks;
2003 return;
2004 case 4:
2005 /* No seek enabled */
9fea808a 2006 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 2007 fdctrl->fifo[3] = kt;
2008 fdctrl->fifo[4] = kh;
2009 fdctrl->fifo[5] = ks;
2010 return;
2011 case 1:
cd30b53d 2012 fdctrl->status0 |= FD_SR0_SEEK;
baca51fa
FB		 2013 break;
2014 default:
2015 break;
2016 }
2017 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
4be74634 2018 if (cur_drv->blk == NULL ||
a7a5b7c0
EB		 2019 blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
2020 BDRV_SECTOR_SIZE, 0) < 0) {
cced7a13 2021 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
9fea808a 2022 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 2023 } else {
4f431960
JM		 2024 if (cur_drv->sect == cur_drv->last_sect) {
2025 fdctrl->data_state &= ~FD_STATE_FORMAT;
2026 /* Last sector done */
cd30b53d 2027 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
4f431960
JM		 2028 } else {
2029 /* More to do */
2030 fdctrl->data_pos = 0;
2031 fdctrl->data_len = 4;
2032 }
baca51fa
FB		 2033 }
2034}
2035
5c02c033 2036static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
65cef780
BS		 2037{
2038 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
2039 fdctrl->fifo[0] = fdctrl->lock << 4;
83a26013 2040 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2041}
2042
5c02c033 2043static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
65cef780 2044{
5c02c033 2045 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2046
2047 /* Drives position */
2048 fdctrl->fifo[0] = drv0(fdctrl)->track;
2049 fdctrl->fifo[1] = drv1(fdctrl)->track;
78ae820c
BS		 2050#if MAX_FD == 4
2051 fdctrl->fifo[2] = drv2(fdctrl)->track;
2052 fdctrl->fifo[3] = drv3(fdctrl)->track;
2053#else
65cef780
BS		 2054 fdctrl->fifo[2] = 0;
2055 fdctrl->fifo[3] = 0;
78ae820c 2056#endif
65cef780
BS		 2057 /* timers */
2058 fdctrl->fifo[4] = fdctrl->timer0;
368df94d 2059 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
65cef780
BS		 2060 fdctrl->fifo[6] = cur_drv->last_sect;
2061 fdctrl->fifo[7] = (fdctrl->lock << 7) |
2062 (cur_drv->perpendicular << 2);
2063 fdctrl->fifo[8] = fdctrl->config;
2064 fdctrl->fifo[9] = fdctrl->precomp_trk;
83a26013 2065 fdctrl_to_result_phase(fdctrl, 10);
65cef780
BS		 2066}
2067
5c02c033 2068static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
65cef780
BS		 2069{
2070 /* Controller's version */
2071 fdctrl->fifo[0] = fdctrl->version;
83a26013 2072 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2073}
2074
5c02c033 2075static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
65cef780
BS		 2076{
2077 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
83a26013 2078 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2079}
2080
5c02c033 2081static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
65cef780 2082{
5c02c033 2083 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2084
2085 /* Drives position */
2086 drv0(fdctrl)->track = fdctrl->fifo[3];
2087 drv1(fdctrl)->track = fdctrl->fifo[4];
78ae820c
BS		 2088#if MAX_FD == 4
2089 drv2(fdctrl)->track = fdctrl->fifo[5];
2090 drv3(fdctrl)->track = fdctrl->fifo[6];
2091#endif
65cef780
BS		 2092 /* timers */
2093 fdctrl->timer0 = fdctrl->fifo[7];
2094 fdctrl->timer1 = fdctrl->fifo[8];
2095 cur_drv->last_sect = fdctrl->fifo[9];
2096 fdctrl->lock = fdctrl->fifo[10] >> 7;
2097 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
2098 fdctrl->config = fdctrl->fifo[11];
2099 fdctrl->precomp_trk = fdctrl->fifo[12];
2100 fdctrl->pwrd = fdctrl->fifo[13];
07e415f2 2101 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2102}
2103
5c02c033 2104static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
65cef780 2105{
5c02c033 2106 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2107
2108 fdctrl->fifo[0] = 0;
2109 fdctrl->fifo[1] = 0;
2110 /* Drives position */
2111 fdctrl->fifo[2] = drv0(fdctrl)->track;
2112 fdctrl->fifo[3] = drv1(fdctrl)->track;
78ae820c
BS		 2113#if MAX_FD == 4
2114 fdctrl->fifo[4] = drv2(fdctrl)->track;
2115 fdctrl->fifo[5] = drv3(fdctrl)->track;
2116#else
65cef780
BS		 2117 fdctrl->fifo[4] = 0;
2118 fdctrl->fifo[5] = 0;
78ae820c 2119#endif
65cef780
BS		 2120 /* timers */
2121 fdctrl->fifo[6] = fdctrl->timer0;
2122 fdctrl->fifo[7] = fdctrl->timer1;
2123 fdctrl->fifo[8] = cur_drv->last_sect;
2124 fdctrl->fifo[9] = (fdctrl->lock << 7) |
2125 (cur_drv->perpendicular << 2);
2126 fdctrl->fifo[10] = fdctrl->config;
2127 fdctrl->fifo[11] = fdctrl->precomp_trk;
2128 fdctrl->fifo[12] = fdctrl->pwrd;
2129 fdctrl->fifo[13] = 0;
2130 fdctrl->fifo[14] = 0;
83a26013 2131 fdctrl_to_result_phase(fdctrl, 15);
65cef780
BS		 2132}
2133
5c02c033 2134static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
65cef780 2135{
5c02c033 2136 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 2137
65cef780 2138 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
73bcb24d
RS		 2139 timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2140 (NANOSECONDS_PER_SECOND / 50));
65cef780
BS		 2141}
2142
5c02c033 2143static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
65cef780 2144{
5c02c033 2145 FDrive *cur_drv;
65cef780 2146
cefec4f5 2147 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 2148 cur_drv = get_cur_drv(fdctrl);
2149 fdctrl->data_state |= FD_STATE_FORMAT;
2150 if (fdctrl->fifo[0] & 0x80)
2151 fdctrl->data_state |= FD_STATE_MULTI;
2152 else
2153 fdctrl->data_state &= ~FD_STATE_MULTI;
65cef780
BS		 2154 cur_drv->bps =
2155 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
2156#if 0
2157 cur_drv->last_sect =
2158 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
2159 fdctrl->fifo[3] / 2;
2160#else
2161 cur_drv->last_sect = fdctrl->fifo[3];
2162#endif
2163 /* TODO: implement format using DMA expected by the Bochs BIOS
2164 * and Linux fdformat (read 3 bytes per sector via DMA and fill
2165 * the sector with the specified fill byte
2166 */
2167 fdctrl->data_state &= ~FD_STATE_FORMAT;
2168 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2169}
2170
5c02c033 2171static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
65cef780
BS		 2172{
2173 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
2174 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
368df94d
BS		 2175 if (fdctrl->fifo[2] & 1)
2176 fdctrl->dor &= ~FD_DOR_DMAEN;
2177 else
2178 fdctrl->dor |= FD_DOR_DMAEN;
65cef780 2179 /* No result back */
07e415f2 2180 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2181}
2182
5c02c033 2183static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
65cef780 2184{
5c02c033 2185 FDrive *cur_drv;
65cef780 2186
cefec4f5 2187 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 2188 cur_drv = get_cur_drv(fdctrl);
2189 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
2190 /* 1 Byte status back */
2191 fdctrl->fifo[0] = (cur_drv->ro << 6) |
2192 (cur_drv->track == 0 ? 0x10 : 0x00) |
2193 (cur_drv->head << 2) |
cefec4f5 2194 GET_CUR_DRV(fdctrl) |
65cef780 2195 0x28;
83a26013 2196 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2197}
2198
5c02c033 2199static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
65cef780 2200{
5c02c033 2201 FDrive *cur_drv;
65cef780 2202
cefec4f5 2203 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 2204 cur_drv = get_cur_drv(fdctrl);
2205 fd_recalibrate(cur_drv);
07e415f2 2206 fdctrl_to_command_phase(fdctrl);
65cef780 2207 /* Raise Interrupt */
d497d534
HP		 2208 fdctrl->status0 |= FD_SR0_SEEK;
2209 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2210}
2211
5c02c033 2212static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
65cef780 2213{
5c02c033 2214 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 2215
2fee0088 2216 if (fdctrl->reset_sensei > 0) {
f2d81b33
BS		 2217 fdctrl->fifo[0] =
2218 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
2219 fdctrl->reset_sensei--;
2fee0088
PH		 2220 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
2221 fdctrl->fifo[0] = FD_SR0_INVCMD;
83a26013 2222 fdctrl_to_result_phase(fdctrl, 1);
2fee0088 2223 return;
f2d81b33 2224 } else {
f2d81b33 2225 fdctrl->fifo[0] =
2fee0088
PH		 2226 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
2227 | GET_CUR_DRV(fdctrl);
f2d81b33
BS		 2228 }
2229
65cef780 2230 fdctrl->fifo[1] = cur_drv->track;
83a26013 2231 fdctrl_to_result_phase(fdctrl, 2);
65cef780 2232 fdctrl_reset_irq(fdctrl);
77370520 2233 fdctrl->status0 = FD_SR0_RDYCHG;
65cef780
BS		 2234}
2235
5c02c033 2236static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
65cef780 2237{
5c02c033 2238 FDrive *cur_drv;
65cef780 2239
cefec4f5 2240 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2241 cur_drv = get_cur_drv(fdctrl);
07e415f2 2242 fdctrl_to_command_phase(fdctrl);
b072a3c8
HP		 2243 /* The seek command just sends step pulses to the drive and doesn't care if
2244 * there is a medium inserted of if it's banging the head against the drive.
2245 */
6be01b1e 2246 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
b072a3c8 2247 /* Raise Interrupt */
d497d534
HP		 2248 fdctrl->status0 |= FD_SR0_SEEK;
2249 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2250}
2251
5c02c033 2252static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
65cef780 2253{
5c02c033 2254 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2255
2256 if (fdctrl->fifo[1] & 0x80)
2257 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
2258 /* No result back */
07e415f2 2259 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2260}
2261
5c02c033 2262static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
65cef780
BS		 2263{
2264 fdctrl->config = fdctrl->fifo[2];
2265 fdctrl->precomp_trk = fdctrl->fifo[3];
2266 /* No result back */
07e415f2 2267 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2268}
2269
5c02c033 2270static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
65cef780
BS		 2271{
2272 fdctrl->pwrd = fdctrl->fifo[1];
2273 fdctrl->fifo[0] = fdctrl->fifo[1];
83a26013 2274 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2275}
2276
5c02c033 2277static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
65cef780
BS		 2278{
2279 /* No result back */
07e415f2 2280 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2281}
2282
5c02c033 2283static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
65cef780 2284{
5c02c033 2285 FDrive *cur_drv = get_cur_drv(fdctrl);
e9077462 2286 uint32_t pos;
65cef780 2287
e9077462
PM		 2288 pos = fdctrl->data_pos - 1;
2289 pos %= FD_SECTOR_LEN;
2290 if (fdctrl->fifo[pos] & 0x80) {
65cef780 2291 /* Command parameters done */
e9077462 2292 if (fdctrl->fifo[pos] & 0x40) {
65cef780
BS		 2293 fdctrl->fifo[0] = fdctrl->fifo[1];
2294 fdctrl->fifo[2] = 0;
2295 fdctrl->fifo[3] = 0;
83a26013 2296 fdctrl_to_result_phase(fdctrl, 4);
65cef780 2297 } else {
07e415f2 2298 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2299 }
2300 } else if (fdctrl->data_len > 7) {
2301 /* ERROR */
2302 fdctrl->fifo[0] = 0x80 |
cefec4f5 2303 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
83a26013 2304 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2305 }
2306}
2307
6d013772 2308static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
65cef780 2309{
5c02c033 2310 FDrive *cur_drv;
65cef780 2311
cefec4f5 2312 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2313 cur_drv = get_cur_drv(fdctrl);
65cef780 2314 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
6be01b1e
PH		 2315 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
2316 cur_drv->sect, 1);
65cef780 2317 } else {
6d013772
PH		 2318 fd_seek(cur_drv, cur_drv->head,
2319 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
65cef780 2320 }
07e415f2 2321 fdctrl_to_command_phase(fdctrl);
77370520 2322 /* Raise Interrupt */
d497d534
HP		 2323 fdctrl->status0 |= FD_SR0_SEEK;
2324 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2325}
2326
6d013772 2327static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
65cef780 2328{
5c02c033 2329 FDrive *cur_drv;
65cef780 2330
cefec4f5 2331 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2332 cur_drv = get_cur_drv(fdctrl);
65cef780 2333 if (fdctrl->fifo[2] > cur_drv->track) {
6be01b1e 2334 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
65cef780 2335 } else {
6d013772
PH		 2336 fd_seek(cur_drv, cur_drv->head,
2337 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
65cef780 2338 }
07e415f2 2339 fdctrl_to_command_phase(fdctrl);
65cef780 2340 /* Raise Interrupt */
d497d534
HP		 2341 fdctrl->status0 |= FD_SR0_SEEK;
2342 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2343}
2344
85d291a0
KW		 2345/*
2346 * Handlers for the execution phase of each command
2347 */
d275b33d 2348typedef struct FDCtrlCommand {
678803ab
BS		 2349 uint8_t value;
2350 uint8_t mask;
2351 const char* name;
2352 int parameters;
5c02c033 2353 void (*handler)(FDCtrl *fdctrl, int direction);
678803ab 2354 int direction;
d275b33d
KW		 2355} FDCtrlCommand;
2356
2357static const FDCtrlCommand handlers[] = {
678803ab
BS		 2358 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
2359 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
2360 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
2361 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
2362 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
2363 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
2364 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
2365 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
2366 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
2367 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
2368 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
7ea004ed 2369 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
678803ab
BS		 2370 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
2371 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
2372 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
2373 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
2374 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
2375 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
2376 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
2377 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
2378 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
2379 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
2380 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
2381 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
2382 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
2383 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
2384 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
2385 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
2386 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
2387 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
2388 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
2389 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
2390};
2391/* Associate command to an index in the 'handlers' array */
2392static uint8_t command_to_handler[256];
2393
d275b33d
KW		 2394static const FDCtrlCommand *get_command(uint8_t cmd)
2395{
2396 int idx;
2397
2398 idx = command_to_handler[cmd];
2399 FLOPPY_DPRINTF("%s command\n", handlers[idx].name);
2400 return &handlers[idx];
2401}
2402
5c02c033 2403static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
baca51fa 2404{
5c02c033 2405 FDrive *cur_drv;
d275b33d 2406 const FDCtrlCommand *cmd;
e9077462 2407 uint32_t pos;
baca51fa 2408
8977f3c1 2409 /* Reset mode */
1c346df2 2410 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 2411 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB		 2412 return;
2413 }
b9b3d225 2414 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
cced7a13 2415 FLOPPY_DPRINTF("error: controller not ready for writing\n");
8977f3c1
FB		 2416 return;
2417 }
b9b3d225 2418 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
5b0a25e8 2419
d275b33d
KW		 2420 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2421
2422 /* If data_len spans multiple sectors, the current position in the FIFO
2423 * wraps around while fdctrl->data_pos is the real position in the whole
2424 * request. */
2425 pos = fdctrl->data_pos++;
2426 pos %= FD_SECTOR_LEN;
2427 fdctrl->fifo[pos] = value;
2428
6cc8a11c
KW		 2429 if (fdctrl->data_pos == fdctrl->data_len) {
2430 fdctrl->msr &= ~FD_MSR_RQM;
2431 }
2432
5b0a25e8
KW		 2433 switch (fdctrl->phase) {
2434 case FD_PHASE_EXECUTION:
2435 /* For DMA requests, RQM should be cleared during execution phase, so
2436 * we would have errored out above. */
2437 assert(fdctrl->msr & FD_MSR_NONDMA);
d275b33d 2438
8977f3c1 2439 /* FIFO data write */
b3bc1540 2440 if (pos == FD_SECTOR_LEN - 1 ||
baca51fa 2441 fdctrl->data_pos == fdctrl->data_len) {
77370520 2442 cur_drv = get_cur_drv(fdctrl);
a7a5b7c0
EB		 2443 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
2444 BDRV_SECTOR_SIZE, 0) < 0) {
cced7a13
BS		 2445 FLOPPY_DPRINTF("error writing sector %d\n",
2446 fd_sector(cur_drv));
5b0a25e8 2447 break;
77370520 2448 }
746d6de7
BS		 2449 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2450 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2451 fd_sector(cur_drv));
5b0a25e8 2452 break;
746d6de7 2453 }
8977f3c1 2454 }
d275b33d
KW		 2455
2456 /* Switch to result phase when done with the transfer */
2457 if (fdctrl->data_pos == fdctrl->data_len) {
c5139bd9 2458 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
d275b33d 2459 }
5b0a25e8 2460 break;
678803ab 2461
5b0a25e8
KW		 2462 case FD_PHASE_COMMAND:
2463 assert(!(fdctrl->msr & FD_MSR_NONDMA));
d275b33d 2464 assert(fdctrl->data_pos < FD_SECTOR_LEN);
5b0a25e8 2465
d275b33d
KW		 2466 if (pos == 0) {
2467 /* The first byte specifies the command. Now we start reading
2468 * as many parameters as this command requires. */
2469 cmd = get_command(value);
2470 fdctrl->data_len = cmd->parameters + 1;
6cc8a11c
KW		 2471 if (cmd->parameters) {
2472 fdctrl->msr |= FD_MSR_RQM;
2473 }
5b0a25e8 2474 fdctrl->msr |= FD_MSR_CMDBUSY;
8977f3c1 2475 }
65cef780 2476
5b0a25e8 2477 if (fdctrl->data_pos == fdctrl->data_len) {
d275b33d 2478 /* We have all parameters now, execute the command */
5b0a25e8 2479 fdctrl->phase = FD_PHASE_EXECUTION;
d275b33d 2480
5b0a25e8
KW		 2481 if (fdctrl->data_state & FD_STATE_FORMAT) {
2482 fdctrl_format_sector(fdctrl);
2483 break;
2484 }
2485
d275b33d
KW		 2486 cmd = get_command(fdctrl->fifo[0]);
2487 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name);
2488 cmd->handler(fdctrl, cmd->direction);
5b0a25e8
KW		 2489 }
2490 break;
2491
2492 case FD_PHASE_RESULT:
2493 default:
2494 abort();
8977f3c1
FB		 2495 }
2496}
ed5fd2cc
FB		 2497
2498static void fdctrl_result_timer(void *opaque)
2499{
5c02c033
BS		 2500 FDCtrl *fdctrl = opaque;
2501 FDrive *cur_drv = get_cur_drv(fdctrl);
4f431960 2502
b7ffa3b1
TS		 2503 /* Pretend we are spinning.
2504 * This is needed for Coherent, which uses READ ID to check for
2505 * sector interleaving.
2506 */
2507 if (cur_drv->last_sect != 0) {
2508 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2509 }
844f65d6
HP		 2510 /* READ_ID can't automatically succeed! */
2511 if (fdctrl->check_media_rate &&
2512 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2513 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2514 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2515 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2516 } else {
2517 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2518 }
ed5fd2cc 2519}
678803ab
BS		 2520
2521/* Init functions */
c0ca74f6
FZ		 2522static void fdctrl_connect_drives(FDCtrl *fdctrl, DeviceState *fdc_dev,
2523 Error **errp)
678803ab 2524{
12a71a02 2525 unsigned int i;
7d0d6950 2526 FDrive *drive;
394ea2ca 2527 DeviceState *dev;
a92bd191 2528 BlockBackend *blk;
394ea2ca 2529 Error *local_err = NULL;
678803ab 2530
678803ab 2531 for (i = 0; i < MAX_FD; i++) {
7d0d6950 2532 drive = &fdctrl->drives[i];
844f65d6 2533 drive->fdctrl = fdctrl;
7d0d6950 2534
394ea2ca
KW		 2535 /* If the drive is not present, we skip creating the qdev device, but
2536 * still have to initialise the controller. */
a92bd191
KW		 2537 blk = fdctrl->qdev_for_drives[i].blk;
2538 if (!blk) {
394ea2ca
KW		 2539 fd_init(drive);
2540 fd_revalidate(drive);
2541 continue;
b47b3525
MA		 2542 }
2543
394ea2ca
KW		 2544 dev = qdev_create(&fdctrl->bus.bus, "floppy");
2545 qdev_prop_set_uint32(dev, "unit", i);
a92bd191
KW		 2546 qdev_prop_set_enum(dev, "drive-type", fdctrl->qdev_for_drives[i].type);
2547
2548 blk_ref(blk);
2549 blk_detach_dev(blk, fdc_dev);
2550 fdctrl->qdev_for_drives[i].blk = NULL;
2551 qdev_prop_set_drive(dev, "drive", blk, &local_err);
2552 blk_unref(blk);
2553
2554 if (local_err) {
2555 error_propagate(errp, local_err);
2556 return;
2557 }
2558
394ea2ca
KW		 2559 object_property_set_bool(OBJECT(dev), true, "realized", &local_err);
2560 if (local_err) {
2561 error_propagate(errp, local_err);
2562 return;
7d0d6950 2563 }
678803ab 2564 }
678803ab
BS		 2565}
2566
dfc65f1f
MA		 2567ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2568{
4a17cc4f
AF		 2569 DeviceState *dev;
2570 ISADevice *isadev;
dfc65f1f 2571
4a17cc4f
AF		 2572 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2573 if (!isadev) {
dfc65f1f
MA		 2574 return NULL;
2575 }
4a17cc4f 2576 dev = DEVICE(isadev);
dfc65f1f
MA		 2577
2578 if (fds[0]) {
6231a6da
MA		 2579 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2580 &error_fatal);
dfc65f1f
MA		 2581 }
2582 if (fds[1]) {
6231a6da
MA		 2583 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2584 &error_fatal);
dfc65f1f 2585 }
4a17cc4f 2586 qdev_init_nofail(dev);
dfc65f1f 2587
4a17cc4f 2588 return isadev;
dfc65f1f
MA		 2589}
2590
63ffb564 2591void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
a8170e5e 2592 hwaddr mmio_base, DriveInfo **fds)
2091ba23 2593{
5c02c033 2594 FDCtrl *fdctrl;
2091ba23 2595 DeviceState *dev;
dd3be742 2596 SysBusDevice *sbd;
5c02c033 2597 FDCtrlSysBus *sys;
2091ba23 2598
19d46d71 2599 dev = qdev_create(NULL, "sysbus-fdc");
dd3be742 2600 sys = SYSBUS_FDC(dev);
99244fa1
GH		 2601 fdctrl = &sys->state;
2602 fdctrl->dma_chann = dma_chann; /* FIXME */
995bf0ca 2603 if (fds[0]) {
6231a6da
MA		 2604 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2605 &error_fatal);
995bf0ca
GH		 2606 }
2607 if (fds[1]) {
6231a6da
MA		 2608 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2609 &error_fatal);
995bf0ca 2610 }
e23a1b33 2611 qdev_init_nofail(dev);
dd3be742
HT		 2612 sbd = SYS_BUS_DEVICE(dev);
2613 sysbus_connect_irq(sbd, 0, irq);
2614 sysbus_mmio_map(sbd, 0, mmio_base);
678803ab
BS		 2615}
2616
a8170e5e 2617void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
63ffb564 2618 DriveInfo **fds, qemu_irq *fdc_tc)
678803ab 2619{
f64ab228 2620 DeviceState *dev;
5c02c033 2621 FDCtrlSysBus *sys;
678803ab 2622
12a71a02 2623 dev = qdev_create(NULL, "SUNW,fdtwo");
995bf0ca 2624 if (fds[0]) {
6231a6da
MA		 2625 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]),
2626 &error_fatal);
995bf0ca 2627 }
e23a1b33 2628 qdev_init_nofail(dev);
dd3be742
HT		 2629 sys = SYSBUS_FDC(dev);
2630 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2631 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
f64ab228 2632 *fdc_tc = qdev_get_gpio_in(dev, 0);
678803ab 2633}
f64ab228 2634
51e6e90e
KW		 2635static void fdctrl_realize_common(DeviceState *dev, FDCtrl *fdctrl,
2636 Error **errp)
f64ab228 2637{
12a71a02
BS		 2638 int i, j;
2639 static int command_tables_inited = 0;
f64ab228 2640
a73275dd
JS		 2641 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) {
2642 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'");
2643 }
2644
12a71a02
BS		 2645 /* Fill 'command_to_handler' lookup table */
2646 if (!command_tables_inited) {
2647 command_tables_inited = 1;
2648 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2649 for (j = 0; j < sizeof(command_to_handler); j++) {
2650 if ((j & handlers[i].mask) == handlers[i].value) {
2651 command_to_handler[j] = i;
2652 }
2653 }
2654 }
2655 }
2656
2657 FLOPPY_DPRINTF("init controller\n");
2658 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
6653d131 2659 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
d7a6c270 2660 fdctrl->fifo_size = 512;
bc72ad67 2661 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
a3ef7a61 2662 fdctrl_result_timer, fdctrl);
12a71a02
BS		 2663
2664 fdctrl->version = 0x90; /* Intel 82078 controller */
2665 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
d7a6c270 2666 fdctrl->num_floppies = MAX_FD;
12a71a02 2667
a3ef7a61 2668 if (fdctrl->dma_chann != -1) {
c8a35f1c
HP		 2669 IsaDmaClass *k;
2670 assert(fdctrl->dma);
2671 k = ISADMA_GET_CLASS(fdctrl->dma);
2672 k->register_channel(fdctrl->dma, fdctrl->dma_chann,
2673 &fdctrl_transfer_handler, fdctrl);
a3ef7a61 2674 }
51e6e90e
KW		 2675
2676 floppy_bus_create(fdctrl, &fdctrl->bus, dev);
c0ca74f6 2677 fdctrl_connect_drives(fdctrl, dev, errp);
f64ab228
BS		 2678}
2679
212ec7ba 2680static const MemoryRegionPortio fdc_portio_list[] = {
2f290a8c 2681 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
212ec7ba
RH		 2682 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2683 PORTIO_END_OF_LIST(),
2f290a8c
RH		 2684};
2685
db895a1e 2686static void isabus_fdc_realize(DeviceState *dev, Error **errp)
8baf73ad 2687{
db895a1e 2688 ISADevice *isadev = ISA_DEVICE(dev);
020c8e76 2689 FDCtrlISABus *isa = ISA_FDC(dev);
5c02c033 2690 FDCtrl *fdctrl = &isa->state;
a3ef7a61 2691 Error *err = NULL;
8baf73ad 2692
e305a165
MAL		 2693 isa_register_portio_list(isadev, &fdctrl->portio_list,
2694 isa->iobase, fdc_portio_list, fdctrl,
db895a1e 2695 "fdc");
dee41d58 2696
db895a1e 2697 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
c9ae703d 2698 fdctrl->dma_chann = isa->dma;
c8a35f1c
HP		 2699 if (fdctrl->dma_chann != -1) {
2700 fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma);
b3da5513
AK		 2701 if (!fdctrl->dma) {
2702 error_setg(errp, "ISA controller does not support DMA");
2703 return;
2704 }
c8a35f1c 2705 }
8baf73ad 2706
db895a1e 2707 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
51e6e90e 2708 fdctrl_realize_common(dev, fdctrl, &err);
a3ef7a61
AF		 2709 if (err != NULL) {
2710 error_propagate(errp, err);
db895a1e
AF		 2711 return;
2712 }
8baf73ad
GH		 2713}
2714
940194c2 2715static void sysbus_fdc_initfn(Object *obj)
12a71a02 2716{
19d46d71 2717 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
940194c2 2718 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
5c02c033 2719 FDCtrl *fdctrl = &sys->state;
12a71a02 2720
19d46d71
AF		 2721 fdctrl->dma_chann = -1;
2722
940194c2 2723 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2d256e6f 2724 "fdc", 0x08);
19d46d71 2725 sysbus_init_mmio(sbd, &fdctrl->iomem);
940194c2
HT		 2726}
2727
19d46d71 2728static void sun4m_fdc_initfn(Object *obj)
940194c2 2729{
19d46d71
AF		 2730 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2731 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
940194c2 2732 FDCtrl *fdctrl = &sys->state;
940194c2 2733
dd446051
HP		 2734 fdctrl->dma_chann = -1;
2735
19d46d71
AF		 2736 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2737 fdctrl, "fdctrl", 0x08);
2738 sysbus_init_mmio(sbd, &fdctrl->iomem);
940194c2 2739}
2be37833 2740
19d46d71 2741static void sysbus_fdc_common_initfn(Object *obj)
940194c2 2742{
19d46d71
AF		 2743 DeviceState *dev = DEVICE(obj);
2744 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
940194c2
HT		 2745 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2746 FDCtrl *fdctrl = &sys->state;
2747
19d46d71
AF		 2748 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2749
2750 sysbus_init_irq(sbd, &fdctrl->irq);
2751 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
12a71a02
BS		 2752}
2753
19d46d71 2754static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
12a71a02 2755{
dd3be742
HT		 2756 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2757 FDCtrl *fdctrl = &sys->state;
12a71a02 2758
51e6e90e 2759 fdctrl_realize_common(dev, fdctrl, errp);
12a71a02 2760}
f64ab228 2761
2da44dd0 2762FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
34d4260e 2763{
020c8e76 2764 FDCtrlISABus *isa = ISA_FDC(fdc);
34d4260e 2765
61a8d649 2766 return isa->state.drives[i].drive;
34d4260e
KW		 2767}
2768
e08fde0c
RK		 2769void isa_fdc_get_drive_max_chs(FloppyDriveType type,
2770 uint8_t *maxc, uint8_t *maxh, uint8_t *maxs)
2771{
2772 const FDFormat *fdf;
2773
2774 *maxc = *maxh = *maxs = 0;
2775 for (fdf = fd_formats; fdf->drive != FLOPPY_DRIVE_TYPE_NONE; fdf++) {
2776 if (fdf->drive != type) {
2777 continue;
2778 }
2779 if (*maxc < fdf->max_track) {
2780 *maxc = fdf->max_track;
2781 }
2782 if (*maxh < fdf->max_head) {
2783 *maxh = fdf->max_head;
2784 }
2785 if (*maxs < fdf->last_sect) {
2786 *maxs = fdf->last_sect;
2787 }
2788 }
2789 (*maxc)--;
2790}
2791
a64405d1
JK		 2792static const VMStateDescription vmstate_isa_fdc ={
2793 .name = "fdc",
2794 .version_id = 2,
2795 .minimum_version_id = 2,
d49805ae 2796 .fields = (VMStateField[]) {
a64405d1
JK		 2797 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2798 VMSTATE_END_OF_LIST()
2799 }
2800};
2801
39bffca2 2802static Property isa_fdc_properties[] = {
c7bcc85d 2803 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
c9ae703d
HP		 2804 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2805 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
a92bd191
KW		 2806 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.qdev_for_drives[0].blk),
2807 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.qdev_for_drives[1].blk),
09c6d585
HP		 2808 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2809 0, true),
85bbd1e7 2810 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlISABus, state.qdev_for_drives[0].type,
fff4687b
JS		 2811 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2812 FloppyDriveType),
85bbd1e7 2813 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlISABus, state.qdev_for_drives[1].type,
fff4687b
JS		 2814 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2815 FloppyDriveType),
85bbd1e7 2816 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
4812fa27 2817 FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type,
a73275dd 2818 FloppyDriveType),
39bffca2
AL		 2819 DEFINE_PROP_END_OF_LIST(),
2820};
2821
020c8e76 2822static void isabus_fdc_class_init(ObjectClass *klass, void *data)
8f04ee08 2823{
39bffca2 2824 DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e
AF		 2825
2826 dc->realize = isabus_fdc_realize;
39bffca2 2827 dc->fw_name = "fdc";
39bffca2
AL		 2828 dc->reset = fdctrl_external_reset_isa;
2829 dc->vmsd = &vmstate_isa_fdc;
2830 dc->props = isa_fdc_properties;
125ee0ed 2831 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
39bffca2
AL		 2832}
2833
81782b6a
GA		 2834static void isabus_fdc_instance_init(Object *obj)
2835{
2836 FDCtrlISABus *isa = ISA_FDC(obj);
2837
2838 device_add_bootindex_property(obj, &isa->bootindexA,
2839 "bootindexA", "/floppy@0",
2840 DEVICE(obj), NULL);
2841 device_add_bootindex_property(obj, &isa->bootindexB,
2842 "bootindexB", "/floppy@1",
2843 DEVICE(obj), NULL);
2844}
2845
8c43a6f0 2846static const TypeInfo isa_fdc_info = {
020c8e76 2847 .name = TYPE_ISA_FDC,
39bffca2
AL		 2848 .parent = TYPE_ISA_DEVICE,
2849 .instance_size = sizeof(FDCtrlISABus),
020c8e76 2850 .class_init = isabus_fdc_class_init,
81782b6a 2851 .instance_init = isabus_fdc_instance_init,
8baf73ad
GH		 2852};
2853
a64405d1
JK		 2854static const VMStateDescription vmstate_sysbus_fdc ={
2855 .name = "fdc",
2856 .version_id = 2,
2857 .minimum_version_id = 2,
d49805ae 2858 .fields = (VMStateField[]) {
a64405d1
JK		 2859 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2860 VMSTATE_END_OF_LIST()
2861 }
2862};
2863
999e12bb 2864static Property sysbus_fdc_properties[] = {
a92bd191
KW		 2865 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.qdev_for_drives[0].blk),
2866 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.qdev_for_drives[1].blk),
85bbd1e7 2867 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlSysBus, state.qdev_for_drives[0].type,
fff4687b
JS		 2868 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2869 FloppyDriveType),
85bbd1e7 2870 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlSysBus, state.qdev_for_drives[1].type,
fff4687b
JS		 2871 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2872 FloppyDriveType),
85bbd1e7 2873 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
a73275dd
JS		 2874 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2875 FloppyDriveType),
999e12bb 2876 DEFINE_PROP_END_OF_LIST(),
12a71a02
BS		 2877};
2878
999e12bb
AL		 2879static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2880{
39bffca2 2881 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 2882
39bffca2 2883 dc->props = sysbus_fdc_properties;
125ee0ed 2884 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
999e12bb
AL		 2885}
2886
8c43a6f0 2887static const TypeInfo sysbus_fdc_info = {
19d46d71
AF		 2888 .name = "sysbus-fdc",
2889 .parent = TYPE_SYSBUS_FDC,
940194c2 2890 .instance_init = sysbus_fdc_initfn,
39bffca2 2891 .class_init = sysbus_fdc_class_init,
999e12bb
AL		 2892};
2893
2894static Property sun4m_fdc_properties[] = {
a92bd191 2895 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.qdev_for_drives[0].blk),
85bbd1e7 2896 DEFINE_PROP_SIGNED("fdtype", FDCtrlSysBus, state.qdev_for_drives[0].type,
fff4687b
JS		 2897 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2898 FloppyDriveType),
85bbd1e7 2899 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
a73275dd
JS		 2900 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2901 FloppyDriveType),
999e12bb
AL		 2902 DEFINE_PROP_END_OF_LIST(),
2903};
2904
2905static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2906{
39bffca2 2907 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 2908
39bffca2 2909 dc->props = sun4m_fdc_properties;
125ee0ed 2910 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
999e12bb
AL		 2911}
2912
8c43a6f0 2913static const TypeInfo sun4m_fdc_info = {
39bffca2 2914 .name = "SUNW,fdtwo",
19d46d71 2915 .parent = TYPE_SYSBUS_FDC,
940194c2 2916 .instance_init = sun4m_fdc_initfn,
39bffca2 2917 .class_init = sun4m_fdc_class_init,
f64ab228
BS		 2918};
2919
19d46d71
AF		 2920static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
2921{
2922 DeviceClass *dc = DEVICE_CLASS(klass);
2923
2924 dc->realize = sysbus_fdc_common_realize;
2925 dc->reset = fdctrl_external_reset_sysbus;
2926 dc->vmsd = &vmstate_sysbus_fdc;
2927}
2928
2929static const TypeInfo sysbus_fdc_type_info = {
2930 .name = TYPE_SYSBUS_FDC,
2931 .parent = TYPE_SYS_BUS_DEVICE,
2932 .instance_size = sizeof(FDCtrlSysBus),
2933 .instance_init = sysbus_fdc_common_initfn,
2934 .abstract = true,
2935 .class_init = sysbus_fdc_common_class_init,
2936};
2937
83f7d43a 2938static void fdc_register_types(void)
f64ab228 2939{
39bffca2 2940 type_register_static(&isa_fdc_info);
19d46d71 2941 type_register_static(&sysbus_fdc_type_info);
39bffca2
AL		 2942 type_register_static(&sysbus_fdc_info);
2943 type_register_static(&sun4m_fdc_info);
51e6e90e 2944 type_register_static(&floppy_bus_info);
394ea2ca 2945 type_register_static(&floppy_drive_info);
f64ab228
BS		 2946}
2947
83f7d43a 2948type_init(fdc_register_types)
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