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nvme: fix oob access issue(CVE-2018-16847)
[qemu.git] / hw / block / fdc.c
CommitLineData
8977f3c1 1/*
890fa6be 2 * QEMU Floppy disk emulator (Intel 82078)
5fafdf24 3 *
3ccacc4a 4 * Copyright (c) 2003, 2007 Jocelyn Mayer
bcc4e41f 5 * Copyright (c) 2008 Hervé Poussineau
5fafdf24 6 *
8977f3c1
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
e80cfcfc
FB		 25/*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
f64ab228 29
80c71a24 30#include "qemu/osdep.h"
83c9f4ca 31#include "hw/hw.h"
0d09e41a 32#include "hw/block/fdc.h"
da34e65c 33#include "qapi/error.h"
1de7afc9
PB		 34#include "qemu/error-report.h"
35#include "qemu/timer.h"
0d09e41a 36#include "hw/isa/isa.h"
83c9f4ca 37#include "hw/sysbus.h"
a92bd191 38#include "hw/block/block.h"
fa1d36df 39#include "sysemu/block-backend.h"
9c17d615
PB		 40#include "sysemu/blockdev.h"
41#include "sysemu/sysemu.h"
1de7afc9 42#include "qemu/log.h"
1a5396d9 43#include "trace.h"
8977f3c1
FB		 44
45/********************************************************/
46/* debug Floppy devices */
8977f3c1 47
c691320f
JS		 48#define DEBUG_FLOPPY 0
49
001faf32 50#define FLOPPY_DPRINTF(fmt, ...) \
c691320f
JS		 51 do { \
52 if (DEBUG_FLOPPY) { \
53 fprintf(stderr, "FLOPPY: " fmt , ## __VA_ARGS__); \
54 } \
55 } while (0)
8977f3c1 56
51e6e90e
KW		 57
58/********************************************************/
59/* qdev floppy bus */
60
61#define TYPE_FLOPPY_BUS "floppy-bus"
62#define FLOPPY_BUS(obj) OBJECT_CHECK(FloppyBus, (obj), TYPE_FLOPPY_BUS)
63
64typedef struct FDCtrl FDCtrl;
394ea2ca
KW		 65typedef struct FDrive FDrive;
66static FDrive *get_drv(FDCtrl *fdctrl, int unit);
51e6e90e
KW		 67
68typedef struct FloppyBus {
69 BusState bus;
70 FDCtrl *fdc;
71} FloppyBus;
72
73static const TypeInfo floppy_bus_info = {
74 .name = TYPE_FLOPPY_BUS,
75 .parent = TYPE_BUS,
76 .instance_size = sizeof(FloppyBus),
77};
78
79static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev)
80{
81 qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
82 bus->fdc = fdc;
83}
84
85
8977f3c1
FB		 86/********************************************************/
87/* Floppy drive emulation */
88
61a8d649
MA		 89typedef enum FDriveRate {
90 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
91 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
92 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
93 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
94} FDriveRate;
95
109c17bc
JS		 96typedef enum FDriveSize {
97 FDRIVE_SIZE_UNKNOWN,
98 FDRIVE_SIZE_350,
99 FDRIVE_SIZE_525,
100} FDriveSize;
101
61a8d649 102typedef struct FDFormat {
2da44dd0 103 FloppyDriveType drive;
61a8d649
MA		 104 uint8_t last_sect;
105 uint8_t max_track;
106 uint8_t max_head;
107 FDriveRate rate;
108} FDFormat;
109
109c17bc
JS		 110/* In many cases, the total sector size of a format is enough to uniquely
111 * identify it. However, there are some total sector collisions between
112 * formats of different physical size, and these are noted below by
113 * highlighting the total sector size for entries with collisions. */
61a8d649
MA		 114static const FDFormat fd_formats[] = {
115 /* First entry is default format */
116 /* 1.44 MB 3"1/2 floppy disks */
109c17bc
JS		 117 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */
118 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */
2da44dd0
JS		 119 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, },
120 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, },
121 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, },
122 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, },
123 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, },
124 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, },
61a8d649 125 /* 2.88 MB 3"1/2 floppy disks */
2da44dd0
JS		 126 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, },
127 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, },
128 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, },
129 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, },
130 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, },
61a8d649 131 /* 720 kB 3"1/2 floppy disks */
109c17bc 132 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */
2da44dd0
JS		 133 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, },
134 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, },
135 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, },
136 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, },
137 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, },
61a8d649 138 /* 1.2 MB 5"1/4 floppy disks */
2da44dd0 139 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, },
109c17bc 140 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */
2da44dd0
JS		 141 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, },
142 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, },
109c17bc 143 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */
61a8d649 144 /* 720 kB 5"1/4 floppy disks */
109c17bc 145 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */
2da44dd0 146 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, },
61a8d649 147 /* 360 kB 5"1/4 floppy disks */
109c17bc 148 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */
2da44dd0
JS		 149 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, },
150 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, },
151 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, },
61a8d649 152 /* 320 kB 5"1/4 floppy disks */
2da44dd0
JS		 153 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, },
154 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, },
61a8d649 155 /* 360 kB must match 5"1/4 better than 3"1/2... */
109c17bc 156 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */
61a8d649 157 /* end */
2da44dd0 158 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, },
61a8d649
MA		 159};
160
109c17bc
JS		 161static FDriveSize drive_size(FloppyDriveType drive)
162{
163 switch (drive) {
164 case FLOPPY_DRIVE_TYPE_120:
165 return FDRIVE_SIZE_525;
166 case FLOPPY_DRIVE_TYPE_144:
167 case FLOPPY_DRIVE_TYPE_288:
168 return FDRIVE_SIZE_350;
169 default:
170 return FDRIVE_SIZE_UNKNOWN;
171 }
172}
173
cefec4f5
BS		 174#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
175#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
176
8977f3c1 177/* Will always be a fixed parameter for us */
f2d81b33
BS		 178#define FD_SECTOR_LEN 512
179#define FD_SECTOR_SC 2 /* Sector size code */
180#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
8977f3c1
FB		 181
182/* Floppy disk drive emulation */
5c02c033 183typedef enum FDiskFlags {
baca51fa 184 FDISK_DBL_SIDES = 0x01,
5c02c033 185} FDiskFlags;
baca51fa 186
394ea2ca 187struct FDrive {
844f65d6 188 FDCtrl *fdctrl;
4be74634 189 BlockBackend *blk;
a17c17a2 190 BlockConf *conf;
8977f3c1 191 /* Drive status */
2da44dd0 192 FloppyDriveType drive; /* CMOS drive type */
8977f3c1 193 uint8_t perpendicular; /* 2.88 MB access mode */
8977f3c1
FB		 194 /* Position */
195 uint8_t head;
196 uint8_t track;
197 uint8_t sect;
8977f3c1 198 /* Media */
16c1e3ec 199 FloppyDriveType disk; /* Current disk type */
5c02c033 200 FDiskFlags flags;
8977f3c1
FB		 201 uint8_t last_sect; /* Nb sector per track */
202 uint8_t max_track; /* Nb of tracks */
baca51fa 203 uint16_t bps; /* Bytes per sector */
8977f3c1 204 uint8_t ro; /* Is read-only */
7d905f71 205 uint8_t media_changed; /* Is media changed */
844f65d6 206 uint8_t media_rate; /* Data rate of medium */
2e1280e8 207
d5d47efc 208 bool media_validated; /* Have we validated the media? */
394ea2ca 209};
8977f3c1 210
a73275dd
JS		 211
212static FloppyDriveType get_fallback_drive_type(FDrive *drv);
213
fd9bdbd3
JS		 214/* Hack: FD_SEEK is expected to work on empty drives. However, QEMU
215 * currently goes through some pains to keep seeks within the bounds
216 * established by last_sect and max_track. Correcting this is difficult,
217 * as refactoring FDC code tends to expose nasty bugs in the Linux kernel.
218 *
219 * For now: allow empty drives to have large bounds so we can seek around,
220 * with the understanding that when a diskette is inserted, the bounds will
221 * properly tighten to match the geometry of that inserted medium.
222 */
223static void fd_empty_seek_hack(FDrive *drv)
224{
225 drv->last_sect = 0xFF;
226 drv->max_track = 0xFF;
227}
228
5c02c033 229static void fd_init(FDrive *drv)
8977f3c1
FB		 230{
231 /* Drive */
8977f3c1 232 drv->perpendicular = 0;
8977f3c1 233 /* Disk */
16c1e3ec 234 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
baca51fa 235 drv->last_sect = 0;
8977f3c1 236 drv->max_track = 0;
d5d47efc
JS		 237 drv->ro = true;
238 drv->media_changed = 1;
8977f3c1
FB		 239}
240
08388273
HP		 241#define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
242
7859cb98 243static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
08388273 244 uint8_t last_sect, uint8_t num_sides)
8977f3c1 245{
08388273 246 return (((track * num_sides) + head) * last_sect) + sect - 1;
8977f3c1
FB		 247}
248
249/* Returns current position, in sectors, for given drive */
5c02c033 250static int fd_sector(FDrive *drv)
8977f3c1 251{
08388273
HP		 252 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
253 NUM_SIDES(drv));
8977f3c1
FB		 254}
255
a7a5b7c0
EB		 256/* Returns current position, in bytes, for given drive */
257static int fd_offset(FDrive *drv)
258{
259 g_assert(fd_sector(drv) < INT_MAX >> BDRV_SECTOR_BITS);
260 return fd_sector(drv) << BDRV_SECTOR_BITS;
261}
262
77370520
BS		 263/* Seek to a new position:
264 * returns 0 if already on right track
265 * returns 1 if track changed
266 * returns 2 if track is invalid
267 * returns 3 if sector is invalid
268 * returns 4 if seek is disabled
269 */
5c02c033
BS		 270static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
271 int enable_seek)
8977f3c1
FB		 272{
273 uint32_t sector;
baca51fa
FB		 274 int ret;
275
276 if (track > drv->max_track ||
4f431960 277 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
ed5fd2cc
FB		 278 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
279 head, track, sect, 1,
280 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
281 drv->max_track, drv->last_sect);
8977f3c1
FB		 282 return 2;
283 }
284 if (sect > drv->last_sect) {
ed5fd2cc
FB		 285 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
286 head, track, sect, 1,
287 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
288 drv->max_track, drv->last_sect);
8977f3c1
FB		 289 return 3;
290 }
08388273 291 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
baca51fa 292 ret = 0;
8977f3c1
FB		 293 if (sector != fd_sector(drv)) {
294#if 0
295 if (!enable_seek) {
cced7a13
BS		 296 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
297 " (max=%d %02x %02x)\n",
298 head, track, sect, 1, drv->max_track,
299 drv->last_sect);
8977f3c1
FB		 300 return 4;
301 }
302#endif
303 drv->head = head;
6be01b1e 304 if (drv->track != track) {
abb3e55b 305 if (drv->blk != NULL && blk_is_inserted(drv->blk)) {
6be01b1e
PH		 306 drv->media_changed = 0;
307 }
4f431960 308 ret = 1;
6be01b1e 309 }
8977f3c1
FB		 310 drv->track = track;
311 drv->sect = sect;
8977f3c1
FB		 312 }
313
abb3e55b 314 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) {
c52acf60
PH		 315 ret = 2;
316 }
317
baca51fa 318 return ret;
8977f3c1
FB		 319}
320
321/* Set drive back to track 0 */
5c02c033 322static void fd_recalibrate(FDrive *drv)
8977f3c1
FB		 323{
324 FLOPPY_DPRINTF("recalibrate\n");
6be01b1e 325 fd_seek(drv, 0, 0, 1, 1);
8977f3c1
FB		 326}
327
d5d47efc
JS		 328/**
329 * Determine geometry based on inserted diskette.
330 * Will not operate on an empty drive.
331 *
332 * @return: 0 on success, -1 if the drive is empty.
333 */
334static int pick_geometry(FDrive *drv)
9a972233 335{
21862658 336 BlockBackend *blk = drv->blk;
9a972233
JS		 337 const FDFormat *parse;
338 uint64_t nb_sectors, size;
f31937aa
JS		 339 int i;
340 int match, size_match, type_match;
341 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO;
9a972233 342
d5d47efc 343 /* We can only pick a geometry if we have a diskette. */
abb3e55b
HR		 344 if (!drv->blk || !blk_is_inserted(drv->blk) ||
345 drv->drive == FLOPPY_DRIVE_TYPE_NONE)
346 {
d5d47efc
JS		 347 return -1;
348 }
349
f31937aa
JS		 350 /* We need to determine the likely geometry of the inserted medium.
351 * In order of preference, we look for:
352 * (1) The same drive type and number of sectors,
353 * (2) The same diskette size and number of sectors,
354 * (3) The same drive type.
355 *
356 * In all cases, matches that occur higher in the drive table will take
357 * precedence over matches that occur later in the table.
358 */
9a972233 359 blk_get_geometry(blk, &nb_sectors);
f31937aa 360 match = size_match = type_match = -1;
9a972233
JS		 361 for (i = 0; ; i++) {
362 parse = &fd_formats[i];
2da44dd0 363 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) {
9a972233
JS		 364 break;
365 }
f31937aa
JS		 366 size = (parse->max_head + 1) * parse->max_track * parse->last_sect;
367 if (nb_sectors == size) {
368 if (magic || parse->drive == drv->drive) {
369 /* (1) perfect match -- nb_sectors and drive type */
370 goto out;
371 } else if (drive_size(parse->drive) == drive_size(drv->drive)) {
372 /* (2) size match -- nb_sectors and physical medium size */
373 match = (match == -1) ? i : match;
374 } else {
375 /* This is suspicious -- Did the user misconfigure? */
376 size_match = (size_match == -1) ? i : size_match;
9a972233 377 }
f31937aa
JS		 378 } else if (type_match == -1) {
379 if ((parse->drive == drv->drive) ||
380 (magic && (parse->drive == get_fallback_drive_type(drv)))) {
381 /* (3) type match -- nb_sectors mismatch, but matches the type
382 * specified explicitly by the user, or matches the fallback
383 * default type when using the drive autodetect mechanism */
384 type_match = i;
9a972233
JS		 385 }
386 }
387 }
f31937aa
JS		 388
389 /* No exact match found */
9a972233 390 if (match == -1) {
f31937aa
JS		 391 if (size_match != -1) {
392 parse = &fd_formats[size_match];
393 FLOPPY_DPRINTF("User requested floppy drive type '%s', "
394 "but inserted medium appears to be a "
c691320f 395 "%"PRId64" sector '%s' type\n",
977c736f 396 FloppyDriveType_str(drv->drive),
f31937aa 397 nb_sectors,
977c736f 398 FloppyDriveType_str(parse->drive));
9a972233 399 }
329b7291 400 assert(type_match != -1 && "misconfigured fd_format");
f31937aa 401 match = type_match;
9a972233 402 }
f31937aa
JS		 403 parse = &(fd_formats[match]);
404
405 out:
21862658
JS		 406 if (parse->max_head == 0) {
407 drv->flags &= ~FDISK_DBL_SIDES;
408 } else {
409 drv->flags |= FDISK_DBL_SIDES;
410 }
411 drv->max_track = parse->max_track;
412 drv->last_sect = parse->last_sect;
d5d47efc 413 drv->disk = parse->drive;
21862658 414 drv->media_rate = parse->rate;
d5d47efc
JS		 415 return 0;
416}
417
418static void pick_drive_type(FDrive *drv)
419{
fff4687b
JS		 420 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) {
421 return;
422 }
423
d5d47efc
JS		 424 if (pick_geometry(drv) == 0) {
425 drv->drive = drv->disk;
426 } else {
a73275dd 427 drv->drive = get_fallback_drive_type(drv);
d5d47efc 428 }
fff4687b
JS		 429
430 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO);
9a972233
JS		 431}
432
8977f3c1 433/* Revalidate a disk drive after a disk change */
5c02c033 434static void fd_revalidate(FDrive *drv)
8977f3c1 435{
d5d47efc
JS		 436 int rc;
437
8977f3c1 438 FLOPPY_DPRINTF("revalidate\n");
4be74634 439 if (drv->blk != NULL) {
21862658 440 drv->ro = blk_is_read_only(drv->blk);
abb3e55b 441 if (!blk_is_inserted(drv->blk)) {
cfb08fba 442 FLOPPY_DPRINTF("No disk in drive\n");
d5d47efc 443 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
fd9bdbd3 444 fd_empty_seek_hack(drv);
d5d47efc
JS		 445 } else if (!drv->media_validated) {
446 rc = pick_geometry(drv);
447 if (rc) {
448 FLOPPY_DPRINTF("Could not validate floppy drive media");
449 } else {
450 drv->media_validated = true;
451 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n",
452 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1,
453 drv->max_track, drv->last_sect,
454 drv->ro ? "ro" : "rw");
455 }
4f431960 456 }
8977f3c1 457 } else {
cfb08fba 458 FLOPPY_DPRINTF("No drive connected\n");
baca51fa 459 drv->last_sect = 0;
4f431960
JM		 460 drv->max_track = 0;
461 drv->flags &= ~FDISK_DBL_SIDES;
d5d47efc
JS		 462 drv->drive = FLOPPY_DRIVE_TYPE_NONE;
463 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
8977f3c1 464 }
caed8802
FB		 465}
466
39829a01 467static void fd_change_cb(void *opaque, bool load, Error **errp)
394ea2ca
KW		 468{
469 FDrive *drive = opaque;
a17c17a2
KW		 470
471 if (!load) {
472 blk_set_perm(drive->blk, 0, BLK_PERM_ALL, &error_abort);
473 } else {
ceff3e1f
MZ		 474 if (!blkconf_apply_backend_options(drive->conf,
475 blk_is_read_only(drive->blk), false,
476 errp)) {
a17c17a2
KW		 477 return;
478 }
479 }
394ea2ca
KW		 480
481 drive->media_changed = 1;
482 drive->media_validated = false;
483 fd_revalidate(drive);
484}
485
486static const BlockDevOps fd_block_ops = {
487 .change_media_cb = fd_change_cb,
488};
489
490
491#define TYPE_FLOPPY_DRIVE "floppy"
492#define FLOPPY_DRIVE(obj) \
493 OBJECT_CHECK(FloppyDrive, (obj), TYPE_FLOPPY_DRIVE)
494
495typedef struct FloppyDrive {
a92bd191
KW		 496 DeviceState qdev;
497 uint32_t unit;
498 BlockConf conf;
499 FloppyDriveType type;
394ea2ca
KW		 500} FloppyDrive;
501
502static Property floppy_drive_properties[] = {
503 DEFINE_PROP_UINT32("unit", FloppyDrive, unit, -1),
a92bd191 504 DEFINE_BLOCK_PROPERTIES(FloppyDrive, conf),
85bbd1e7 505 DEFINE_PROP_SIGNED("drive-type", FloppyDrive, type,
a92bd191
KW		 506 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
507 FloppyDriveType),
394ea2ca
KW		 508 DEFINE_PROP_END_OF_LIST(),
509};
510
ae34fce5 511static void floppy_drive_realize(DeviceState *qdev, Error **errp)
394ea2ca
KW		 512{
513 FloppyDrive *dev = FLOPPY_DRIVE(qdev);
514 FloppyBus *bus = FLOPPY_BUS(qdev->parent_bus);
515 FDrive *drive;
a92bd191 516 int ret;
394ea2ca
KW		 517
518 if (dev->unit == -1) {
519 for (dev->unit = 0; dev->unit < MAX_FD; dev->unit++) {
520 drive = get_drv(bus->fdc, dev->unit);
521 if (!drive->blk) {
522 break;
523 }
524 }
525 }
526
527 if (dev->unit >= MAX_FD) {
ae34fce5
MZ		 528 error_setg(errp, "Can't create floppy unit %d, bus supports "
529 "only %d units", dev->unit, MAX_FD);
530 return;
394ea2ca
KW		 531 }
532
394ea2ca 533 drive = get_drv(bus->fdc, dev->unit);
394ea2ca 534 if (drive->blk) {
ae34fce5
MZ		 535 error_setg(errp, "Floppy unit %d is in use", dev->unit);
536 return;
a92bd191
KW		 537 }
538
539 if (!dev->conf.blk) {
394ea2ca 540 /* Anonymous BlockBackend for an empty drive */
6d0eb64d 541 dev->conf.blk = blk_new(0, BLK_PERM_ALL);
a92bd191
KW		 542 ret = blk_attach_dev(dev->conf.blk, qdev);
543 assert(ret == 0);
394ea2ca
KW		 544 }
545
a92bd191
KW		 546 blkconf_blocksizes(&dev->conf);
547 if (dev->conf.logical_block_size != 512 ||
548 dev->conf.physical_block_size != 512)
549 {
ae34fce5
MZ		 550 error_setg(errp, "Physical and logical block size must "
551 "be 512 for floppy");
552 return;
a92bd191
KW		 553 }
554
555 /* rerror/werror aren't supported by fdc and therefore not even registered
556 * with qdev. So set the defaults manually before they are used in
557 * blkconf_apply_backend_options(). */
558 dev->conf.rerror = BLOCKDEV_ON_ERROR_AUTO;
559 dev->conf.werror = BLOCKDEV_ON_ERROR_AUTO;
a17c17a2 560
ceff3e1f
MZ		 561 if (!blkconf_apply_backend_options(&dev->conf,
562 blk_is_read_only(dev->conf.blk),
563 false, errp)) {
ae34fce5 564 return;
a17c17a2 565 }
a92bd191
KW		 566
567 /* 'enospc' is the default for -drive, 'report' is what blk_new() gives us
568 * for empty drives. */
569 if (blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC &&
570 blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_REPORT) {
ae34fce5
MZ		 571 error_setg(errp, "fdc doesn't support drive option werror");
572 return;
394ea2ca 573 }
a92bd191 574 if (blk_get_on_error(dev->conf.blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
ae34fce5
MZ		 575 error_setg(errp, "fdc doesn't support drive option rerror");
576 return;
a92bd191
KW		 577 }
578
a17c17a2 579 drive->conf = &dev->conf;
a92bd191
KW		 580 drive->blk = dev->conf.blk;
581 drive->fdctrl = bus->fdc;
582
583 fd_init(drive);
584 blk_set_dev_ops(drive->blk, &fd_block_ops, drive);
585
586 /* Keep 'type' qdev property and FDrive->drive in sync */
587 drive->drive = dev->type;
588 pick_drive_type(drive);
589 dev->type = drive->drive;
590
394ea2ca 591 fd_revalidate(drive);
394ea2ca
KW		 592}
593
594static void floppy_drive_class_init(ObjectClass *klass, void *data)
595{
596 DeviceClass *k = DEVICE_CLASS(klass);
ae34fce5 597 k->realize = floppy_drive_realize;
394ea2ca
KW		 598 set_bit(DEVICE_CATEGORY_STORAGE, k->categories);
599 k->bus_type = TYPE_FLOPPY_BUS;
600 k->props = floppy_drive_properties;
601 k->desc = "virtual floppy drive";
602}
603
604static const TypeInfo floppy_drive_info = {
605 .name = TYPE_FLOPPY_DRIVE,
606 .parent = TYPE_DEVICE,
607 .instance_size = sizeof(FloppyDrive),
608 .class_init = floppy_drive_class_init,
609};
610
8977f3c1 611/********************************************************/
4b19ec0c 612/* Intel 82078 floppy disk controller emulation */
8977f3c1 613
5c02c033 614static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
07e415f2 615static void fdctrl_to_command_phase(FDCtrl *fdctrl);
85571bc7 616static int fdctrl_transfer_handler (void *opaque, int nchan,
c227f099 617 int dma_pos, int dma_len);
d497d534 618static void fdctrl_raise_irq(FDCtrl *fdctrl);
a2df5fa3 619static FDrive *get_cur_drv(FDCtrl *fdctrl);
5c02c033
BS		 620
621static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
622static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
623static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
624static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
625static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
626static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
627static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
628static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
629static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
630static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
631static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
a758f8f4 632static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
8977f3c1 633
8977f3c1
FB		 634enum {
635 FD_DIR_WRITE = 0,
636 FD_DIR_READ = 1,
637 FD_DIR_SCANE = 2,
638 FD_DIR_SCANL = 3,
639 FD_DIR_SCANH = 4,
7ea004ed 640 FD_DIR_VERIFY = 5,
8977f3c1
FB		 641};
642
643enum {
b9b3d225
BS		 644 FD_STATE_MULTI = 0x01, /* multi track flag */
645 FD_STATE_FORMAT = 0x02, /* format flag */
8977f3c1
FB		 646};
647
9fea808a 648enum {
8c6a4d77
BS		 649 FD_REG_SRA = 0x00,
650 FD_REG_SRB = 0x01,
9fea808a
BS		 651 FD_REG_DOR = 0x02,
652 FD_REG_TDR = 0x03,
653 FD_REG_MSR = 0x04,
654 FD_REG_DSR = 0x04,
655 FD_REG_FIFO = 0x05,
656 FD_REG_DIR = 0x07,
a758f8f4 657 FD_REG_CCR = 0x07,
9fea808a
BS		 658};
659
660enum {
65cef780 661 FD_CMD_READ_TRACK = 0x02,
9fea808a
BS		 662 FD_CMD_SPECIFY = 0x03,
663 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
65cef780
BS		 664 FD_CMD_WRITE = 0x05,
665 FD_CMD_READ = 0x06,
9fea808a
BS		 666 FD_CMD_RECALIBRATE = 0x07,
667 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
65cef780
BS		 668 FD_CMD_WRITE_DELETED = 0x09,
669 FD_CMD_READ_ID = 0x0a,
670 FD_CMD_READ_DELETED = 0x0c,
671 FD_CMD_FORMAT_TRACK = 0x0d,
9fea808a
BS		 672 FD_CMD_DUMPREG = 0x0e,
673 FD_CMD_SEEK = 0x0f,
674 FD_CMD_VERSION = 0x10,
65cef780 675 FD_CMD_SCAN_EQUAL = 0x11,
9fea808a
BS		 676 FD_CMD_PERPENDICULAR_MODE = 0x12,
677 FD_CMD_CONFIGURE = 0x13,
65cef780
BS		 678 FD_CMD_LOCK = 0x14,
679 FD_CMD_VERIFY = 0x16,
9fea808a
BS		 680 FD_CMD_POWERDOWN_MODE = 0x17,
681 FD_CMD_PART_ID = 0x18,
65cef780
BS		 682 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
683 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
bb350a5e 684 FD_CMD_SAVE = 0x2e,
9fea808a 685 FD_CMD_OPTION = 0x33,
bb350a5e 686 FD_CMD_RESTORE = 0x4e,
9fea808a
BS		 687 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
688 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
9fea808a
BS		 689 FD_CMD_FORMAT_AND_WRITE = 0xcd,
690 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
691};
692
693enum {
694 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
695 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
696 FD_CONFIG_POLL = 0x10, /* Poll enabled */
697 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
698 FD_CONFIG_EIS = 0x40, /* No implied seeks */
699};
700
701enum {
2fee0088
PH		 702 FD_SR0_DS0 = 0x01,
703 FD_SR0_DS1 = 0x02,
704 FD_SR0_HEAD = 0x04,
9fea808a
BS		 705 FD_SR0_EQPMT = 0x10,
706 FD_SR0_SEEK = 0x20,
707 FD_SR0_ABNTERM = 0x40,
708 FD_SR0_INVCMD = 0x80,
709 FD_SR0_RDYCHG = 0xc0,
710};
711
77370520 712enum {
844f65d6 713 FD_SR1_MA = 0x01, /* Missing address mark */
8510854e 714 FD_SR1_NW = 0x02, /* Not writable */
77370520
BS		 715 FD_SR1_EC = 0x80, /* End of cylinder */
716};
717
718enum {
719 FD_SR2_SNS = 0x04, /* Scan not satisfied */
720 FD_SR2_SEH = 0x08, /* Scan equal hit */
721};
722
8c6a4d77
BS		 723enum {
724 FD_SRA_DIR = 0x01,
725 FD_SRA_nWP = 0x02,
726 FD_SRA_nINDX = 0x04,
727 FD_SRA_HDSEL = 0x08,
728 FD_SRA_nTRK0 = 0x10,
729 FD_SRA_STEP = 0x20,
730 FD_SRA_nDRV2 = 0x40,
731 FD_SRA_INTPEND = 0x80,
732};
733
734enum {
735 FD_SRB_MTR0 = 0x01,
736 FD_SRB_MTR1 = 0x02,
737 FD_SRB_WGATE = 0x04,
738 FD_SRB_RDATA = 0x08,
739 FD_SRB_WDATA = 0x10,
740 FD_SRB_DR0 = 0x20,
741};
742
9fea808a 743enum {
78ae820c
BS		 744#if MAX_FD == 4
745 FD_DOR_SELMASK = 0x03,
746#else
9fea808a 747 FD_DOR_SELMASK = 0x01,
78ae820c 748#endif
9fea808a
BS		 749 FD_DOR_nRESET = 0x04,
750 FD_DOR_DMAEN = 0x08,
751 FD_DOR_MOTEN0 = 0x10,
752 FD_DOR_MOTEN1 = 0x20,
753 FD_DOR_MOTEN2 = 0x40,
754 FD_DOR_MOTEN3 = 0x80,
755};
756
757enum {
78ae820c 758#if MAX_FD == 4
9fea808a 759 FD_TDR_BOOTSEL = 0x0c,
78ae820c
BS		 760#else
761 FD_TDR_BOOTSEL = 0x04,
762#endif
9fea808a
BS		 763};
764
765enum {
766 FD_DSR_DRATEMASK= 0x03,
767 FD_DSR_PWRDOWN = 0x40,
768 FD_DSR_SWRESET = 0x80,
769};
770
771enum {
772 FD_MSR_DRV0BUSY = 0x01,
773 FD_MSR_DRV1BUSY = 0x02,
774 FD_MSR_DRV2BUSY = 0x04,
775 FD_MSR_DRV3BUSY = 0x08,
776 FD_MSR_CMDBUSY = 0x10,
777 FD_MSR_NONDMA = 0x20,
778 FD_MSR_DIO = 0x40,
779 FD_MSR_RQM = 0x80,
780};
781
782enum {
783 FD_DIR_DSKCHG = 0x80,
784};
785
85d291a0
KW		 786/*
787 * See chapter 5.0 "Controller phases" of the spec:
788 *
789 * Command phase:
790 * The host writes a command and its parameters into the FIFO. The command
791 * phase is completed when all parameters for the command have been supplied,
792 * and execution phase is entered.
793 *
794 * Execution phase:
795 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
796 * contains the payload now, otherwise it's unused. When all bytes of the
797 * required data have been transferred, the state is switched to either result
798 * phase (if the command produces status bytes) or directly back into the
799 * command phase for the next command.
800 *
801 * Result phase:
802 * The host reads out the FIFO, which contains one or more result bytes now.
803 */
804enum {
805 /* Only for migration: reconstruct phase from registers like qemu 2.3 */
806 FD_PHASE_RECONSTRUCT = 0,
807
808 FD_PHASE_COMMAND = 1,
809 FD_PHASE_EXECUTION = 2,
810 FD_PHASE_RESULT = 3,
811};
812
8977f3c1 813#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
baca51fa 814#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
8977f3c1 815
5c02c033 816struct FDCtrl {
dc6c1b37 817 MemoryRegion iomem;
d537cf6c 818 qemu_irq irq;
4b19ec0c 819 /* Controller state */
ed5fd2cc 820 QEMUTimer *result_timer;
242cca4f 821 int dma_chann;
85d291a0 822 uint8_t phase;
c8a35f1c 823 IsaDma *dma;
242cca4f
BS		 824 /* Controller's identification */
825 uint8_t version;
826 /* HW */
8c6a4d77
BS		 827 uint8_t sra;
828 uint8_t srb;
368df94d 829 uint8_t dor;
d7a6c270 830 uint8_t dor_vmstate; /* only used as temp during vmstate */
46d3233b 831 uint8_t tdr;
b9b3d225 832 uint8_t dsr;
368df94d 833 uint8_t msr;
8977f3c1 834 uint8_t cur_drv;
77370520
BS		 835 uint8_t status0;
836 uint8_t status1;
837 uint8_t status2;
8977f3c1 838 /* Command FIFO */
33f00271 839 uint8_t *fifo;
d7a6c270 840 int32_t fifo_size;
8977f3c1
FB		 841 uint32_t data_pos;
842 uint32_t data_len;
843 uint8_t data_state;
844 uint8_t data_dir;
890fa6be 845 uint8_t eot; /* last wanted sector */
8977f3c1 846 /* States kept only to be returned back */
8977f3c1
FB		 847 /* precompensation */
848 uint8_t precomp_trk;
849 uint8_t config;
850 uint8_t lock;
851 /* Power down config (also with status regB access mode */
852 uint8_t pwrd;
853 /* Floppy drives */
51e6e90e 854 FloppyBus bus;
d7a6c270 855 uint8_t num_floppies;
5c02c033 856 FDrive drives[MAX_FD];
a92bd191
KW		 857 struct {
858 BlockBackend *blk;
859 FloppyDriveType type;
860 } qdev_for_drives[MAX_FD];
f2d81b33 861 int reset_sensei;
09c6d585 862 uint32_t check_media_rate;
a73275dd 863 FloppyDriveType fallback; /* type=auto failure fallback */
242cca4f
BS		 864 /* Timers state */
865 uint8_t timer0;
866 uint8_t timer1;
e305a165 867 PortioList portio_list;
baca51fa
FB		 868};
869
a73275dd
JS		 870static FloppyDriveType get_fallback_drive_type(FDrive *drv)
871{
872 return drv->fdctrl->fallback;
873}
874
19d46d71 875#define TYPE_SYSBUS_FDC "base-sysbus-fdc"
dd3be742
HT		 876#define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
877
5c02c033 878typedef struct FDCtrlSysBus {
dd3be742
HT		 879 /*< private >*/
880 SysBusDevice parent_obj;
881 /*< public >*/
882
5c02c033
BS		 883 struct FDCtrl state;
884} FDCtrlSysBus;
8baf73ad 885
020c8e76
AF		 886#define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
887
5c02c033 888typedef struct FDCtrlISABus {
020c8e76
AF		 889 ISADevice parent_obj;
890
c9ae703d
HP		 891 uint32_t iobase;
892 uint32_t irq;
893 uint32_t dma;
5c02c033 894 struct FDCtrl state;
1ca4d09a
GN		 895 int32_t bootindexA;
896 int32_t bootindexB;
5c02c033 897} FDCtrlISABus;
8baf73ad 898
baca51fa
FB		 899static uint32_t fdctrl_read (void *opaque, uint32_t reg)
900{
5c02c033 901 FDCtrl *fdctrl = opaque;
baca51fa
FB		 902 uint32_t retval;
903
a18e67f5 904 reg &= 7;
e64d7d59 905 switch (reg) {
8c6a4d77
BS		 906 case FD_REG_SRA:
907 retval = fdctrl_read_statusA(fdctrl);
4f431960 908 break;
8c6a4d77 909 case FD_REG_SRB:
4f431960
JM		 910 retval = fdctrl_read_statusB(fdctrl);
911 break;
9fea808a 912 case FD_REG_DOR:
4f431960
JM		 913 retval = fdctrl_read_dor(fdctrl);
914 break;
9fea808a 915 case FD_REG_TDR:
baca51fa 916 retval = fdctrl_read_tape(fdctrl);
4f431960 917 break;
9fea808a 918 case FD_REG_MSR:
baca51fa 919 retval = fdctrl_read_main_status(fdctrl);
4f431960 920 break;
9fea808a 921 case FD_REG_FIFO:
baca51fa 922 retval = fdctrl_read_data(fdctrl);
4f431960 923 break;
9fea808a 924 case FD_REG_DIR:
baca51fa 925 retval = fdctrl_read_dir(fdctrl);
4f431960 926 break;
a541f297 927 default:
4f431960
JM		 928 retval = (uint32_t)(-1);
929 break;
a541f297 930 }
1a5396d9 931 trace_fdc_ioport_read(reg, retval);
baca51fa
FB		 932
933 return retval;
934}
935
936static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
937{
5c02c033 938 FDCtrl *fdctrl = opaque;
baca51fa 939
a18e67f5 940 reg &= 7;
1a5396d9 941 trace_fdc_ioport_write(reg, value);
e64d7d59 942 switch (reg) {
9fea808a 943 case FD_REG_DOR:
4f431960
JM		 944 fdctrl_write_dor(fdctrl, value);
945 break;
9fea808a 946 case FD_REG_TDR:
baca51fa 947 fdctrl_write_tape(fdctrl, value);
4f431960 948 break;
9fea808a 949 case FD_REG_DSR:
baca51fa 950 fdctrl_write_rate(fdctrl, value);
4f431960 951 break;
9fea808a 952 case FD_REG_FIFO:
baca51fa 953 fdctrl_write_data(fdctrl, value);
4f431960 954 break;
a758f8f4
HP		 955 case FD_REG_CCR:
956 fdctrl_write_ccr(fdctrl, value);
957 break;
a541f297 958 default:
4f431960 959 break;
a541f297 960 }
baca51fa
FB		 961}
962
a8170e5e 963static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
dc6c1b37 964 unsigned ize)
62a46c61 965{
5dcb6b91 966 return fdctrl_read(opaque, (uint32_t)reg);
62a46c61
FB		 967}
968
a8170e5e 969static void fdctrl_write_mem (void *opaque, hwaddr reg,
dc6c1b37 970 uint64_t value, unsigned size)
62a46c61 971{
5dcb6b91 972 fdctrl_write(opaque, (uint32_t)reg, value);
62a46c61
FB		 973}
974
dc6c1b37
AK		 975static const MemoryRegionOps fdctrl_mem_ops = {
976 .read = fdctrl_read_mem,
977 .write = fdctrl_write_mem,
978 .endianness = DEVICE_NATIVE_ENDIAN,
e80cfcfc
FB		 979};
980
dc6c1b37
AK		 981static const MemoryRegionOps fdctrl_mem_strict_ops = {
982 .read = fdctrl_read_mem,
983 .write = fdctrl_write_mem,
984 .endianness = DEVICE_NATIVE_ENDIAN,
985 .valid = {
986 .min_access_size = 1,
987 .max_access_size = 1,
988 },
7c560456
BS		 989};
990
7d905f71
JW		 991static bool fdrive_media_changed_needed(void *opaque)
992{
993 FDrive *drive = opaque;
994
abb3e55b 995 return (drive->blk != NULL && drive->media_changed != 1);
7d905f71
JW		 996}
997
998static const VMStateDescription vmstate_fdrive_media_changed = {
999 .name = "fdrive/media_changed",
1000 .version_id = 1,
1001 .minimum_version_id = 1,
5cd8cada 1002 .needed = fdrive_media_changed_needed,
d49805ae 1003 .fields = (VMStateField[]) {
7d905f71
JW		 1004 VMSTATE_UINT8(media_changed, FDrive),
1005 VMSTATE_END_OF_LIST()
1006 }
1007};
1008
844f65d6
HP		 1009static bool fdrive_media_rate_needed(void *opaque)
1010{
1011 FDrive *drive = opaque;
1012
1013 return drive->fdctrl->check_media_rate;
1014}
1015
1016static const VMStateDescription vmstate_fdrive_media_rate = {
1017 .name = "fdrive/media_rate",
1018 .version_id = 1,
1019 .minimum_version_id = 1,
5cd8cada 1020 .needed = fdrive_media_rate_needed,
d49805ae 1021 .fields = (VMStateField[]) {
844f65d6
HP		 1022 VMSTATE_UINT8(media_rate, FDrive),
1023 VMSTATE_END_OF_LIST()
1024 }
1025};
1026
c0b92f30
PD		 1027static bool fdrive_perpendicular_needed(void *opaque)
1028{
1029 FDrive *drive = opaque;
1030
1031 return drive->perpendicular != 0;
1032}
1033
1034static const VMStateDescription vmstate_fdrive_perpendicular = {
1035 .name = "fdrive/perpendicular",
1036 .version_id = 1,
1037 .minimum_version_id = 1,
5cd8cada 1038 .needed = fdrive_perpendicular_needed,
c0b92f30
PD		 1039 .fields = (VMStateField[]) {
1040 VMSTATE_UINT8(perpendicular, FDrive),
1041 VMSTATE_END_OF_LIST()
1042 }
1043};
1044
1045static int fdrive_post_load(void *opaque, int version_id)
1046{
1047 fd_revalidate(opaque);
1048 return 0;
1049}
1050
d7a6c270
JQ		 1051static const VMStateDescription vmstate_fdrive = {
1052 .name = "fdrive",
1053 .version_id = 1,
1054 .minimum_version_id = 1,
c0b92f30 1055 .post_load = fdrive_post_load,
d49805ae 1056 .fields = (VMStateField[]) {
5c02c033
BS		 1057 VMSTATE_UINT8(head, FDrive),
1058 VMSTATE_UINT8(track, FDrive),
1059 VMSTATE_UINT8(sect, FDrive),
d7a6c270 1060 VMSTATE_END_OF_LIST()
7d905f71 1061 },
5cd8cada
JQ		 1062 .subsections = (const VMStateDescription*[]) {
1063 &vmstate_fdrive_media_changed,
1064 &vmstate_fdrive_media_rate,
1065 &vmstate_fdrive_perpendicular,
1066 NULL
d7a6c270
JQ		 1067 }
1068};
3ccacc4a 1069
85d291a0
KW		 1070/*
1071 * Reconstructs the phase from register values according to the logic that was
1072 * implemented in qemu 2.3. This is the default value that is used if the phase
1073 * subsection is not present on migration.
1074 *
1075 * Don't change this function to reflect newer qemu versions, it is part of
1076 * the migration ABI.
1077 */
1078static int reconstruct_phase(FDCtrl *fdctrl)
1079{
1080 if (fdctrl->msr & FD_MSR_NONDMA) {
1081 return FD_PHASE_EXECUTION;
1082 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
1083 /* qemu 2.3 disabled RQM only during DMA transfers */
1084 return FD_PHASE_EXECUTION;
1085 } else if (fdctrl->msr & FD_MSR_DIO) {
1086 return FD_PHASE_RESULT;
1087 } else {
1088 return FD_PHASE_COMMAND;
1089 }
1090}
1091
44b1ff31 1092static int fdc_pre_save(void *opaque)
3ccacc4a 1093{
5c02c033 1094 FDCtrl *s = opaque;
3ccacc4a 1095
d7a6c270 1096 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
44b1ff31
DDAG		 1097
1098 return 0;
3ccacc4a
BS		 1099}
1100
85d291a0
KW		 1101static int fdc_pre_load(void *opaque)
1102{
1103 FDCtrl *s = opaque;
1104 s->phase = FD_PHASE_RECONSTRUCT;
1105 return 0;
1106}
1107
e59fb374 1108static int fdc_post_load(void *opaque, int version_id)
3ccacc4a 1109{
5c02c033 1110 FDCtrl *s = opaque;
3ccacc4a 1111
d7a6c270
JQ		 1112 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
1113 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
85d291a0
KW		 1114
1115 if (s->phase == FD_PHASE_RECONSTRUCT) {
1116 s->phase = reconstruct_phase(s);
1117 }
1118
3ccacc4a
BS		 1119 return 0;
1120}
1121
c0b92f30
PD		 1122static bool fdc_reset_sensei_needed(void *opaque)
1123{
1124 FDCtrl *s = opaque;
1125
1126 return s->reset_sensei != 0;
1127}
1128
1129static const VMStateDescription vmstate_fdc_reset_sensei = {
1130 .name = "fdc/reset_sensei",
1131 .version_id = 1,
1132 .minimum_version_id = 1,
5cd8cada 1133 .needed = fdc_reset_sensei_needed,
c0b92f30
PD		 1134 .fields = (VMStateField[]) {
1135 VMSTATE_INT32(reset_sensei, FDCtrl),
1136 VMSTATE_END_OF_LIST()
1137 }
1138};
1139
1140static bool fdc_result_timer_needed(void *opaque)
1141{
1142 FDCtrl *s = opaque;
1143
1144 return timer_pending(s->result_timer);
1145}
1146
1147static const VMStateDescription vmstate_fdc_result_timer = {
1148 .name = "fdc/result_timer",
1149 .version_id = 1,
1150 .minimum_version_id = 1,
5cd8cada 1151 .needed = fdc_result_timer_needed,
c0b92f30 1152 .fields = (VMStateField[]) {
e720677e 1153 VMSTATE_TIMER_PTR(result_timer, FDCtrl),
c0b92f30
PD		 1154 VMSTATE_END_OF_LIST()
1155 }
1156};
1157
85d291a0
KW		 1158static bool fdc_phase_needed(void *opaque)
1159{
1160 FDCtrl *fdctrl = opaque;
1161
1162 return reconstruct_phase(fdctrl) != fdctrl->phase;
1163}
1164
1165static const VMStateDescription vmstate_fdc_phase = {
1166 .name = "fdc/phase",
1167 .version_id = 1,
1168 .minimum_version_id = 1,
5cd8cada 1169 .needed = fdc_phase_needed,
85d291a0
KW		 1170 .fields = (VMStateField[]) {
1171 VMSTATE_UINT8(phase, FDCtrl),
1172 VMSTATE_END_OF_LIST()
1173 }
1174};
1175
d7a6c270 1176static const VMStateDescription vmstate_fdc = {
aef30c3c 1177 .name = "fdc",
d7a6c270
JQ		 1178 .version_id = 2,
1179 .minimum_version_id = 2,
d7a6c270 1180 .pre_save = fdc_pre_save,
85d291a0 1181 .pre_load = fdc_pre_load,
d7a6c270 1182 .post_load = fdc_post_load,
d49805ae 1183 .fields = (VMStateField[]) {
d7a6c270 1184 /* Controller State */
5c02c033
BS		 1185 VMSTATE_UINT8(sra, FDCtrl),
1186 VMSTATE_UINT8(srb, FDCtrl),
1187 VMSTATE_UINT8(dor_vmstate, FDCtrl),
1188 VMSTATE_UINT8(tdr, FDCtrl),
1189 VMSTATE_UINT8(dsr, FDCtrl),
1190 VMSTATE_UINT8(msr, FDCtrl),
1191 VMSTATE_UINT8(status0, FDCtrl),
1192 VMSTATE_UINT8(status1, FDCtrl),
1193 VMSTATE_UINT8(status2, FDCtrl),
d7a6c270 1194 /* Command FIFO */
8ec68b06
BS		 1195 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
1196 uint8_t),
5c02c033
BS		 1197 VMSTATE_UINT32(data_pos, FDCtrl),
1198 VMSTATE_UINT32(data_len, FDCtrl),
1199 VMSTATE_UINT8(data_state, FDCtrl),
1200 VMSTATE_UINT8(data_dir, FDCtrl),
1201 VMSTATE_UINT8(eot, FDCtrl),
d7a6c270 1202 /* States kept only to be returned back */
5c02c033
BS		 1203 VMSTATE_UINT8(timer0, FDCtrl),
1204 VMSTATE_UINT8(timer1, FDCtrl),
1205 VMSTATE_UINT8(precomp_trk, FDCtrl),
1206 VMSTATE_UINT8(config, FDCtrl),
1207 VMSTATE_UINT8(lock, FDCtrl),
1208 VMSTATE_UINT8(pwrd, FDCtrl),
d2164ad3 1209 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl, NULL),
5c02c033
BS		 1210 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
1211 vmstate_fdrive, FDrive),
d7a6c270 1212 VMSTATE_END_OF_LIST()
c0b92f30 1213 },
5cd8cada
JQ		 1214 .subsections = (const VMStateDescription*[]) {
1215 &vmstate_fdc_reset_sensei,
1216 &vmstate_fdc_result_timer,
1217 &vmstate_fdc_phase,
1218 NULL
78ae820c 1219 }
d7a6c270 1220};
3ccacc4a 1221
2be37833 1222static void fdctrl_external_reset_sysbus(DeviceState *d)
3ccacc4a 1223{
dd3be742 1224 FDCtrlSysBus *sys = SYSBUS_FDC(d);
5c02c033 1225 FDCtrl *s = &sys->state;
2be37833
BS		 1226
1227 fdctrl_reset(s, 0);
1228}
1229
1230static void fdctrl_external_reset_isa(DeviceState *d)
1231{
020c8e76 1232 FDCtrlISABus *isa = ISA_FDC(d);
5c02c033 1233 FDCtrl *s = &isa->state;
3ccacc4a
BS		 1234
1235 fdctrl_reset(s, 0);
1236}
1237
2be17ebd
BS		 1238static void fdctrl_handle_tc(void *opaque, int irq, int level)
1239{
5c02c033 1240 //FDCtrl *s = opaque;
2be17ebd
BS		 1241
1242 if (level) {
1243 // XXX
1244 FLOPPY_DPRINTF("TC pulsed\n");
1245 }
1246}
1247
8977f3c1 1248/* Change IRQ state */
5c02c033 1249static void fdctrl_reset_irq(FDCtrl *fdctrl)
8977f3c1 1250{
d497d534 1251 fdctrl->status0 = 0;
8c6a4d77
BS		 1252 if (!(fdctrl->sra & FD_SRA_INTPEND))
1253 return;
ed5fd2cc 1254 FLOPPY_DPRINTF("Reset interrupt\n");
d537cf6c 1255 qemu_set_irq(fdctrl->irq, 0);
8c6a4d77 1256 fdctrl->sra &= ~FD_SRA_INTPEND;
8977f3c1
FB		 1257}
1258
d497d534 1259static void fdctrl_raise_irq(FDCtrl *fdctrl)
8977f3c1 1260{
8c6a4d77 1261 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
d537cf6c 1262 qemu_set_irq(fdctrl->irq, 1);
8c6a4d77 1263 fdctrl->sra |= FD_SRA_INTPEND;
8977f3c1 1264 }
21fcf360 1265
f2d81b33 1266 fdctrl->reset_sensei = 0;
77370520 1267 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
8977f3c1
FB		 1268}
1269
4b19ec0c 1270/* Reset controller */
5c02c033 1271static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
8977f3c1
FB		 1272{
1273 int i;
1274
4b19ec0c 1275 FLOPPY_DPRINTF("reset controller\n");
baca51fa 1276 fdctrl_reset_irq(fdctrl);
4b19ec0c 1277 /* Initialise controller */
8c6a4d77
BS		 1278 fdctrl->sra = 0;
1279 fdctrl->srb = 0xc0;
4be74634 1280 if (!fdctrl->drives[1].blk) {
8c6a4d77 1281 fdctrl->sra |= FD_SRA_nDRV2;
4be74634 1282 }
baca51fa 1283 fdctrl->cur_drv = 0;
1c346df2 1284 fdctrl->dor = FD_DOR_nRESET;
368df94d 1285 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
b9b3d225 1286 fdctrl->msr = FD_MSR_RQM;
c0b92f30
PD		 1287 fdctrl->reset_sensei = 0;
1288 timer_del(fdctrl->result_timer);
8977f3c1 1289 /* FIFO state */
baca51fa
FB		 1290 fdctrl->data_pos = 0;
1291 fdctrl->data_len = 0;
b9b3d225 1292 fdctrl->data_state = 0;
baca51fa 1293 fdctrl->data_dir = FD_DIR_WRITE;
8977f3c1 1294 for (i = 0; i < MAX_FD; i++)
1c346df2 1295 fd_recalibrate(&fdctrl->drives[i]);
07e415f2 1296 fdctrl_to_command_phase(fdctrl);
77370520 1297 if (do_irq) {
d497d534
HP		 1298 fdctrl->status0 |= FD_SR0_RDYCHG;
1299 fdctrl_raise_irq(fdctrl);
f2d81b33 1300 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
77370520 1301 }
baca51fa
FB		 1302}
1303
5c02c033 1304static inline FDrive *drv0(FDCtrl *fdctrl)
baca51fa 1305{
46d3233b 1306 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
baca51fa
FB		 1307}
1308
5c02c033 1309static inline FDrive *drv1(FDCtrl *fdctrl)
baca51fa 1310{
46d3233b
BS		 1311 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
1312 return &fdctrl->drives[1];
1313 else
1314 return &fdctrl->drives[0];
baca51fa
FB		 1315}
1316
78ae820c 1317#if MAX_FD == 4
5c02c033 1318static inline FDrive *drv2(FDCtrl *fdctrl)
78ae820c
BS		 1319{
1320 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
1321 return &fdctrl->drives[2];
1322 else
1323 return &fdctrl->drives[1];
1324}
1325
5c02c033 1326static inline FDrive *drv3(FDCtrl *fdctrl)
78ae820c
BS		 1327{
1328 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
1329 return &fdctrl->drives[3];
1330 else
1331 return &fdctrl->drives[2];
1332}
1333#endif
1334
394ea2ca 1335static FDrive *get_drv(FDCtrl *fdctrl, int unit)
baca51fa 1336{
394ea2ca 1337 switch (unit) {
78ae820c
BS		 1338 case 0: return drv0(fdctrl);
1339 case 1: return drv1(fdctrl);
1340#if MAX_FD == 4
1341 case 2: return drv2(fdctrl);
1342 case 3: return drv3(fdctrl);
1343#endif
1344 default: return NULL;
1345 }
8977f3c1
FB		 1346}
1347
394ea2ca
KW		 1348static FDrive *get_cur_drv(FDCtrl *fdctrl)
1349{
1350 return get_drv(fdctrl, fdctrl->cur_drv);
1351}
1352
8c6a4d77 1353/* Status A register : 0x00 (read-only) */
5c02c033 1354static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
8c6a4d77
BS		 1355{
1356 uint32_t retval = fdctrl->sra;
1357
1358 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
1359
1360 return retval;
1361}
1362
8977f3c1 1363/* Status B register : 0x01 (read-only) */
5c02c033 1364static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
8977f3c1 1365{
8c6a4d77
BS		 1366 uint32_t retval = fdctrl->srb;
1367
1368 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
1369
1370 return retval;
8977f3c1
FB		 1371}
1372
1373/* Digital output register : 0x02 */
5c02c033 1374static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
8977f3c1 1375{
1c346df2 1376 uint32_t retval = fdctrl->dor;
8977f3c1 1377
8977f3c1 1378 /* Selected drive */
baca51fa 1379 retval |= fdctrl->cur_drv;
8977f3c1
FB		 1380 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1381
1382 return retval;
1383}
1384
5c02c033 1385static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1386{
8977f3c1 1387 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
8c6a4d77
BS		 1388
1389 /* Motors */
1390 if (value & FD_DOR_MOTEN0)
1391 fdctrl->srb |= FD_SRB_MTR0;
1392 else
1393 fdctrl->srb &= ~FD_SRB_MTR0;
1394 if (value & FD_DOR_MOTEN1)
1395 fdctrl->srb |= FD_SRB_MTR1;
1396 else
1397 fdctrl->srb &= ~FD_SRB_MTR1;
1398
1399 /* Drive */
1400 if (value & 1)
1401 fdctrl->srb |= FD_SRB_DR0;
1402 else
1403 fdctrl->srb &= ~FD_SRB_DR0;
1404
8977f3c1 1405 /* Reset */
9fea808a 1406 if (!(value & FD_DOR_nRESET)) {
1c346df2 1407 if (fdctrl->dor & FD_DOR_nRESET) {
4b19ec0c 1408 FLOPPY_DPRINTF("controller enter RESET state\n");
8977f3c1
FB		 1409 }
1410 } else {
1c346df2 1411 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 1412 FLOPPY_DPRINTF("controller out of RESET state\n");
fb6cf1d0 1413 fdctrl_reset(fdctrl, 1);
b9b3d225 1414 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
8977f3c1
FB		 1415 }
1416 }
1417 /* Selected drive */
9fea808a 1418 fdctrl->cur_drv = value & FD_DOR_SELMASK;
368df94d
BS		 1419
1420 fdctrl->dor = value;
8977f3c1
FB		 1421}
1422
1423/* Tape drive register : 0x03 */
5c02c033 1424static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
8977f3c1 1425{
46d3233b 1426 uint32_t retval = fdctrl->tdr;
8977f3c1 1427
8977f3c1
FB		 1428 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1429
1430 return retval;
1431}
1432
5c02c033 1433static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1434{
8977f3c1 1435 /* Reset mode */
1c346df2 1436 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 1437 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB		 1438 return;
1439 }
1440 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1441 /* Disk boot selection indicator */
46d3233b 1442 fdctrl->tdr = value & FD_TDR_BOOTSEL;
8977f3c1
FB		 1443 /* Tape indicators: never allow */
1444}
1445
1446/* Main status register : 0x04 (read) */
5c02c033 1447static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
8977f3c1 1448{
b9b3d225 1449 uint32_t retval = fdctrl->msr;
8977f3c1 1450
b9b3d225 1451 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1c346df2 1452 fdctrl->dor |= FD_DOR_nRESET;
b9b3d225 1453
8977f3c1
FB		 1454 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1455
1456 return retval;
1457}
1458
1459/* Data select rate register : 0x04 (write) */
5c02c033 1460static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1461{
8977f3c1 1462 /* Reset mode */
1c346df2 1463 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4f431960
JM		 1464 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1465 return;
1466 }
8977f3c1
FB		 1467 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1468 /* Reset: autoclear */
9fea808a 1469 if (value & FD_DSR_SWRESET) {
1c346df2 1470 fdctrl->dor &= ~FD_DOR_nRESET;
baca51fa 1471 fdctrl_reset(fdctrl, 1);
1c346df2 1472 fdctrl->dor |= FD_DOR_nRESET;
8977f3c1 1473 }
9fea808a 1474 if (value & FD_DSR_PWRDOWN) {
baca51fa 1475 fdctrl_reset(fdctrl, 1);
8977f3c1 1476 }
b9b3d225 1477 fdctrl->dsr = value;
8977f3c1
FB		 1478}
1479
a758f8f4
HP		 1480/* Configuration control register: 0x07 (write) */
1481static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1482{
1483 /* Reset mode */
1484 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1485 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1486 return;
1487 }
1488 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1489
1490 /* Only the rate selection bits used in AT mode, and we
1491 * store those in the DSR.
1492 */
1493 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1494 (value & FD_DSR_DRATEMASK);
1495}
1496
5c02c033 1497static int fdctrl_media_changed(FDrive *drv)
ea185bbd 1498{
21fcf360 1499 return drv->media_changed;
ea185bbd
FB		 1500}
1501
8977f3c1 1502/* Digital input register : 0x07 (read-only) */
5c02c033 1503static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
8977f3c1 1504{
8977f3c1
FB		 1505 uint32_t retval = 0;
1506
a2df5fa3 1507 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
9fea808a 1508 retval |= FD_DIR_DSKCHG;
a2df5fa3 1509 }
3c83eb4f 1510 if (retval != 0) {
baca51fa 1511 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
3c83eb4f 1512 }
8977f3c1
FB		 1513
1514 return retval;
1515}
1516
07e415f2
KW		 1517/* Clear the FIFO and update the state for receiving the next command */
1518static void fdctrl_to_command_phase(FDCtrl *fdctrl)
8977f3c1 1519{
85d291a0 1520 fdctrl->phase = FD_PHASE_COMMAND;
baca51fa
FB		 1521 fdctrl->data_dir = FD_DIR_WRITE;
1522 fdctrl->data_pos = 0;
6cc8a11c 1523 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */
b9b3d225 1524 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
6cc8a11c 1525 fdctrl->msr |= FD_MSR_RQM;
8977f3c1
FB		 1526}
1527
83a26013
KW		 1528/* Update the state to allow the guest to read out the command status.
1529 * @fifo_len is the number of result bytes to be read out. */
1530static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
8977f3c1 1531{
85d291a0 1532 fdctrl->phase = FD_PHASE_RESULT;
baca51fa
FB		 1533 fdctrl->data_dir = FD_DIR_READ;
1534 fdctrl->data_len = fifo_len;
1535 fdctrl->data_pos = 0;
b9b3d225 1536 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
8977f3c1
FB		 1537}
1538
1539/* Set an error: unimplemented/unknown command */
5c02c033 1540static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
8977f3c1 1541{
cced7a13
BS		 1542 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1543 fdctrl->fifo[0]);
9fea808a 1544 fdctrl->fifo[0] = FD_SR0_INVCMD;
83a26013 1545 fdctrl_to_result_phase(fdctrl, 1);
8977f3c1
FB		 1546}
1547
6be01b1e
PH		 1548/* Seek to next sector
1549 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1550 * otherwise returns 1
1551 */
5c02c033 1552static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
746d6de7
BS		 1553{
1554 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1555 cur_drv->head, cur_drv->track, cur_drv->sect,
1556 fd_sector(cur_drv));
1557 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1558 error in fact */
6be01b1e
PH		 1559 uint8_t new_head = cur_drv->head;
1560 uint8_t new_track = cur_drv->track;
1561 uint8_t new_sect = cur_drv->sect;
1562
1563 int ret = 1;
1564
1565 if (new_sect >= cur_drv->last_sect ||
1566 new_sect == fdctrl->eot) {
1567 new_sect = 1;
746d6de7 1568 if (FD_MULTI_TRACK(fdctrl->data_state)) {
6be01b1e 1569 if (new_head == 0 &&
746d6de7 1570 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
6be01b1e 1571 new_head = 1;
746d6de7 1572 } else {
6be01b1e
PH		 1573 new_head = 0;
1574 new_track++;
c5139bd9 1575 fdctrl->status0 |= FD_SR0_SEEK;
6be01b1e
PH		 1576 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1577 ret = 0;
1578 }
746d6de7
BS		 1579 }
1580 } else {
c5139bd9 1581 fdctrl->status0 |= FD_SR0_SEEK;
6be01b1e
PH		 1582 new_track++;
1583 ret = 0;
1584 }
1585 if (ret == 1) {
1586 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1587 new_head, new_track, new_sect, fd_sector(cur_drv));
746d6de7 1588 }
746d6de7 1589 } else {
6be01b1e 1590 new_sect++;
746d6de7 1591 }
6be01b1e
PH		 1592 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1593 return ret;
746d6de7
BS		 1594}
1595
8977f3c1 1596/* Callback for transfer end (stop or abort) */
5c02c033
BS		 1597static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1598 uint8_t status1, uint8_t status2)
8977f3c1 1599{
5c02c033 1600 FDrive *cur_drv;
baca51fa 1601 cur_drv = get_cur_drv(fdctrl);
075f5532
HP		 1602
1603 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1604 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1605 if (cur_drv->head) {
1606 fdctrl->status0 |= FD_SR0_HEAD;
1607 }
1608 fdctrl->status0 |= status0;
2fee0088 1609
8977f3c1 1610 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
2fee0088
PH		 1611 status0, status1, status2, fdctrl->status0);
1612 fdctrl->fifo[0] = fdctrl->status0;
baca51fa
FB		 1613 fdctrl->fifo[1] = status1;
1614 fdctrl->fifo[2] = status2;
1615 fdctrl->fifo[3] = cur_drv->track;
1616 fdctrl->fifo[4] = cur_drv->head;
1617 fdctrl->fifo[5] = cur_drv->sect;
1618 fdctrl->fifo[6] = FD_SECTOR_SC;
1619 fdctrl->data_dir = FD_DIR_READ;
368df94d 1620 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
c8a35f1c
HP		 1621 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1622 k->release_DREQ(fdctrl->dma, fdctrl->dma_chann);
ed5fd2cc 1623 }
b9b3d225 1624 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
368df94d 1625 fdctrl->msr &= ~FD_MSR_NONDMA;
34abf9a7 1626
83a26013 1627 fdctrl_to_result_phase(fdctrl, 7);
d497d534 1628 fdctrl_raise_irq(fdctrl);
8977f3c1
FB		 1629}
1630
1631/* Prepare a data transfer (either DMA or FIFO) */
5c02c033 1632static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
8977f3c1 1633{
5c02c033 1634 FDrive *cur_drv;
8977f3c1 1635 uint8_t kh, kt, ks;
8977f3c1 1636
cefec4f5 1637 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB		 1638 cur_drv = get_cur_drv(fdctrl);
1639 kt = fdctrl->fifo[2];
1640 kh = fdctrl->fifo[3];
1641 ks = fdctrl->fifo[4];
4b19ec0c 1642 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
cefec4f5 1643 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP		 1644 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1645 NUM_SIDES(cur_drv)));
77370520 1646 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
8977f3c1
FB		 1647 case 2:
1648 /* sect too big */
9fea808a 1649 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1650 fdctrl->fifo[3] = kt;
1651 fdctrl->fifo[4] = kh;
1652 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1653 return;
1654 case 3:
1655 /* track too big */
77370520 1656 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB		 1657 fdctrl->fifo[3] = kt;
1658 fdctrl->fifo[4] = kh;
1659 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1660 return;
1661 case 4:
1662 /* No seek enabled */
9fea808a 1663 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1664 fdctrl->fifo[3] = kt;
1665 fdctrl->fifo[4] = kh;
1666 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1667 return;
1668 case 1:
d6ed4e21 1669 fdctrl->status0 |= FD_SR0_SEEK;
8977f3c1
FB		 1670 break;
1671 default:
1672 break;
1673 }
b9b3d225 1674
844f65d6
HP		 1675 /* Check the data rate. If the programmed data rate does not match
1676 * the currently inserted medium, the operation has to fail. */
1677 if (fdctrl->check_media_rate &&
1678 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1679 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1680 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1681 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1682 fdctrl->fifo[3] = kt;
1683 fdctrl->fifo[4] = kh;
1684 fdctrl->fifo[5] = ks;
1685 return;
1686 }
1687
8977f3c1 1688 /* Set the FIFO state */
baca51fa
FB		 1689 fdctrl->data_dir = direction;
1690 fdctrl->data_pos = 0;
27c86e24 1691 assert(fdctrl->msr & FD_MSR_CMDBUSY);
baca51fa
FB		 1692 if (fdctrl->fifo[0] & 0x80)
1693 fdctrl->data_state |= FD_STATE_MULTI;
1694 else
1695 fdctrl->data_state &= ~FD_STATE_MULTI;
c83f97b5 1696 if (fdctrl->fifo[5] == 0) {
baca51fa
FB		 1697 fdctrl->data_len = fdctrl->fifo[8];
1698 } else {
4f431960 1699 int tmp;
3bcb80f1 1700 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
771effeb 1701 tmp = (fdctrl->fifo[6] - ks + 1);
baca51fa 1702 if (fdctrl->fifo[0] & 0x80)
771effeb 1703 tmp += fdctrl->fifo[6];
4f431960 1704 fdctrl->data_len *= tmp;
baca51fa 1705 }
890fa6be 1706 fdctrl->eot = fdctrl->fifo[6];
368df94d 1707 if (fdctrl->dor & FD_DOR_DMAEN) {
c8a35f1c
HP		 1708 IsaDmaTransferMode dma_mode;
1709 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1710 bool dma_mode_ok;
8977f3c1 1711 /* DMA transfer are enabled. Check if DMA channel is well programmed */
c8a35f1c 1712 dma_mode = k->get_transfer_mode(fdctrl->dma, fdctrl->dma_chann);
baca51fa 1713 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
4f431960 1714 dma_mode, direction,
baca51fa 1715 (128 << fdctrl->fifo[5]) *
4f431960 1716 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
c8a35f1c
HP		 1717 switch (direction) {
1718 case FD_DIR_SCANE:
1719 case FD_DIR_SCANL:
1720 case FD_DIR_SCANH:
1721 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_VERIFY);
1722 break;
1723 case FD_DIR_WRITE:
1724 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_WRITE);
1725 break;
1726 case FD_DIR_READ:
1727 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_READ);
1728 break;
1729 case FD_DIR_VERIFY:
1730 dma_mode_ok = true;
1731 break;
1732 default:
1733 dma_mode_ok = false;
1734 break;
1735 }
1736 if (dma_mode_ok) {
8977f3c1 1737 /* No access is allowed until DMA transfer has completed */
b9b3d225 1738 fdctrl->msr &= ~FD_MSR_RQM;
7ea004ed
HP		 1739 if (direction != FD_DIR_VERIFY) {
1740 /* Now, we just have to wait for the DMA controller to
1741 * recall us...
1742 */
c8a35f1c
HP		 1743 k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann);
1744 k->schedule(fdctrl->dma);
7ea004ed
HP		 1745 } else {
1746 /* Start transfer */
1747 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1748 fdctrl->data_len);
1749 }
8977f3c1 1750 return;
baca51fa 1751 } else {
cced7a13
BS		 1752 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1753 direction);
8977f3c1
FB		 1754 }
1755 }
1756 FLOPPY_DPRINTF("start non-DMA transfer\n");
6cc8a11c 1757 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM;
b9b3d225
BS		 1758 if (direction != FD_DIR_WRITE)
1759 fdctrl->msr |= FD_MSR_DIO;
8977f3c1 1760 /* IO based transfer: calculate len */
d497d534 1761 fdctrl_raise_irq(fdctrl);
8977f3c1
FB		 1762}
1763
1764/* Prepare a transfer of deleted data */
5c02c033 1765static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
8977f3c1 1766{
cced7a13 1767 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
77370520 1768
8977f3c1
FB		 1769 /* We don't handle deleted data,
1770 * so we don't return *ANYTHING*
1771 */
9fea808a 1772 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
8977f3c1
FB		 1773}
1774
1775/* handlers for DMA transfers */
85571bc7
FB		 1776static int fdctrl_transfer_handler (void *opaque, int nchan,
1777 int dma_pos, int dma_len)
8977f3c1 1778{
5c02c033
BS		 1779 FDCtrl *fdctrl;
1780 FDrive *cur_drv;
baca51fa 1781 int len, start_pos, rel_pos;
8977f3c1 1782 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
c8a35f1c 1783 IsaDmaClass *k;
8977f3c1 1784
baca51fa 1785 fdctrl = opaque;
b9b3d225 1786 if (fdctrl->msr & FD_MSR_RQM) {
8977f3c1
FB		 1787 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1788 return 0;
1789 }
c8a35f1c 1790 k = ISADMA_GET_CLASS(fdctrl->dma);
baca51fa
FB		 1791 cur_drv = get_cur_drv(fdctrl);
1792 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1793 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1794 status2 = FD_SR2_SNS;
85571bc7
FB		 1795 if (dma_len > fdctrl->data_len)
1796 dma_len = fdctrl->data_len;
4be74634 1797 if (cur_drv->blk == NULL) {
4f431960 1798 if (fdctrl->data_dir == FD_DIR_WRITE)
9fea808a 1799 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
4f431960 1800 else
9fea808a 1801 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
4f431960 1802 len = 0;
890fa6be
FB		 1803 goto transfer_error;
1804 }
baca51fa 1805 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
85571bc7
FB		 1806 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1807 len = dma_len - fdctrl->data_pos;
baca51fa
FB		 1808 if (len + rel_pos > FD_SECTOR_LEN)
1809 len = FD_SECTOR_LEN - rel_pos;
6f7e9aec
FB		 1810 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1811 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
cefec4f5 1812 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
baca51fa 1813 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
9fea808a 1814 fd_sector(cur_drv) * FD_SECTOR_LEN);
baca51fa 1815 if (fdctrl->data_dir != FD_DIR_WRITE ||
4f431960 1816 len < FD_SECTOR_LEN || rel_pos != 0) {
baca51fa 1817 /* READ & SCAN commands and realign to a sector for WRITE */
a7a5b7c0
EB		 1818 if (blk_pread(cur_drv->blk, fd_offset(cur_drv),
1819 fdctrl->fifo, BDRV_SECTOR_SIZE) < 0) {
8977f3c1
FB		 1820 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1821 fd_sector(cur_drv));
1822 /* Sure, image size is too small... */
baca51fa 1823 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
8977f3c1 1824 }
890fa6be 1825 }
4f431960
JM		 1826 switch (fdctrl->data_dir) {
1827 case FD_DIR_READ:
1828 /* READ commands */
c8a35f1c
HP		 1829 k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1830 fdctrl->data_pos, len);
4f431960
JM		 1831 break;
1832 case FD_DIR_WRITE:
baca51fa 1833 /* WRITE commands */
8510854e
HP		 1834 if (cur_drv->ro) {
1835 /* Handle readonly medium early, no need to do DMA, touch the
1836 * LED or attempt any writes. A real floppy doesn't attempt
1837 * to write to readonly media either. */
1838 fdctrl_stop_transfer(fdctrl,
1839 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1840 0x00);
1841 goto transfer_error;
1842 }
1843
c8a35f1c
HP		 1844 k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1845 fdctrl->data_pos, len);
a7a5b7c0
EB		 1846 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv),
1847 fdctrl->fifo, BDRV_SECTOR_SIZE, 0) < 0) {
cced7a13
BS		 1848 FLOPPY_DPRINTF("error writing sector %d\n",
1849 fd_sector(cur_drv));
9fea808a 1850 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 1851 goto transfer_error;
890fa6be 1852 }
4f431960 1853 break;
7ea004ed
HP		 1854 case FD_DIR_VERIFY:
1855 /* VERIFY commands */
1856 break;
4f431960
JM		 1857 default:
1858 /* SCAN commands */
baca51fa 1859 {
4f431960 1860 uint8_t tmpbuf[FD_SECTOR_LEN];
baca51fa 1861 int ret;
c8a35f1c
HP		 1862 k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos,
1863 len);
baca51fa 1864 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
8977f3c1 1865 if (ret == 0) {
77370520 1866 status2 = FD_SR2_SEH;
8977f3c1
FB		 1867 goto end_transfer;
1868 }
baca51fa
FB		 1869 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1870 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
8977f3c1
FB		 1871 status2 = 0x00;
1872 goto end_transfer;
1873 }
1874 }
4f431960 1875 break;
8977f3c1 1876 }
4f431960
JM		 1877 fdctrl->data_pos += len;
1878 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
baca51fa 1879 if (rel_pos == 0) {
8977f3c1 1880 /* Seek to next sector */
746d6de7
BS		 1881 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1882 break;
8977f3c1
FB		 1883 }
1884 }
4f431960 1885 end_transfer:
baca51fa
FB		 1886 len = fdctrl->data_pos - start_pos;
1887 FLOPPY_DPRINTF("end transfer %d %d %d\n",
4f431960 1888 fdctrl->data_pos, len, fdctrl->data_len);
baca51fa
FB		 1889 if (fdctrl->data_dir == FD_DIR_SCANE ||
1890 fdctrl->data_dir == FD_DIR_SCANL ||
1891 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1892 status2 = FD_SR2_SEH;
baca51fa 1893 fdctrl->data_len -= len;
890fa6be 1894 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
4f431960 1895 transfer_error:
8977f3c1 1896
baca51fa 1897 return len;
8977f3c1
FB		 1898}
1899
8977f3c1 1900/* Data register : 0x05 */
5c02c033 1901static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
8977f3c1 1902{
5c02c033 1903 FDrive *cur_drv;
8977f3c1 1904 uint32_t retval = 0;
e9077462 1905 uint32_t pos;
8977f3c1 1906
baca51fa 1907 cur_drv = get_cur_drv(fdctrl);
b9b3d225
BS		 1908 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1909 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
cced7a13 1910 FLOPPY_DPRINTF("error: controller not ready for reading\n");
8977f3c1
FB		 1911 return 0;
1912 }
f6c2d1d8
KW		 1913
1914 /* If data_len spans multiple sectors, the current position in the FIFO
1915 * wraps around while fdctrl->data_pos is the real position in the whole
1916 * request. */
baca51fa 1917 pos = fdctrl->data_pos;
e9077462 1918 pos %= FD_SECTOR_LEN;
f6c2d1d8
KW		 1919
1920 switch (fdctrl->phase) {
1921 case FD_PHASE_EXECUTION:
1922 assert(fdctrl->msr & FD_MSR_NONDMA);
8977f3c1 1923 if (pos == 0) {
746d6de7
BS		 1924 if (fdctrl->data_pos != 0)
1925 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1926 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1927 fd_sector(cur_drv));
1928 return 0;
1929 }
a7a5b7c0
EB		 1930 if (blk_pread(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
1931 BDRV_SECTOR_SIZE)
4be74634 1932 < 0) {
77370520
BS		 1933 FLOPPY_DPRINTF("error getting sector %d\n",
1934 fd_sector(cur_drv));
1935 /* Sure, image size is too small... */
1936 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1937 }
8977f3c1 1938 }
f6c2d1d8
KW		 1939
1940 if (++fdctrl->data_pos == fdctrl->data_len) {
6cc8a11c 1941 fdctrl->msr &= ~FD_MSR_RQM;
c5139bd9 1942 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
f6c2d1d8
KW		 1943 }
1944 break;
1945
1946 case FD_PHASE_RESULT:
1947 assert(!(fdctrl->msr & FD_MSR_NONDMA));
1948 if (++fdctrl->data_pos == fdctrl->data_len) {
6cc8a11c 1949 fdctrl->msr &= ~FD_MSR_RQM;
07e415f2 1950 fdctrl_to_command_phase(fdctrl);
ed5fd2cc
FB		 1951 fdctrl_reset_irq(fdctrl);
1952 }
f6c2d1d8
KW		 1953 break;
1954
1955 case FD_PHASE_COMMAND:
1956 default:
1957 abort();
8977f3c1 1958 }
f6c2d1d8
KW		 1959
1960 retval = fdctrl->fifo[pos];
8977f3c1
FB		 1961 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1962
1963 return retval;
1964}
1965
5c02c033 1966static void fdctrl_format_sector(FDCtrl *fdctrl)
8977f3c1 1967{
5c02c033 1968 FDrive *cur_drv;
baca51fa 1969 uint8_t kh, kt, ks;
8977f3c1 1970
cefec4f5 1971 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB		 1972 cur_drv = get_cur_drv(fdctrl);
1973 kt = fdctrl->fifo[6];
1974 kh = fdctrl->fifo[7];
1975 ks = fdctrl->fifo[8];
1976 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
cefec4f5 1977 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP		 1978 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1979 NUM_SIDES(cur_drv)));
9fea808a 1980 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
baca51fa
FB		 1981 case 2:
1982 /* sect too big */
9fea808a 1983 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1984 fdctrl->fifo[3] = kt;
1985 fdctrl->fifo[4] = kh;
1986 fdctrl->fifo[5] = ks;
1987 return;
1988 case 3:
1989 /* track too big */
77370520 1990 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB		 1991 fdctrl->fifo[3] = kt;
1992 fdctrl->fifo[4] = kh;
1993 fdctrl->fifo[5] = ks;
1994 return;
1995 case 4:
1996 /* No seek enabled */
9fea808a 1997 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1998 fdctrl->fifo[3] = kt;
1999 fdctrl->fifo[4] = kh;
2000 fdctrl->fifo[5] = ks;
2001 return;
2002 case 1:
cd30b53d 2003 fdctrl->status0 |= FD_SR0_SEEK;
baca51fa
FB		 2004 break;
2005 default:
2006 break;
2007 }
2008 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
4be74634 2009 if (cur_drv->blk == NULL ||
a7a5b7c0
EB		 2010 blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
2011 BDRV_SECTOR_SIZE, 0) < 0) {
cced7a13 2012 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
9fea808a 2013 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 2014 } else {
4f431960
JM		 2015 if (cur_drv->sect == cur_drv->last_sect) {
2016 fdctrl->data_state &= ~FD_STATE_FORMAT;
2017 /* Last sector done */
cd30b53d 2018 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
4f431960
JM		 2019 } else {
2020 /* More to do */
2021 fdctrl->data_pos = 0;
2022 fdctrl->data_len = 4;
2023 }
baca51fa
FB		 2024 }
2025}
2026
5c02c033 2027static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
65cef780
BS		 2028{
2029 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
2030 fdctrl->fifo[0] = fdctrl->lock << 4;
83a26013 2031 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2032}
2033
5c02c033 2034static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
65cef780 2035{
5c02c033 2036 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2037
2038 /* Drives position */
2039 fdctrl->fifo[0] = drv0(fdctrl)->track;
2040 fdctrl->fifo[1] = drv1(fdctrl)->track;
78ae820c
BS		 2041#if MAX_FD == 4
2042 fdctrl->fifo[2] = drv2(fdctrl)->track;
2043 fdctrl->fifo[3] = drv3(fdctrl)->track;
2044#else
65cef780
BS		 2045 fdctrl->fifo[2] = 0;
2046 fdctrl->fifo[3] = 0;
78ae820c 2047#endif
65cef780
BS		 2048 /* timers */
2049 fdctrl->fifo[4] = fdctrl->timer0;
368df94d 2050 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
65cef780
BS		 2051 fdctrl->fifo[6] = cur_drv->last_sect;
2052 fdctrl->fifo[7] = (fdctrl->lock << 7) |
2053 (cur_drv->perpendicular << 2);
2054 fdctrl->fifo[8] = fdctrl->config;
2055 fdctrl->fifo[9] = fdctrl->precomp_trk;
83a26013 2056 fdctrl_to_result_phase(fdctrl, 10);
65cef780
BS		 2057}
2058
5c02c033 2059static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
65cef780
BS		 2060{
2061 /* Controller's version */
2062 fdctrl->fifo[0] = fdctrl->version;
83a26013 2063 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2064}
2065
5c02c033 2066static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
65cef780
BS		 2067{
2068 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
83a26013 2069 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2070}
2071
5c02c033 2072static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
65cef780 2073{
5c02c033 2074 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2075
2076 /* Drives position */
2077 drv0(fdctrl)->track = fdctrl->fifo[3];
2078 drv1(fdctrl)->track = fdctrl->fifo[4];
78ae820c
BS		 2079#if MAX_FD == 4
2080 drv2(fdctrl)->track = fdctrl->fifo[5];
2081 drv3(fdctrl)->track = fdctrl->fifo[6];
2082#endif
65cef780
BS		 2083 /* timers */
2084 fdctrl->timer0 = fdctrl->fifo[7];
2085 fdctrl->timer1 = fdctrl->fifo[8];
2086 cur_drv->last_sect = fdctrl->fifo[9];
2087 fdctrl->lock = fdctrl->fifo[10] >> 7;
2088 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
2089 fdctrl->config = fdctrl->fifo[11];
2090 fdctrl->precomp_trk = fdctrl->fifo[12];
2091 fdctrl->pwrd = fdctrl->fifo[13];
07e415f2 2092 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2093}
2094
5c02c033 2095static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
65cef780 2096{
5c02c033 2097 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2098
2099 fdctrl->fifo[0] = 0;
2100 fdctrl->fifo[1] = 0;
2101 /* Drives position */
2102 fdctrl->fifo[2] = drv0(fdctrl)->track;
2103 fdctrl->fifo[3] = drv1(fdctrl)->track;
78ae820c
BS		 2104#if MAX_FD == 4
2105 fdctrl->fifo[4] = drv2(fdctrl)->track;
2106 fdctrl->fifo[5] = drv3(fdctrl)->track;
2107#else
65cef780
BS		 2108 fdctrl->fifo[4] = 0;
2109 fdctrl->fifo[5] = 0;
78ae820c 2110#endif
65cef780
BS		 2111 /* timers */
2112 fdctrl->fifo[6] = fdctrl->timer0;
2113 fdctrl->fifo[7] = fdctrl->timer1;
2114 fdctrl->fifo[8] = cur_drv->last_sect;
2115 fdctrl->fifo[9] = (fdctrl->lock << 7) |
2116 (cur_drv->perpendicular << 2);
2117 fdctrl->fifo[10] = fdctrl->config;
2118 fdctrl->fifo[11] = fdctrl->precomp_trk;
2119 fdctrl->fifo[12] = fdctrl->pwrd;
2120 fdctrl->fifo[13] = 0;
2121 fdctrl->fifo[14] = 0;
83a26013 2122 fdctrl_to_result_phase(fdctrl, 15);
65cef780
BS		 2123}
2124
5c02c033 2125static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
65cef780 2126{
5c02c033 2127 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 2128
65cef780 2129 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
73bcb24d
RS		 2130 timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2131 (NANOSECONDS_PER_SECOND / 50));
65cef780
BS		 2132}
2133
5c02c033 2134static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
65cef780 2135{
5c02c033 2136 FDrive *cur_drv;
65cef780 2137
cefec4f5 2138 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 2139 cur_drv = get_cur_drv(fdctrl);
2140 fdctrl->data_state |= FD_STATE_FORMAT;
2141 if (fdctrl->fifo[0] & 0x80)
2142 fdctrl->data_state |= FD_STATE_MULTI;
2143 else
2144 fdctrl->data_state &= ~FD_STATE_MULTI;
65cef780
BS		 2145 cur_drv->bps =
2146 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
2147#if 0
2148 cur_drv->last_sect =
2149 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
2150 fdctrl->fifo[3] / 2;
2151#else
2152 cur_drv->last_sect = fdctrl->fifo[3];
2153#endif
2154 /* TODO: implement format using DMA expected by the Bochs BIOS
2155 * and Linux fdformat (read 3 bytes per sector via DMA and fill
2156 * the sector with the specified fill byte
2157 */
2158 fdctrl->data_state &= ~FD_STATE_FORMAT;
2159 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2160}
2161
5c02c033 2162static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
65cef780
BS		 2163{
2164 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
2165 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
368df94d
BS		 2166 if (fdctrl->fifo[2] & 1)
2167 fdctrl->dor &= ~FD_DOR_DMAEN;
2168 else
2169 fdctrl->dor |= FD_DOR_DMAEN;
65cef780 2170 /* No result back */
07e415f2 2171 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2172}
2173
5c02c033 2174static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
65cef780 2175{
5c02c033 2176 FDrive *cur_drv;
65cef780 2177
cefec4f5 2178 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 2179 cur_drv = get_cur_drv(fdctrl);
2180 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
2181 /* 1 Byte status back */
2182 fdctrl->fifo[0] = (cur_drv->ro << 6) |
2183 (cur_drv->track == 0 ? 0x10 : 0x00) |
2184 (cur_drv->head << 2) |
cefec4f5 2185 GET_CUR_DRV(fdctrl) |
65cef780 2186 0x28;
83a26013 2187 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2188}
2189
5c02c033 2190static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
65cef780 2191{
5c02c033 2192 FDrive *cur_drv;
65cef780 2193
cefec4f5 2194 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 2195 cur_drv = get_cur_drv(fdctrl);
2196 fd_recalibrate(cur_drv);
07e415f2 2197 fdctrl_to_command_phase(fdctrl);
65cef780 2198 /* Raise Interrupt */
d497d534
HP		 2199 fdctrl->status0 |= FD_SR0_SEEK;
2200 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2201}
2202
5c02c033 2203static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
65cef780 2204{
5c02c033 2205 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 2206
2fee0088 2207 if (fdctrl->reset_sensei > 0) {
f2d81b33
BS		 2208 fdctrl->fifo[0] =
2209 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
2210 fdctrl->reset_sensei--;
2fee0088
PH		 2211 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
2212 fdctrl->fifo[0] = FD_SR0_INVCMD;
83a26013 2213 fdctrl_to_result_phase(fdctrl, 1);
2fee0088 2214 return;
f2d81b33 2215 } else {
f2d81b33 2216 fdctrl->fifo[0] =
2fee0088
PH		 2217 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
2218 | GET_CUR_DRV(fdctrl);
f2d81b33
BS		 2219 }
2220
65cef780 2221 fdctrl->fifo[1] = cur_drv->track;
83a26013 2222 fdctrl_to_result_phase(fdctrl, 2);
65cef780 2223 fdctrl_reset_irq(fdctrl);
77370520 2224 fdctrl->status0 = FD_SR0_RDYCHG;
65cef780
BS		 2225}
2226
5c02c033 2227static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
65cef780 2228{
5c02c033 2229 FDrive *cur_drv;
65cef780 2230
cefec4f5 2231 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2232 cur_drv = get_cur_drv(fdctrl);
07e415f2 2233 fdctrl_to_command_phase(fdctrl);
b072a3c8
HP		 2234 /* The seek command just sends step pulses to the drive and doesn't care if
2235 * there is a medium inserted of if it's banging the head against the drive.
2236 */
6be01b1e 2237 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
b072a3c8 2238 /* Raise Interrupt */
d497d534
HP		 2239 fdctrl->status0 |= FD_SR0_SEEK;
2240 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2241}
2242
5c02c033 2243static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
65cef780 2244{
5c02c033 2245 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2246
2247 if (fdctrl->fifo[1] & 0x80)
2248 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
2249 /* No result back */
07e415f2 2250 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2251}
2252
5c02c033 2253static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
65cef780
BS		 2254{
2255 fdctrl->config = fdctrl->fifo[2];
2256 fdctrl->precomp_trk = fdctrl->fifo[3];
2257 /* No result back */
07e415f2 2258 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2259}
2260
5c02c033 2261static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
65cef780
BS		 2262{
2263 fdctrl->pwrd = fdctrl->fifo[1];
2264 fdctrl->fifo[0] = fdctrl->fifo[1];
83a26013 2265 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2266}
2267
5c02c033 2268static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
65cef780
BS		 2269{
2270 /* No result back */
07e415f2 2271 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2272}
2273
5c02c033 2274static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
65cef780 2275{
5c02c033 2276 FDrive *cur_drv = get_cur_drv(fdctrl);
e9077462 2277 uint32_t pos;
65cef780 2278
e9077462
PM		 2279 pos = fdctrl->data_pos - 1;
2280 pos %= FD_SECTOR_LEN;
2281 if (fdctrl->fifo[pos] & 0x80) {
65cef780 2282 /* Command parameters done */
e9077462 2283 if (fdctrl->fifo[pos] & 0x40) {
65cef780
BS		 2284 fdctrl->fifo[0] = fdctrl->fifo[1];
2285 fdctrl->fifo[2] = 0;
2286 fdctrl->fifo[3] = 0;
83a26013 2287 fdctrl_to_result_phase(fdctrl, 4);
65cef780 2288 } else {
07e415f2 2289 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2290 }
2291 } else if (fdctrl->data_len > 7) {
2292 /* ERROR */
2293 fdctrl->fifo[0] = 0x80 |
cefec4f5 2294 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
83a26013 2295 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2296 }
2297}
2298
6d013772 2299static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
65cef780 2300{
5c02c033 2301 FDrive *cur_drv;
65cef780 2302
cefec4f5 2303 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2304 cur_drv = get_cur_drv(fdctrl);
65cef780 2305 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
6be01b1e
PH		 2306 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
2307 cur_drv->sect, 1);
65cef780 2308 } else {
6d013772
PH		 2309 fd_seek(cur_drv, cur_drv->head,
2310 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
65cef780 2311 }
07e415f2 2312 fdctrl_to_command_phase(fdctrl);
77370520 2313 /* Raise Interrupt */
d497d534
HP		 2314 fdctrl->status0 |= FD_SR0_SEEK;
2315 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2316}
2317
6d013772 2318static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
65cef780 2319{
5c02c033 2320 FDrive *cur_drv;
65cef780 2321
cefec4f5 2322 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2323 cur_drv = get_cur_drv(fdctrl);
65cef780 2324 if (fdctrl->fifo[2] > cur_drv->track) {
6be01b1e 2325 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
65cef780 2326 } else {
6d013772
PH		 2327 fd_seek(cur_drv, cur_drv->head,
2328 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
65cef780 2329 }
07e415f2 2330 fdctrl_to_command_phase(fdctrl);
65cef780 2331 /* Raise Interrupt */
d497d534
HP		 2332 fdctrl->status0 |= FD_SR0_SEEK;
2333 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2334}
2335
85d291a0
KW		 2336/*
2337 * Handlers for the execution phase of each command
2338 */
d275b33d 2339typedef struct FDCtrlCommand {
678803ab
BS		 2340 uint8_t value;
2341 uint8_t mask;
2342 const char* name;
2343 int parameters;
5c02c033 2344 void (*handler)(FDCtrl *fdctrl, int direction);
678803ab 2345 int direction;
d275b33d
KW		 2346} FDCtrlCommand;
2347
2348static const FDCtrlCommand handlers[] = {
678803ab
BS		 2349 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
2350 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
2351 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
2352 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
2353 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
2354 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
2355 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
2356 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
2357 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
2358 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
2359 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
7ea004ed 2360 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
678803ab
BS		 2361 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
2362 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
2363 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
2364 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
2365 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
2366 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
2367 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
2368 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
2369 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
2370 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
2371 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
2372 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
2373 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
2374 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
2375 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
2376 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
2377 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
2378 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
2379 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
2380 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
2381};
2382/* Associate command to an index in the 'handlers' array */
2383static uint8_t command_to_handler[256];
2384
d275b33d
KW		 2385static const FDCtrlCommand *get_command(uint8_t cmd)
2386{
2387 int idx;
2388
2389 idx = command_to_handler[cmd];
2390 FLOPPY_DPRINTF("%s command\n", handlers[idx].name);
2391 return &handlers[idx];
2392}
2393
5c02c033 2394static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
baca51fa 2395{
5c02c033 2396 FDrive *cur_drv;
d275b33d 2397 const FDCtrlCommand *cmd;
e9077462 2398 uint32_t pos;
baca51fa 2399
8977f3c1 2400 /* Reset mode */
1c346df2 2401 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 2402 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB		 2403 return;
2404 }
b9b3d225 2405 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
cced7a13 2406 FLOPPY_DPRINTF("error: controller not ready for writing\n");
8977f3c1
FB		 2407 return;
2408 }
b9b3d225 2409 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
5b0a25e8 2410
d275b33d
KW		 2411 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2412
2413 /* If data_len spans multiple sectors, the current position in the FIFO
2414 * wraps around while fdctrl->data_pos is the real position in the whole
2415 * request. */
2416 pos = fdctrl->data_pos++;
2417 pos %= FD_SECTOR_LEN;
2418 fdctrl->fifo[pos] = value;
2419
6cc8a11c
KW		 2420 if (fdctrl->data_pos == fdctrl->data_len) {
2421 fdctrl->msr &= ~FD_MSR_RQM;
2422 }
2423
5b0a25e8
KW		 2424 switch (fdctrl->phase) {
2425 case FD_PHASE_EXECUTION:
2426 /* For DMA requests, RQM should be cleared during execution phase, so
2427 * we would have errored out above. */
2428 assert(fdctrl->msr & FD_MSR_NONDMA);
d275b33d 2429
8977f3c1 2430 /* FIFO data write */
b3bc1540 2431 if (pos == FD_SECTOR_LEN - 1 ||
baca51fa 2432 fdctrl->data_pos == fdctrl->data_len) {
77370520 2433 cur_drv = get_cur_drv(fdctrl);
a7a5b7c0
EB		 2434 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
2435 BDRV_SECTOR_SIZE, 0) < 0) {
cced7a13
BS		 2436 FLOPPY_DPRINTF("error writing sector %d\n",
2437 fd_sector(cur_drv));
5b0a25e8 2438 break;
77370520 2439 }
746d6de7
BS		 2440 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2441 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2442 fd_sector(cur_drv));
5b0a25e8 2443 break;
746d6de7 2444 }
8977f3c1 2445 }
d275b33d
KW		 2446
2447 /* Switch to result phase when done with the transfer */
2448 if (fdctrl->data_pos == fdctrl->data_len) {
c5139bd9 2449 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
d275b33d 2450 }
5b0a25e8 2451 break;
678803ab 2452
5b0a25e8
KW		 2453 case FD_PHASE_COMMAND:
2454 assert(!(fdctrl->msr & FD_MSR_NONDMA));
d275b33d 2455 assert(fdctrl->data_pos < FD_SECTOR_LEN);
5b0a25e8 2456
d275b33d
KW		 2457 if (pos == 0) {
2458 /* The first byte specifies the command. Now we start reading
2459 * as many parameters as this command requires. */
2460 cmd = get_command(value);
2461 fdctrl->data_len = cmd->parameters + 1;
6cc8a11c
KW		 2462 if (cmd->parameters) {
2463 fdctrl->msr |= FD_MSR_RQM;
2464 }
5b0a25e8 2465 fdctrl->msr |= FD_MSR_CMDBUSY;
8977f3c1 2466 }
65cef780 2467
5b0a25e8 2468 if (fdctrl->data_pos == fdctrl->data_len) {
d275b33d 2469 /* We have all parameters now, execute the command */
5b0a25e8 2470 fdctrl->phase = FD_PHASE_EXECUTION;
d275b33d 2471
5b0a25e8
KW		 2472 if (fdctrl->data_state & FD_STATE_FORMAT) {
2473 fdctrl_format_sector(fdctrl);
2474 break;
2475 }
2476
d275b33d
KW		 2477 cmd = get_command(fdctrl->fifo[0]);
2478 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name);
2479 cmd->handler(fdctrl, cmd->direction);
5b0a25e8
KW		 2480 }
2481 break;
2482
2483 case FD_PHASE_RESULT:
2484 default:
2485 abort();
8977f3c1
FB		 2486 }
2487}
ed5fd2cc
FB		 2488
2489static void fdctrl_result_timer(void *opaque)
2490{
5c02c033
BS		 2491 FDCtrl *fdctrl = opaque;
2492 FDrive *cur_drv = get_cur_drv(fdctrl);
4f431960 2493
b7ffa3b1
TS		 2494 /* Pretend we are spinning.
2495 * This is needed for Coherent, which uses READ ID to check for
2496 * sector interleaving.
2497 */
2498 if (cur_drv->last_sect != 0) {
2499 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2500 }
844f65d6
HP		 2501 /* READ_ID can't automatically succeed! */
2502 if (fdctrl->check_media_rate &&
2503 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2504 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2505 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2506 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2507 } else {
2508 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2509 }
ed5fd2cc 2510}
678803ab
BS		 2511
2512/* Init functions */
c0ca74f6
FZ		 2513static void fdctrl_connect_drives(FDCtrl *fdctrl, DeviceState *fdc_dev,
2514 Error **errp)
678803ab 2515{
12a71a02 2516 unsigned int i;
7d0d6950 2517 FDrive *drive;
394ea2ca 2518 DeviceState *dev;
a92bd191 2519 BlockBackend *blk;
394ea2ca 2520 Error *local_err = NULL;
678803ab 2521
678803ab 2522 for (i = 0; i < MAX_FD; i++) {
7d0d6950 2523 drive = &fdctrl->drives[i];
844f65d6 2524 drive->fdctrl = fdctrl;
7d0d6950 2525
394ea2ca
KW		 2526 /* If the drive is not present, we skip creating the qdev device, but
2527 * still have to initialise the controller. */
a92bd191
KW		 2528 blk = fdctrl->qdev_for_drives[i].blk;
2529 if (!blk) {
394ea2ca
KW		 2530 fd_init(drive);
2531 fd_revalidate(drive);
2532 continue;
b47b3525
MA		 2533 }
2534
394ea2ca
KW		 2535 dev = qdev_create(&fdctrl->bus.bus, "floppy");
2536 qdev_prop_set_uint32(dev, "unit", i);
a92bd191
KW		 2537 qdev_prop_set_enum(dev, "drive-type", fdctrl->qdev_for_drives[i].type);
2538
2539 blk_ref(blk);
2540 blk_detach_dev(blk, fdc_dev);
2541 fdctrl->qdev_for_drives[i].blk = NULL;
2542 qdev_prop_set_drive(dev, "drive", blk, &local_err);
2543 blk_unref(blk);
2544
2545 if (local_err) {
2546 error_propagate(errp, local_err);
2547 return;
2548 }
2549
394ea2ca
KW		 2550 object_property_set_bool(OBJECT(dev), true, "realized", &local_err);
2551 if (local_err) {
2552 error_propagate(errp, local_err);
2553 return;
7d0d6950 2554 }
678803ab 2555 }
678803ab
BS		 2556}
2557
dfc65f1f
MA		 2558ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2559{
4a17cc4f
AF		 2560 DeviceState *dev;
2561 ISADevice *isadev;
dfc65f1f 2562
4a17cc4f
AF		 2563 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2564 if (!isadev) {
dfc65f1f
MA		 2565 return NULL;
2566 }
4a17cc4f 2567 dev = DEVICE(isadev);
dfc65f1f
MA		 2568
2569 if (fds[0]) {
6231a6da
MA		 2570 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2571 &error_fatal);
dfc65f1f
MA		 2572 }
2573 if (fds[1]) {
6231a6da
MA		 2574 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2575 &error_fatal);
dfc65f1f 2576 }
4a17cc4f 2577 qdev_init_nofail(dev);
dfc65f1f 2578
4a17cc4f 2579 return isadev;
dfc65f1f
MA		 2580}
2581
63ffb564 2582void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
a8170e5e 2583 hwaddr mmio_base, DriveInfo **fds)
2091ba23 2584{
5c02c033 2585 FDCtrl *fdctrl;
2091ba23 2586 DeviceState *dev;
dd3be742 2587 SysBusDevice *sbd;
5c02c033 2588 FDCtrlSysBus *sys;
2091ba23 2589
19d46d71 2590 dev = qdev_create(NULL, "sysbus-fdc");
dd3be742 2591 sys = SYSBUS_FDC(dev);
99244fa1
GH		 2592 fdctrl = &sys->state;
2593 fdctrl->dma_chann = dma_chann; /* FIXME */
995bf0ca 2594 if (fds[0]) {
6231a6da
MA		 2595 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2596 &error_fatal);
995bf0ca
GH		 2597 }
2598 if (fds[1]) {
6231a6da
MA		 2599 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2600 &error_fatal);
995bf0ca 2601 }
e23a1b33 2602 qdev_init_nofail(dev);
dd3be742
HT		 2603 sbd = SYS_BUS_DEVICE(dev);
2604 sysbus_connect_irq(sbd, 0, irq);
2605 sysbus_mmio_map(sbd, 0, mmio_base);
678803ab
BS		 2606}
2607
a8170e5e 2608void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
63ffb564 2609 DriveInfo **fds, qemu_irq *fdc_tc)
678803ab 2610{
f64ab228 2611 DeviceState *dev;
5c02c033 2612 FDCtrlSysBus *sys;
678803ab 2613
12a71a02 2614 dev = qdev_create(NULL, "SUNW,fdtwo");
995bf0ca 2615 if (fds[0]) {
6231a6da
MA		 2616 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]),
2617 &error_fatal);
995bf0ca 2618 }
e23a1b33 2619 qdev_init_nofail(dev);
dd3be742
HT		 2620 sys = SYSBUS_FDC(dev);
2621 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2622 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
f64ab228 2623 *fdc_tc = qdev_get_gpio_in(dev, 0);
678803ab 2624}
f64ab228 2625
51e6e90e
KW		 2626static void fdctrl_realize_common(DeviceState *dev, FDCtrl *fdctrl,
2627 Error **errp)
f64ab228 2628{
12a71a02
BS		 2629 int i, j;
2630 static int command_tables_inited = 0;
f64ab228 2631
a73275dd
JS		 2632 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) {
2633 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'");
2634 }
2635
12a71a02
BS		 2636 /* Fill 'command_to_handler' lookup table */
2637 if (!command_tables_inited) {
2638 command_tables_inited = 1;
2639 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2640 for (j = 0; j < sizeof(command_to_handler); j++) {
2641 if ((j & handlers[i].mask) == handlers[i].value) {
2642 command_to_handler[j] = i;
2643 }
2644 }
2645 }
2646 }
2647
2648 FLOPPY_DPRINTF("init controller\n");
2649 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
d7a6c270 2650 fdctrl->fifo_size = 512;
bc72ad67 2651 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
a3ef7a61 2652 fdctrl_result_timer, fdctrl);
12a71a02
BS		 2653
2654 fdctrl->version = 0x90; /* Intel 82078 controller */
2655 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
d7a6c270 2656 fdctrl->num_floppies = MAX_FD;
12a71a02 2657
a3ef7a61 2658 if (fdctrl->dma_chann != -1) {
c8a35f1c
HP		 2659 IsaDmaClass *k;
2660 assert(fdctrl->dma);
2661 k = ISADMA_GET_CLASS(fdctrl->dma);
2662 k->register_channel(fdctrl->dma, fdctrl->dma_chann,
2663 &fdctrl_transfer_handler, fdctrl);
a3ef7a61 2664 }
51e6e90e
KW		 2665
2666 floppy_bus_create(fdctrl, &fdctrl->bus, dev);
c0ca74f6 2667 fdctrl_connect_drives(fdctrl, dev, errp);
f64ab228
BS		 2668}
2669
212ec7ba 2670static const MemoryRegionPortio fdc_portio_list[] = {
2f290a8c 2671 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
212ec7ba
RH		 2672 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2673 PORTIO_END_OF_LIST(),
2f290a8c
RH		 2674};
2675
db895a1e 2676static void isabus_fdc_realize(DeviceState *dev, Error **errp)
8baf73ad 2677{
db895a1e 2678 ISADevice *isadev = ISA_DEVICE(dev);
020c8e76 2679 FDCtrlISABus *isa = ISA_FDC(dev);
5c02c033 2680 FDCtrl *fdctrl = &isa->state;
a3ef7a61 2681 Error *err = NULL;
8baf73ad 2682
e305a165
MAL		 2683 isa_register_portio_list(isadev, &fdctrl->portio_list,
2684 isa->iobase, fdc_portio_list, fdctrl,
db895a1e 2685 "fdc");
dee41d58 2686
db895a1e 2687 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
c9ae703d 2688 fdctrl->dma_chann = isa->dma;
c8a35f1c
HP		 2689 if (fdctrl->dma_chann != -1) {
2690 fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma);
b3da5513
AK		 2691 if (!fdctrl->dma) {
2692 error_setg(errp, "ISA controller does not support DMA");
2693 return;
2694 }
c8a35f1c 2695 }
8baf73ad 2696
db895a1e 2697 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
51e6e90e 2698 fdctrl_realize_common(dev, fdctrl, &err);
a3ef7a61
AF		 2699 if (err != NULL) {
2700 error_propagate(errp, err);
db895a1e
AF		 2701 return;
2702 }
8baf73ad
GH		 2703}
2704
940194c2 2705static void sysbus_fdc_initfn(Object *obj)
12a71a02 2706{
19d46d71 2707 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
940194c2 2708 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
5c02c033 2709 FDCtrl *fdctrl = &sys->state;
12a71a02 2710
19d46d71
AF		 2711 fdctrl->dma_chann = -1;
2712
940194c2 2713 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2d256e6f 2714 "fdc", 0x08);
19d46d71 2715 sysbus_init_mmio(sbd, &fdctrl->iomem);
940194c2
HT		 2716}
2717
19d46d71 2718static void sun4m_fdc_initfn(Object *obj)
940194c2 2719{
19d46d71
AF		 2720 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2721 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
940194c2 2722 FDCtrl *fdctrl = &sys->state;
940194c2 2723
dd446051
HP		 2724 fdctrl->dma_chann = -1;
2725
19d46d71
AF		 2726 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2727 fdctrl, "fdctrl", 0x08);
2728 sysbus_init_mmio(sbd, &fdctrl->iomem);
940194c2 2729}
2be37833 2730
19d46d71 2731static void sysbus_fdc_common_initfn(Object *obj)
940194c2 2732{
19d46d71
AF		 2733 DeviceState *dev = DEVICE(obj);
2734 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
940194c2
HT		 2735 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2736 FDCtrl *fdctrl = &sys->state;
2737
19d46d71
AF		 2738 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2739
2740 sysbus_init_irq(sbd, &fdctrl->irq);
2741 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
12a71a02
BS		 2742}
2743
19d46d71 2744static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
12a71a02 2745{
dd3be742
HT		 2746 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2747 FDCtrl *fdctrl = &sys->state;
12a71a02 2748
51e6e90e 2749 fdctrl_realize_common(dev, fdctrl, errp);
12a71a02 2750}
f64ab228 2751
2da44dd0 2752FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
34d4260e 2753{
020c8e76 2754 FDCtrlISABus *isa = ISA_FDC(fdc);
34d4260e 2755
61a8d649 2756 return isa->state.drives[i].drive;
34d4260e
KW		 2757}
2758
e08fde0c
RK		 2759void isa_fdc_get_drive_max_chs(FloppyDriveType type,
2760 uint8_t *maxc, uint8_t *maxh, uint8_t *maxs)
2761{
2762 const FDFormat *fdf;
2763
2764 *maxc = *maxh = *maxs = 0;
2765 for (fdf = fd_formats; fdf->drive != FLOPPY_DRIVE_TYPE_NONE; fdf++) {
2766 if (fdf->drive != type) {
2767 continue;
2768 }
2769 if (*maxc < fdf->max_track) {
2770 *maxc = fdf->max_track;
2771 }
2772 if (*maxh < fdf->max_head) {
2773 *maxh = fdf->max_head;
2774 }
2775 if (*maxs < fdf->last_sect) {
2776 *maxs = fdf->last_sect;
2777 }
2778 }
2779 (*maxc)--;
2780}
2781
a64405d1
JK		 2782static const VMStateDescription vmstate_isa_fdc ={
2783 .name = "fdc",
2784 .version_id = 2,
2785 .minimum_version_id = 2,
d49805ae 2786 .fields = (VMStateField[]) {
a64405d1
JK		 2787 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2788 VMSTATE_END_OF_LIST()
2789 }
2790};
2791
39bffca2 2792static Property isa_fdc_properties[] = {
c7bcc85d 2793 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
c9ae703d
HP		 2794 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2795 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
a92bd191
KW		 2796 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.qdev_for_drives[0].blk),
2797 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.qdev_for_drives[1].blk),
09c6d585
HP		 2798 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2799 0, true),
85bbd1e7 2800 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlISABus, state.qdev_for_drives[0].type,
fff4687b
JS		 2801 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2802 FloppyDriveType),
85bbd1e7 2803 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlISABus, state.qdev_for_drives[1].type,
fff4687b
JS		 2804 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2805 FloppyDriveType),
85bbd1e7 2806 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
4812fa27 2807 FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type,
a73275dd 2808 FloppyDriveType),
39bffca2
AL		 2809 DEFINE_PROP_END_OF_LIST(),
2810};
2811
020c8e76 2812static void isabus_fdc_class_init(ObjectClass *klass, void *data)
8f04ee08 2813{
39bffca2 2814 DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e
AF		 2815
2816 dc->realize = isabus_fdc_realize;
39bffca2 2817 dc->fw_name = "fdc";
39bffca2
AL		 2818 dc->reset = fdctrl_external_reset_isa;
2819 dc->vmsd = &vmstate_isa_fdc;
2820 dc->props = isa_fdc_properties;
125ee0ed 2821 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
39bffca2
AL		 2822}
2823
81782b6a
GA		 2824static void isabus_fdc_instance_init(Object *obj)
2825{
2826 FDCtrlISABus *isa = ISA_FDC(obj);
2827
2828 device_add_bootindex_property(obj, &isa->bootindexA,
2829 "bootindexA", "/floppy@0",
2830 DEVICE(obj), NULL);
2831 device_add_bootindex_property(obj, &isa->bootindexB,
2832 "bootindexB", "/floppy@1",
2833 DEVICE(obj), NULL);
2834}
2835
8c43a6f0 2836static const TypeInfo isa_fdc_info = {
020c8e76 2837 .name = TYPE_ISA_FDC,
39bffca2
AL		 2838 .parent = TYPE_ISA_DEVICE,
2839 .instance_size = sizeof(FDCtrlISABus),
020c8e76 2840 .class_init = isabus_fdc_class_init,
81782b6a 2841 .instance_init = isabus_fdc_instance_init,
8baf73ad
GH		 2842};
2843
a64405d1
JK		 2844static const VMStateDescription vmstate_sysbus_fdc ={
2845 .name = "fdc",
2846 .version_id = 2,
2847 .minimum_version_id = 2,
d49805ae 2848 .fields = (VMStateField[]) {
a64405d1
JK		 2849 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2850 VMSTATE_END_OF_LIST()
2851 }
2852};
2853
999e12bb 2854static Property sysbus_fdc_properties[] = {
a92bd191
KW		 2855 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.qdev_for_drives[0].blk),
2856 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.qdev_for_drives[1].blk),
85bbd1e7 2857 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlSysBus, state.qdev_for_drives[0].type,
fff4687b
JS		 2858 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2859 FloppyDriveType),
85bbd1e7 2860 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlSysBus, state.qdev_for_drives[1].type,
fff4687b
JS		 2861 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2862 FloppyDriveType),
85bbd1e7 2863 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
a73275dd
JS		 2864 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2865 FloppyDriveType),
999e12bb 2866 DEFINE_PROP_END_OF_LIST(),
12a71a02
BS		 2867};
2868
999e12bb
AL		 2869static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2870{
39bffca2 2871 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 2872
39bffca2 2873 dc->props = sysbus_fdc_properties;
125ee0ed 2874 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
999e12bb
AL		 2875}
2876
8c43a6f0 2877static const TypeInfo sysbus_fdc_info = {
19d46d71
AF		 2878 .name = "sysbus-fdc",
2879 .parent = TYPE_SYSBUS_FDC,
940194c2 2880 .instance_init = sysbus_fdc_initfn,
39bffca2 2881 .class_init = sysbus_fdc_class_init,
999e12bb
AL		 2882};
2883
2884static Property sun4m_fdc_properties[] = {
a92bd191 2885 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.qdev_for_drives[0].blk),
85bbd1e7 2886 DEFINE_PROP_SIGNED("fdtype", FDCtrlSysBus, state.qdev_for_drives[0].type,
fff4687b
JS		 2887 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2888 FloppyDriveType),
85bbd1e7 2889 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
a73275dd
JS		 2890 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2891 FloppyDriveType),
999e12bb
AL		 2892 DEFINE_PROP_END_OF_LIST(),
2893};
2894
2895static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2896{
39bffca2 2897 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 2898
39bffca2 2899 dc->props = sun4m_fdc_properties;
125ee0ed 2900 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
999e12bb
AL		 2901}
2902
8c43a6f0 2903static const TypeInfo sun4m_fdc_info = {
39bffca2 2904 .name = "SUNW,fdtwo",
19d46d71 2905 .parent = TYPE_SYSBUS_FDC,
940194c2 2906 .instance_init = sun4m_fdc_initfn,
39bffca2 2907 .class_init = sun4m_fdc_class_init,
f64ab228
BS		 2908};
2909
19d46d71
AF		 2910static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
2911{
2912 DeviceClass *dc = DEVICE_CLASS(klass);
2913
2914 dc->realize = sysbus_fdc_common_realize;
2915 dc->reset = fdctrl_external_reset_sysbus;
2916 dc->vmsd = &vmstate_sysbus_fdc;
2917}
2918
2919static const TypeInfo sysbus_fdc_type_info = {
2920 .name = TYPE_SYSBUS_FDC,
2921 .parent = TYPE_SYS_BUS_DEVICE,
2922 .instance_size = sizeof(FDCtrlSysBus),
2923 .instance_init = sysbus_fdc_common_initfn,
2924 .abstract = true,
2925 .class_init = sysbus_fdc_common_class_init,
2926};
2927
83f7d43a 2928static void fdc_register_types(void)
f64ab228 2929{
39bffca2 2930 type_register_static(&isa_fdc_info);
19d46d71 2931 type_register_static(&sysbus_fdc_type_info);
39bffca2
AL		 2932 type_register_static(&sysbus_fdc_info);
2933 type_register_static(&sun4m_fdc_info);
51e6e90e 2934 type_register_static(&floppy_bus_info);
394ea2ca 2935 type_register_static(&floppy_drive_info);
f64ab228
BS		 2936}
2937
83f7d43a 2938type_init(fdc_register_types)
Empty description
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