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pci: mark device having guest unplug request pending
[qemu.git] / hw / pci / pci.c
CommitLineData
69b91039
FB		 1/*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5fafdf24 5 *
69b91039
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
e688df6b 24
97d5408f 25#include "qemu/osdep.h"
a8d25326 26#include "qemu-common.h"
64552b6b 27#include "hw/irq.h"
c759b24f
MT		 28#include "hw/pci/pci.h"
29#include "hw/pci/pci_bridge.h"
06aac7bd 30#include "hw/pci/pci_bus.h"
568f0690 31#include "hw/pci/pci_host.h"
a27bd6c7 32#include "hw/qdev-properties.h"
ca77ee28 33#include "migration/qemu-file-types.h"
d6454270 34#include "migration/vmstate.h"
83c9089e 35#include "monitor/monitor.h"
1422e32d 36#include "net/net.h"
b58c5c2d 37#include "sysemu/numa.h"
46517dd4 38#include "sysemu/sysemu.h"
c759b24f 39#include "hw/loader.h"
d49b6836 40#include "qemu/error-report.h"
1de7afc9 41#include "qemu/range.h"
7828d750 42#include "trace.h"
c759b24f
MT		 43#include "hw/pci/msi.h"
44#include "hw/pci/msix.h"
022c62cb 45#include "exec/address-spaces.h"
5e954943 46#include "hw/hotplug.h"
e4024630 47#include "hw/boards.h"
e688df6b 48#include "qapi/error.h"
112ed241 49#include "qapi/qapi-commands-misc.h"
f348b6d1 50#include "qemu/cutils.h"
69b91039
FB		 51
52//#define DEBUG_PCI
d8d2e079 53#ifdef DEBUG_PCI
2e49d64a 54# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
d8d2e079
IY		 55#else
56# define PCI_DPRINTF(format, ...) do { } while (0)
57#endif
69b91039 58
88c725c7
CH		 59bool pci_available = true;
60
10c4c98a 61static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
4f43c1ff 62static char *pcibus_get_dev_path(DeviceState *dev);
5e0259e7 63static char *pcibus_get_fw_dev_path(DeviceState *dev);
dcc20931 64static void pcibus_reset(BusState *qbus);
10c4c98a 65
3cb75a7c
PB		 66static Property pci_props[] = {
67 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
68 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
69 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
70 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
71 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
72 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
73 QEMU_PCI_CAP_SERR_BITNR, true),
6b449540
MT		 74 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
75 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),
f03d8ea3
MA		 76 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
77 QEMU_PCIE_EXTCAP_INIT_BITNR, true),
4f5b6a05
JF		 78 DEFINE_PROP_STRING("failover_pair_id", PCIDevice,
79 failover_pair_id),
3cb75a7c
PB		 80 DEFINE_PROP_END_OF_LIST()
81};
82
d2f69df7
BD		 83static const VMStateDescription vmstate_pcibus = {
84 .name = "PCIBUS",
85 .version_id = 1,
86 .minimum_version_id = 1,
d49805ae 87 .fields = (VMStateField[]) {
d2164ad3 88 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL),
d2f69df7
BD		 89 VMSTATE_VARRAY_INT32(irq_count, PCIBus,
90 nirq, 0, vmstate_info_int32,
91 int32_t),
92 VMSTATE_END_OF_LIST()
93 }
94};
95
b86eacb8
MA		 96static void pci_init_bus_master(PCIDevice *pci_dev)
97{
98 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev);
99
100 memory_region_init_alias(&pci_dev->bus_master_enable_region,
101 OBJECT(pci_dev), "bus master",
102 dma_as->root, 0, memory_region_size(dma_as->root));
103 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
3716d590
JW		 104 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0,
105 &pci_dev->bus_master_enable_region);
b86eacb8
MA		 106}
107
108static void pcibus_machine_done(Notifier *notifier, void *data)
109{
110 PCIBus *bus = container_of(notifier, PCIBus, machine_done);
111 int i;
112
113 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
114 if (bus->devices[i]) {
115 pci_init_bus_master(bus->devices[i]);
116 }
117 }
118}
119
d2f69df7
BD		 120static void pci_bus_realize(BusState *qbus, Error **errp)
121{
122 PCIBus *bus = PCI_BUS(qbus);
123
b86eacb8
MA		 124 bus->machine_done.notify = pcibus_machine_done;
125 qemu_add_machine_init_done_notifier(&bus->machine_done);
126
d2f69df7
BD		 127 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
128}
129
2f57db8a
DG		 130static void pcie_bus_realize(BusState *qbus, Error **errp)
131{
132 PCIBus *bus = PCI_BUS(qbus);
133
134 pci_bus_realize(qbus, errp);
135
136 /*
137 * A PCI-E bus can support extended config space if it's the root
138 * bus, or if the bus/bridge above it does as well
139 */
140 if (pci_bus_is_root(bus)) {
141 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
142 } else {
143 PCIBus *parent_bus = pci_get_bus(bus->parent_dev);
144
145 if (pci_bus_allows_extended_config_space(parent_bus)) {
146 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
147 }
148 }
149}
150
d2f69df7
BD		 151static void pci_bus_unrealize(BusState *qbus, Error **errp)
152{
153 PCIBus *bus = PCI_BUS(qbus);
154
b86eacb8
MA		 155 qemu_remove_machine_init_done_notifier(&bus->machine_done);
156
d2f69df7
BD		 157 vmstate_unregister(NULL, &vmstate_pcibus, bus);
158}
159
602141d9
MA		 160static int pcibus_num(PCIBus *bus)
161{
b0e5196a 162 if (pci_bus_is_root(bus)) {
602141d9
MA		 163 return 0; /* pci host bridge */
164 }
165 return bus->parent_dev->config[PCI_SECONDARY_BUS];
166}
167
6a3042b2
MA		 168static uint16_t pcibus_numa_node(PCIBus *bus)
169{
170 return NUMA_NODE_UNASSIGNED;
171}
172
0d936928
AL		 173static void pci_bus_class_init(ObjectClass *klass, void *data)
174{
175 BusClass *k = BUS_CLASS(klass);
ce6a28ee 176 PCIBusClass *pbc = PCI_BUS_CLASS(klass);
0d936928
AL		 177
178 k->print_dev = pcibus_dev_print;
179 k->get_dev_path = pcibus_get_dev_path;
180 k->get_fw_dev_path = pcibus_get_fw_dev_path;
d2f69df7
BD		 181 k->realize = pci_bus_realize;
182 k->unrealize = pci_bus_unrealize;
0d936928 183 k->reset = pcibus_reset;
ce6a28ee 184
602141d9 185 pbc->bus_num = pcibus_num;
6a3042b2 186 pbc->numa_node = pcibus_numa_node;
0d936928
AL		 187}
188
189static const TypeInfo pci_bus_info = {
190 .name = TYPE_PCI_BUS,
191 .parent = TYPE_BUS,
192 .instance_size = sizeof(PCIBus),
ce6a28ee 193 .class_size = sizeof(PCIBusClass),
0d936928 194 .class_init = pci_bus_class_init,
30468f78 195};
69b91039 196
619f02ae
EH		 197static const TypeInfo pcie_interface_info = {
198 .name = INTERFACE_PCIE_DEVICE,
199 .parent = TYPE_INTERFACE,
200};
201
202static const TypeInfo conventional_pci_interface_info = {
203 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE,
204 .parent = TYPE_INTERFACE,
205};
206
1c685a90
GK		 207static void pcie_bus_class_init(ObjectClass *klass, void *data)
208{
2f57db8a 209 BusClass *k = BUS_CLASS(klass);
1c685a90 210
2f57db8a 211 k->realize = pcie_bus_realize;
1c685a90
GK		 212}
213
3a861c46
AW		 214static const TypeInfo pcie_bus_info = {
215 .name = TYPE_PCIE_BUS,
216 .parent = TYPE_PCI_BUS,
1c685a90 217 .class_init = pcie_bus_class_init,
3a861c46
AW		 218};
219
d662210a 220static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
1941d19c 221static void pci_update_mappings(PCIDevice *d);
d98f08f5 222static void pci_irq_handler(void *opaque, int irq_num, int level);
133e9b22 223static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
230741dc 224static void pci_del_option_rom(PCIDevice *pdev);
1941d19c 225
d350d97d
AL		 226static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
227static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
e822a52a 228
7588e2b0 229static QLIST_HEAD(, PCIHostState) pci_host_bridges;
30468f78 230
cf8c704d 231int pci_bar(PCIDevice *d, int reg)
5330de09 232{
b3b11697
IY		 233 uint8_t type;
234
235 if (reg != PCI_ROM_SLOT)
236 return PCI_BASE_ADDRESS_0 + reg * 4;
237
238 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
239 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
5330de09
MT		 240}
241
d036bb21
MT		 242static inline int pci_irq_state(PCIDevice *d, int irq_num)
243{
7d37435b 244 return (d->irq_state >> irq_num) & 0x1;
d036bb21
MT		 245}
246
247static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
248{
7d37435b
PB		 249 d->irq_state &= ~(0x1 << irq_num);
250 d->irq_state |= level << irq_num;
d036bb21
MT		 251}
252
253static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
254{
255 PCIBus *bus;
256 for (;;) {
fd56e061 257 bus = pci_get_bus(pci_dev);
d036bb21
MT		 258 irq_num = bus->map_irq(pci_dev, irq_num);
259 if (bus->set_irq)
260 break;
261 pci_dev = bus->parent_dev;
262 }
263 bus->irq_count[irq_num] += change;
264 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
265}
266
9ddf8437
IY		 267int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
268{
269 assert(irq_num >= 0);
270 assert(irq_num < bus->nirq);
271 return !!bus->irq_count[irq_num];
272}
273
f9bf77dd
MT		 274/* Update interrupt status bit in config space on interrupt
275 * state change. */
276static void pci_update_irq_status(PCIDevice *dev)
277{
278 if (dev->irq_state) {
279 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
280 } else {
281 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
282 }
283}
284
4c92325b
IY		 285void pci_device_deassert_intx(PCIDevice *dev)
286{
287 int i;
288 for (i = 0; i < PCI_NUM_PINS; ++i) {
d98f08f5 289 pci_irq_handler(dev, i, 0);
4c92325b
IY		 290 }
291}
292
dcc20931 293static void pci_do_device_reset(PCIDevice *dev)
5330de09 294{
c0b1905b 295 int r;
6fc4925b 296
4c92325b 297 pci_device_deassert_intx(dev);
58b59014
CR		 298 assert(dev->irq_state == 0);
299
ebabb67a 300 /* Clear all writable bits */
99443c21 301 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
f9aebe2e
MT		 302 pci_get_word(dev->wmask + PCI_COMMAND) |
303 pci_get_word(dev->w1cmask + PCI_COMMAND));
89d437df
IY		 304 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
305 pci_get_word(dev->wmask + PCI_STATUS) |
306 pci_get_word(dev->w1cmask + PCI_STATUS));
c0b1905b
MT		 307 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
308 dev->config[PCI_INTERRUPT_LINE] = 0x0;
309 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
71ebd6dc
IY		 310 PCIIORegion *region = &dev->io_regions[r];
311 if (!region->size) {
c0b1905b
MT		 312 continue;
313 }
71ebd6dc
IY		 314
315 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
316 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
317 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
318 } else {
319 pci_set_long(dev->config + pci_bar(dev, r), region->type);
320 }
c0b1905b
MT		 321 }
322 pci_update_mappings(dev);
cbd2d434
JK		 323
324 msi_reset(dev);
325 msix_reset(dev);
5330de09
MT		 326}
327
dcc20931
PB		 328/*
329 * This function is called on #RST and FLR.
330 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
331 */
332void pci_device_reset(PCIDevice *dev)
333{
334 qdev_reset_all(&dev->qdev);
335 pci_do_device_reset(dev);
336}
337
9bb33586
IY		 338/*
339 * Trigger pci bus reset under a given bus.
dcc20931
PB		 340 * Called via qbus_reset_all on RST# assert, after the devices
341 * have been reset qdev_reset_all-ed already.
9bb33586 342 */
dcc20931 343static void pcibus_reset(BusState *qbus)
6eaa6847 344{
81e3e75b 345 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
6eaa6847
GN		 346 int i;
347
5330de09
MT		 348 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
349 if (bus->devices[i]) {
dcc20931 350 pci_do_device_reset(bus->devices[i]);
5330de09 351 }
6eaa6847 352 }
9bb33586 353
9bdbbfc3
PB		 354 for (i = 0; i < bus->nirq; i++) {
355 assert(bus->irq_count[i] == 0);
356 }
9bb33586
IY		 357}
358
3dbc01ae 359static void pci_host_bus_register(DeviceState *host)
e822a52a 360{
3dbc01ae 361 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
7588e2b0
DG		 362
363 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
e822a52a
IY		 364}
365
c13ee169
MR		 366static void pci_host_bus_unregister(DeviceState *host)
367{
368 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
369
370 QLIST_REMOVE(host_bridge, next);
371}
372
c473d18d 373PCIBus *pci_device_root_bus(const PCIDevice *d)
e075e788 374{
fd56e061 375 PCIBus *bus = pci_get_bus(d);
e075e788 376
ce6a28ee
MA		 377 while (!pci_bus_is_root(bus)) {
378 d = bus->parent_dev;
379 assert(d != NULL);
380
fd56e061 381 bus = pci_get_bus(d);
e075e788
IY		 382 }
383
c473d18d
DG		 384 return bus;
385}
386
568f0690 387const char *pci_root_bus_path(PCIDevice *dev)
c473d18d 388{
568f0690
DG		 389 PCIBus *rootbus = pci_device_root_bus(dev);
390 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
391 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
c473d18d 392
568f0690
DG		 393 assert(host_bridge->bus == rootbus);
394
395 if (hc->root_bus_path) {
396 return (*hc->root_bus_path)(host_bridge, rootbus);
e075e788
IY		 397 }
398
568f0690 399 return rootbus->qbus.name;
e075e788
IY		 400}
401
1115ff6d
DG		 402static void pci_root_bus_init(PCIBus *bus, DeviceState *parent,
403 MemoryRegion *address_space_mem,
404 MemoryRegion *address_space_io,
405 uint8_t devfn_min)
30468f78 406{
6fa84913 407 assert(PCI_FUNC(devfn_min) == 0);
502a5395 408 bus->devfn_min = devfn_min;
8b884984 409 bus->slot_reserved_mask = 0x0;
5968eca3
AK		 410 bus->address_space_mem = address_space_mem;
411 bus->address_space_io = address_space_io;
b0e5196a 412 bus->flags |= PCI_BUS_IS_ROOT;
e822a52a
IY		 413
414 /* host bridge */
415 QLIST_INIT(&bus->child);
2b8cc89a 416
3dbc01ae 417 pci_host_bus_register(parent);
21eea4b3
GH		 418}
419
c13ee169
MR		 420static void pci_bus_uninit(PCIBus *bus)
421{
422 pci_host_bus_unregister(BUS(bus)->parent);
423}
424
8c0bf9e2
AW		 425bool pci_bus_is_express(PCIBus *bus)
426{
427 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
428}
429
1115ff6d
DG		 430void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
431 const char *name,
432 MemoryRegion *address_space_mem,
433 MemoryRegion *address_space_io,
434 uint8_t devfn_min, const char *typename)
4fec6404 435{
fb17dfe0 436 qbus_create_inplace(bus, bus_size, typename, parent, name);
1115ff6d
DG		 437 pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
438 devfn_min);
4fec6404
PB		 439}
440
1115ff6d
DG		 441PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
442 MemoryRegion *address_space_mem,
443 MemoryRegion *address_space_io,
444 uint8_t devfn_min, const char *typename)
21eea4b3
GH		 445{
446 PCIBus *bus;
447
60a0e443 448 bus = PCI_BUS(qbus_create(typename, parent, name));
1115ff6d
DG		 449 pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
450 devfn_min);
21eea4b3
GH		 451 return bus;
452}
453
c13ee169
MR		 454void pci_root_bus_cleanup(PCIBus *bus)
455{
456 pci_bus_uninit(bus);
07578b0a
DH		 457 /* the caller of the unplug hotplug handler will delete this device */
458 object_property_set_bool(OBJECT(bus), false, "realized", NULL);
c13ee169
MR		 459}
460
21eea4b3
GH		 461void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
462 void *irq_opaque, int nirq)
463{
464 bus->set_irq = set_irq;
465 bus->map_irq = map_irq;
466 bus->irq_opaque = irq_opaque;
467 bus->nirq = nirq;
7267c094 468 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
21eea4b3
GH		 469}
470
c13ee169
MR		 471void pci_bus_irqs_cleanup(PCIBus *bus)
472{
473 bus->set_irq = NULL;
474 bus->map_irq = NULL;
475 bus->irq_opaque = NULL;
476 bus->nirq = 0;
477 g_free(bus->irq_count);
478}
479
1115ff6d
DG		 480PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
481 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
482 void *irq_opaque,
483 MemoryRegion *address_space_mem,
484 MemoryRegion *address_space_io,
485 uint8_t devfn_min, int nirq,
486 const char *typename)
21eea4b3
GH		 487{
488 PCIBus *bus;
489
1115ff6d
DG		 490 bus = pci_root_bus_new(parent, name, address_space_mem,
491 address_space_io, devfn_min, typename);
21eea4b3 492 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
30468f78
FB		 493 return bus;
494}
69b91039 495
c13ee169
MR		 496void pci_unregister_root_bus(PCIBus *bus)
497{
498 pci_bus_irqs_cleanup(bus);
499 pci_root_bus_cleanup(bus);
500}
501
502a5395
PB		 502int pci_bus_num(PCIBus *s)
503{
602141d9 504 return PCI_BUS_GET_CLASS(s)->bus_num(s);
502a5395
PB		 505}
506
6a3042b2
MA		 507int pci_bus_numa_node(PCIBus *bus)
508{
509 return PCI_BUS_GET_CLASS(bus)->numa_node(bus);
502a5395
PB		 510}
511
2c21ee76 512static int get_pci_config_device(QEMUFile *f, void *pv, size_t size,
03fee66f 513 const VMStateField *field)
30ca2aab 514{
73534f2f 515 PCIDevice *s = container_of(pv, PCIDevice, config);
e78e9ae4 516 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
a9f49946 517 uint8_t *config;
52fc1d83
AZ		 518 int i;
519
a9f49946 520 assert(size == pci_config_size(s));
7267c094 521 config = g_malloc(size);
a9f49946
IY		 522
523 qemu_get_buffer(f, config, size);
524 for (i = 0; i < size; ++i) {
f9aebe2e
MT		 525 if ((config[i] ^ s->config[i]) &
526 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
7c59364d
DDAG		 527 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
528 "cmask: %x wmask: %x w1cmask:%x", __func__,
529 i, config[i], s->config[i],
530 s->cmask[i], s->wmask[i], s->w1cmask[i]);
7267c094 531 g_free(config);
bd4b65ee 532 return -EINVAL;
a9f49946
IY		 533 }
534 }
535 memcpy(s->config, config, size);
bd4b65ee 536
1941d19c 537 pci_update_mappings(s);
e78e9ae4 538 if (pc->is_bridge) {
f055e96b 539 PCIBridge *b = PCI_BRIDGE(s);
e78e9ae4
DK		 540 pci_bridge_update_mappings(b);
541 }
52fc1d83 542
4ea375bf
GH		 543 memory_region_set_enabled(&s->bus_master_enable_region,
544 pci_get_word(s->config + PCI_COMMAND)
545 & PCI_COMMAND_MASTER);
546
7267c094 547 g_free(config);
30ca2aab
FB		 548 return 0;
549}
550
73534f2f 551/* just put buffer */
2c21ee76 552static int put_pci_config_device(QEMUFile *f, void *pv, size_t size,
03fee66f 553 const VMStateField *field, QJSON *vmdesc)
73534f2f 554{
dbe73d7f 555 const uint8_t **v = pv;
a9f49946 556 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
dbe73d7f 557 qemu_put_buffer(f, *v, size);
2c21ee76
JD		 558
559 return 0;
73534f2f
JQ		 560}
561
562static VMStateInfo vmstate_info_pci_config = {
563 .name = "pci config",
564 .get = get_pci_config_device,
565 .put = put_pci_config_device,
566};
567
2c21ee76 568static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size,
03fee66f 569 const VMStateField *field)
d036bb21 570{
c3f8f611 571 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
d036bb21
MT		 572 uint32_t irq_state[PCI_NUM_PINS];
573 int i;
574 for (i = 0; i < PCI_NUM_PINS; ++i) {
575 irq_state[i] = qemu_get_be32(f);
576 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
577 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
578 irq_state[i]);
579 return -EINVAL;
580 }
581 }
582
583 for (i = 0; i < PCI_NUM_PINS; ++i) {
584 pci_set_irq_state(s, i, irq_state[i]);
585 }
586
587 return 0;
588}
589
2c21ee76 590static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size,
03fee66f 591 const VMStateField *field, QJSON *vmdesc)
d036bb21
MT		 592{
593 int i;
c3f8f611 594 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
d036bb21
MT		 595
596 for (i = 0; i < PCI_NUM_PINS; ++i) {
597 qemu_put_be32(f, pci_irq_state(s, i));
598 }
2c21ee76
JD		 599
600 return 0;
d036bb21
MT		 601}
602
603static VMStateInfo vmstate_info_pci_irq_state = {
604 .name = "pci irq state",
605 .get = get_pci_irq_state,
606 .put = put_pci_irq_state,
607};
608
20daa90a
DDAG		 609static bool migrate_is_pcie(void *opaque, int version_id)
610{
611 return pci_is_express((PCIDevice *)opaque);
612}
613
614static bool migrate_is_not_pcie(void *opaque, int version_id)
615{
616 return !pci_is_express((PCIDevice *)opaque);
617}
618
73534f2f
JQ		 619const VMStateDescription vmstate_pci_device = {
620 .name = "PCIDevice",
621 .version_id = 2,
622 .minimum_version_id = 1,
d49805ae 623 .fields = (VMStateField[]) {
3476436a 624 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
20daa90a
DDAG		 625 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
626 migrate_is_not_pcie,
627 0, vmstate_info_pci_config,
a9f49946 628 PCI_CONFIG_SPACE_SIZE),
20daa90a
DDAG		 629 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
630 migrate_is_pcie,
631 0, vmstate_info_pci_config,
a9f49946 632 PCIE_CONFIG_SPACE_SIZE),
d036bb21 633 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
7d37435b
PB		 634 vmstate_info_pci_irq_state,
635 PCI_NUM_PINS * sizeof(int32_t)),
73534f2f
JQ		 636 VMSTATE_END_OF_LIST()
637 }
638};
639
a9f49946 640
73534f2f
JQ		 641void pci_device_save(PCIDevice *s, QEMUFile *f)
642{
f9bf77dd
MT		 643 /* Clear interrupt status bit: it is implicit
644 * in irq_state which we are saving.
645 * This makes us compatible with old devices
646 * which never set or clear this bit. */
647 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
20daa90a 648 vmstate_save_state(f, &vmstate_pci_device, s, NULL);
f9bf77dd
MT		 649 /* Restore the interrupt status bit. */
650 pci_update_irq_status(s);
73534f2f
JQ		 651}
652
653int pci_device_load(PCIDevice *s, QEMUFile *f)
654{
f9bf77dd 655 int ret;
20daa90a 656 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
f9bf77dd
MT		 657 /* Restore the interrupt status bit. */
658 pci_update_irq_status(s);
659 return ret;
73534f2f
JQ		 660}
661
5e434f4e 662static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
d350d97d 663{
5e434f4e
IY		 664 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
665 pci_default_sub_vendor_id);
666 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
667 pci_default_sub_device_id);
d350d97d
AL		 668}
669
880345c4 670/*
43c945f1
IY		 671 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
672 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
880345c4 673 */
6dbcb819
MA		 674static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
675 unsigned int *slotp, unsigned int *funcp)
880345c4
AL		 676{
677 const char *p;
678 char *e;
679 unsigned long val;
680 unsigned long dom = 0, bus = 0;
43c945f1
IY		 681 unsigned int slot = 0;
682 unsigned int func = 0;
880345c4
AL		 683
684 p = addr;
685 val = strtoul(p, &e, 16);
686 if (e == p)
7d37435b 687 return -1;
880345c4 688 if (*e == ':') {
7d37435b
PB		 689 bus = val;
690 p = e + 1;
691 val = strtoul(p, &e, 16);
692 if (e == p)
693 return -1;
694 if (*e == ':') {
695 dom = bus;
696 bus = val;
697 p = e + 1;
698 val = strtoul(p, &e, 16);
699 if (e == p)
700 return -1;
701 }
880345c4
AL		 702 }
703
880345c4
AL		 704 slot = val;
705
43c945f1
IY		 706 if (funcp != NULL) {
707 if (*e != '.')
708 return -1;
709
710 p = e + 1;
711 val = strtoul(p, &e, 16);
712 if (e == p)
713 return -1;
714
715 func = val;
716 }
717
718 /* if funcp == NULL func is 0 */
719 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
7d37435b 720 return -1;
43c945f1 721
880345c4 722 if (*e)
7d37435b 723 return -1;
880345c4 724
880345c4
AL		 725 *domp = dom;
726 *busp = bus;
727 *slotp = slot;
43c945f1
IY		 728 if (funcp != NULL)
729 *funcp = func;
880345c4
AL		 730 return 0;
731}
732
bd4b65ee
MT		 733static void pci_init_cmask(PCIDevice *dev)
734{
735 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
736 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
737 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
738 dev->cmask[PCI_REVISION_ID] = 0xff;
739 dev->cmask[PCI_CLASS_PROG] = 0xff;
740 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
741 dev->cmask[PCI_HEADER_TYPE] = 0xff;
742 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
743}
744
b7ee1603
MT		 745static void pci_init_wmask(PCIDevice *dev)
746{
a9f49946
IY		 747 int config_size = pci_config_size(dev);
748
b7ee1603
MT		 749 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
750 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
67a51b48 751 pci_set_word(dev->wmask + PCI_COMMAND,
a7b15a5c
MT		 752 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
753 PCI_COMMAND_INTX_DISABLE);
b1aeb926
IY		 754 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
755 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
756 }
3e21ffc9
IY		 757
758 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
759 config_size - PCI_CONFIG_HEADER_SIZE);
b7ee1603
MT		 760}
761
89d437df
IY		 762static void pci_init_w1cmask(PCIDevice *dev)
763{
764 /*
f6bdfcc9 765 * Note: It's okay to set w1cmask even for readonly bits as
89d437df
IY		 766 * long as their value is hardwired to 0.
767 */
768 pci_set_word(dev->w1cmask + PCI_STATUS,
769 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
770 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
771 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
772}
773
d5f27e88 774static void pci_init_mask_bridge(PCIDevice *d)
fb231628
IY		 775{
776 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
777 PCI_SEC_LETENCY_TIMER */
778 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
779
780 /* base and limit */
781 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
782 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
783 pci_set_word(d->wmask + PCI_MEMORY_BASE,
784 PCI_MEMORY_RANGE_MASK & 0xffff);
785 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
786 PCI_MEMORY_RANGE_MASK & 0xffff);
787 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
788 PCI_PREF_RANGE_MASK & 0xffff);
789 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
790 PCI_PREF_RANGE_MASK & 0xffff);
791
792 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
793 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
794
d5f27e88 795 /* Supported memory and i/o types */
68917102
MT		 796 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
797 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
d5f27e88
MT		 798 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
799 PCI_PREF_RANGE_TYPE_64);
800 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
801 PCI_PREF_RANGE_TYPE_64);
802
45eb768c
MT		 803 /*
804 * TODO: Bridges default to 10-bit VGA decoding but we currently only
805 * implement 16-bit decoding (no alias support).
806 */
f6bdfcc9
MT		 807 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
808 PCI_BRIDGE_CTL_PARITY |
809 PCI_BRIDGE_CTL_SERR |
810 PCI_BRIDGE_CTL_ISA |
811 PCI_BRIDGE_CTL_VGA |
812 PCI_BRIDGE_CTL_VGA_16BIT |
813 PCI_BRIDGE_CTL_MASTER_ABORT |
814 PCI_BRIDGE_CTL_BUS_RESET |
815 PCI_BRIDGE_CTL_FAST_BACK |
816 PCI_BRIDGE_CTL_DISCARD |
817 PCI_BRIDGE_CTL_SEC_DISCARD |
f6bdfcc9
MT		 818 PCI_BRIDGE_CTL_DISCARD_SERR);
819 /* Below does not do anything as we never set this bit, put here for
820 * completeness. */
821 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
822 PCI_BRIDGE_CTL_DISCARD_STATUS);
d5f27e88 823 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
15ab7a75 824 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
d5f27e88
MT		 825 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
826 PCI_PREF_RANGE_TYPE_MASK);
15ab7a75
MT		 827 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
828 PCI_PREF_RANGE_TYPE_MASK);
fb231628
IY		 829}
830
133e9b22 831static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
6eab3de1
IY		 832{
833 uint8_t slot = PCI_SLOT(dev->devfn);
834 uint8_t func;
835
836 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
837 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
838 }
839
840 /*
b0cd712c 841 * multifunction bit is interpreted in two ways as follows.
6eab3de1
IY		 842 * - all functions must set the bit to 1.
843 * Example: Intel X53
844 * - function 0 must set the bit, but the rest function (> 0)
845 * is allowed to leave the bit to 0.
846 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
847 *
848 * So OS (at least Linux) checks the bit of only function 0,
849 * and doesn't see the bit of function > 0.
850 *
851 * The below check allows both interpretation.
852 */
853 if (PCI_FUNC(dev->devfn)) {
854 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
855 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
856 /* function 0 should set multifunction bit */
133e9b22
MA		 857 error_setg(errp, "PCI: single function device can't be populated "
858 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
859 return;
6eab3de1 860 }
133e9b22 861 return;
6eab3de1
IY		 862 }
863
864 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
133e9b22 865 return;
6eab3de1
IY		 866 }
867 /* function 0 indicates single function, so function > 0 must be NULL */
868 for (func = 1; func < PCI_FUNC_MAX; ++func) {
869 if (bus->devices[PCI_DEVFN(slot, func)]) {
133e9b22
MA		 870 error_setg(errp, "PCI: %x.0 indicates single function, "
871 "but %x.%x is already populated.",
872 slot, slot, func);
873 return;
6eab3de1
IY		 874 }
875 }
6eab3de1
IY		 876}
877
a9f49946
IY		 878static void pci_config_alloc(PCIDevice *pci_dev)
879{
880 int config_size = pci_config_size(pci_dev);
881
7267c094
AL		 882 pci_dev->config = g_malloc0(config_size);
883 pci_dev->cmask = g_malloc0(config_size);
884 pci_dev->wmask = g_malloc0(config_size);
885 pci_dev->w1cmask = g_malloc0(config_size);
886 pci_dev->used = g_malloc0(config_size);
a9f49946
IY		 887}
888
889static void pci_config_free(PCIDevice *pci_dev)
890{
7267c094
AL		 891 g_free(pci_dev->config);
892 g_free(pci_dev->cmask);
893 g_free(pci_dev->wmask);
894 g_free(pci_dev->w1cmask);
895 g_free(pci_dev->used);
a9f49946
IY		 896}
897
30607764
MA		 898static void do_pci_unregister_device(PCIDevice *pci_dev)
899{
fd56e061 900 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL;
30607764
MA		 901 pci_config_free(pci_dev);
902
193982c6
AK		 903 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) {
904 memory_region_del_subregion(&pci_dev->bus_master_container_region,
905 &pci_dev->bus_master_enable_region);
906 }
30607764 907 address_space_destroy(&pci_dev->bus_master_as);
30607764
MA		 908}
909
4a94b3aa
PX		 910/* Extract PCIReqIDCache into BDF format */
911static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache)
912{
913 uint8_t bus_n;
914 uint16_t result;
915
916 switch (cache->type) {
917 case PCI_REQ_ID_BDF:
918 result = pci_get_bdf(cache->dev);
919 break;
920 case PCI_REQ_ID_SECONDARY_BUS:
fd56e061 921 bus_n = pci_dev_bus_num(cache->dev);
4a94b3aa
PX		 922 result = PCI_BUILD_BDF(bus_n, 0);
923 break;
924 default:
eaf27fab 925 error_report("Invalid PCI requester ID cache type: %d",
4a94b3aa
PX		 926 cache->type);
927 exit(1);
928 break;
929 }
930
931 return result;
932}
933
934/* Parse bridges up to the root complex and return requester ID
935 * cache for specific device. For full PCIe topology, the cache
936 * result would be exactly the same as getting BDF of the device.
937 * However, several tricks are required when system mixed up with
938 * legacy PCI devices and PCIe-to-PCI bridges.
939 *
940 * Here we cache the proxy device (and type) not requester ID since
941 * bus number might change from time to time.
942 */
943static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev)
944{
945 PCIDevice *parent;
946 PCIReqIDCache cache = {
947 .dev = dev,
948 .type = PCI_REQ_ID_BDF,
949 };
950
fd56e061 951 while (!pci_bus_is_root(pci_get_bus(dev))) {
4a94b3aa 952 /* We are under PCI/PCIe bridges */
fd56e061 953 parent = pci_get_bus(dev)->parent_dev;
4a94b3aa
PX		 954 if (pci_is_express(parent)) {
955 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
956 /* When we pass through PCIe-to-PCI/PCIX bridges, we
957 * override the requester ID using secondary bus
958 * number of parent bridge with zeroed devfn
959 * (pcie-to-pci bridge spec chap 2.3). */
960 cache.type = PCI_REQ_ID_SECONDARY_BUS;
961 cache.dev = dev;
962 }
963 } else {
964 /* Legacy PCI, override requester ID with the bridge's
965 * BDF upstream. When the root complex connects to
966 * legacy PCI devices (including buses), it can only
967 * obtain requester ID info from directly attached
968 * devices. If devices are attached under bridges, only
969 * the requester ID of the bridge that is directly
970 * attached to the root complex can be recognized. */
971 cache.type = PCI_REQ_ID_BDF;
972 cache.dev = parent;
973 }
974 dev = parent;
975 }
976
977 return cache;
978}
979
980uint16_t pci_requester_id(PCIDevice *dev)
981{
982 return pci_req_id_cache_extract(&dev->requester_id_cache);
983}
984
9b717a3a
MCA		 985static bool pci_bus_devfn_available(PCIBus *bus, int devfn)
986{
987 return !(bus->devices[devfn]);
988}
989
8b884984
MCA		 990static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn)
991{
992 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn));
993}
994
69b91039 995/* -1 for devfn means auto assign */
fd56e061 996static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
133e9b22
MA		 997 const char *name, int devfn,
998 Error **errp)
69b91039 999{
40021f08
AL		 1000 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1001 PCIConfigReadFunc *config_read = pc->config_read;
1002 PCIConfigWriteFunc *config_write = pc->config_write;
133e9b22 1003 Error *local_err = NULL;
3f1e1478 1004 DeviceState *dev = DEVICE(pci_dev);
fd56e061 1005 PCIBus *bus = pci_get_bus(pci_dev);
3f1e1478 1006
0144f6f1
MA		 1007 /* Only pci bridges can be attached to extra PCI root buses */
1008 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) {
1009 error_setg(errp,
1010 "PCI: Only PCI/PCIe bridges can be plugged into %s",
1011 bus->parent_dev->name);
1012 return NULL;
1013 }
113f89df 1014
69b91039 1015 if (devfn < 0) {
b47b0706 1016 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
6fa84913 1017 devfn += PCI_FUNC_MAX) {
8b884984
MCA		 1018 if (pci_bus_devfn_available(bus, devfn) &&
1019 !pci_bus_devfn_reserved(bus, devfn)) {
69b91039 1020 goto found;
9b717a3a 1021 }
69b91039 1022 }
8b884984
MCA		 1023 error_setg(errp, "PCI: no slot/function available for %s, all in use "
1024 "or reserved", name);
09e3acc6 1025 return NULL;
69b91039 1026 found: ;
8b884984
MCA		 1027 } else if (pci_bus_devfn_reserved(bus, devfn)) {
1028 error_setg(errp, "PCI: slot %d function %d not available for %s,"
1029 " reserved",
1030 PCI_SLOT(devfn), PCI_FUNC(devfn), name);
1031 return NULL;
9b717a3a 1032 } else if (!pci_bus_devfn_available(bus, devfn)) {
133e9b22
MA		 1033 error_setg(errp, "PCI: slot %d function %d not available for %s,"
1034 " in use by %s",
1035 PCI_SLOT(devfn), PCI_FUNC(devfn), name,
1036 bus->devices[devfn]->name);
09e3acc6 1037 return NULL;
3f1e1478
C		 1038 } else if (dev->hotplugged &&
1039 pci_get_function_0(pci_dev)) {
1040 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s,"
1041 " new func %s cannot be exposed to guest.",
d93ddfb1
MT		 1042 PCI_SLOT(pci_get_function_0(pci_dev)->devfn),
1043 pci_get_function_0(pci_dev)->name,
3f1e1478
C		 1044 name);
1045
1046 return NULL;
69b91039 1047 }
e00387d5 1048
efc8188e 1049 pci_dev->devfn = devfn;
4a94b3aa 1050 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev);
d06bce95 1051 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
e00387d5 1052
3716d590
JW		 1053 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
1054 "bus master container", UINT64_MAX);
1055 address_space_init(&pci_dev->bus_master_as,
1056 &pci_dev->bus_master_container_region, pci_dev->name);
1057
b86eacb8
MA		 1058 if (qdev_hotplug) {
1059 pci_init_bus_master(pci_dev);
1060 }
d036bb21 1061 pci_dev->irq_state = 0;
a9f49946 1062 pci_config_alloc(pci_dev);
fb231628 1063
40021f08
AL		 1064 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
1065 pci_config_set_device_id(pci_dev->config, pc->device_id);
1066 pci_config_set_revision(pci_dev->config, pc->revision);
1067 pci_config_set_class(pci_dev->config, pc->class_id);
113f89df 1068
40021f08
AL		 1069 if (!pc->is_bridge) {
1070 if (pc->subsystem_vendor_id || pc->subsystem_id) {
113f89df 1071 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
40021f08 1072 pc->subsystem_vendor_id);
113f89df 1073 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
40021f08 1074 pc->subsystem_id);
113f89df
IY		 1075 } else {
1076 pci_set_default_subsystem_id(pci_dev);
1077 }
1078 } else {
1079 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
40021f08
AL		 1080 assert(!pc->subsystem_vendor_id);
1081 assert(!pc->subsystem_id);
fb231628 1082 }
bd4b65ee 1083 pci_init_cmask(pci_dev);
b7ee1603 1084 pci_init_wmask(pci_dev);
89d437df 1085 pci_init_w1cmask(pci_dev);
40021f08 1086 if (pc->is_bridge) {
d5f27e88 1087 pci_init_mask_bridge(pci_dev);
fb231628 1088 }
133e9b22
MA		 1089 pci_init_multifunction(bus, pci_dev, &local_err);
1090 if (local_err) {
1091 error_propagate(errp, local_err);
30607764 1092 do_pci_unregister_device(pci_dev);
6eab3de1
IY		 1093 return NULL;
1094 }
0ac32c83
FB		 1095
1096 if (!config_read)
1097 config_read = pci_default_read_config;
1098 if (!config_write)
1099 config_write = pci_default_write_config;
69b91039
FB		 1100 pci_dev->config_read = config_read;
1101 pci_dev->config_write = config_write;
30468f78 1102 bus->devices[devfn] = pci_dev;
f16c4abf 1103 pci_dev->version_id = 2; /* Current pci device vmstate version */
69b91039
FB		 1104 return pci_dev;
1105}
1106
5851e08c
AL		 1107static void pci_unregister_io_regions(PCIDevice *pci_dev)
1108{
1109 PCIIORegion *r;
1110 int i;
1111
1112 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1113 r = &pci_dev->io_regions[i];
182f9c8a 1114 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
5851e08c 1115 continue;
03952339 1116 memory_region_del_subregion(r->address_space, r->memory);
5851e08c 1117 }
e01fd687
AW		 1118
1119 pci_unregister_vga(pci_dev);
5851e08c
AL		 1120}
1121
133e9b22 1122static void pci_qdev_unrealize(DeviceState *dev, Error **errp)
5851e08c 1123{
40021f08
AL		 1124 PCIDevice *pci_dev = PCI_DEVICE(dev);
1125 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
5851e08c
AL		 1126
1127 pci_unregister_io_regions(pci_dev);
230741dc 1128 pci_del_option_rom(pci_dev);
7cf1b0fd 1129
f90c2bcd
AW		 1130 if (pc->exit) {
1131 pc->exit(pci_dev);
1132 }
5851e08c 1133
3936161f 1134 pci_device_deassert_intx(pci_dev);
925fe64a 1135 do_pci_unregister_device(pci_dev);
5851e08c
AL		 1136}
1137
e824b2cc
AK		 1138void pci_register_bar(PCIDevice *pci_dev, int region_num,
1139 uint8_t type, MemoryRegion *memory)
69b91039
FB		 1140{
1141 PCIIORegion *r;
5178ecd8 1142 uint32_t addr; /* offset in pci config space */
5a9ff381 1143 uint64_t wmask;
cfc0be25 1144 pcibus_t size = memory_region_size(memory);
a4c20c6a 1145
2bbb9c2f
IY		 1146 assert(region_num >= 0);
1147 assert(region_num < PCI_NUM_REGIONS);
a4c20c6a 1148 if (size & (size-1)) {
0151abe4
AF		 1149 error_report("ERROR: PCI region size must be pow2 "
1150 "type=0x%x, size=0x%"FMT_PCIBUS"", type, size);
a4c20c6a
AL		 1151 exit(1);
1152 }
1153
69b91039 1154 r = &pci_dev->io_regions[region_num];
182f9c8a 1155 r->addr = PCI_BAR_UNMAPPED;
69b91039
FB		 1156 r->size = size;
1157 r->type = type;
5178ecd8
C		 1158 r->memory = memory;
1159 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO
fd56e061
DG		 1160 ? pci_get_bus(pci_dev)->address_space_io
1161 : pci_get_bus(pci_dev)->address_space_mem;
b7ee1603
MT		 1162
1163 wmask = ~(size - 1);
d7ce493a 1164 if (region_num == PCI_ROM_SLOT) {
ebabb67a 1165 /* ROM enable bit is writable */
5330de09 1166 wmask |= PCI_ROM_ADDRESS_ENABLE;
d7ce493a 1167 }
5178ecd8
C		 1168
1169 addr = pci_bar(pci_dev, region_num);
b0ff8eb2 1170 pci_set_long(pci_dev->config + addr, type);
5178ecd8 1171
14421258
IY		 1172 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
1173 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1174 pci_set_quad(pci_dev->wmask + addr, wmask);
1175 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
1176 } else {
1177 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
1178 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
1179 }
79ff8cb0
AK		 1180}
1181
e01fd687
AW		 1182static void pci_update_vga(PCIDevice *pci_dev)
1183{
1184 uint16_t cmd;
1185
1186 if (!pci_dev->has_vga) {
1187 return;
1188 }
1189
1190 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
1191
1192 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
1193 cmd & PCI_COMMAND_MEMORY);
1194 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
1195 cmd & PCI_COMMAND_IO);
1196 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
1197 cmd & PCI_COMMAND_IO);
1198}
1199
1200void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
1201 MemoryRegion *io_lo, MemoryRegion *io_hi)
1202{
fd56e061
DG		 1203 PCIBus *bus = pci_get_bus(pci_dev);
1204
e01fd687
AW		 1205 assert(!pci_dev->has_vga);
1206
1207 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
1208 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
fd56e061 1209 memory_region_add_subregion_overlap(bus->address_space_mem,
e01fd687
AW		 1210 QEMU_PCI_VGA_MEM_BASE, mem, 1);
1211
1212 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
1213 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
fd56e061 1214 memory_region_add_subregion_overlap(bus->address_space_io,
e01fd687
AW		 1215 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
1216
1217 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
1218 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
fd56e061 1219 memory_region_add_subregion_overlap(bus->address_space_io,
e01fd687
AW		 1220 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
1221 pci_dev->has_vga = true;
1222
1223 pci_update_vga(pci_dev);
1224}
1225
1226void pci_unregister_vga(PCIDevice *pci_dev)
1227{
fd56e061
DG		 1228 PCIBus *bus = pci_get_bus(pci_dev);
1229
e01fd687
AW		 1230 if (!pci_dev->has_vga) {
1231 return;
1232 }
1233
fd56e061 1234 memory_region_del_subregion(bus->address_space_mem,
e01fd687 1235 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
fd56e061 1236 memory_region_del_subregion(bus->address_space_io,
e01fd687 1237 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
fd56e061 1238 memory_region_del_subregion(bus->address_space_io,
e01fd687
AW		 1239 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1240 pci_dev->has_vga = false;
1241}
1242
16a96f28
AK		 1243pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1244{
1245 return pci_dev->io_regions[region_num].addr;
1246}
1247
876a350d 1248static pcibus_t pci_bar_address(PCIDevice *d,
7d37435b 1249 int reg, uint8_t type, pcibus_t size)
876a350d
MT		 1250{
1251 pcibus_t new_addr, last_addr;
1252 int bar = pci_bar(d, reg);
1253 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
e4024630
LV		 1254 Object *machine = qdev_get_machine();
1255 ObjectClass *oc = object_get_class(machine);
1256 MachineClass *mc = MACHINE_CLASS(oc);
1257 bool allow_0_address = mc->pci_allow_0_address;
876a350d
MT		 1258
1259 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1260 if (!(cmd & PCI_COMMAND_IO)) {
1261 return PCI_BAR_UNMAPPED;
1262 }
1263 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1264 last_addr = new_addr + size - 1;
9f1a029a
HP		 1265 /* Check if 32 bit BAR wraps around explicitly.
1266 * TODO: make priorities correct and remove this work around.
1267 */
e4024630
LV		 1268 if (last_addr <= new_addr || last_addr >= UINT32_MAX ||
1269 (!allow_0_address && new_addr == 0)) {
876a350d
MT		 1270 return PCI_BAR_UNMAPPED;
1271 }
1272 return new_addr;
1273 }
1274
1275 if (!(cmd & PCI_COMMAND_MEMORY)) {
1276 return PCI_BAR_UNMAPPED;
1277 }
1278 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1279 new_addr = pci_get_quad(d->config + bar);
1280 } else {
1281 new_addr = pci_get_long(d->config + bar);
1282 }
1283 /* the ROM slot has a specific enable bit */
1284 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1285 return PCI_BAR_UNMAPPED;
1286 }
1287 new_addr &= ~(size - 1);
1288 last_addr = new_addr + size - 1;
1289 /* NOTE: we do not support wrapping */
1290 /* XXX: as we cannot support really dynamic
1291 mappings, we handle specific values as invalid
1292 mappings. */
e4024630
LV		 1293 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED ||
1294 (!allow_0_address && new_addr == 0)) {
876a350d
MT		 1295 return PCI_BAR_UNMAPPED;
1296 }
1297
1298 /* Now pcibus_t is 64bit.
1299 * Check if 32 bit BAR wraps around explicitly.
1300 * Without this, PC ide doesn't work well.
1301 * TODO: remove this work around.
1302 */
1303 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1304 return PCI_BAR_UNMAPPED;
1305 }
1306
1307 /*
1308 * OS is allowed to set BAR beyond its addressable
1309 * bits. For example, 32 bit OS can set 64bit bar
1310 * to >4G. Check it. TODO: we might need to support
1311 * it in the future for e.g. PAE.
1312 */
a8170e5e 1313 if (last_addr >= HWADDR_MAX) {
876a350d
MT		 1314 return PCI_BAR_UNMAPPED;
1315 }
1316
1317 return new_addr;
1318}
1319
0ac32c83
FB		 1320static void pci_update_mappings(PCIDevice *d)
1321{
1322 PCIIORegion *r;
876a350d 1323 int i;
7df32ca0 1324 pcibus_t new_addr;
3b46e624 1325
8a8696a3 1326 for(i = 0; i < PCI_NUM_REGIONS; i++) {
0ac32c83 1327 r = &d->io_regions[i];
a9688570
IY		 1328
1329 /* this region isn't registered */
ec503442 1330 if (!r->size)
a9688570
IY		 1331 continue;
1332
876a350d 1333 new_addr = pci_bar_address(d, i, r->type, r->size);
a9688570
IY		 1334
1335 /* This bar isn't changed */
7df32ca0 1336 if (new_addr == r->addr)
a9688570
IY		 1337 continue;
1338
1339 /* now do the real mapping */
1340 if (r->addr != PCI_BAR_UNMAPPED) {
fd56e061 1341 trace_pci_update_mappings_del(d, pci_dev_bus_num(d),
7828d750 1342 PCI_SLOT(d->devfn),
0f288f85 1343 PCI_FUNC(d->devfn),
7828d750 1344 i, r->addr, r->size);
03952339 1345 memory_region_del_subregion(r->address_space, r->memory);
0ac32c83 1346 }
a9688570
IY		 1347 r->addr = new_addr;
1348 if (r->addr != PCI_BAR_UNMAPPED) {
fd56e061 1349 trace_pci_update_mappings_add(d, pci_dev_bus_num(d),
7828d750 1350 PCI_SLOT(d->devfn),
0f288f85 1351 PCI_FUNC(d->devfn),
7828d750 1352 i, r->addr, r->size);
8b881e77
AK		 1353 memory_region_add_subregion_overlap(r->address_space,
1354 r->addr, r->memory, 1);
a9688570 1355 }
0ac32c83 1356 }
e01fd687
AW		 1357
1358 pci_update_vga(d);
0ac32c83
FB		 1359}
1360
a7b15a5c
MT		 1361static inline int pci_irq_disabled(PCIDevice *d)
1362{
1363 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1364}
1365
1366/* Called after interrupt disabled field update in config space,
1367 * assert/deassert interrupts if necessary.
1368 * Gets original interrupt disable bit value (before update). */
1369static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1370{
1371 int i, disabled = pci_irq_disabled(d);
1372 if (disabled == was_irq_disabled)
1373 return;
1374 for (i = 0; i < PCI_NUM_PINS; ++i) {
1375 int state = pci_irq_state(d, i);
1376 pci_change_irq_level(d, i, disabled ? -state : state);
1377 }
1378}
1379
5fafdf24 1380uint32_t pci_default_read_config(PCIDevice *d,
0ac32c83 1381 uint32_t address, int len)
69b91039 1382{
5029fe12 1383 uint32_t val = 0;
42e4126b 1384
727b4866
AW		 1385 if (pci_is_express_downstream_port(d) &&
1386 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) {
1387 pcie_sync_bridge_lnk(d);
1388 }
5029fe12
IY		 1389 memcpy(&val, d->config + address, len);
1390 return le32_to_cpu(val);
0ac32c83
FB		 1391}
1392
d7efb7e0 1393void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
0ac32c83 1394{
a7b15a5c 1395 int i, was_irq_disabled = pci_irq_disabled(d);
d7efb7e0 1396 uint32_t val = val_in;
0ac32c83 1397
42e4126b 1398 for (i = 0; i < l; val >>= 8, ++i) {
91011d4f 1399 uint8_t wmask = d->wmask[addr + i];
92ba5f51
IY		 1400 uint8_t w1cmask = d->w1cmask[addr + i];
1401 assert(!(wmask & w1cmask));
91011d4f 1402 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
92ba5f51 1403 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
0ac32c83 1404 }
260c0cd3 1405 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
edb00035
IY		 1406 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1407 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
260c0cd3 1408 range_covers_byte(addr, l, PCI_COMMAND))
0ac32c83 1409 pci_update_mappings(d);
a7b15a5c 1410
1c380f94 1411 if (range_covers_byte(addr, l, PCI_COMMAND)) {
a7b15a5c 1412 pci_update_irq_disabled(d, was_irq_disabled);
1c380f94
AK		 1413 memory_region_set_enabled(&d->bus_master_enable_region,
1414 pci_get_word(d->config + PCI_COMMAND)
1415 & PCI_COMMAND_MASTER);
1416 }
95d65800 1417
d7efb7e0
KO		 1418 msi_write_config(d, addr, val_in, l);
1419 msix_write_config(d, addr, val_in, l);
69b91039
FB		 1420}
1421
502a5395
PB		 1422/***********************************************************/
1423/* generic PCI irq support */
30468f78 1424
502a5395 1425/* 0 <= irq_num <= 3. level must be 0 or 1 */
d98f08f5 1426static void pci_irq_handler(void *opaque, int irq_num, int level)
69b91039 1427{
a60380a5 1428 PCIDevice *pci_dev = opaque;
80b3ada7 1429 int change;
3b46e624 1430
d036bb21 1431 change = level - pci_irq_state(pci_dev, irq_num);
80b3ada7
PB		 1432 if (!change)
1433 return;
d2b59317 1434
d036bb21 1435 pci_set_irq_state(pci_dev, irq_num, level);
f9bf77dd 1436 pci_update_irq_status(pci_dev);
a7b15a5c
MT		 1437 if (pci_irq_disabled(pci_dev))
1438 return;
d036bb21 1439 pci_change_irq_level(pci_dev, irq_num, change);
69b91039
FB		 1440}
1441
d98f08f5
MA		 1442static inline int pci_intx(PCIDevice *pci_dev)
1443{
1444 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1445}
1446
1447qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1448{
1449 int intx = pci_intx(pci_dev);
1450
1451 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1452}
1453
1454void pci_set_irq(PCIDevice *pci_dev, int level)
1455{
1456 int intx = pci_intx(pci_dev);
1457 pci_irq_handler(pci_dev, intx, level);
1458}
1459
3afa9bb4
MT		 1460/* Special hooks used by device assignment */
1461void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1462{
0889464a 1463 assert(pci_bus_is_root(bus));
3afa9bb4
MT		 1464 bus->route_intx_to_irq = route_intx_to_irq;
1465}
1466
1467PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1468{
1469 PCIBus *bus;
1470
1471 do {
fd56e061
DG		 1472 bus = pci_get_bus(dev);
1473 pin = bus->map_irq(dev, pin);
1474 dev = bus->parent_dev;
3afa9bb4 1475 } while (dev);
05c0621e
AW		 1476
1477 if (!bus->route_intx_to_irq) {
312fd5f2 1478 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
05c0621e
AW		 1479 object_get_typename(OBJECT(bus->qbus.parent)));
1480 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1481 }
1482
3afa9bb4 1483 return bus->route_intx_to_irq(bus->irq_opaque, pin);
0ae16251
JK		 1484}
1485
d6e65d54
AW		 1486bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1487{
1488 return old->mode != new->mode || old->irq != new->irq;
1489}
1490
0ae16251
JK		 1491void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1492{
1493 PCIDevice *dev;
1494 PCIBus *sec;
1495 int i;
1496
1497 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1498 dev = bus->devices[i];
1499 if (dev && dev->intx_routing_notifier) {
1500 dev->intx_routing_notifier(dev);
1501 }
e5368f0d
AW		 1502 }
1503
1504 QLIST_FOREACH(sec, &bus->child, sibling) {
1505 pci_bus_fire_intx_routing_notifier(sec);
0ae16251
JK		 1506 }
1507}
1508
1509void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1510 PCIINTxRoutingNotifier notifier)
1511{
1512 dev->intx_routing_notifier = notifier;
69b91039
FB		 1513}
1514
91e56159
IY		 1515/*
1516 * PCI-to-PCI bridge specification
1517 * 9.1: Interrupt routing. Table 9-1
1518 *
1519 * the PCI Express Base Specification, Revision 2.1
1520 * 2.2.8.1: INTx interrutp signaling - Rules
1521 * the Implementation Note
1522 * Table 2-20
1523 */
1524/*
1525 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1526 * 0-origin unlike PCI interrupt pin register.
1527 */
1528int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1529{
e8ec4adf 1530 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin);
91e56159
IY		 1531}
1532
502a5395
PB		 1533/***********************************************************/
1534/* monitor info on PCI */
0ac32c83 1535
6650ee6d
PB		 1536typedef struct {
1537 uint16_t class;
1538 const char *desc;
5e0259e7
GN		 1539 const char *fw_name;
1540 uint16_t fw_ign_bits;
6650ee6d
PB		 1541} pci_class_desc;
1542
09bc878a 1543static const pci_class_desc pci_class_descriptions[] =
6650ee6d 1544{
5e0259e7
GN		 1545 { 0x0001, "VGA controller", "display"},
1546 { 0x0100, "SCSI controller", "scsi"},
1547 { 0x0101, "IDE controller", "ide"},
1548 { 0x0102, "Floppy controller", "fdc"},
1549 { 0x0103, "IPI controller", "ipi"},
1550 { 0x0104, "RAID controller", "raid"},
dcb5b19a
TS		 1551 { 0x0106, "SATA controller"},
1552 { 0x0107, "SAS controller"},
1553 { 0x0180, "Storage controller"},
5e0259e7
GN		 1554 { 0x0200, "Ethernet controller", "ethernet"},
1555 { 0x0201, "Token Ring controller", "token-ring"},
1556 { 0x0202, "FDDI controller", "fddi"},
1557 { 0x0203, "ATM controller", "atm"},
dcb5b19a 1558 { 0x0280, "Network controller"},
5e0259e7 1559 { 0x0300, "VGA controller", "display", 0x00ff},
dcb5b19a
TS		 1560 { 0x0301, "XGA controller"},
1561 { 0x0302, "3D controller"},
1562 { 0x0380, "Display controller"},
5e0259e7
GN		 1563 { 0x0400, "Video controller", "video"},
1564 { 0x0401, "Audio controller", "sound"},
dcb5b19a 1565 { 0x0402, "Phone"},
602ef4d9 1566 { 0x0403, "Audio controller", "sound"},
dcb5b19a 1567 { 0x0480, "Multimedia controller"},
5e0259e7
GN		 1568 { 0x0500, "RAM controller", "memory"},
1569 { 0x0501, "Flash controller", "flash"},
dcb5b19a 1570 { 0x0580, "Memory controller"},
5e0259e7
GN		 1571 { 0x0600, "Host bridge", "host"},
1572 { 0x0601, "ISA bridge", "isa"},
1573 { 0x0602, "EISA bridge", "eisa"},
1574 { 0x0603, "MC bridge", "mca"},
4c41425d 1575 { 0x0604, "PCI bridge", "pci-bridge"},
5e0259e7
GN		 1576 { 0x0605, "PCMCIA bridge", "pcmcia"},
1577 { 0x0606, "NUBUS bridge", "nubus"},
1578 { 0x0607, "CARDBUS bridge", "cardbus"},
dcb5b19a
TS		 1579 { 0x0608, "RACEWAY bridge"},
1580 { 0x0680, "Bridge"},
5e0259e7
GN		 1581 { 0x0700, "Serial port", "serial"},
1582 { 0x0701, "Parallel port", "parallel"},
1583 { 0x0800, "Interrupt controller", "interrupt-controller"},
1584 { 0x0801, "DMA controller", "dma-controller"},
1585 { 0x0802, "Timer", "timer"},
1586 { 0x0803, "RTC", "rtc"},
1587 { 0x0900, "Keyboard", "keyboard"},
1588 { 0x0901, "Pen", "pen"},
1589 { 0x0902, "Mouse", "mouse"},
1590 { 0x0A00, "Dock station", "dock", 0x00ff},
1591 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1592 { 0x0c00, "Fireware contorller", "fireware"},
1593 { 0x0c01, "Access bus controller", "access-bus"},
1594 { 0x0c02, "SSA controller", "ssa"},
1595 { 0x0c03, "USB controller", "usb"},
1596 { 0x0c04, "Fibre channel controller", "fibre-channel"},
f7748569 1597 { 0x0c05, "SMBus"},
6650ee6d
PB		 1598 { 0, NULL}
1599};
1600
a8eeafda
GK		 1601static void pci_for_each_device_under_bus_reverse(PCIBus *bus,
1602 void (*fn)(PCIBus *b,
1603 PCIDevice *d,
1604 void *opaque),
1605 void *opaque)
1606{
1607 PCIDevice *d;
1608 int devfn;
1609
1610 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1611 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn];
1612 if (d) {
1613 fn(bus, d, opaque);
1614 }
1615 }
1616}
1617
1618void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
1619 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1620 void *opaque)
1621{
1622 bus = pci_find_bus_nr(bus, bus_num);
1623
1624 if (bus) {
1625 pci_for_each_device_under_bus_reverse(bus, fn, opaque);
1626 }
1627}
1628
163c8a59 1629static void pci_for_each_device_under_bus(PCIBus *bus,
7aa8cbb9
AP		 1630 void (*fn)(PCIBus *b, PCIDevice *d,
1631 void *opaque),
1632 void *opaque)
30468f78 1633{
163c8a59
LC		 1634 PCIDevice *d;
1635 int devfn;
30468f78 1636
163c8a59
LC		 1637 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1638 d = bus->devices[devfn];
1639 if (d) {
7aa8cbb9 1640 fn(bus, d, opaque);
163c8a59
LC		 1641 }
1642 }
1643}
1644
1645void pci_for_each_device(PCIBus *bus, int bus_num,
7aa8cbb9
AP		 1646 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1647 void *opaque)
163c8a59 1648{
d662210a 1649 bus = pci_find_bus_nr(bus, bus_num);
163c8a59
LC		 1650
1651 if (bus) {
7aa8cbb9 1652 pci_for_each_device_under_bus(bus, fn, opaque);
163c8a59
LC		 1653 }
1654}
1655
79627472 1656static const pci_class_desc *get_class_desc(int class)
163c8a59 1657{
79627472 1658 const pci_class_desc *desc;
163c8a59 1659
79627472
LC		 1660 desc = pci_class_descriptions;
1661 while (desc->desc && class != desc->class) {
1662 desc++;
30468f78 1663 }
b4dccd8d 1664
79627472
LC		 1665 return desc;
1666}
14421258 1667
79627472 1668static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
163c8a59 1669
79627472
LC		 1670static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1671{
1672 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1673 int i;
163c8a59 1674
79627472
LC		 1675 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1676 const PCIIORegion *r = &dev->io_regions[i];
1677 PciMemoryRegionList *region;
1678
1679 if (!r->size) {
1680 continue;
502a5395 1681 }
163c8a59 1682
79627472
LC		 1683 region = g_malloc0(sizeof(*region));
1684 region->value = g_malloc0(sizeof(*region->value));
163c8a59 1685
79627472
LC		 1686 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1687 region->value->type = g_strdup("io");
1688 } else {
1689 region->value->type = g_strdup("memory");
1690 region->value->has_prefetch = true;
1691 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1692 region->value->has_mem_type_64 = true;
1693 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
d5e4acf7 1694 }
163c8a59 1695
79627472
LC		 1696 region->value->bar = i;
1697 region->value->address = r->addr;
1698 region->value->size = r->size;
163c8a59 1699
79627472
LC		 1700 /* XXX: waiting for the qapi to support GSList */
1701 if (!cur_item) {
1702 head = cur_item = region;
1703 } else {
1704 cur_item->next = region;
1705 cur_item = region;
163c8a59 1706 }
80b3ada7 1707 }
384d8876 1708
79627472 1709 return head;
163c8a59
LC		 1710}
1711
79627472
LC		 1712static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1713 int bus_num)
163c8a59 1714{
79627472 1715 PciBridgeInfo *info;
9fa02cd1 1716 PciMemoryRange *range;
163c8a59 1717
9fa02cd1 1718 info = g_new0(PciBridgeInfo, 1);
163c8a59 1719
9fa02cd1
EB		 1720 info->bus = g_new0(PciBusInfo, 1);
1721 info->bus->number = dev->config[PCI_PRIMARY_BUS];
1722 info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
1723 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
163c8a59 1724
9fa02cd1
EB		 1725 range = info->bus->io_range = g_new0(PciMemoryRange, 1);
1726 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1727 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
163c8a59 1728
9fa02cd1
EB		 1729 range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
1730 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1731 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
163c8a59 1732
9fa02cd1
EB		 1733 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
1734 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1735 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
163c8a59 1736
79627472 1737 if (dev->config[PCI_SECONDARY_BUS] != 0) {
d662210a 1738 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
79627472
LC		 1739 if (child_bus) {
1740 info->has_devices = true;
1741 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1742 }
163c8a59
LC		 1743 }
1744
79627472 1745 return info;
163c8a59
LC		 1746}
1747
79627472
LC		 1748static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1749 int bus_num)
163c8a59 1750{
79627472
LC		 1751 const pci_class_desc *desc;
1752 PciDeviceInfo *info;
b5937f29 1753 uint8_t type;
79627472 1754 int class;
163c8a59 1755
9fa02cd1 1756 info = g_new0(PciDeviceInfo, 1);
79627472
LC		 1757 info->bus = bus_num;
1758 info->slot = PCI_SLOT(dev->devfn);
1759 info->function = PCI_FUNC(dev->devfn);
1760
9fa02cd1 1761 info->class_info = g_new0(PciDeviceClass, 1);
79627472 1762 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
9fa02cd1 1763 info->class_info->q_class = class;
79627472
LC		 1764 desc = get_class_desc(class);
1765 if (desc->desc) {
9fa02cd1
EB		 1766 info->class_info->has_desc = true;
1767 info->class_info->desc = g_strdup(desc->desc);
79627472
LC		 1768 }
1769
9fa02cd1
EB		 1770 info->id = g_new0(PciDeviceId, 1);
1771 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1772 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
79627472
LC		 1773 info->regions = qmp_query_pci_regions(dev);
1774 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
163c8a59
LC		 1775
1776 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
79627472
LC		 1777 info->has_irq = true;
1778 info->irq = dev->config[PCI_INTERRUPT_LINE];
163c8a59
LC		 1779 }
1780
b5937f29
IY		 1781 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1782 if (type == PCI_HEADER_TYPE_BRIDGE) {
79627472
LC		 1783 info->has_pci_bridge = true;
1784 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
18613dc6
DL		 1785 } else if (type == PCI_HEADER_TYPE_NORMAL) {
1786 info->id->has_subsystem = info->id->has_subsystem_vendor = true;
1787 info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID);
1788 info->id->subsystem_vendor =
1789 pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID);
1790 } else if (type == PCI_HEADER_TYPE_CARDBUS) {
1791 info->id->has_subsystem = info->id->has_subsystem_vendor = true;
1792 info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID);
1793 info->id->subsystem_vendor =
1794 pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID);
163c8a59
LC		 1795 }
1796
79627472 1797 return info;
163c8a59
LC		 1798}
1799
79627472 1800static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
384d8876 1801{
79627472 1802 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
163c8a59 1803 PCIDevice *dev;
79627472 1804 int devfn;
163c8a59
LC		 1805
1806 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1807 dev = bus->devices[devfn];
1808 if (dev) {
79627472
LC		 1809 info = g_malloc0(sizeof(*info));
1810 info->value = qmp_query_pci_device(dev, bus, bus_num);
1811
1812 /* XXX: waiting for the qapi to support GSList */
1813 if (!cur_item) {
1814 head = cur_item = info;
1815 } else {
1816 cur_item->next = info;
1817 cur_item = info;
1818 }
163c8a59 1819 }
1074df4f 1820 }
163c8a59 1821
79627472 1822 return head;
1074df4f
IY		 1823}
1824
79627472 1825static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1074df4f 1826{
79627472
LC		 1827 PciInfo *info = NULL;
1828
d662210a 1829 bus = pci_find_bus_nr(bus, bus_num);
502a5395 1830 if (bus) {
79627472
LC		 1831 info = g_malloc0(sizeof(*info));
1832 info->bus = bus_num;
1833 info->devices = qmp_query_pci_devices(bus, bus_num);
f2aa58c6 1834 }
163c8a59 1835
79627472 1836 return info;
f2aa58c6
FB		 1837}
1838
79627472 1839PciInfoList *qmp_query_pci(Error **errp)
f2aa58c6 1840{
79627472 1841 PciInfoList *info, *head = NULL, *cur_item = NULL;
7588e2b0 1842 PCIHostState *host_bridge;
163c8a59 1843
7588e2b0 1844 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
79627472 1845 info = g_malloc0(sizeof(*info));
cb2ed8b3
MA		 1846 info->value = qmp_query_pci_bus(host_bridge->bus,
1847 pci_bus_num(host_bridge->bus));
79627472
LC		 1848
1849 /* XXX: waiting for the qapi to support GSList */
1850 if (!cur_item) {
1851 head = cur_item = info;
1852 } else {
1853 cur_item->next = info;
1854 cur_item = info;
163c8a59 1855 }
e822a52a 1856 }
163c8a59 1857
79627472 1858 return head;
77d4bc34 1859}
a41b2ff2
PB		 1860
1861/* Initialize a PCI NIC. */
51f7cb97 1862PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
6dbcb819 1863 const char *default_model,
51f7cb97 1864 const char *default_devaddr)
a41b2ff2 1865{
5607c388 1866 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
52310c3f
PB		 1867 GSList *list;
1868 GPtrArray *pci_nic_models;
07caea31 1869 PCIBus *bus;
5607c388 1870 PCIDevice *pci_dev;
9d07d757 1871 DeviceState *dev;
51f7cb97 1872 int devfn;
cb457d76 1873 int i;
2ad778b8
DG		 1874 int dom, busnr;
1875 unsigned slot;
cb457d76 1876
52310c3f
PB		 1877 if (nd->model && !strcmp(nd->model, "virtio")) {
1878 g_free(nd->model);
1879 nd->model = g_strdup("virtio-net-pci");
1880 }
1881
1882 list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false);
1883 pci_nic_models = g_ptr_array_new();
1884 while (list) {
1885 DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data,
1886 TYPE_DEVICE);
1887 GSList *next;
1888 if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) &&
1889 dc->user_creatable) {
1890 const char *name = object_class_get_name(list->data);
1891 g_ptr_array_add(pci_nic_models, (gpointer)name);
1892 }
1893 next = list->next;
1894 g_slist_free_1(list);
1895 list = next;
1896 }
1897 g_ptr_array_add(pci_nic_models, NULL);
1898
1899 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) {
51f7cb97
TH		 1900 exit(0);
1901 }
1902
52310c3f
PB		 1903 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata,
1904 default_model);
51f7cb97
TH		 1905 if (i < 0) {
1906 exit(1);
1907 }
07caea31 1908
2ad778b8
DG		 1909 if (!rootbus) {
1910 error_report("No primary PCI bus");
1911 exit(1);
1912 }
1913
1914 assert(!rootbus->parent_dev);
1915
1916 if (!devaddr) {
1917 devfn = -1;
1918 busnr = 0;
1919 } else {
1920 if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) {
1921 error_report("Invalid PCI device address %s for device %s",
1922 devaddr, nd->model);
1923 exit(1);
1924 }
1925
1926 if (dom != 0) {
1927 error_report("No support for non-zero PCI domains");
1928 exit(1);
1929 }
1930
1931 devfn = PCI_DEVFN(slot, 0);
1932 }
1933
1934 bus = pci_find_bus_nr(rootbus, busnr);
07caea31 1935 if (!bus) {
1ecda02b 1936 error_report("Invalid PCI device address %s for device %s",
52310c3f 1937 devaddr, nd->model);
51f7cb97 1938 exit(1);
07caea31
MA		 1939 }
1940
52310c3f 1941 pci_dev = pci_create(bus, devfn, nd->model);
9ee05825 1942 dev = &pci_dev->qdev;
1cc33683 1943 qdev_set_nic_properties(dev, nd);
a023b7ac 1944 qdev_init_nofail(dev);
52310c3f 1945 g_ptr_array_free(pci_nic_models, true);
51f7cb97 1946 return pci_dev;
07caea31
MA		 1947}
1948
129d42fb
AJ		 1949PCIDevice *pci_vga_init(PCIBus *bus)
1950{
1951 switch (vga_interface_type) {
1952 case VGA_CIRRUS:
1953 return pci_create_simple(bus, -1, "cirrus-vga");
1954 case VGA_QXL:
1955 return pci_create_simple(bus, -1, "qxl-vga");
1956 case VGA_STD:
1957 return pci_create_simple(bus, -1, "VGA");
1958 case VGA_VMWARE:
1959 return pci_create_simple(bus, -1, "vmware-svga");
a94f0c5c
GH		 1960 case VGA_VIRTIO:
1961 return pci_create_simple(bus, -1, "virtio-vga");
129d42fb
AJ		 1962 case VGA_NONE:
1963 default: /* Other non-PCI types. Checking for unsupported types is already
1964 done in vl.c. */
1965 return NULL;
1966 }
1967}
1968
929176c3
MT		 1969/* Whether a given bus number is in range of the secondary
1970 * bus of the given bridge device. */
1971static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1972{
1973 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1974 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
09e5b819 1975 dev->config[PCI_SECONDARY_BUS] <= bus_num &&
929176c3
MT		 1976 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1977}
1978
09e5b819
MA		 1979/* Whether a given bus number is in a range of a root bus */
1980static bool pci_root_bus_in_range(PCIBus *bus, int bus_num)
1981{
1982 int i;
1983
1984 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1985 PCIDevice *dev = bus->devices[i];
1986
1987 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) {
1988 if (pci_secondary_bus_in_range(dev, bus_num)) {
1989 return true;
1990 }
1991 }
1992 }
1993
1994 return false;
1995}
1996
d662210a 1997static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
3ae80618 1998{
470e6363 1999 PCIBus *sec;
3ae80618 2000
470e6363 2001 if (!bus) {
e822a52a 2002 return NULL;
470e6363 2003 }
3ae80618 2004
e822a52a
IY		 2005 if (pci_bus_num(bus) == bus_num) {
2006 return bus;
2007 }
2008
929176c3 2009 /* Consider all bus numbers in range for the host pci bridge. */
0889464a 2010 if (!pci_bus_is_root(bus) &&
929176c3
MT		 2011 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
2012 return NULL;
2013 }
2014
e822a52a 2015 /* try child bus */
929176c3
MT		 2016 for (; bus; bus = sec) {
2017 QLIST_FOREACH(sec, &bus->child, sibling) {
09e5b819 2018 if (pci_bus_num(sec) == bus_num) {
929176c3
MT		 2019 return sec;
2020 }
09e5b819
MA		 2021 /* PXB buses assumed to be children of bus 0 */
2022 if (pci_bus_is_root(sec)) {
2023 if (pci_root_bus_in_range(sec, bus_num)) {
2024 break;
2025 }
2026 } else {
2027 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
2028 break;
2029 }
c021f8e6 2030 }
e822a52a
IY		 2031 }
2032 }
2033
2034 return NULL;
3ae80618
AL		 2035}
2036
eb0acfdd
MT		 2037void pci_for_each_bus_depth_first(PCIBus *bus,
2038 void *(*begin)(PCIBus *bus, void *parent_state),
2039 void (*end)(PCIBus *bus, void *state),
2040 void *parent_state)
2041{
2042 PCIBus *sec;
2043 void *state;
2044
2045 if (!bus) {
2046 return;
2047 }
2048
2049 if (begin) {
2050 state = begin(bus, parent_state);
2051 } else {
2052 state = parent_state;
2053 }
2054
2055 QLIST_FOREACH(sec, &bus->child, sibling) {
2056 pci_for_each_bus_depth_first(sec, begin, end, state);
2057 }
2058
2059 if (end) {
2060 end(bus, state);
2061 }
2062}
2063
2064
5256d8bf 2065PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
3ae80618 2066{
d662210a 2067 bus = pci_find_bus_nr(bus, bus_num);
3ae80618
AL		 2068
2069 if (!bus)
2070 return NULL;
2071
5256d8bf 2072 return bus->devices[devfn];
3ae80618
AL		 2073}
2074
133e9b22 2075static void pci_qdev_realize(DeviceState *qdev, Error **errp)
6b1b92d3
PB		 2076{
2077 PCIDevice *pci_dev = (PCIDevice *)qdev;
40021f08 2078 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
d61a363d 2079 ObjectClass *klass = OBJECT_CLASS(pc);
133e9b22 2080 Error *local_err = NULL;
ab85ceb1 2081 bool is_default_rom;
4f5b6a05 2082 uint16_t class_id;
6b1b92d3 2083
d61a363d
YB		 2084 /* initialize cap_present for pci_is_express() and pci_config_size(),
2085 * Note that hybrid PCIs are not set automatically and need to manage
2086 * QEMU_PCI_CAP_EXPRESS manually */
2087 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) &&
2088 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) {
a9f49946
IY		 2089 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2090 }
2091
fd56e061 2092 pci_dev = do_pci_register_device(pci_dev,
6e008585 2093 object_get_typename(OBJECT(qdev)),
133e9b22 2094 pci_dev->devfn, errp);
09e3acc6 2095 if (pci_dev == NULL)
133e9b22 2096 return;
2897ae02 2097
7ee6c1e1
MA		 2098 if (pc->realize) {
2099 pc->realize(pci_dev, &local_err);
2100 if (local_err) {
2101 error_propagate(errp, local_err);
c2afc922 2102 do_pci_unregister_device(pci_dev);
133e9b22 2103 return;
c2afc922 2104 }
925fe64a 2105 }
8c52c8f3 2106
4f5b6a05
JF		 2107 if (pci_dev->failover_pair_id) {
2108 if (!pci_bus_is_express(pci_get_bus(pci_dev))) {
2109 error_setg(errp, "failover primary device must be on "
2110 "PCIExpress bus");
2111 error_propagate(errp, local_err);
2112 pci_qdev_unrealize(DEVICE(pci_dev), NULL);
2113 return;
2114 }
2115 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE);
2116 if (class_id != PCI_CLASS_NETWORK_ETHERNET) {
2117 error_setg(errp, "failover primary device is not an "
2118 "Ethernet device");
2119 error_propagate(errp, local_err);
2120 pci_qdev_unrealize(DEVICE(pci_dev), NULL);
2121 return;
2122 }
2123 if (!(pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)
2124 && (PCI_FUNC(pci_dev->devfn) == 0)) {
2125 qdev->allow_unplug_during_migration = true;
2126 } else {
2127 error_setg(errp, "failover: primary device must be in its own "
2128 "PCI slot");
2129 error_propagate(errp, local_err);
2130 pci_qdev_unrealize(DEVICE(pci_dev), NULL);
2131 return;
2132 }
2133 }
2134
8c52c8f3 2135 /* rom loading */
ab85ceb1 2136 is_default_rom = false;
40021f08
AL		 2137 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
2138 pci_dev->romfile = g_strdup(pc->romfile);
ab85ceb1
SW		 2139 is_default_rom = true;
2140 }
178e785f 2141
133e9b22
MA		 2142 pci_add_option_rom(pci_dev, is_default_rom, &local_err);
2143 if (local_err) {
2144 error_propagate(errp, local_err);
2145 pci_qdev_unrealize(DEVICE(pci_dev), NULL);
2146 return;
178e785f 2147 }
ee995ffb
GH		 2148}
2149
49823868
IY		 2150PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
2151 const char *name)
6b1b92d3
PB		 2152{
2153 DeviceState *dev;
2154
02e2da45 2155 dev = qdev_create(&bus->qbus, name);
09f1bbcd 2156 qdev_prop_set_int32(dev, "addr", devfn);
49823868 2157 qdev_prop_set_bit(dev, "multifunction", multifunction);
40021f08 2158 return PCI_DEVICE(dev);
71077c1c 2159}
6b1b92d3 2160
49823868
IY		 2161PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
2162 bool multifunction,
2163 const char *name)
71077c1c 2164{
49823868 2165 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
e23a1b33 2166 qdev_init_nofail(&dev->qdev);
71077c1c 2167 return dev;
6b1b92d3 2168}
6f4cbd39 2169
49823868
IY		 2170PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
2171{
2172 return pci_create_multifunction(bus, devfn, false, name);
2173}
2174
2175PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
2176{
2177 return pci_create_simple_multifunction(bus, devfn, false, name);
2178}
2179
b56d701f 2180static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
6f4cbd39
MT		 2181{
2182 int offset = PCI_CONFIG_HEADER_SIZE;
2183 int i;
b56d701f 2184 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
6f4cbd39
MT		 2185 if (pdev->used[i])
2186 offset = i + 1;
2187 else if (i - offset + 1 == size)
2188 return offset;
b56d701f 2189 }
6f4cbd39
MT		 2190 return 0;
2191}
2192
2193static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
2194 uint8_t *prev_p)
2195{
2196 uint8_t next, prev;
2197
2198 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
2199 return 0;
2200
2201 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2202 prev = next + PCI_CAP_LIST_NEXT)
2203 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
2204 break;
2205
2206 if (prev_p)
2207 *prev_p = prev;
2208 return next;
2209}
2210
c9abe111
JK		 2211static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
2212{
2213 uint8_t next, prev, found = 0;
2214
2215 if (!(pdev->used[offset])) {
2216 return 0;
2217 }
2218
2219 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
2220
2221 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2222 prev = next + PCI_CAP_LIST_NEXT) {
2223 if (next <= offset && next > found) {
2224 found = next;
2225 }
2226 }
2227 return found;
2228}
2229
ab85ceb1
SW		 2230/* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2231 This is needed for an option rom which is used for more than one device. */
2232static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
2233{
2234 uint16_t vendor_id;
2235 uint16_t device_id;
2236 uint16_t rom_vendor_id;
2237 uint16_t rom_device_id;
2238 uint16_t rom_magic;
2239 uint16_t pcir_offset;
2240 uint8_t checksum;
2241
2242 /* Words in rom data are little endian (like in PCI configuration),
2243 so they can be read / written with pci_get_word / pci_set_word. */
2244
2245 /* Only a valid rom will be patched. */
2246 rom_magic = pci_get_word(ptr);
2247 if (rom_magic != 0xaa55) {
2248 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
2249 return;
2250 }
2251 pcir_offset = pci_get_word(ptr + 0x18);
2252 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
2253 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
2254 return;
2255 }
2256
2257 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
2258 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
2259 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
2260 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
2261
2262 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
2263 vendor_id, device_id, rom_vendor_id, rom_device_id);
2264
2265 checksum = ptr[6];
2266
2267 if (vendor_id != rom_vendor_id) {
2268 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2269 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
2270 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
2271 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2272 ptr[6] = checksum;
2273 pci_set_word(ptr + pcir_offset + 4, vendor_id);
2274 }
2275
2276 if (device_id != rom_device_id) {
2277 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2278 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
2279 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
2280 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2281 ptr[6] = checksum;
2282 pci_set_word(ptr + pcir_offset + 6, device_id);
2283 }
2284}
2285
c2039bd0 2286/* Add an option rom for the device */
133e9b22
MA		 2287static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
2288 Error **errp)
c2039bd0
AL		 2289{
2290 int size;
2291 char *path;
2292 void *ptr;
1724f049 2293 char name[32];
4be9f0d1 2294 const VMStateDescription *vmsd;
c2039bd0 2295
8c52c8f3 2296 if (!pdev->romfile)
133e9b22 2297 return;
8c52c8f3 2298 if (strlen(pdev->romfile) == 0)
133e9b22 2299 return;
8c52c8f3 2300
88169ddf
GH		 2301 if (!pdev->rom_bar) {
2302 /*
2303 * Load rom via fw_cfg instead of creating a rom bar,
2304 * for 0.11 compatibility.
2305 */
2306 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
db80c7b9
MA		 2307
2308 /*
2309 * Hot-plugged devices can't use the option ROM
2310 * if the rom bar is disabled.
2311 */
2312 if (DEVICE(pdev)->hotplugged) {
133e9b22
MA		 2313 error_setg(errp, "Hot-plugged device without ROM bar"
2314 " can't have an option ROM");
2315 return;
db80c7b9
MA		 2316 }
2317
88169ddf
GH		 2318 if (class == 0x0300) {
2319 rom_add_vga(pdev->romfile);
2320 } else {
2e55e842 2321 rom_add_option(pdev->romfile, -1);
88169ddf 2322 }
133e9b22 2323 return;
88169ddf
GH		 2324 }
2325
8c52c8f3 2326 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
c2039bd0 2327 if (path == NULL) {
7267c094 2328 path = g_strdup(pdev->romfile);
c2039bd0
AL		 2329 }
2330
2331 size = get_image_size(path);
8c52c8f3 2332 if (size < 0) {
133e9b22 2333 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile);
8c7f3dd0 2334 g_free(path);
133e9b22 2335 return;
8c7f3dd0 2336 } else if (size == 0) {
133e9b22 2337 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
7267c094 2338 g_free(path);
133e9b22 2339 return;
8c52c8f3 2340 }
9bff5d81 2341 size = pow2ceil(size);
c2039bd0 2342
4be9f0d1
AL		 2343 vmsd = qdev_get_vmsd(DEVICE(pdev));
2344
2345 if (vmsd) {
2346 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
2347 } else {
f79f2bfc 2348 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
4be9f0d1 2349 }
14caaf7f 2350 pdev->has_rom = true;
fefa9256 2351 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal);
14caaf7f 2352 ptr = memory_region_get_ram_ptr(&pdev->rom);
36bde091
PM		 2353 if (load_image_size(path, ptr, size) < 0) {
2354 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile);
2355 g_free(path);
2356 return;
2357 }
7267c094 2358 g_free(path);
c2039bd0 2359
ab85ceb1
SW		 2360 if (is_default_rom) {
2361 /* Only the default rom images will be patched (if needed). */
2362 pci_patch_ids(pdev, ptr, size);
2363 }
2364
e824b2cc 2365 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
c2039bd0
AL		 2366}
2367
230741dc
AW		 2368static void pci_del_option_rom(PCIDevice *pdev)
2369{
14caaf7f 2370 if (!pdev->has_rom)
230741dc
AW		 2371 return;
2372
c5705a77 2373 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
14caaf7f 2374 pdev->has_rom = false;
230741dc
AW		 2375}
2376
ca77089d 2377/*
27841278 2378 * On success, pci_add_capability() returns a positive value
eacbc632
MZ		 2379 * that the offset of the pci capability.
2380 * On failure, it sets an error and returns a negative error
2381 * code.
2382 */
27841278 2383int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
cd9aa33e
LE		 2384 uint8_t offset, uint8_t size,
2385 Error **errp)
6f4cbd39 2386{
ca77089d 2387 uint8_t *config;
c9abe111
JK		 2388 int i, overlapping_cap;
2389
ca77089d
IY		 2390 if (!offset) {
2391 offset = pci_find_space(pdev, size);
97fe42f1
C		 2392 /* out of PCI config space is programming error */
2393 assert(offset);
c9abe111
JK		 2394 } else {
2395 /* Verify that capabilities don't overlap. Note: device assignment
2396 * depends on this check to verify that the device is not broken.
2397 * Should never trigger for emulated devices, but it's helpful
2398 * for debugging these. */
2399 for (i = offset; i < offset + size; i++) {
2400 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2401 if (overlapping_cap) {
cd9aa33e
LE		 2402 error_setg(errp, "%s:%02x:%02x.%x "
2403 "Attempt to add PCI capability %x at offset "
2404 "%x overlaps existing capability %x at offset %x",
fd56e061 2405 pci_root_bus_path(pdev), pci_dev_bus_num(pdev),
cd9aa33e
LE		 2406 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2407 cap_id, offset, overlapping_cap, i);
c9abe111
JK		 2408 return -EINVAL;
2409 }
2410 }
ca77089d
IY		 2411 }
2412
2413 config = pdev->config + offset;
6f4cbd39
MT		 2414 config[PCI_CAP_LIST_ID] = cap_id;
2415 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2416 pdev->config[PCI_CAPABILITY_LIST] = offset;
2417 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
e26631b7 2418 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
6f4cbd39
MT		 2419 /* Make capability read-only by default */
2420 memset(pdev->wmask + offset, 0, size);
bd4b65ee
MT		 2421 /* Check capability by default */
2422 memset(pdev->cmask + offset, 0xFF, size);
6f4cbd39
MT		 2423 return offset;
2424}
2425
2426/* Unlink capability from the pci config space. */
2427void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2428{
2429 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2430 if (!offset)
2431 return;
2432 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
ebabb67a 2433 /* Make capability writable again */
6f4cbd39 2434 memset(pdev->wmask + offset, 0xff, size);
1a4f5971 2435 memset(pdev->w1cmask + offset, 0, size);
bd4b65ee
MT		 2436 /* Clear cmask as device-specific registers can't be checked */
2437 memset(pdev->cmask + offset, 0, size);
e26631b7 2438 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
6f4cbd39
MT		 2439
2440 if (!pdev->config[PCI_CAPABILITY_LIST])
2441 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2442}
2443
6f4cbd39
MT		 2444uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2445{
2446 return pci_find_capability_list(pdev, cap_id, NULL);
2447}
10c4c98a
GH		 2448
2449static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2450{
2451 PCIDevice *d = (PCIDevice *)dev;
2452 const pci_class_desc *desc;
2453 char ctxt[64];
2454 PCIIORegion *r;
2455 int i, class;
2456
b0ff8eb2 2457 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
10c4c98a
GH		 2458 desc = pci_class_descriptions;
2459 while (desc->desc && class != desc->class)
2460 desc++;
2461 if (desc->desc) {
2462 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2463 } else {
2464 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2465 }
2466
2467 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2468 "pci id %04x:%04x (sub %04x:%04x)\n",
fd56e061 2469 indent, "", ctxt, pci_dev_bus_num(d),
e822a52a 2470 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
b0ff8eb2
IY		 2471 pci_get_word(d->config + PCI_VENDOR_ID),
2472 pci_get_word(d->config + PCI_DEVICE_ID),
2473 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2474 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
10c4c98a
GH		 2475 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2476 r = &d->io_regions[i];
2477 if (!r->size)
2478 continue;
89e8b13c
IY		 2479 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2480 " [0x%"FMT_PCIBUS"]\n",
2481 indent, "",
0392a017 2482 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
10c4c98a
GH		 2483 r->addr, r->addr + r->size - 1);
2484 }
2485}
03587182 2486
5e0259e7
GN		 2487static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2488{
2489 PCIDevice *d = (PCIDevice *)dev;
2490 const char *name = NULL;
2491 const pci_class_desc *desc = pci_class_descriptions;
2492 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2493
2494 while (desc->desc &&
2495 (class & ~desc->fw_ign_bits) !=
2496 (desc->class & ~desc->fw_ign_bits)) {
2497 desc++;
2498 }
2499
2500 if (desc->desc) {
2501 name = desc->fw_name;
2502 }
2503
2504 if (name) {
2505 pstrcpy(buf, len, name);
2506 } else {
2507 snprintf(buf, len, "pci%04x,%04x",
2508 pci_get_word(d->config + PCI_VENDOR_ID),
2509 pci_get_word(d->config + PCI_DEVICE_ID));
2510 }
2511
2512 return buf;
2513}
2514
2515static char *pcibus_get_fw_dev_path(DeviceState *dev)
2516{
2517 PCIDevice *d = (PCIDevice *)dev;
2518 char path[50], name[33];
2519 int off;
2520
2521 off = snprintf(path, sizeof(path), "%s@%x",
2522 pci_dev_fw_name(dev, name, sizeof name),
2523 PCI_SLOT(d->devfn));
2524 if (PCI_FUNC(d->devfn))
2525 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
a5cf8262 2526 return g_strdup(path);
5e0259e7
GN		 2527}
2528
4f43c1ff
AW		 2529static char *pcibus_get_dev_path(DeviceState *dev)
2530{
a6a7005d
MT		 2531 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2532 PCIDevice *t;
2533 int slot_depth;
2534 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2535 * 00 is added here to make this format compatible with
2536 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2537 * Slot.Function list specifies the slot and function numbers for all
2538 * devices on the path from root to the specific device. */
568f0690
DG		 2539 const char *root_bus_path;
2540 int root_bus_len;
2991181a 2541 char slot[] = ":SS.F";
2991181a 2542 int slot_len = sizeof slot - 1 /* For '\0' */;
a6a7005d
MT		 2543 int path_len;
2544 char *path, *p;
2991181a 2545 int s;
a6a7005d 2546
568f0690
DG		 2547 root_bus_path = pci_root_bus_path(d);
2548 root_bus_len = strlen(root_bus_path);
2549
a6a7005d
MT		 2550 /* Calculate # of slots on path between device and root. */;
2551 slot_depth = 0;
fd56e061 2552 for (t = d; t; t = pci_get_bus(t)->parent_dev) {
a6a7005d
MT		 2553 ++slot_depth;
2554 }
2555
568f0690 2556 path_len = root_bus_len + slot_len * slot_depth;
a6a7005d
MT		 2557
2558 /* Allocate memory, fill in the terminating null byte. */
7267c094 2559 path = g_malloc(path_len + 1 /* For '\0' */);
a6a7005d
MT		 2560 path[path_len] = '\0';
2561
568f0690 2562 memcpy(path, root_bus_path, root_bus_len);
a6a7005d
MT		 2563
2564 /* Fill in slot numbers. We walk up from device to root, so need to print
2565 * them in the reverse order, last to first. */
2566 p = path + path_len;
fd56e061 2567 for (t = d; t; t = pci_get_bus(t)->parent_dev) {
a6a7005d 2568 p -= slot_len;
2991181a 2569 s = snprintf(slot, sizeof slot, ":%02x.%x",
4c900518 2570 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2991181a
MT		 2571 assert(s == slot_len);
2572 memcpy(p, slot, slot_len);
a6a7005d
MT		 2573 }
2574
2575 return path;
4f43c1ff
AW		 2576}
2577
f3006dd1
IY		 2578static int pci_qdev_find_recursive(PCIBus *bus,
2579 const char *id, PCIDevice **pdev)
2580{
2581 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2582 if (!qdev) {
2583 return -ENODEV;
2584 }
2585
2586 /* roughly check if given qdev is pci device */
4be9f0d1 2587 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
40021f08 2588 *pdev = PCI_DEVICE(qdev);
f3006dd1
IY		 2589 return 0;
2590 }
2591 return -EINVAL;
2592}
2593
2594int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2595{
7588e2b0 2596 PCIHostState *host_bridge;
f3006dd1
IY		 2597 int rc = -ENODEV;
2598
7588e2b0
DG		 2599 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2600 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
f3006dd1
IY		 2601 if (!tmp) {
2602 rc = 0;
2603 break;
2604 }
2605 if (tmp != -ENODEV) {
2606 rc = tmp;
2607 }
2608 }
2609
2610 return rc;
2611}
f5e6fed8
AK		 2612
2613MemoryRegion *pci_address_space(PCIDevice *dev)
2614{
fd56e061 2615 return pci_get_bus(dev)->address_space_mem;
f5e6fed8 2616}
e11d6439
RH		 2617
2618MemoryRegion *pci_address_space_io(PCIDevice *dev)
2619{
fd56e061 2620 return pci_get_bus(dev)->address_space_io;
e11d6439 2621}
40021f08 2622
39bffca2
AL		 2623static void pci_device_class_init(ObjectClass *klass, void *data)
2624{
2625 DeviceClass *k = DEVICE_CLASS(klass);
7ee6c1e1 2626
133e9b22
MA		 2627 k->realize = pci_qdev_realize;
2628 k->unrealize = pci_qdev_unrealize;
0d936928 2629 k->bus_type = TYPE_PCI_BUS;
bce54474 2630 k->props = pci_props;
39bffca2
AL		 2631}
2632
2fefa16c
EH		 2633static void pci_device_class_base_init(ObjectClass *klass, void *data)
2634{
2635 if (!object_class_is_abstract(klass)) {
2636 ObjectClass *conventional =
2637 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE);
2638 ObjectClass *pcie =
2639 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE);
2640 assert(conventional || pcie);
2641 }
2642}
2643
9eda7d37
AK		 2644AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2645{
fd56e061 2646 PCIBus *bus = pci_get_bus(dev);
5af2ae23 2647 PCIBus *iommu_bus = bus;
9eda7d37 2648
5af2ae23 2649 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) {
fd56e061 2650 iommu_bus = pci_get_bus(iommu_bus->parent_dev);
9eda7d37 2651 }
5af2ae23
BH		 2652 if (iommu_bus && iommu_bus->iommu_fn) {
2653 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn);
9eda7d37 2654 }
9eda7d37
AK		 2655 return &address_space_memory;
2656}
2657
e00387d5 2658void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
5fa45de5 2659{
e00387d5
AK		 2660 bus->iommu_fn = fn;
2661 bus->iommu_opaque = opaque;
5fa45de5
DG		 2662}
2663
43864069
MT		 2664static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2665{
2666 Range *range = opaque;
2667 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2668 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
77d6f4ea 2669 int i;
43864069
MT		 2670
2671 if (!(cmd & PCI_COMMAND_MEMORY)) {
2672 return;
2673 }
2674
2675 if (pc->is_bridge) {
2676 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2677 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2678
2679 base = MAX(base, 0x1ULL << 32);
2680
2681 if (limit >= base) {
2682 Range pref_range;
a0efbf16 2683 range_set_bounds(&pref_range, base, limit);
43864069
MT		 2684 range_extend(range, &pref_range);
2685 }
2686 }
77d6f4ea
MT		 2687 for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2688 PCIIORegion *r = &dev->io_regions[i];
a0efbf16 2689 pcibus_t lob, upb;
43864069
MT		 2690 Range region_range;
2691
77d6f4ea
MT		 2692 if (!r->size ||
2693 (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2694 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2695 continue;
2696 }
77d6f4ea 2697
a0efbf16
MA		 2698 lob = pci_bar_address(dev, i, r->type, r->size);
2699 upb = lob + r->size - 1;
2700 if (lob == PCI_BAR_UNMAPPED) {
43864069
MT		 2701 continue;
2702 }
43864069 2703
a0efbf16 2704 lob = MAX(lob, 0x1ULL << 32);
43864069 2705
a0efbf16
MA		 2706 if (upb >= lob) {
2707 range_set_bounds(&region_range, lob, upb);
43864069
MT		 2708 range_extend(range, &region_range);
2709 }
2710 }
2711}
2712
2713void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2714{
a0efbf16 2715 range_make_empty(range);
43864069
MT		 2716 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2717}
2718
3f1e1478
C		 2719static bool pcie_has_upstream_port(PCIDevice *dev)
2720{
fd56e061 2721 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev));
3f1e1478
C		 2722
2723 /* Device associated with an upstream port.
2724 * As there are several types of these, it's easier to check the
2725 * parent device: upstream ports are always connected to
2726 * root or downstream ports.
2727 */
2728 return parent_dev &&
2729 pci_is_express(parent_dev) &&
2730 parent_dev->exp.exp_cap &&
2731 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT ||
2732 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM);
2733}
2734
2735PCIDevice *pci_get_function_0(PCIDevice *pci_dev)
2736{
fd56e061
DG		 2737 PCIBus *bus = pci_get_bus(pci_dev);
2738
3f1e1478
C		 2739 if(pcie_has_upstream_port(pci_dev)) {
2740 /* With an upstream PCIe port, we only support 1 device at slot 0 */
fd56e061 2741 return bus->devices[0];
3f1e1478
C		 2742 } else {
2743 /* Other bus types might support multiple devices at slots 0-31 */
fd56e061 2744 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)];
3f1e1478
C		 2745 }
2746}
2747
e1d4fb2d
PX		 2748MSIMessage pci_get_msi_message(PCIDevice *dev, int vector)
2749{
2750 MSIMessage msg;
2751 if (msix_enabled(dev)) {
2752 msg = msix_get_message(dev, vector);
2753 } else if (msi_enabled(dev)) {
2754 msg = msi_get_message(dev, vector);
2755 } else {
2756 /* Should never happen */
2757 error_report("%s: unknown interrupt type", __func__);
2758 abort();
2759 }
2760 return msg;
2761}
2762
8c43a6f0 2763static const TypeInfo pci_device_type_info = {
40021f08
AL		 2764 .name = TYPE_PCI_DEVICE,
2765 .parent = TYPE_DEVICE,
2766 .instance_size = sizeof(PCIDevice),
2767 .abstract = true,
2768 .class_size = sizeof(PCIDeviceClass),
39bffca2 2769 .class_init = pci_device_class_init,
2fefa16c 2770 .class_base_init = pci_device_class_base_init,
40021f08
AL		 2771};
2772
83f7d43a 2773static void pci_register_types(void)
40021f08 2774{
0d936928 2775 type_register_static(&pci_bus_info);
3a861c46 2776 type_register_static(&pcie_bus_info);
619f02ae
EH		 2777 type_register_static(&conventional_pci_interface_info);
2778 type_register_static(&pcie_interface_info);
40021f08
AL		 2779 type_register_static(&pci_device_type_info);
2780}
2781
83f7d43a 2782type_init(pci_register_types)
Empty description
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