]> Git Repo - qemu.git/blame - hw/pci/pci.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
PCI: PCIe access should always be little endian
[qemu.git] / hw / pci / pci.c
CommitLineData
69b91039
FB		 1/*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5fafdf24 5 *
69b91039
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
97d5408f 24#include "qemu/osdep.h"
c759b24f
MT		 25#include "hw/hw.h"
26#include "hw/pci/pci.h"
27#include "hw/pci/pci_bridge.h"
06aac7bd 28#include "hw/pci/pci_bus.h"
568f0690 29#include "hw/pci/pci_host.h"
83c9089e 30#include "monitor/monitor.h"
1422e32d 31#include "net/net.h"
9c17d615 32#include "sysemu/sysemu.h"
c759b24f 33#include "hw/loader.h"
d49b6836 34#include "qemu/error-report.h"
1de7afc9 35#include "qemu/range.h"
79627472 36#include "qmp-commands.h"
7828d750 37#include "trace.h"
c759b24f
MT		 38#include "hw/pci/msi.h"
39#include "hw/pci/msix.h"
022c62cb 40#include "exec/address-spaces.h"
5e954943 41#include "hw/hotplug.h"
e4024630 42#include "hw/boards.h"
f348b6d1 43#include "qemu/cutils.h"
69b91039
FB		 44
45//#define DEBUG_PCI
d8d2e079 46#ifdef DEBUG_PCI
2e49d64a 47# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
d8d2e079
IY		 48#else
49# define PCI_DPRINTF(format, ...) do { } while (0)
50#endif
69b91039 51
88c725c7
CH		 52bool pci_available = true;
53
10c4c98a 54static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
4f43c1ff 55static char *pcibus_get_dev_path(DeviceState *dev);
5e0259e7 56static char *pcibus_get_fw_dev_path(DeviceState *dev);
dcc20931 57static void pcibus_reset(BusState *qbus);
10c4c98a 58
3cb75a7c
PB		 59static Property pci_props[] = {
60 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
61 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
62 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
63 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
64 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
65 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
66 QEMU_PCI_CAP_SERR_BITNR, true),
6b449540
MT		 67 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
68 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),
f03d8ea3
MA		 69 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
70 QEMU_PCIE_EXTCAP_INIT_BITNR, true),
3cb75a7c
PB		 71 DEFINE_PROP_END_OF_LIST()
72};
73
d2f69df7
BD		 74static const VMStateDescription vmstate_pcibus = {
75 .name = "PCIBUS",
76 .version_id = 1,
77 .minimum_version_id = 1,
d49805ae 78 .fields = (VMStateField[]) {
d2164ad3 79 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL),
d2f69df7
BD		 80 VMSTATE_VARRAY_INT32(irq_count, PCIBus,
81 nirq, 0, vmstate_info_int32,
82 int32_t),
83 VMSTATE_END_OF_LIST()
84 }
85};
86
b86eacb8
MA		 87static void pci_init_bus_master(PCIDevice *pci_dev)
88{
89 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev);
90
91 memory_region_init_alias(&pci_dev->bus_master_enable_region,
92 OBJECT(pci_dev), "bus master",
93 dma_as->root, 0, memory_region_size(dma_as->root));
94 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
3716d590
JW		 95 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0,
96 &pci_dev->bus_master_enable_region);
b86eacb8
MA		 97}
98
99static void pcibus_machine_done(Notifier *notifier, void *data)
100{
101 PCIBus *bus = container_of(notifier, PCIBus, machine_done);
102 int i;
103
104 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
105 if (bus->devices[i]) {
106 pci_init_bus_master(bus->devices[i]);
107 }
108 }
109}
110
d2f69df7
BD		 111static void pci_bus_realize(BusState *qbus, Error **errp)
112{
113 PCIBus *bus = PCI_BUS(qbus);
114
b86eacb8
MA		 115 bus->machine_done.notify = pcibus_machine_done;
116 qemu_add_machine_init_done_notifier(&bus->machine_done);
117
d2f69df7
BD		 118 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
119}
120
121static void pci_bus_unrealize(BusState *qbus, Error **errp)
122{
123 PCIBus *bus = PCI_BUS(qbus);
124
b86eacb8
MA		 125 qemu_remove_machine_init_done_notifier(&bus->machine_done);
126
d2f69df7
BD		 127 vmstate_unregister(NULL, &vmstate_pcibus, bus);
128}
129
ce6a28ee
MA		 130static bool pcibus_is_root(PCIBus *bus)
131{
132 return !bus->parent_dev;
133}
134
602141d9
MA		 135static int pcibus_num(PCIBus *bus)
136{
137 if (pcibus_is_root(bus)) {
138 return 0; /* pci host bridge */
139 }
140 return bus->parent_dev->config[PCI_SECONDARY_BUS];
141}
142
6a3042b2
MA		 143static uint16_t pcibus_numa_node(PCIBus *bus)
144{
145 return NUMA_NODE_UNASSIGNED;
146}
147
0d936928
AL		 148static void pci_bus_class_init(ObjectClass *klass, void *data)
149{
150 BusClass *k = BUS_CLASS(klass);
ce6a28ee 151 PCIBusClass *pbc = PCI_BUS_CLASS(klass);
0d936928
AL		 152
153 k->print_dev = pcibus_dev_print;
154 k->get_dev_path = pcibus_get_dev_path;
155 k->get_fw_dev_path = pcibus_get_fw_dev_path;
d2f69df7
BD		 156 k->realize = pci_bus_realize;
157 k->unrealize = pci_bus_unrealize;
0d936928 158 k->reset = pcibus_reset;
ce6a28ee
MA		 159
160 pbc->is_root = pcibus_is_root;
602141d9 161 pbc->bus_num = pcibus_num;
6a3042b2 162 pbc->numa_node = pcibus_numa_node;
0d936928
AL		 163}
164
165static const TypeInfo pci_bus_info = {
166 .name = TYPE_PCI_BUS,
167 .parent = TYPE_BUS,
168 .instance_size = sizeof(PCIBus),
ce6a28ee 169 .class_size = sizeof(PCIBusClass),
0d936928 170 .class_init = pci_bus_class_init,
30468f78 171};
69b91039 172
3a861c46
AW		 173static const TypeInfo pcie_bus_info = {
174 .name = TYPE_PCIE_BUS,
175 .parent = TYPE_PCI_BUS,
176};
177
d662210a 178static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
1941d19c 179static void pci_update_mappings(PCIDevice *d);
d98f08f5 180static void pci_irq_handler(void *opaque, int irq_num, int level);
133e9b22 181static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
230741dc 182static void pci_del_option_rom(PCIDevice *pdev);
1941d19c 183
d350d97d
AL		 184static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
185static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
e822a52a 186
7588e2b0 187static QLIST_HEAD(, PCIHostState) pci_host_bridges;
30468f78 188
cf8c704d 189int pci_bar(PCIDevice *d, int reg)
5330de09 190{
b3b11697
IY		 191 uint8_t type;
192
193 if (reg != PCI_ROM_SLOT)
194 return PCI_BASE_ADDRESS_0 + reg * 4;
195
196 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
197 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
5330de09
MT		 198}
199
d036bb21
MT		 200static inline int pci_irq_state(PCIDevice *d, int irq_num)
201{
202 return (d->irq_state >> irq_num) & 0x1;
203}
204
205static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
206{
207 d->irq_state &= ~(0x1 << irq_num);
208 d->irq_state |= level << irq_num;
209}
210
211static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
212{
213 PCIBus *bus;
214 for (;;) {
215 bus = pci_dev->bus;
216 irq_num = bus->map_irq(pci_dev, irq_num);
217 if (bus->set_irq)
218 break;
219 pci_dev = bus->parent_dev;
220 }
221 bus->irq_count[irq_num] += change;
222 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
223}
224
9ddf8437
IY		 225int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
226{
227 assert(irq_num >= 0);
228 assert(irq_num < bus->nirq);
229 return !!bus->irq_count[irq_num];
230}
231
f9bf77dd
MT		 232/* Update interrupt status bit in config space on interrupt
233 * state change. */
234static void pci_update_irq_status(PCIDevice *dev)
235{
236 if (dev->irq_state) {
237 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
238 } else {
239 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
240 }
241}
242
4c92325b
IY		 243void pci_device_deassert_intx(PCIDevice *dev)
244{
245 int i;
246 for (i = 0; i < PCI_NUM_PINS; ++i) {
d98f08f5 247 pci_irq_handler(dev, i, 0);
4c92325b
IY		 248 }
249}
250
dcc20931 251static void pci_do_device_reset(PCIDevice *dev)
5330de09 252{
c0b1905b 253 int r;
6fc4925b 254
4c92325b 255 pci_device_deassert_intx(dev);
58b59014
CR		 256 assert(dev->irq_state == 0);
257
ebabb67a 258 /* Clear all writable bits */
99443c21 259 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
f9aebe2e
MT		 260 pci_get_word(dev->wmask + PCI_COMMAND) |
261 pci_get_word(dev->w1cmask + PCI_COMMAND));
89d437df
IY		 262 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
263 pci_get_word(dev->wmask + PCI_STATUS) |
264 pci_get_word(dev->w1cmask + PCI_STATUS));
c0b1905b
MT		 265 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
266 dev->config[PCI_INTERRUPT_LINE] = 0x0;
267 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
71ebd6dc
IY		 268 PCIIORegion *region = &dev->io_regions[r];
269 if (!region->size) {
c0b1905b
MT		 270 continue;
271 }
71ebd6dc
IY		 272
273 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
274 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
275 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
276 } else {
277 pci_set_long(dev->config + pci_bar(dev, r), region->type);
278 }
c0b1905b
MT		 279 }
280 pci_update_mappings(dev);
cbd2d434
JK		 281
282 msi_reset(dev);
283 msix_reset(dev);
5330de09
MT		 284}
285
dcc20931
PB		 286/*
287 * This function is called on #RST and FLR.
288 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
289 */
290void pci_device_reset(PCIDevice *dev)
291{
292 qdev_reset_all(&dev->qdev);
293 pci_do_device_reset(dev);
294}
295
9bb33586
IY		 296/*
297 * Trigger pci bus reset under a given bus.
dcc20931
PB		 298 * Called via qbus_reset_all on RST# assert, after the devices
299 * have been reset qdev_reset_all-ed already.
9bb33586 300 */
dcc20931 301static void pcibus_reset(BusState *qbus)
6eaa6847 302{
81e3e75b 303 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
6eaa6847
GN		 304 int i;
305
5330de09
MT		 306 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
307 if (bus->devices[i]) {
dcc20931 308 pci_do_device_reset(bus->devices[i]);
5330de09 309 }
6eaa6847 310 }
9bb33586 311
9bdbbfc3
PB		 312 for (i = 0; i < bus->nirq; i++) {
313 assert(bus->irq_count[i] == 0);
314 }
9bb33586
IY		 315}
316
3dbc01ae 317static void pci_host_bus_register(DeviceState *host)
e822a52a 318{
3dbc01ae 319 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
7588e2b0
DG		 320
321 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
e822a52a
IY		 322}
323
1ef7a2a2 324PCIBus *pci_find_primary_bus(void)
e822a52a 325{
9bc47305 326 PCIBus *primary_bus = NULL;
7588e2b0 327 PCIHostState *host;
e822a52a 328
7588e2b0 329 QLIST_FOREACH(host, &pci_host_bridges, next) {
9bc47305
DG		 330 if (primary_bus) {
331 /* We have multiple root buses, refuse to select a primary */
332 return NULL;
e822a52a 333 }
9bc47305 334 primary_bus = host->bus;
e822a52a
IY		 335 }
336
9bc47305 337 return primary_bus;
e822a52a
IY		 338}
339
c473d18d 340PCIBus *pci_device_root_bus(const PCIDevice *d)
e075e788 341{
c473d18d 342 PCIBus *bus = d->bus;
e075e788 343
ce6a28ee
MA		 344 while (!pci_bus_is_root(bus)) {
345 d = bus->parent_dev;
346 assert(d != NULL);
347
e075e788
IY		 348 bus = d->bus;
349 }
350
c473d18d
DG		 351 return bus;
352}
353
568f0690 354const char *pci_root_bus_path(PCIDevice *dev)
c473d18d 355{
568f0690
DG		 356 PCIBus *rootbus = pci_device_root_bus(dev);
357 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
358 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
c473d18d 359
568f0690
DG		 360 assert(host_bridge->bus == rootbus);
361
362 if (hc->root_bus_path) {
363 return (*hc->root_bus_path)(host_bridge, rootbus);
e075e788
IY		 364 }
365
568f0690 366 return rootbus->qbus.name;
e075e788
IY		 367}
368
4fec6404 369static void pci_bus_init(PCIBus *bus, DeviceState *parent,
aee97b84
AK		 370 MemoryRegion *address_space_mem,
371 MemoryRegion *address_space_io,
1e39101c 372 uint8_t devfn_min)
30468f78 373{
6fa84913 374 assert(PCI_FUNC(devfn_min) == 0);
502a5395 375 bus->devfn_min = devfn_min;
8b884984 376 bus->slot_reserved_mask = 0x0;
5968eca3
AK		 377 bus->address_space_mem = address_space_mem;
378 bus->address_space_io = address_space_io;
e822a52a
IY		 379
380 /* host bridge */
381 QLIST_INIT(&bus->child);
2b8cc89a 382
3dbc01ae 383 pci_host_bus_register(parent);
21eea4b3
GH		 384}
385
8c0bf9e2
AW		 386bool pci_bus_is_express(PCIBus *bus)
387{
388 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
389}
390
0889464a
AW		 391bool pci_bus_is_root(PCIBus *bus)
392{
ce6a28ee 393 return PCI_BUS_GET_CLASS(bus)->is_root(bus);
0889464a
AW		 394}
395
dd301ca6 396void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
4fec6404
PB		 397 const char *name,
398 MemoryRegion *address_space_mem,
399 MemoryRegion *address_space_io,
60a0e443 400 uint8_t devfn_min, const char *typename)
4fec6404 401{
fb17dfe0 402 qbus_create_inplace(bus, bus_size, typename, parent, name);
9ae91bc4 403 pci_bus_init(bus, parent, address_space_mem, address_space_io, devfn_min);
4fec6404
PB		 404}
405
1e39101c 406PCIBus *pci_bus_new(DeviceState *parent, const char *name,
aee97b84
AK		 407 MemoryRegion *address_space_mem,
408 MemoryRegion *address_space_io,
60a0e443 409 uint8_t devfn_min, const char *typename)
21eea4b3
GH		 410{
411 PCIBus *bus;
412
60a0e443 413 bus = PCI_BUS(qbus_create(typename, parent, name));
9ae91bc4 414 pci_bus_init(bus, parent, address_space_mem, address_space_io, devfn_min);
21eea4b3
GH		 415 return bus;
416}
417
418void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
419 void *irq_opaque, int nirq)
420{
421 bus->set_irq = set_irq;
422 bus->map_irq = map_irq;
423 bus->irq_opaque = irq_opaque;
424 bus->nirq = nirq;
7267c094 425 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
21eea4b3
GH		 426}
427
428PCIBus *pci_register_bus(DeviceState *parent, const char *name,
429 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
1e39101c 430 void *irq_opaque,
aee97b84
AK		 431 MemoryRegion *address_space_mem,
432 MemoryRegion *address_space_io,
60a0e443 433 uint8_t devfn_min, int nirq, const char *typename)
21eea4b3
GH		 434{
435 PCIBus *bus;
436
aee97b84 437 bus = pci_bus_new(parent, name, address_space_mem,
60a0e443 438 address_space_io, devfn_min, typename);
21eea4b3 439 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
30468f78
FB		 440 return bus;
441}
69b91039 442
502a5395
PB		 443int pci_bus_num(PCIBus *s)
444{
602141d9 445 return PCI_BUS_GET_CLASS(s)->bus_num(s);
502a5395
PB		 446}
447
6a3042b2
MA		 448int pci_bus_numa_node(PCIBus *bus)
449{
450 return PCI_BUS_GET_CLASS(bus)->numa_node(bus);
502a5395
PB		 451}
452
2c21ee76
JD		 453static int get_pci_config_device(QEMUFile *f, void *pv, size_t size,
454 VMStateField *field)
30ca2aab 455{
73534f2f 456 PCIDevice *s = container_of(pv, PCIDevice, config);
e78e9ae4 457 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
a9f49946 458 uint8_t *config;
52fc1d83
AZ		 459 int i;
460
a9f49946 461 assert(size == pci_config_size(s));
7267c094 462 config = g_malloc(size);
a9f49946
IY		 463
464 qemu_get_buffer(f, config, size);
465 for (i = 0; i < size; ++i) {
f9aebe2e
MT		 466 if ((config[i] ^ s->config[i]) &
467 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
7c59364d
DDAG		 468 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
469 "cmask: %x wmask: %x w1cmask:%x", __func__,
470 i, config[i], s->config[i],
471 s->cmask[i], s->wmask[i], s->w1cmask[i]);
7267c094 472 g_free(config);
bd4b65ee 473 return -EINVAL;
a9f49946
IY		 474 }
475 }
476 memcpy(s->config, config, size);
bd4b65ee 477
1941d19c 478 pci_update_mappings(s);
e78e9ae4 479 if (pc->is_bridge) {
f055e96b 480 PCIBridge *b = PCI_BRIDGE(s);
e78e9ae4
DK		 481 pci_bridge_update_mappings(b);
482 }
52fc1d83 483
4ea375bf
GH		 484 memory_region_set_enabled(&s->bus_master_enable_region,
485 pci_get_word(s->config + PCI_COMMAND)
486 & PCI_COMMAND_MASTER);
487
7267c094 488 g_free(config);
30ca2aab
FB		 489 return 0;
490}
491
73534f2f 492/* just put buffer */
2c21ee76
JD		 493static int put_pci_config_device(QEMUFile *f, void *pv, size_t size,
494 VMStateField *field, QJSON *vmdesc)
73534f2f 495{
dbe73d7f 496 const uint8_t **v = pv;
a9f49946 497 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
dbe73d7f 498 qemu_put_buffer(f, *v, size);
2c21ee76
JD		 499
500 return 0;
73534f2f
JQ		 501}
502
503static VMStateInfo vmstate_info_pci_config = {
504 .name = "pci config",
505 .get = get_pci_config_device,
506 .put = put_pci_config_device,
507};
508
2c21ee76
JD		 509static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size,
510 VMStateField *field)
d036bb21 511{
c3f8f611 512 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
d036bb21
MT		 513 uint32_t irq_state[PCI_NUM_PINS];
514 int i;
515 for (i = 0; i < PCI_NUM_PINS; ++i) {
516 irq_state[i] = qemu_get_be32(f);
517 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
518 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
519 irq_state[i]);
520 return -EINVAL;
521 }
522 }
523
524 for (i = 0; i < PCI_NUM_PINS; ++i) {
525 pci_set_irq_state(s, i, irq_state[i]);
526 }
527
528 return 0;
529}
530
2c21ee76
JD		 531static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size,
532 VMStateField *field, QJSON *vmdesc)
d036bb21
MT		 533{
534 int i;
c3f8f611 535 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
d036bb21
MT		 536
537 for (i = 0; i < PCI_NUM_PINS; ++i) {
538 qemu_put_be32(f, pci_irq_state(s, i));
539 }
2c21ee76
JD		 540
541 return 0;
d036bb21
MT		 542}
543
544static VMStateInfo vmstate_info_pci_irq_state = {
545 .name = "pci irq state",
546 .get = get_pci_irq_state,
547 .put = put_pci_irq_state,
548};
549
20daa90a
DDAG		 550static bool migrate_is_pcie(void *opaque, int version_id)
551{
552 return pci_is_express((PCIDevice *)opaque);
553}
554
555static bool migrate_is_not_pcie(void *opaque, int version_id)
556{
557 return !pci_is_express((PCIDevice *)opaque);
558}
559
73534f2f
JQ		 560const VMStateDescription vmstate_pci_device = {
561 .name = "PCIDevice",
562 .version_id = 2,
563 .minimum_version_id = 1,
d49805ae 564 .fields = (VMStateField[]) {
3476436a 565 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
20daa90a
DDAG		 566 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
567 migrate_is_not_pcie,
568 0, vmstate_info_pci_config,
a9f49946 569 PCI_CONFIG_SPACE_SIZE),
20daa90a
DDAG		 570 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
571 migrate_is_pcie,
572 0, vmstate_info_pci_config,
a9f49946 573 PCIE_CONFIG_SPACE_SIZE),
d036bb21
MT		 574 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
575 vmstate_info_pci_irq_state,
576 PCI_NUM_PINS * sizeof(int32_t)),
73534f2f
JQ		 577 VMSTATE_END_OF_LIST()
578 }
579};
580
a9f49946 581
73534f2f
JQ		 582void pci_device_save(PCIDevice *s, QEMUFile *f)
583{
f9bf77dd
MT		 584 /* Clear interrupt status bit: it is implicit
585 * in irq_state which we are saving.
586 * This makes us compatible with old devices
587 * which never set or clear this bit. */
588 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
20daa90a 589 vmstate_save_state(f, &vmstate_pci_device, s, NULL);
f9bf77dd
MT		 590 /* Restore the interrupt status bit. */
591 pci_update_irq_status(s);
73534f2f
JQ		 592}
593
594int pci_device_load(PCIDevice *s, QEMUFile *f)
595{
f9bf77dd 596 int ret;
20daa90a 597 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
f9bf77dd
MT		 598 /* Restore the interrupt status bit. */
599 pci_update_irq_status(s);
600 return ret;
73534f2f
JQ		 601}
602
5e434f4e 603static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
d350d97d 604{
5e434f4e
IY		 605 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
606 pci_default_sub_vendor_id);
607 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
608 pci_default_sub_device_id);
d350d97d
AL		 609}
610
880345c4 611/*
43c945f1
IY		 612 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
613 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
880345c4 614 */
6dbcb819
MA		 615static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
616 unsigned int *slotp, unsigned int *funcp)
880345c4
AL		 617{
618 const char *p;
619 char *e;
620 unsigned long val;
621 unsigned long dom = 0, bus = 0;
43c945f1
IY		 622 unsigned int slot = 0;
623 unsigned int func = 0;
880345c4
AL		 624
625 p = addr;
626 val = strtoul(p, &e, 16);
627 if (e == p)
628 return -1;
629 if (*e == ':') {
630 bus = val;
631 p = e + 1;
632 val = strtoul(p, &e, 16);
633 if (e == p)
634 return -1;
635 if (*e == ':') {
636 dom = bus;
637 bus = val;
638 p = e + 1;
639 val = strtoul(p, &e, 16);
640 if (e == p)
641 return -1;
642 }
643 }
644
880345c4
AL		 645 slot = val;
646
43c945f1
IY		 647 if (funcp != NULL) {
648 if (*e != '.')
649 return -1;
650
651 p = e + 1;
652 val = strtoul(p, &e, 16);
653 if (e == p)
654 return -1;
655
656 func = val;
657 }
658
659 /* if funcp == NULL func is 0 */
660 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
661 return -1;
662
880345c4
AL		 663 if (*e)
664 return -1;
665
880345c4
AL		 666 *domp = dom;
667 *busp = bus;
668 *slotp = slot;
43c945f1
IY		 669 if (funcp != NULL)
670 *funcp = func;
880345c4
AL		 671 return 0;
672}
673
6dbcb819
MA		 674static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root,
675 const char *devaddr)
5607c388
MA		 676{
677 int dom, bus;
678 unsigned slot;
679
1ef7a2a2
DG		 680 if (!root) {
681 fprintf(stderr, "No primary PCI bus\n");
682 return NULL;
683 }
684
b645000e
S		 685 assert(!root->parent_dev);
686
5607c388
MA		 687 if (!devaddr) {
688 *devfnp = -1;
1ef7a2a2 689 return pci_find_bus_nr(root, 0);
5607c388
MA		 690 }
691
43c945f1 692 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
5607c388
MA		 693 return NULL;
694 }
695
1ef7a2a2
DG		 696 if (dom != 0) {
697 fprintf(stderr, "No support for non-zero PCI domains\n");
698 return NULL;
699 }
700
6ff534b6 701 *devfnp = PCI_DEVFN(slot, 0);
1ef7a2a2 702 return pci_find_bus_nr(root, bus);
5607c388
MA		 703}
704
bd4b65ee
MT		 705static void pci_init_cmask(PCIDevice *dev)
706{
707 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
708 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
709 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
710 dev->cmask[PCI_REVISION_ID] = 0xff;
711 dev->cmask[PCI_CLASS_PROG] = 0xff;
712 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
713 dev->cmask[PCI_HEADER_TYPE] = 0xff;
714 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
715}
716
b7ee1603
MT		 717static void pci_init_wmask(PCIDevice *dev)
718{
a9f49946
IY		 719 int config_size = pci_config_size(dev);
720
b7ee1603
MT		 721 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
722 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
67a51b48 723 pci_set_word(dev->wmask + PCI_COMMAND,
a7b15a5c
MT		 724 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
725 PCI_COMMAND_INTX_DISABLE);
b1aeb926
IY		 726 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
727 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
728 }
3e21ffc9
IY		 729
730 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
731 config_size - PCI_CONFIG_HEADER_SIZE);
b7ee1603
MT		 732}
733
89d437df
IY		 734static void pci_init_w1cmask(PCIDevice *dev)
735{
736 /*
f6bdfcc9 737 * Note: It's okay to set w1cmask even for readonly bits as
89d437df
IY		 738 * long as their value is hardwired to 0.
739 */
740 pci_set_word(dev->w1cmask + PCI_STATUS,
741 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
742 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
743 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
744}
745
d5f27e88 746static void pci_init_mask_bridge(PCIDevice *d)
fb231628
IY		 747{
748 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
749 PCI_SEC_LETENCY_TIMER */
750 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
751
752 /* base and limit */
753 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
754 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
755 pci_set_word(d->wmask + PCI_MEMORY_BASE,
756 PCI_MEMORY_RANGE_MASK & 0xffff);
757 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
758 PCI_MEMORY_RANGE_MASK & 0xffff);
759 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
760 PCI_PREF_RANGE_MASK & 0xffff);
761 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
762 PCI_PREF_RANGE_MASK & 0xffff);
763
764 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
765 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
766
d5f27e88 767 /* Supported memory and i/o types */
68917102
MT		 768 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
769 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
d5f27e88
MT		 770 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
771 PCI_PREF_RANGE_TYPE_64);
772 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
773 PCI_PREF_RANGE_TYPE_64);
774
45eb768c
MT		 775 /*
776 * TODO: Bridges default to 10-bit VGA decoding but we currently only
777 * implement 16-bit decoding (no alias support).
778 */
f6bdfcc9
MT		 779 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
780 PCI_BRIDGE_CTL_PARITY |
781 PCI_BRIDGE_CTL_SERR |
782 PCI_BRIDGE_CTL_ISA |
783 PCI_BRIDGE_CTL_VGA |
784 PCI_BRIDGE_CTL_VGA_16BIT |
785 PCI_BRIDGE_CTL_MASTER_ABORT |
786 PCI_BRIDGE_CTL_BUS_RESET |
787 PCI_BRIDGE_CTL_FAST_BACK |
788 PCI_BRIDGE_CTL_DISCARD |
789 PCI_BRIDGE_CTL_SEC_DISCARD |
f6bdfcc9
MT		 790 PCI_BRIDGE_CTL_DISCARD_SERR);
791 /* Below does not do anything as we never set this bit, put here for
792 * completeness. */
793 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
794 PCI_BRIDGE_CTL_DISCARD_STATUS);
d5f27e88 795 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
15ab7a75 796 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
d5f27e88
MT		 797 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
798 PCI_PREF_RANGE_TYPE_MASK);
15ab7a75
MT		 799 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
800 PCI_PREF_RANGE_TYPE_MASK);
fb231628
IY		 801}
802
133e9b22 803static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
6eab3de1
IY		 804{
805 uint8_t slot = PCI_SLOT(dev->devfn);
806 uint8_t func;
807
808 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
809 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
810 }
811
812 /*
b0cd712c 813 * multifunction bit is interpreted in two ways as follows.
6eab3de1
IY		 814 * - all functions must set the bit to 1.
815 * Example: Intel X53
816 * - function 0 must set the bit, but the rest function (> 0)
817 * is allowed to leave the bit to 0.
818 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
819 *
820 * So OS (at least Linux) checks the bit of only function 0,
821 * and doesn't see the bit of function > 0.
822 *
823 * The below check allows both interpretation.
824 */
825 if (PCI_FUNC(dev->devfn)) {
826 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
827 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
828 /* function 0 should set multifunction bit */
133e9b22
MA		 829 error_setg(errp, "PCI: single function device can't be populated "
830 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
831 return;
6eab3de1 832 }
133e9b22 833 return;
6eab3de1
IY		 834 }
835
836 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
133e9b22 837 return;
6eab3de1
IY		 838 }
839 /* function 0 indicates single function, so function > 0 must be NULL */
840 for (func = 1; func < PCI_FUNC_MAX; ++func) {
841 if (bus->devices[PCI_DEVFN(slot, func)]) {
133e9b22
MA		 842 error_setg(errp, "PCI: %x.0 indicates single function, "
843 "but %x.%x is already populated.",
844 slot, slot, func);
845 return;
6eab3de1
IY		 846 }
847 }
6eab3de1
IY		 848}
849
a9f49946
IY		 850static void pci_config_alloc(PCIDevice *pci_dev)
851{
852 int config_size = pci_config_size(pci_dev);
853
7267c094
AL		 854 pci_dev->config = g_malloc0(config_size);
855 pci_dev->cmask = g_malloc0(config_size);
856 pci_dev->wmask = g_malloc0(config_size);
857 pci_dev->w1cmask = g_malloc0(config_size);
858 pci_dev->used = g_malloc0(config_size);
a9f49946
IY		 859}
860
861static void pci_config_free(PCIDevice *pci_dev)
862{
7267c094
AL		 863 g_free(pci_dev->config);
864 g_free(pci_dev->cmask);
865 g_free(pci_dev->wmask);
866 g_free(pci_dev->w1cmask);
867 g_free(pci_dev->used);
a9f49946
IY		 868}
869
30607764
MA		 870static void do_pci_unregister_device(PCIDevice *pci_dev)
871{
872 pci_dev->bus->devices[pci_dev->devfn] = NULL;
873 pci_config_free(pci_dev);
874
193982c6
AK		 875 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) {
876 memory_region_del_subregion(&pci_dev->bus_master_container_region,
877 &pci_dev->bus_master_enable_region);
878 }
30607764 879 address_space_destroy(&pci_dev->bus_master_as);
30607764
MA		 880}
881
4a94b3aa
PX		 882/* Extract PCIReqIDCache into BDF format */
883static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache)
884{
885 uint8_t bus_n;
886 uint16_t result;
887
888 switch (cache->type) {
889 case PCI_REQ_ID_BDF:
890 result = pci_get_bdf(cache->dev);
891 break;
892 case PCI_REQ_ID_SECONDARY_BUS:
893 bus_n = pci_bus_num(cache->dev->bus);
894 result = PCI_BUILD_BDF(bus_n, 0);
895 break;
896 default:
897 error_printf("Invalid PCI requester ID cache type: %d\n",
898 cache->type);
899 exit(1);
900 break;
901 }
902
903 return result;
904}
905
906/* Parse bridges up to the root complex and return requester ID
907 * cache for specific device. For full PCIe topology, the cache
908 * result would be exactly the same as getting BDF of the device.
909 * However, several tricks are required when system mixed up with
910 * legacy PCI devices and PCIe-to-PCI bridges.
911 *
912 * Here we cache the proxy device (and type) not requester ID since
913 * bus number might change from time to time.
914 */
915static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev)
916{
917 PCIDevice *parent;
918 PCIReqIDCache cache = {
919 .dev = dev,
920 .type = PCI_REQ_ID_BDF,
921 };
922
923 while (!pci_bus_is_root(dev->bus)) {
924 /* We are under PCI/PCIe bridges */
925 parent = dev->bus->parent_dev;
926 if (pci_is_express(parent)) {
927 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
928 /* When we pass through PCIe-to-PCI/PCIX bridges, we
929 * override the requester ID using secondary bus
930 * number of parent bridge with zeroed devfn
931 * (pcie-to-pci bridge spec chap 2.3). */
932 cache.type = PCI_REQ_ID_SECONDARY_BUS;
933 cache.dev = dev;
934 }
935 } else {
936 /* Legacy PCI, override requester ID with the bridge's
937 * BDF upstream. When the root complex connects to
938 * legacy PCI devices (including buses), it can only
939 * obtain requester ID info from directly attached
940 * devices. If devices are attached under bridges, only
941 * the requester ID of the bridge that is directly
942 * attached to the root complex can be recognized. */
943 cache.type = PCI_REQ_ID_BDF;
944 cache.dev = parent;
945 }
946 dev = parent;
947 }
948
949 return cache;
950}
951
952uint16_t pci_requester_id(PCIDevice *dev)
953{
954 return pci_req_id_cache_extract(&dev->requester_id_cache);
955}
956
9b717a3a
MCA		 957static bool pci_bus_devfn_available(PCIBus *bus, int devfn)
958{
959 return !(bus->devices[devfn]);
960}
961
8b884984
MCA		 962static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn)
963{
964 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn));
965}
966
69b91039 967/* -1 for devfn means auto assign */
6b1b92d3 968static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
133e9b22
MA		 969 const char *name, int devfn,
970 Error **errp)
69b91039 971{
40021f08
AL		 972 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
973 PCIConfigReadFunc *config_read = pc->config_read;
974 PCIConfigWriteFunc *config_write = pc->config_write;
133e9b22 975 Error *local_err = NULL;
3f1e1478
C		 976 DeviceState *dev = DEVICE(pci_dev);
977
978 pci_dev->bus = bus;
0144f6f1
MA		 979 /* Only pci bridges can be attached to extra PCI root buses */
980 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) {
981 error_setg(errp,
982 "PCI: Only PCI/PCIe bridges can be plugged into %s",
983 bus->parent_dev->name);
984 return NULL;
985 }
113f89df 986
69b91039 987 if (devfn < 0) {
b47b0706 988 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
6fa84913 989 devfn += PCI_FUNC_MAX) {
8b884984
MCA		 990 if (pci_bus_devfn_available(bus, devfn) &&
991 !pci_bus_devfn_reserved(bus, devfn)) {
69b91039 992 goto found;
9b717a3a 993 }
69b91039 994 }
8b884984
MCA		 995 error_setg(errp, "PCI: no slot/function available for %s, all in use "
996 "or reserved", name);
09e3acc6 997 return NULL;
69b91039 998 found: ;
8b884984
MCA		 999 } else if (pci_bus_devfn_reserved(bus, devfn)) {
1000 error_setg(errp, "PCI: slot %d function %d not available for %s,"
1001 " reserved",
1002 PCI_SLOT(devfn), PCI_FUNC(devfn), name);
1003 return NULL;
9b717a3a 1004 } else if (!pci_bus_devfn_available(bus, devfn)) {
133e9b22
MA		 1005 error_setg(errp, "PCI: slot %d function %d not available for %s,"
1006 " in use by %s",
1007 PCI_SLOT(devfn), PCI_FUNC(devfn), name,
1008 bus->devices[devfn]->name);
09e3acc6 1009 return NULL;
3f1e1478
C		 1010 } else if (dev->hotplugged &&
1011 pci_get_function_0(pci_dev)) {
1012 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s,"
1013 " new func %s cannot be exposed to guest.",
d93ddfb1
MT		 1014 PCI_SLOT(pci_get_function_0(pci_dev)->devfn),
1015 pci_get_function_0(pci_dev)->name,
3f1e1478
C		 1016 name);
1017
1018 return NULL;
69b91039 1019 }
e00387d5 1020
efc8188e 1021 pci_dev->devfn = devfn;
4a94b3aa 1022 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev);
e00387d5 1023
3716d590
JW		 1024 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
1025 "bus master container", UINT64_MAX);
1026 address_space_init(&pci_dev->bus_master_as,
1027 &pci_dev->bus_master_container_region, pci_dev->name);
1028
b86eacb8
MA		 1029 if (qdev_hotplug) {
1030 pci_init_bus_master(pci_dev);
1031 }
69b91039 1032 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
d036bb21 1033 pci_dev->irq_state = 0;
a9f49946 1034 pci_config_alloc(pci_dev);
fb231628 1035
40021f08
AL		 1036 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
1037 pci_config_set_device_id(pci_dev->config, pc->device_id);
1038 pci_config_set_revision(pci_dev->config, pc->revision);
1039 pci_config_set_class(pci_dev->config, pc->class_id);
113f89df 1040
40021f08
AL		 1041 if (!pc->is_bridge) {
1042 if (pc->subsystem_vendor_id || pc->subsystem_id) {
113f89df 1043 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
40021f08 1044 pc->subsystem_vendor_id);
113f89df 1045 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
40021f08 1046 pc->subsystem_id);
113f89df
IY		 1047 } else {
1048 pci_set_default_subsystem_id(pci_dev);
1049 }
1050 } else {
1051 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
40021f08
AL		 1052 assert(!pc->subsystem_vendor_id);
1053 assert(!pc->subsystem_id);
fb231628 1054 }
bd4b65ee 1055 pci_init_cmask(pci_dev);
b7ee1603 1056 pci_init_wmask(pci_dev);
89d437df 1057 pci_init_w1cmask(pci_dev);
40021f08 1058 if (pc->is_bridge) {
d5f27e88 1059 pci_init_mask_bridge(pci_dev);
fb231628 1060 }
133e9b22
MA		 1061 pci_init_multifunction(bus, pci_dev, &local_err);
1062 if (local_err) {
1063 error_propagate(errp, local_err);
30607764 1064 do_pci_unregister_device(pci_dev);
6eab3de1
IY		 1065 return NULL;
1066 }
0ac32c83
FB		 1067
1068 if (!config_read)
1069 config_read = pci_default_read_config;
1070 if (!config_write)
1071 config_write = pci_default_write_config;
69b91039
FB		 1072 pci_dev->config_read = config_read;
1073 pci_dev->config_write = config_write;
30468f78 1074 bus->devices[devfn] = pci_dev;
f16c4abf 1075 pci_dev->version_id = 2; /* Current pci device vmstate version */
69b91039
FB		 1076 return pci_dev;
1077}
1078
5851e08c
AL		 1079static void pci_unregister_io_regions(PCIDevice *pci_dev)
1080{
1081 PCIIORegion *r;
1082 int i;
1083
1084 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1085 r = &pci_dev->io_regions[i];
182f9c8a 1086 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
5851e08c 1087 continue;
03952339 1088 memory_region_del_subregion(r->address_space, r->memory);
5851e08c 1089 }
e01fd687
AW		 1090
1091 pci_unregister_vga(pci_dev);
5851e08c
AL		 1092}
1093
133e9b22 1094static void pci_qdev_unrealize(DeviceState *dev, Error **errp)
5851e08c 1095{
40021f08
AL		 1096 PCIDevice *pci_dev = PCI_DEVICE(dev);
1097 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
5851e08c
AL		 1098
1099 pci_unregister_io_regions(pci_dev);
230741dc 1100 pci_del_option_rom(pci_dev);
7cf1b0fd 1101
f90c2bcd
AW		 1102 if (pc->exit) {
1103 pc->exit(pci_dev);
1104 }
5851e08c 1105
3936161f 1106 pci_device_deassert_intx(pci_dev);
925fe64a 1107 do_pci_unregister_device(pci_dev);
5851e08c
AL		 1108}
1109
e824b2cc
AK		 1110void pci_register_bar(PCIDevice *pci_dev, int region_num,
1111 uint8_t type, MemoryRegion *memory)
69b91039
FB		 1112{
1113 PCIIORegion *r;
5178ecd8 1114 uint32_t addr; /* offset in pci config space */
5a9ff381 1115 uint64_t wmask;
cfc0be25 1116 pcibus_t size = memory_region_size(memory);
a4c20c6a 1117
2bbb9c2f
IY		 1118 assert(region_num >= 0);
1119 assert(region_num < PCI_NUM_REGIONS);
a4c20c6a
AL		 1120 if (size & (size-1)) {
1121 fprintf(stderr, "ERROR: PCI region size must be pow2 "
89e8b13c 1122 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
a4c20c6a
AL		 1123 exit(1);
1124 }
1125
69b91039 1126 r = &pci_dev->io_regions[region_num];
182f9c8a 1127 r->addr = PCI_BAR_UNMAPPED;
69b91039
FB		 1128 r->size = size;
1129 r->type = type;
5178ecd8
C		 1130 r->memory = memory;
1131 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO
1132 ? pci_dev->bus->address_space_io
1133 : pci_dev->bus->address_space_mem;
b7ee1603
MT		 1134
1135 wmask = ~(size - 1);
d7ce493a 1136 if (region_num == PCI_ROM_SLOT) {
ebabb67a 1137 /* ROM enable bit is writable */
5330de09 1138 wmask |= PCI_ROM_ADDRESS_ENABLE;
d7ce493a 1139 }
5178ecd8
C		 1140
1141 addr = pci_bar(pci_dev, region_num);
b0ff8eb2 1142 pci_set_long(pci_dev->config + addr, type);
5178ecd8 1143
14421258
IY		 1144 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
1145 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1146 pci_set_quad(pci_dev->wmask + addr, wmask);
1147 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
1148 } else {
1149 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
1150 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
1151 }
79ff8cb0
AK		 1152}
1153
e01fd687
AW		 1154static void pci_update_vga(PCIDevice *pci_dev)
1155{
1156 uint16_t cmd;
1157
1158 if (!pci_dev->has_vga) {
1159 return;
1160 }
1161
1162 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
1163
1164 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
1165 cmd & PCI_COMMAND_MEMORY);
1166 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
1167 cmd & PCI_COMMAND_IO);
1168 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
1169 cmd & PCI_COMMAND_IO);
1170}
1171
1172void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
1173 MemoryRegion *io_lo, MemoryRegion *io_hi)
1174{
1175 assert(!pci_dev->has_vga);
1176
1177 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
1178 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
1179 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem,
1180 QEMU_PCI_VGA_MEM_BASE, mem, 1);
1181
1182 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
1183 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
1184 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
1185 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
1186
1187 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
1188 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
1189 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
1190 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
1191 pci_dev->has_vga = true;
1192
1193 pci_update_vga(pci_dev);
1194}
1195
1196void pci_unregister_vga(PCIDevice *pci_dev)
1197{
1198 if (!pci_dev->has_vga) {
1199 return;
1200 }
1201
1202 memory_region_del_subregion(pci_dev->bus->address_space_mem,
1203 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1204 memory_region_del_subregion(pci_dev->bus->address_space_io,
1205 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1206 memory_region_del_subregion(pci_dev->bus->address_space_io,
1207 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1208 pci_dev->has_vga = false;
1209}
1210
16a96f28
AK		 1211pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1212{
1213 return pci_dev->io_regions[region_num].addr;
1214}
1215
876a350d
MT		 1216static pcibus_t pci_bar_address(PCIDevice *d,
1217 int reg, uint8_t type, pcibus_t size)
1218{
1219 pcibus_t new_addr, last_addr;
1220 int bar = pci_bar(d, reg);
1221 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
e4024630
LV		 1222 Object *machine = qdev_get_machine();
1223 ObjectClass *oc = object_get_class(machine);
1224 MachineClass *mc = MACHINE_CLASS(oc);
1225 bool allow_0_address = mc->pci_allow_0_address;
876a350d
MT		 1226
1227 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1228 if (!(cmd & PCI_COMMAND_IO)) {
1229 return PCI_BAR_UNMAPPED;
1230 }
1231 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1232 last_addr = new_addr + size - 1;
9f1a029a
HP		 1233 /* Check if 32 bit BAR wraps around explicitly.
1234 * TODO: make priorities correct and remove this work around.
1235 */
e4024630
LV		 1236 if (last_addr <= new_addr || last_addr >= UINT32_MAX ||
1237 (!allow_0_address && new_addr == 0)) {
876a350d
MT		 1238 return PCI_BAR_UNMAPPED;
1239 }
1240 return new_addr;
1241 }
1242
1243 if (!(cmd & PCI_COMMAND_MEMORY)) {
1244 return PCI_BAR_UNMAPPED;
1245 }
1246 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1247 new_addr = pci_get_quad(d->config + bar);
1248 } else {
1249 new_addr = pci_get_long(d->config + bar);
1250 }
1251 /* the ROM slot has a specific enable bit */
1252 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1253 return PCI_BAR_UNMAPPED;
1254 }
1255 new_addr &= ~(size - 1);
1256 last_addr = new_addr + size - 1;
1257 /* NOTE: we do not support wrapping */
1258 /* XXX: as we cannot support really dynamic
1259 mappings, we handle specific values as invalid
1260 mappings. */
e4024630
LV		 1261 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED ||
1262 (!allow_0_address && new_addr == 0)) {
876a350d
MT		 1263 return PCI_BAR_UNMAPPED;
1264 }
1265
1266 /* Now pcibus_t is 64bit.
1267 * Check if 32 bit BAR wraps around explicitly.
1268 * Without this, PC ide doesn't work well.
1269 * TODO: remove this work around.
1270 */
1271 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1272 return PCI_BAR_UNMAPPED;
1273 }
1274
1275 /*
1276 * OS is allowed to set BAR beyond its addressable
1277 * bits. For example, 32 bit OS can set 64bit bar
1278 * to >4G. Check it. TODO: we might need to support
1279 * it in the future for e.g. PAE.
1280 */
a8170e5e 1281 if (last_addr >= HWADDR_MAX) {
876a350d
MT		 1282 return PCI_BAR_UNMAPPED;
1283 }
1284
1285 return new_addr;
1286}
1287
0ac32c83
FB		 1288static void pci_update_mappings(PCIDevice *d)
1289{
1290 PCIIORegion *r;
876a350d 1291 int i;
7df32ca0 1292 pcibus_t new_addr;
3b46e624 1293
8a8696a3 1294 for(i = 0; i < PCI_NUM_REGIONS; i++) {
0ac32c83 1295 r = &d->io_regions[i];
a9688570
IY		 1296
1297 /* this region isn't registered */
ec503442 1298 if (!r->size)
a9688570
IY		 1299 continue;
1300
876a350d 1301 new_addr = pci_bar_address(d, i, r->type, r->size);
a9688570
IY		 1302
1303 /* This bar isn't changed */
7df32ca0 1304 if (new_addr == r->addr)
a9688570
IY		 1305 continue;
1306
1307 /* now do the real mapping */
1308 if (r->addr != PCI_BAR_UNMAPPED) {
7828d750 1309 trace_pci_update_mappings_del(d, pci_bus_num(d->bus),
7828d750 1310 PCI_SLOT(d->devfn),
0f288f85 1311 PCI_FUNC(d->devfn),
7828d750 1312 i, r->addr, r->size);
03952339 1313 memory_region_del_subregion(r->address_space, r->memory);
0ac32c83 1314 }
a9688570
IY		 1315 r->addr = new_addr;
1316 if (r->addr != PCI_BAR_UNMAPPED) {
7828d750 1317 trace_pci_update_mappings_add(d, pci_bus_num(d->bus),
7828d750 1318 PCI_SLOT(d->devfn),
0f288f85 1319 PCI_FUNC(d->devfn),
7828d750 1320 i, r->addr, r->size);
8b881e77
AK		 1321 memory_region_add_subregion_overlap(r->address_space,
1322 r->addr, r->memory, 1);
a9688570 1323 }
0ac32c83 1324 }
e01fd687
AW		 1325
1326 pci_update_vga(d);
0ac32c83
FB		 1327}
1328
a7b15a5c
MT		 1329static inline int pci_irq_disabled(PCIDevice *d)
1330{
1331 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1332}
1333
1334/* Called after interrupt disabled field update in config space,
1335 * assert/deassert interrupts if necessary.
1336 * Gets original interrupt disable bit value (before update). */
1337static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1338{
1339 int i, disabled = pci_irq_disabled(d);
1340 if (disabled == was_irq_disabled)
1341 return;
1342 for (i = 0; i < PCI_NUM_PINS; ++i) {
1343 int state = pci_irq_state(d, i);
1344 pci_change_irq_level(d, i, disabled ? -state : state);
1345 }
1346}
1347
5fafdf24 1348uint32_t pci_default_read_config(PCIDevice *d,
0ac32c83 1349 uint32_t address, int len)
69b91039 1350{
5029fe12 1351 uint32_t val = 0;
42e4126b 1352
5029fe12
IY		 1353 memcpy(&val, d->config + address, len);
1354 return le32_to_cpu(val);
0ac32c83
FB		 1355}
1356
d7efb7e0 1357void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
0ac32c83 1358{
a7b15a5c 1359 int i, was_irq_disabled = pci_irq_disabled(d);
d7efb7e0 1360 uint32_t val = val_in;
0ac32c83 1361
42e4126b 1362 for (i = 0; i < l; val >>= 8, ++i) {
91011d4f 1363 uint8_t wmask = d->wmask[addr + i];
92ba5f51
IY		 1364 uint8_t w1cmask = d->w1cmask[addr + i];
1365 assert(!(wmask & w1cmask));
91011d4f 1366 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
92ba5f51 1367 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
0ac32c83 1368 }
260c0cd3 1369 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
edb00035
IY		 1370 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1371 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
260c0cd3 1372 range_covers_byte(addr, l, PCI_COMMAND))
0ac32c83 1373 pci_update_mappings(d);
a7b15a5c 1374
1c380f94 1375 if (range_covers_byte(addr, l, PCI_COMMAND)) {
a7b15a5c 1376 pci_update_irq_disabled(d, was_irq_disabled);
1c380f94
AK		 1377 memory_region_set_enabled(&d->bus_master_enable_region,
1378 pci_get_word(d->config + PCI_COMMAND)
1379 & PCI_COMMAND_MASTER);
1380 }
95d65800 1381
d7efb7e0
KO		 1382 msi_write_config(d, addr, val_in, l);
1383 msix_write_config(d, addr, val_in, l);
69b91039
FB		 1384}
1385
502a5395
PB		 1386/***********************************************************/
1387/* generic PCI irq support */
30468f78 1388
502a5395 1389/* 0 <= irq_num <= 3. level must be 0 or 1 */
d98f08f5 1390static void pci_irq_handler(void *opaque, int irq_num, int level)
69b91039 1391{
a60380a5 1392 PCIDevice *pci_dev = opaque;
80b3ada7 1393 int change;
3b46e624 1394
d036bb21 1395 change = level - pci_irq_state(pci_dev, irq_num);
80b3ada7
PB		 1396 if (!change)
1397 return;
d2b59317 1398
d036bb21 1399 pci_set_irq_state(pci_dev, irq_num, level);
f9bf77dd 1400 pci_update_irq_status(pci_dev);
a7b15a5c
MT		 1401 if (pci_irq_disabled(pci_dev))
1402 return;
d036bb21 1403 pci_change_irq_level(pci_dev, irq_num, change);
69b91039
FB		 1404}
1405
d98f08f5
MA		 1406static inline int pci_intx(PCIDevice *pci_dev)
1407{
1408 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1409}
1410
1411qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1412{
1413 int intx = pci_intx(pci_dev);
1414
1415 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1416}
1417
1418void pci_set_irq(PCIDevice *pci_dev, int level)
1419{
1420 int intx = pci_intx(pci_dev);
1421 pci_irq_handler(pci_dev, intx, level);
1422}
1423
3afa9bb4
MT		 1424/* Special hooks used by device assignment */
1425void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1426{
0889464a 1427 assert(pci_bus_is_root(bus));
3afa9bb4
MT		 1428 bus->route_intx_to_irq = route_intx_to_irq;
1429}
1430
1431PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1432{
1433 PCIBus *bus;
1434
1435 do {
1436 bus = dev->bus;
1437 pin = bus->map_irq(dev, pin);
1438 dev = bus->parent_dev;
1439 } while (dev);
05c0621e
AW		 1440
1441 if (!bus->route_intx_to_irq) {
312fd5f2 1442 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
05c0621e
AW		 1443 object_get_typename(OBJECT(bus->qbus.parent)));
1444 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1445 }
1446
3afa9bb4 1447 return bus->route_intx_to_irq(bus->irq_opaque, pin);
0ae16251
JK		 1448}
1449
d6e65d54
AW		 1450bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1451{
1452 return old->mode != new->mode || old->irq != new->irq;
1453}
1454
0ae16251
JK		 1455void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1456{
1457 PCIDevice *dev;
1458 PCIBus *sec;
1459 int i;
1460
1461 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1462 dev = bus->devices[i];
1463 if (dev && dev->intx_routing_notifier) {
1464 dev->intx_routing_notifier(dev);
1465 }
e5368f0d
AW		 1466 }
1467
1468 QLIST_FOREACH(sec, &bus->child, sibling) {
1469 pci_bus_fire_intx_routing_notifier(sec);
0ae16251
JK		 1470 }
1471}
1472
1473void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1474 PCIINTxRoutingNotifier notifier)
1475{
1476 dev->intx_routing_notifier = notifier;
69b91039
FB		 1477}
1478
91e56159
IY		 1479/*
1480 * PCI-to-PCI bridge specification
1481 * 9.1: Interrupt routing. Table 9-1
1482 *
1483 * the PCI Express Base Specification, Revision 2.1
1484 * 2.2.8.1: INTx interrutp signaling - Rules
1485 * the Implementation Note
1486 * Table 2-20
1487 */
1488/*
1489 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1490 * 0-origin unlike PCI interrupt pin register.
1491 */
1492int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1493{
1494 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
1495}
1496
502a5395
PB		 1497/***********************************************************/
1498/* monitor info on PCI */
0ac32c83 1499
6650ee6d
PB		 1500typedef struct {
1501 uint16_t class;
1502 const char *desc;
5e0259e7
GN		 1503 const char *fw_name;
1504 uint16_t fw_ign_bits;
6650ee6d
PB		 1505} pci_class_desc;
1506
09bc878a 1507static const pci_class_desc pci_class_descriptions[] =
6650ee6d 1508{
5e0259e7
GN		 1509 { 0x0001, "VGA controller", "display"},
1510 { 0x0100, "SCSI controller", "scsi"},
1511 { 0x0101, "IDE controller", "ide"},
1512 { 0x0102, "Floppy controller", "fdc"},
1513 { 0x0103, "IPI controller", "ipi"},
1514 { 0x0104, "RAID controller", "raid"},
dcb5b19a
TS		 1515 { 0x0106, "SATA controller"},
1516 { 0x0107, "SAS controller"},
1517 { 0x0180, "Storage controller"},
5e0259e7
GN		 1518 { 0x0200, "Ethernet controller", "ethernet"},
1519 { 0x0201, "Token Ring controller", "token-ring"},
1520 { 0x0202, "FDDI controller", "fddi"},
1521 { 0x0203, "ATM controller", "atm"},
dcb5b19a 1522 { 0x0280, "Network controller"},
5e0259e7 1523 { 0x0300, "VGA controller", "display", 0x00ff},
dcb5b19a
TS		 1524 { 0x0301, "XGA controller"},
1525 { 0x0302, "3D controller"},
1526 { 0x0380, "Display controller"},
5e0259e7
GN		 1527 { 0x0400, "Video controller", "video"},
1528 { 0x0401, "Audio controller", "sound"},
dcb5b19a 1529 { 0x0402, "Phone"},
602ef4d9 1530 { 0x0403, "Audio controller", "sound"},
dcb5b19a 1531 { 0x0480, "Multimedia controller"},
5e0259e7
GN		 1532 { 0x0500, "RAM controller", "memory"},
1533 { 0x0501, "Flash controller", "flash"},
dcb5b19a 1534 { 0x0580, "Memory controller"},
5e0259e7
GN		 1535 { 0x0600, "Host bridge", "host"},
1536 { 0x0601, "ISA bridge", "isa"},
1537 { 0x0602, "EISA bridge", "eisa"},
1538 { 0x0603, "MC bridge", "mca"},
4c41425d 1539 { 0x0604, "PCI bridge", "pci-bridge"},
5e0259e7
GN		 1540 { 0x0605, "PCMCIA bridge", "pcmcia"},
1541 { 0x0606, "NUBUS bridge", "nubus"},
1542 { 0x0607, "CARDBUS bridge", "cardbus"},
dcb5b19a
TS		 1543 { 0x0608, "RACEWAY bridge"},
1544 { 0x0680, "Bridge"},
5e0259e7
GN		 1545 { 0x0700, "Serial port", "serial"},
1546 { 0x0701, "Parallel port", "parallel"},
1547 { 0x0800, "Interrupt controller", "interrupt-controller"},
1548 { 0x0801, "DMA controller", "dma-controller"},
1549 { 0x0802, "Timer", "timer"},
1550 { 0x0803, "RTC", "rtc"},
1551 { 0x0900, "Keyboard", "keyboard"},
1552 { 0x0901, "Pen", "pen"},
1553 { 0x0902, "Mouse", "mouse"},
1554 { 0x0A00, "Dock station", "dock", 0x00ff},
1555 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1556 { 0x0c00, "Fireware contorller", "fireware"},
1557 { 0x0c01, "Access bus controller", "access-bus"},
1558 { 0x0c02, "SSA controller", "ssa"},
1559 { 0x0c03, "USB controller", "usb"},
1560 { 0x0c04, "Fibre channel controller", "fibre-channel"},
f7748569 1561 { 0x0c05, "SMBus"},
6650ee6d
PB		 1562 { 0, NULL}
1563};
1564
a8eeafda
GK		 1565static void pci_for_each_device_under_bus_reverse(PCIBus *bus,
1566 void (*fn)(PCIBus *b,
1567 PCIDevice *d,
1568 void *opaque),
1569 void *opaque)
1570{
1571 PCIDevice *d;
1572 int devfn;
1573
1574 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1575 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn];
1576 if (d) {
1577 fn(bus, d, opaque);
1578 }
1579 }
1580}
1581
1582void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
1583 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1584 void *opaque)
1585{
1586 bus = pci_find_bus_nr(bus, bus_num);
1587
1588 if (bus) {
1589 pci_for_each_device_under_bus_reverse(bus, fn, opaque);
1590 }
1591}
1592
163c8a59 1593static void pci_for_each_device_under_bus(PCIBus *bus,
7aa8cbb9
AP		 1594 void (*fn)(PCIBus *b, PCIDevice *d,
1595 void *opaque),
1596 void *opaque)
30468f78 1597{
163c8a59
LC		 1598 PCIDevice *d;
1599 int devfn;
30468f78 1600
163c8a59
LC		 1601 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1602 d = bus->devices[devfn];
1603 if (d) {
7aa8cbb9 1604 fn(bus, d, opaque);
163c8a59
LC		 1605 }
1606 }
1607}
1608
1609void pci_for_each_device(PCIBus *bus, int bus_num,
7aa8cbb9
AP		 1610 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1611 void *opaque)
163c8a59 1612{
d662210a 1613 bus = pci_find_bus_nr(bus, bus_num);
163c8a59
LC		 1614
1615 if (bus) {
7aa8cbb9 1616 pci_for_each_device_under_bus(bus, fn, opaque);
163c8a59
LC		 1617 }
1618}
1619
79627472 1620static const pci_class_desc *get_class_desc(int class)
163c8a59 1621{
79627472 1622 const pci_class_desc *desc;
163c8a59 1623
79627472
LC		 1624 desc = pci_class_descriptions;
1625 while (desc->desc && class != desc->class) {
1626 desc++;
30468f78 1627 }
b4dccd8d 1628
79627472
LC		 1629 return desc;
1630}
14421258 1631
79627472 1632static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
163c8a59 1633
79627472
LC		 1634static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1635{
1636 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1637 int i;
163c8a59 1638
79627472
LC		 1639 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1640 const PCIIORegion *r = &dev->io_regions[i];
1641 PciMemoryRegionList *region;
1642
1643 if (!r->size) {
1644 continue;
502a5395 1645 }
163c8a59 1646
79627472
LC		 1647 region = g_malloc0(sizeof(*region));
1648 region->value = g_malloc0(sizeof(*region->value));
163c8a59 1649
79627472
LC		 1650 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1651 region->value->type = g_strdup("io");
1652 } else {
1653 region->value->type = g_strdup("memory");
1654 region->value->has_prefetch = true;
1655 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1656 region->value->has_mem_type_64 = true;
1657 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
d5e4acf7 1658 }
163c8a59 1659
79627472
LC		 1660 region->value->bar = i;
1661 region->value->address = r->addr;
1662 region->value->size = r->size;
163c8a59 1663
79627472
LC		 1664 /* XXX: waiting for the qapi to support GSList */
1665 if (!cur_item) {
1666 head = cur_item = region;
1667 } else {
1668 cur_item->next = region;
1669 cur_item = region;
163c8a59 1670 }
80b3ada7 1671 }
384d8876 1672
79627472 1673 return head;
163c8a59
LC		 1674}
1675
79627472
LC		 1676static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1677 int bus_num)
163c8a59 1678{
79627472 1679 PciBridgeInfo *info;
9fa02cd1 1680 PciMemoryRange *range;
163c8a59 1681
9fa02cd1 1682 info = g_new0(PciBridgeInfo, 1);
163c8a59 1683
9fa02cd1
EB		 1684 info->bus = g_new0(PciBusInfo, 1);
1685 info->bus->number = dev->config[PCI_PRIMARY_BUS];
1686 info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
1687 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
163c8a59 1688
9fa02cd1
EB		 1689 range = info->bus->io_range = g_new0(PciMemoryRange, 1);
1690 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1691 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
163c8a59 1692
9fa02cd1
EB		 1693 range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
1694 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1695 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
163c8a59 1696
9fa02cd1
EB		 1697 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
1698 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1699 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
163c8a59 1700
79627472 1701 if (dev->config[PCI_SECONDARY_BUS] != 0) {
d662210a 1702 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
79627472
LC		 1703 if (child_bus) {
1704 info->has_devices = true;
1705 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1706 }
163c8a59
LC		 1707 }
1708
79627472 1709 return info;
163c8a59
LC		 1710}
1711
79627472
LC		 1712static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1713 int bus_num)
163c8a59 1714{
79627472
LC		 1715 const pci_class_desc *desc;
1716 PciDeviceInfo *info;
b5937f29 1717 uint8_t type;
79627472 1718 int class;
163c8a59 1719
9fa02cd1 1720 info = g_new0(PciDeviceInfo, 1);
79627472
LC		 1721 info->bus = bus_num;
1722 info->slot = PCI_SLOT(dev->devfn);
1723 info->function = PCI_FUNC(dev->devfn);
1724
9fa02cd1 1725 info->class_info = g_new0(PciDeviceClass, 1);
79627472 1726 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
9fa02cd1 1727 info->class_info->q_class = class;
79627472
LC		 1728 desc = get_class_desc(class);
1729 if (desc->desc) {
9fa02cd1
EB		 1730 info->class_info->has_desc = true;
1731 info->class_info->desc = g_strdup(desc->desc);
79627472
LC		 1732 }
1733
9fa02cd1
EB		 1734 info->id = g_new0(PciDeviceId, 1);
1735 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1736 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
79627472
LC		 1737 info->regions = qmp_query_pci_regions(dev);
1738 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
163c8a59
LC		 1739
1740 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
79627472
LC		 1741 info->has_irq = true;
1742 info->irq = dev->config[PCI_INTERRUPT_LINE];
163c8a59
LC		 1743 }
1744
b5937f29
IY		 1745 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1746 if (type == PCI_HEADER_TYPE_BRIDGE) {
79627472
LC		 1747 info->has_pci_bridge = true;
1748 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
163c8a59
LC		 1749 }
1750
79627472 1751 return info;
163c8a59
LC		 1752}
1753
79627472 1754static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
384d8876 1755{
79627472 1756 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
163c8a59 1757 PCIDevice *dev;
79627472 1758 int devfn;
163c8a59
LC		 1759
1760 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1761 dev = bus->devices[devfn];
1762 if (dev) {
79627472
LC		 1763 info = g_malloc0(sizeof(*info));
1764 info->value = qmp_query_pci_device(dev, bus, bus_num);
1765
1766 /* XXX: waiting for the qapi to support GSList */
1767 if (!cur_item) {
1768 head = cur_item = info;
1769 } else {
1770 cur_item->next = info;
1771 cur_item = info;
1772 }
163c8a59 1773 }
1074df4f 1774 }
163c8a59 1775
79627472 1776 return head;
1074df4f
IY		 1777}
1778
79627472 1779static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1074df4f 1780{
79627472
LC		 1781 PciInfo *info = NULL;
1782
d662210a 1783 bus = pci_find_bus_nr(bus, bus_num);
502a5395 1784 if (bus) {
79627472
LC		 1785 info = g_malloc0(sizeof(*info));
1786 info->bus = bus_num;
1787 info->devices = qmp_query_pci_devices(bus, bus_num);
f2aa58c6 1788 }
163c8a59 1789
79627472 1790 return info;
f2aa58c6
FB		 1791}
1792
79627472 1793PciInfoList *qmp_query_pci(Error **errp)
f2aa58c6 1794{
79627472 1795 PciInfoList *info, *head = NULL, *cur_item = NULL;
7588e2b0 1796 PCIHostState *host_bridge;
163c8a59 1797
7588e2b0 1798 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
79627472 1799 info = g_malloc0(sizeof(*info));
cb2ed8b3
MA		 1800 info->value = qmp_query_pci_bus(host_bridge->bus,
1801 pci_bus_num(host_bridge->bus));
79627472
LC		 1802
1803 /* XXX: waiting for the qapi to support GSList */
1804 if (!cur_item) {
1805 head = cur_item = info;
1806 } else {
1807 cur_item->next = info;
1808 cur_item = info;
163c8a59 1809 }
e822a52a 1810 }
163c8a59 1811
79627472 1812 return head;
77d4bc34 1813}
a41b2ff2 1814
cb457d76
AL		 1815static const char * const pci_nic_models[] = {
1816 "ne2k_pci",
1817 "i82551",
1818 "i82557b",
1819 "i82559er",
1820 "rtl8139",
1821 "e1000",
1822 "pcnet",
1823 "virtio",
f85504b2 1824 "sungem",
cb457d76
AL		 1825 NULL
1826};
1827
9d07d757
PB		 1828static const char * const pci_nic_names[] = {
1829 "ne2k_pci",
1830 "i82551",
1831 "i82557b",
1832 "i82559er",
1833 "rtl8139",
1834 "e1000",
1835 "pcnet",
53c25cea 1836 "virtio-net-pci",
f85504b2 1837 "sungem",
cb457d76
AL		 1838 NULL
1839};
1840
a41b2ff2 1841/* Initialize a PCI NIC. */
51f7cb97 1842PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
6dbcb819 1843 const char *default_model,
51f7cb97 1844 const char *default_devaddr)
a41b2ff2 1845{
5607c388 1846 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
07caea31 1847 PCIBus *bus;
5607c388 1848 PCIDevice *pci_dev;
9d07d757 1849 DeviceState *dev;
51f7cb97 1850 int devfn;
cb457d76
AL		 1851 int i;
1852
51f7cb97
TH		 1853 if (qemu_show_nic_models(nd->model, pci_nic_models)) {
1854 exit(0);
1855 }
1856
07caea31 1857 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
51f7cb97
TH		 1858 if (i < 0) {
1859 exit(1);
1860 }
07caea31 1861
29b358f9 1862 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
07caea31 1863 if (!bus) {
1ecda02b
MA		 1864 error_report("Invalid PCI device address %s for device %s",
1865 devaddr, pci_nic_names[i]);
51f7cb97 1866 exit(1);
07caea31
MA		 1867 }
1868
499cf102 1869 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
9ee05825 1870 dev = &pci_dev->qdev;
1cc33683 1871 qdev_set_nic_properties(dev, nd);
a023b7ac 1872 qdev_init_nofail(dev);
51f7cb97
TH		 1873
1874 return pci_dev;
07caea31
MA		 1875}
1876
129d42fb
AJ		 1877PCIDevice *pci_vga_init(PCIBus *bus)
1878{
1879 switch (vga_interface_type) {
1880 case VGA_CIRRUS:
1881 return pci_create_simple(bus, -1, "cirrus-vga");
1882 case VGA_QXL:
1883 return pci_create_simple(bus, -1, "qxl-vga");
1884 case VGA_STD:
1885 return pci_create_simple(bus, -1, "VGA");
1886 case VGA_VMWARE:
1887 return pci_create_simple(bus, -1, "vmware-svga");
a94f0c5c
GH		 1888 case VGA_VIRTIO:
1889 return pci_create_simple(bus, -1, "virtio-vga");
129d42fb
AJ		 1890 case VGA_NONE:
1891 default: /* Other non-PCI types. Checking for unsupported types is already
1892 done in vl.c. */
1893 return NULL;
1894 }
1895}
1896
929176c3
MT		 1897/* Whether a given bus number is in range of the secondary
1898 * bus of the given bridge device. */
1899static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1900{
1901 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1902 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
09e5b819 1903 dev->config[PCI_SECONDARY_BUS] <= bus_num &&
929176c3
MT		 1904 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1905}
1906
09e5b819
MA		 1907/* Whether a given bus number is in a range of a root bus */
1908static bool pci_root_bus_in_range(PCIBus *bus, int bus_num)
1909{
1910 int i;
1911
1912 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1913 PCIDevice *dev = bus->devices[i];
1914
1915 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) {
1916 if (pci_secondary_bus_in_range(dev, bus_num)) {
1917 return true;
1918 }
1919 }
1920 }
1921
1922 return false;
1923}
1924
d662210a 1925static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
3ae80618 1926{
470e6363 1927 PCIBus *sec;
3ae80618 1928
470e6363 1929 if (!bus) {
e822a52a 1930 return NULL;
470e6363 1931 }
3ae80618 1932
e822a52a
IY		 1933 if (pci_bus_num(bus) == bus_num) {
1934 return bus;
1935 }
1936
929176c3 1937 /* Consider all bus numbers in range for the host pci bridge. */
0889464a 1938 if (!pci_bus_is_root(bus) &&
929176c3
MT		 1939 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1940 return NULL;
1941 }
1942
e822a52a 1943 /* try child bus */
929176c3
MT		 1944 for (; bus; bus = sec) {
1945 QLIST_FOREACH(sec, &bus->child, sibling) {
09e5b819 1946 if (pci_bus_num(sec) == bus_num) {
929176c3
MT		 1947 return sec;
1948 }
09e5b819
MA		 1949 /* PXB buses assumed to be children of bus 0 */
1950 if (pci_bus_is_root(sec)) {
1951 if (pci_root_bus_in_range(sec, bus_num)) {
1952 break;
1953 }
1954 } else {
1955 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1956 break;
1957 }
c021f8e6 1958 }
e822a52a
IY		 1959 }
1960 }
1961
1962 return NULL;
3ae80618
AL		 1963}
1964
eb0acfdd
MT		 1965void pci_for_each_bus_depth_first(PCIBus *bus,
1966 void *(*begin)(PCIBus *bus, void *parent_state),
1967 void (*end)(PCIBus *bus, void *state),
1968 void *parent_state)
1969{
1970 PCIBus *sec;
1971 void *state;
1972
1973 if (!bus) {
1974 return;
1975 }
1976
1977 if (begin) {
1978 state = begin(bus, parent_state);
1979 } else {
1980 state = parent_state;
1981 }
1982
1983 QLIST_FOREACH(sec, &bus->child, sibling) {
1984 pci_for_each_bus_depth_first(sec, begin, end, state);
1985 }
1986
1987 if (end) {
1988 end(bus, state);
1989 }
1990}
1991
1992
5256d8bf 1993PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
3ae80618 1994{
d662210a 1995 bus = pci_find_bus_nr(bus, bus_num);
3ae80618
AL		 1996
1997 if (!bus)
1998 return NULL;
1999
5256d8bf 2000 return bus->devices[devfn];
3ae80618
AL		 2001}
2002
133e9b22 2003static void pci_qdev_realize(DeviceState *qdev, Error **errp)
6b1b92d3
PB		 2004{
2005 PCIDevice *pci_dev = (PCIDevice *)qdev;
40021f08 2006 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
133e9b22 2007 Error *local_err = NULL;
6b1b92d3 2008 PCIBus *bus;
ab85ceb1 2009 bool is_default_rom;
6b1b92d3 2010
a9f49946 2011 /* initialize cap_present for pci_is_express() and pci_config_size() */
40021f08 2012 if (pc->is_express) {
a9f49946
IY		 2013 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2014 }
2015
fef7fbc9 2016 bus = PCI_BUS(qdev_get_parent_bus(qdev));
6e008585
AL		 2017 pci_dev = do_pci_register_device(pci_dev, bus,
2018 object_get_typename(OBJECT(qdev)),
133e9b22 2019 pci_dev->devfn, errp);
09e3acc6 2020 if (pci_dev == NULL)
133e9b22 2021 return;
2897ae02 2022
7ee6c1e1
MA		 2023 if (pc->realize) {
2024 pc->realize(pci_dev, &local_err);
2025 if (local_err) {
2026 error_propagate(errp, local_err);
c2afc922 2027 do_pci_unregister_device(pci_dev);
133e9b22 2028 return;
c2afc922 2029 }
925fe64a 2030 }
8c52c8f3
GH		 2031
2032 /* rom loading */
ab85ceb1 2033 is_default_rom = false;
40021f08
AL		 2034 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
2035 pci_dev->romfile = g_strdup(pc->romfile);
ab85ceb1
SW		 2036 is_default_rom = true;
2037 }
178e785f 2038
133e9b22
MA		 2039 pci_add_option_rom(pci_dev, is_default_rom, &local_err);
2040 if (local_err) {
2041 error_propagate(errp, local_err);
2042 pci_qdev_unrealize(DEVICE(pci_dev), NULL);
2043 return;
178e785f 2044 }
ee995ffb
GH		 2045}
2046
7ee6c1e1
MA		 2047static void pci_default_realize(PCIDevice *dev, Error **errp)
2048{
2049 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2050
2051 if (pc->init) {
2052 if (pc->init(dev) < 0) {
2053 error_setg(errp, "Device initialization failed");
2054 return;
2055 }
2056 }
2057}
2058
49823868
IY		 2059PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
2060 const char *name)
6b1b92d3
PB		 2061{
2062 DeviceState *dev;
2063
02e2da45 2064 dev = qdev_create(&bus->qbus, name);
09f1bbcd 2065 qdev_prop_set_int32(dev, "addr", devfn);
49823868 2066 qdev_prop_set_bit(dev, "multifunction", multifunction);
40021f08 2067 return PCI_DEVICE(dev);
71077c1c 2068}
6b1b92d3 2069
49823868
IY		 2070PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
2071 bool multifunction,
2072 const char *name)
71077c1c 2073{
49823868 2074 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
e23a1b33 2075 qdev_init_nofail(&dev->qdev);
71077c1c 2076 return dev;
6b1b92d3 2077}
6f4cbd39 2078
49823868
IY		 2079PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
2080{
2081 return pci_create_multifunction(bus, devfn, false, name);
2082}
2083
2084PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
2085{
2086 return pci_create_simple_multifunction(bus, devfn, false, name);
2087}
2088
b56d701f 2089static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
6f4cbd39
MT		 2090{
2091 int offset = PCI_CONFIG_HEADER_SIZE;
2092 int i;
b56d701f 2093 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
6f4cbd39
MT		 2094 if (pdev->used[i])
2095 offset = i + 1;
2096 else if (i - offset + 1 == size)
2097 return offset;
b56d701f 2098 }
6f4cbd39
MT		 2099 return 0;
2100}
2101
2102static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
2103 uint8_t *prev_p)
2104{
2105 uint8_t next, prev;
2106
2107 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
2108 return 0;
2109
2110 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2111 prev = next + PCI_CAP_LIST_NEXT)
2112 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
2113 break;
2114
2115 if (prev_p)
2116 *prev_p = prev;
2117 return next;
2118}
2119
c9abe111
JK		 2120static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
2121{
2122 uint8_t next, prev, found = 0;
2123
2124 if (!(pdev->used[offset])) {
2125 return 0;
2126 }
2127
2128 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
2129
2130 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2131 prev = next + PCI_CAP_LIST_NEXT) {
2132 if (next <= offset && next > found) {
2133 found = next;
2134 }
2135 }
2136 return found;
2137}
2138
ab85ceb1
SW		 2139/* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2140 This is needed for an option rom which is used for more than one device. */
2141static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
2142{
2143 uint16_t vendor_id;
2144 uint16_t device_id;
2145 uint16_t rom_vendor_id;
2146 uint16_t rom_device_id;
2147 uint16_t rom_magic;
2148 uint16_t pcir_offset;
2149 uint8_t checksum;
2150
2151 /* Words in rom data are little endian (like in PCI configuration),
2152 so they can be read / written with pci_get_word / pci_set_word. */
2153
2154 /* Only a valid rom will be patched. */
2155 rom_magic = pci_get_word(ptr);
2156 if (rom_magic != 0xaa55) {
2157 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
2158 return;
2159 }
2160 pcir_offset = pci_get_word(ptr + 0x18);
2161 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
2162 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
2163 return;
2164 }
2165
2166 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
2167 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
2168 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
2169 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
2170
2171 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
2172 vendor_id, device_id, rom_vendor_id, rom_device_id);
2173
2174 checksum = ptr[6];
2175
2176 if (vendor_id != rom_vendor_id) {
2177 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2178 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
2179 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
2180 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2181 ptr[6] = checksum;
2182 pci_set_word(ptr + pcir_offset + 4, vendor_id);
2183 }
2184
2185 if (device_id != rom_device_id) {
2186 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2187 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
2188 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
2189 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2190 ptr[6] = checksum;
2191 pci_set_word(ptr + pcir_offset + 6, device_id);
2192 }
2193}
2194
c2039bd0 2195/* Add an option rom for the device */
133e9b22
MA		 2196static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
2197 Error **errp)
c2039bd0
AL		 2198{
2199 int size;
2200 char *path;
2201 void *ptr;
1724f049 2202 char name[32];
4be9f0d1 2203 const VMStateDescription *vmsd;
c2039bd0 2204
8c52c8f3 2205 if (!pdev->romfile)
133e9b22 2206 return;
8c52c8f3 2207 if (strlen(pdev->romfile) == 0)
133e9b22 2208 return;
8c52c8f3 2209
88169ddf
GH		 2210 if (!pdev->rom_bar) {
2211 /*
2212 * Load rom via fw_cfg instead of creating a rom bar,
2213 * for 0.11 compatibility.
2214 */
2215 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
db80c7b9
MA		 2216
2217 /*
2218 * Hot-plugged devices can't use the option ROM
2219 * if the rom bar is disabled.
2220 */
2221 if (DEVICE(pdev)->hotplugged) {
133e9b22
MA		 2222 error_setg(errp, "Hot-plugged device without ROM bar"
2223 " can't have an option ROM");
2224 return;
db80c7b9
MA		 2225 }
2226
88169ddf
GH		 2227 if (class == 0x0300) {
2228 rom_add_vga(pdev->romfile);
2229 } else {
2e55e842 2230 rom_add_option(pdev->romfile, -1);
88169ddf 2231 }
133e9b22 2232 return;
88169ddf
GH		 2233 }
2234
8c52c8f3 2235 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
c2039bd0 2236 if (path == NULL) {
7267c094 2237 path = g_strdup(pdev->romfile);
c2039bd0
AL		 2238 }
2239
2240 size = get_image_size(path);
8c52c8f3 2241 if (size < 0) {
133e9b22 2242 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile);
8c7f3dd0 2243 g_free(path);
133e9b22 2244 return;
8c7f3dd0 2245 } else if (size == 0) {
133e9b22 2246 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
7267c094 2247 g_free(path);
133e9b22 2248 return;
8c52c8f3 2249 }
9bff5d81 2250 size = pow2ceil(size);
c2039bd0 2251
4be9f0d1
AL		 2252 vmsd = qdev_get_vmsd(DEVICE(pdev));
2253
2254 if (vmsd) {
2255 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
2256 } else {
f79f2bfc 2257 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
4be9f0d1 2258 }
14caaf7f 2259 pdev->has_rom = true;
fefa9256 2260 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal);
14caaf7f 2261 ptr = memory_region_get_ram_ptr(&pdev->rom);
c2039bd0 2262 load_image(path, ptr);
7267c094 2263 g_free(path);
c2039bd0 2264
ab85ceb1
SW		 2265 if (is_default_rom) {
2266 /* Only the default rom images will be patched (if needed). */
2267 pci_patch_ids(pdev, ptr, size);
2268 }
2269
e824b2cc 2270 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
c2039bd0
AL		 2271}
2272
230741dc
AW		 2273static void pci_del_option_rom(PCIDevice *pdev)
2274{
14caaf7f 2275 if (!pdev->has_rom)
230741dc
AW		 2276 return;
2277
c5705a77 2278 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
14caaf7f 2279 pdev->has_rom = false;
230741dc
AW		 2280}
2281
ca77089d 2282/*
27841278 2283 * On success, pci_add_capability() returns a positive value
eacbc632
MZ		 2284 * that the offset of the pci capability.
2285 * On failure, it sets an error and returns a negative error
2286 * code.
2287 */
27841278 2288int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
cd9aa33e
LE		 2289 uint8_t offset, uint8_t size,
2290 Error **errp)
6f4cbd39 2291{
ca77089d 2292 uint8_t *config;
c9abe111
JK		 2293 int i, overlapping_cap;
2294
ca77089d
IY		 2295 if (!offset) {
2296 offset = pci_find_space(pdev, size);
97fe42f1
C		 2297 /* out of PCI config space is programming error */
2298 assert(offset);
c9abe111
JK		 2299 } else {
2300 /* Verify that capabilities don't overlap. Note: device assignment
2301 * depends on this check to verify that the device is not broken.
2302 * Should never trigger for emulated devices, but it's helpful
2303 * for debugging these. */
2304 for (i = offset; i < offset + size; i++) {
2305 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2306 if (overlapping_cap) {
cd9aa33e
LE		 2307 error_setg(errp, "%s:%02x:%02x.%x "
2308 "Attempt to add PCI capability %x at offset "
2309 "%x overlaps existing capability %x at offset %x",
2310 pci_root_bus_path(pdev), pci_bus_num(pdev->bus),
2311 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2312 cap_id, offset, overlapping_cap, i);
c9abe111
JK		 2313 return -EINVAL;
2314 }
2315 }
ca77089d
IY		 2316 }
2317
2318 config = pdev->config + offset;
6f4cbd39
MT		 2319 config[PCI_CAP_LIST_ID] = cap_id;
2320 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2321 pdev->config[PCI_CAPABILITY_LIST] = offset;
2322 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
e26631b7 2323 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
6f4cbd39
MT		 2324 /* Make capability read-only by default */
2325 memset(pdev->wmask + offset, 0, size);
bd4b65ee
MT		 2326 /* Check capability by default */
2327 memset(pdev->cmask + offset, 0xFF, size);
6f4cbd39
MT		 2328 return offset;
2329}
2330
2331/* Unlink capability from the pci config space. */
2332void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2333{
2334 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2335 if (!offset)
2336 return;
2337 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
ebabb67a 2338 /* Make capability writable again */
6f4cbd39 2339 memset(pdev->wmask + offset, 0xff, size);
1a4f5971 2340 memset(pdev->w1cmask + offset, 0, size);
bd4b65ee
MT		 2341 /* Clear cmask as device-specific registers can't be checked */
2342 memset(pdev->cmask + offset, 0, size);
e26631b7 2343 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
6f4cbd39
MT		 2344
2345 if (!pdev->config[PCI_CAPABILITY_LIST])
2346 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2347}
2348
6f4cbd39
MT		 2349uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2350{
2351 return pci_find_capability_list(pdev, cap_id, NULL);
2352}
10c4c98a
GH		 2353
2354static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2355{
2356 PCIDevice *d = (PCIDevice *)dev;
2357 const pci_class_desc *desc;
2358 char ctxt[64];
2359 PCIIORegion *r;
2360 int i, class;
2361
b0ff8eb2 2362 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
10c4c98a
GH		 2363 desc = pci_class_descriptions;
2364 while (desc->desc && class != desc->class)
2365 desc++;
2366 if (desc->desc) {
2367 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2368 } else {
2369 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2370 }
2371
2372 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2373 "pci id %04x:%04x (sub %04x:%04x)\n",
7f5feab4 2374 indent, "", ctxt, pci_bus_num(d->bus),
e822a52a 2375 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
b0ff8eb2
IY		 2376 pci_get_word(d->config + PCI_VENDOR_ID),
2377 pci_get_word(d->config + PCI_DEVICE_ID),
2378 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2379 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
10c4c98a
GH		 2380 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2381 r = &d->io_regions[i];
2382 if (!r->size)
2383 continue;
89e8b13c
IY		 2384 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2385 " [0x%"FMT_PCIBUS"]\n",
2386 indent, "",
0392a017 2387 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
10c4c98a
GH		 2388 r->addr, r->addr + r->size - 1);
2389 }
2390}
03587182 2391
5e0259e7
GN		 2392static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2393{
2394 PCIDevice *d = (PCIDevice *)dev;
2395 const char *name = NULL;
2396 const pci_class_desc *desc = pci_class_descriptions;
2397 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2398
2399 while (desc->desc &&
2400 (class & ~desc->fw_ign_bits) !=
2401 (desc->class & ~desc->fw_ign_bits)) {
2402 desc++;
2403 }
2404
2405 if (desc->desc) {
2406 name = desc->fw_name;
2407 }
2408
2409 if (name) {
2410 pstrcpy(buf, len, name);
2411 } else {
2412 snprintf(buf, len, "pci%04x,%04x",
2413 pci_get_word(d->config + PCI_VENDOR_ID),
2414 pci_get_word(d->config + PCI_DEVICE_ID));
2415 }
2416
2417 return buf;
2418}
2419
2420static char *pcibus_get_fw_dev_path(DeviceState *dev)
2421{
2422 PCIDevice *d = (PCIDevice *)dev;
2423 char path[50], name[33];
2424 int off;
2425
2426 off = snprintf(path, sizeof(path), "%s@%x",
2427 pci_dev_fw_name(dev, name, sizeof name),
2428 PCI_SLOT(d->devfn));
2429 if (PCI_FUNC(d->devfn))
2430 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
a5cf8262 2431 return g_strdup(path);
5e0259e7
GN		 2432}
2433
4f43c1ff
AW		 2434static char *pcibus_get_dev_path(DeviceState *dev)
2435{
a6a7005d
MT		 2436 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2437 PCIDevice *t;
2438 int slot_depth;
2439 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2440 * 00 is added here to make this format compatible with
2441 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2442 * Slot.Function list specifies the slot and function numbers for all
2443 * devices on the path from root to the specific device. */
568f0690
DG		 2444 const char *root_bus_path;
2445 int root_bus_len;
2991181a 2446 char slot[] = ":SS.F";
2991181a 2447 int slot_len = sizeof slot - 1 /* For '\0' */;
a6a7005d
MT		 2448 int path_len;
2449 char *path, *p;
2991181a 2450 int s;
a6a7005d 2451
568f0690
DG		 2452 root_bus_path = pci_root_bus_path(d);
2453 root_bus_len = strlen(root_bus_path);
2454
a6a7005d
MT		 2455 /* Calculate # of slots on path between device and root. */;
2456 slot_depth = 0;
2457 for (t = d; t; t = t->bus->parent_dev) {
2458 ++slot_depth;
2459 }
2460
568f0690 2461 path_len = root_bus_len + slot_len * slot_depth;
a6a7005d
MT		 2462
2463 /* Allocate memory, fill in the terminating null byte. */
7267c094 2464 path = g_malloc(path_len + 1 /* For '\0' */);
a6a7005d
MT		 2465 path[path_len] = '\0';
2466
568f0690 2467 memcpy(path, root_bus_path, root_bus_len);
a6a7005d
MT		 2468
2469 /* Fill in slot numbers. We walk up from device to root, so need to print
2470 * them in the reverse order, last to first. */
2471 p = path + path_len;
2472 for (t = d; t; t = t->bus->parent_dev) {
2473 p -= slot_len;
2991181a 2474 s = snprintf(slot, sizeof slot, ":%02x.%x",
4c900518 2475 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2991181a
MT		 2476 assert(s == slot_len);
2477 memcpy(p, slot, slot_len);
a6a7005d
MT		 2478 }
2479
2480 return path;
4f43c1ff
AW		 2481}
2482
f3006dd1
IY		 2483static int pci_qdev_find_recursive(PCIBus *bus,
2484 const char *id, PCIDevice **pdev)
2485{
2486 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2487 if (!qdev) {
2488 return -ENODEV;
2489 }
2490
2491 /* roughly check if given qdev is pci device */
4be9f0d1 2492 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
40021f08 2493 *pdev = PCI_DEVICE(qdev);
f3006dd1
IY		 2494 return 0;
2495 }
2496 return -EINVAL;
2497}
2498
2499int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2500{
7588e2b0 2501 PCIHostState *host_bridge;
f3006dd1
IY		 2502 int rc = -ENODEV;
2503
7588e2b0
DG		 2504 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2505 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
f3006dd1
IY		 2506 if (!tmp) {
2507 rc = 0;
2508 break;
2509 }
2510 if (tmp != -ENODEV) {
2511 rc = tmp;
2512 }
2513 }
2514
2515 return rc;
2516}
f5e6fed8
AK		 2517
2518MemoryRegion *pci_address_space(PCIDevice *dev)
2519{
2520 return dev->bus->address_space_mem;
2521}
e11d6439
RH		 2522
2523MemoryRegion *pci_address_space_io(PCIDevice *dev)
2524{
2525 return dev->bus->address_space_io;
2526}
40021f08 2527
39bffca2
AL		 2528static void pci_device_class_init(ObjectClass *klass, void *data)
2529{
2530 DeviceClass *k = DEVICE_CLASS(klass);
7ee6c1e1
MA		 2531 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
2532
133e9b22
MA		 2533 k->realize = pci_qdev_realize;
2534 k->unrealize = pci_qdev_unrealize;
0d936928 2535 k->bus_type = TYPE_PCI_BUS;
bce54474 2536 k->props = pci_props;
7ee6c1e1 2537 pc->realize = pci_default_realize;
39bffca2
AL		 2538}
2539
9eda7d37
AK		 2540AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2541{
2542 PCIBus *bus = PCI_BUS(dev->bus);
5af2ae23 2543 PCIBus *iommu_bus = bus;
9eda7d37 2544
5af2ae23
BH		 2545 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) {
2546 iommu_bus = PCI_BUS(iommu_bus->parent_dev->bus);
9eda7d37 2547 }
5af2ae23
BH		 2548 if (iommu_bus && iommu_bus->iommu_fn) {
2549 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn);
9eda7d37 2550 }
9eda7d37
AK		 2551 return &address_space_memory;
2552}
2553
e00387d5 2554void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
5fa45de5 2555{
e00387d5
AK		 2556 bus->iommu_fn = fn;
2557 bus->iommu_opaque = opaque;
5fa45de5
DG		 2558}
2559
43864069
MT		 2560static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2561{
2562 Range *range = opaque;
2563 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2564 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
77d6f4ea 2565 int i;
43864069
MT		 2566
2567 if (!(cmd & PCI_COMMAND_MEMORY)) {
2568 return;
2569 }
2570
2571 if (pc->is_bridge) {
2572 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2573 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2574
2575 base = MAX(base, 0x1ULL << 32);
2576
2577 if (limit >= base) {
2578 Range pref_range;
a0efbf16 2579 range_set_bounds(&pref_range, base, limit);
43864069
MT		 2580 range_extend(range, &pref_range);
2581 }
2582 }
77d6f4ea
MT		 2583 for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2584 PCIIORegion *r = &dev->io_regions[i];
a0efbf16 2585 pcibus_t lob, upb;
43864069
MT		 2586 Range region_range;
2587
77d6f4ea
MT		 2588 if (!r->size ||
2589 (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2590 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2591 continue;
2592 }
77d6f4ea 2593
a0efbf16
MA		 2594 lob = pci_bar_address(dev, i, r->type, r->size);
2595 upb = lob + r->size - 1;
2596 if (lob == PCI_BAR_UNMAPPED) {
43864069
MT		 2597 continue;
2598 }
43864069 2599
a0efbf16 2600 lob = MAX(lob, 0x1ULL << 32);
43864069 2601
a0efbf16
MA		 2602 if (upb >= lob) {
2603 range_set_bounds(&region_range, lob, upb);
43864069
MT		 2604 range_extend(range, &region_range);
2605 }
2606 }
2607}
2608
2609void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2610{
a0efbf16 2611 range_make_empty(range);
43864069
MT		 2612 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2613}
2614
3f1e1478
C		 2615static bool pcie_has_upstream_port(PCIDevice *dev)
2616{
2617 PCIDevice *parent_dev = pci_bridge_get_device(dev->bus);
2618
2619 /* Device associated with an upstream port.
2620 * As there are several types of these, it's easier to check the
2621 * parent device: upstream ports are always connected to
2622 * root or downstream ports.
2623 */
2624 return parent_dev &&
2625 pci_is_express(parent_dev) &&
2626 parent_dev->exp.exp_cap &&
2627 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT ||
2628 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM);
2629}
2630
2631PCIDevice *pci_get_function_0(PCIDevice *pci_dev)
2632{
2633 if(pcie_has_upstream_port(pci_dev)) {
2634 /* With an upstream PCIe port, we only support 1 device at slot 0 */
2635 return pci_dev->bus->devices[0];
2636 } else {
2637 /* Other bus types might support multiple devices at slots 0-31 */
2638 return pci_dev->bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)];
2639 }
2640}
2641
e1d4fb2d
PX		 2642MSIMessage pci_get_msi_message(PCIDevice *dev, int vector)
2643{
2644 MSIMessage msg;
2645 if (msix_enabled(dev)) {
2646 msg = msix_get_message(dev, vector);
2647 } else if (msi_enabled(dev)) {
2648 msg = msi_get_message(dev, vector);
2649 } else {
2650 /* Should never happen */
2651 error_report("%s: unknown interrupt type", __func__);
2652 abort();
2653 }
2654 return msg;
2655}
2656
8c43a6f0 2657static const TypeInfo pci_device_type_info = {
40021f08
AL		 2658 .name = TYPE_PCI_DEVICE,
2659 .parent = TYPE_DEVICE,
2660 .instance_size = sizeof(PCIDevice),
2661 .abstract = true,
2662 .class_size = sizeof(PCIDeviceClass),
39bffca2 2663 .class_init = pci_device_class_init,
40021f08
AL		 2664};
2665
83f7d43a 2666static void pci_register_types(void)
40021f08 2667{
0d936928 2668 type_register_static(&pci_bus_info);
3a861c46 2669 type_register_static(&pcie_bus_info);
40021f08
AL		 2670 type_register_static(&pci_device_type_info);
2671}
2672
83f7d43a 2673type_init(pci_register_types)
Empty description
This page took 1.551991 seconds and 4 git commands to generate.