[qemu.git] / hw / xics.c

/*
 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
 *
 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
 *
 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */

#include "hw.h"
#include "hw/spapr.h"
#include "hw/xics.h"

/*
 * ICP: Presentation layer
 */

struct icp_server_state {
    uint32_t xirr;
    uint8_t pending_priority;
    uint8_t mfrr;
    qemu_irq output;
};

#define XISR_MASK  0x00ffffff
#define CPPR_MASK  0xff000000

#define XISR(ss)   (((ss)->xirr) & XISR_MASK)
#define CPPR(ss)   (((ss)->xirr) >> 24)

struct ics_state;

struct icp_state {
    long nr_servers;
    struct icp_server_state *ss;
    struct ics_state *ics;
};

static void ics_reject(struct ics_state *ics, int nr);
static void ics_resend(struct ics_state *ics);
static void ics_eoi(struct ics_state *ics, int nr);

static void icp_check_ipi(struct icp_state *icp, int server)
{
    struct icp_server_state *ss = icp->ss + server;

    if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
        return;
    }

    if (XISR(ss)) {
        ics_reject(icp->ics, XISR(ss));
    }

    ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
    ss->pending_priority = ss->mfrr;
    qemu_irq_raise(ss->output);
}

static void icp_resend(struct icp_state *icp, int server)
{
    struct icp_server_state *ss = icp->ss + server;

    if (ss->mfrr < CPPR(ss)) {
        icp_check_ipi(icp, server);
    }
    ics_resend(icp->ics);
}

static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
{
    struct icp_server_state *ss = icp->ss + server;
    uint8_t old_cppr;
    uint32_t old_xisr;

    old_cppr = CPPR(ss);
    ss->xirr = (ss->xirr & ~CPPR_MASK) | (cppr << 24);

    if (cppr < old_cppr) {
        if (XISR(ss) && (cppr <= ss->pending_priority)) {
            old_xisr = XISR(ss);
            ss->xirr &= ~XISR_MASK; /* Clear XISR */
            qemu_irq_lower(ss->output);
            ics_reject(icp->ics, old_xisr);
        }
    } else {
        if (!XISR(ss)) {
            icp_resend(icp, server);
        }
    }
}

static void icp_set_mfrr(struct icp_state *icp, int server, uint8_t mfrr)
{
    struct icp_server_state *ss = icp->ss + server;

    ss->mfrr = mfrr;
    if (mfrr < CPPR(ss)) {
        icp_check_ipi(icp, server);
    }
}

static uint32_t icp_accept(struct icp_server_state *ss)
{
    uint32_t xirr;

    qemu_irq_lower(ss->output);
    xirr = ss->xirr;
    ss->xirr = ss->pending_priority << 24;
    return xirr;
}

static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr)
{
    struct icp_server_state *ss = icp->ss + server;

    /* Send EOI -> ICS */
    ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
    ics_eoi(icp->ics, xirr & XISR_MASK);
    if (!XISR(ss)) {
        icp_resend(icp, server);
    }
}

static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority)
{
    struct icp_server_state *ss = icp->ss + server;

    if ((priority >= CPPR(ss))
        || (XISR(ss) && (ss->pending_priority <= priority))) {
        ics_reject(icp->ics, nr);
    } else {
        if (XISR(ss)) {
            ics_reject(icp->ics, XISR(ss));
        }
        ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
        ss->pending_priority = priority;
        qemu_irq_raise(ss->output);
    }
}

/*
 * ICS: Source layer
 */

struct ics_irq_state {
    int server;
    uint8_t priority;
    uint8_t saved_priority;
#define XICS_STATUS_ASSERTED           0x1
#define XICS_STATUS_SENT               0x2
#define XICS_STATUS_REJECTED           0x4
#define XICS_STATUS_MASKED_PENDING     0x8
    uint8_t status;
    bool lsi;
};

struct ics_state {
    int nr_irqs;
    int offset;
    qemu_irq *qirqs;
    struct ics_irq_state *irqs;
    struct icp_state *icp;
};

static int ics_valid_irq(struct ics_state *ics, uint32_t nr)
{
    return (nr >= ics->offset)
        && (nr < (ics->offset + ics->nr_irqs));
}

static void resend_msi(struct ics_state *ics, int srcno)
{
    struct ics_irq_state *irq = ics->irqs + srcno;

    /* FIXME: filter by server#? */
    if (irq->status & XICS_STATUS_REJECTED) {
        irq->status &= ~XICS_STATUS_REJECTED;
        if (irq->priority != 0xff) {
            icp_irq(ics->icp, irq->server, srcno + ics->offset,
                    irq->priority);
        }
    }
}

static void resend_lsi(struct ics_state *ics, int srcno)
{
    struct ics_irq_state *irq = ics->irqs + srcno;

    if ((irq->priority != 0xff)
        && (irq->status & XICS_STATUS_ASSERTED)
        && !(irq->status & XICS_STATUS_SENT)) {
        irq->status |= XICS_STATUS_SENT;
        icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
    }
}

static void set_irq_msi(struct ics_state *ics, int srcno, int val)
{
    struct ics_irq_state *irq = ics->irqs + srcno;

    if (val) {
        if (irq->priority == 0xff) {
            irq->status |= XICS_STATUS_MASKED_PENDING;
            /* masked pending */ ;
        } else  {
            icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
        }
    }
}

static void set_irq_lsi(struct ics_state *ics, int srcno, int val)
{
    struct ics_irq_state *irq = ics->irqs + srcno;

    if (val) {
        irq->status |= XICS_STATUS_ASSERTED;
    } else {
        irq->status &= ~XICS_STATUS_ASSERTED;
    }
    resend_lsi(ics, srcno);
}

static void ics_set_irq(void *opaque, int srcno, int val)
{
    struct ics_state *ics = (struct ics_state *)opaque;
    struct ics_irq_state *irq = ics->irqs + srcno;

    if (irq->lsi) {
        set_irq_lsi(ics, srcno, val);
    } else {
        set_irq_msi(ics, srcno, val);
    }
}

static void write_xive_msi(struct ics_state *ics, int srcno)
{
    struct ics_irq_state *irq = ics->irqs + srcno;

    if (!(irq->status & XICS_STATUS_MASKED_PENDING)
        || (irq->priority == 0xff)) {
        return;
    }

    irq->status &= ~XICS_STATUS_MASKED_PENDING;
    icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
}

static void write_xive_lsi(struct ics_state *ics, int srcno)
{
    resend_lsi(ics, srcno);
}

static void ics_write_xive(struct ics_state *ics, int nr, int server,
                           uint8_t priority, uint8_t saved_priority)
{
    int srcno = nr - ics->offset;
    struct ics_irq_state *irq = ics->irqs + srcno;

    irq->server = server;
    irq->priority = priority;
    irq->saved_priority = saved_priority;

    if (irq->lsi) {
        write_xive_lsi(ics, srcno);
    } else {
        write_xive_msi(ics, srcno);
    }
}

static void ics_reject(struct ics_state *ics, int nr)
{
    struct ics_irq_state *irq = ics->irqs + nr - ics->offset;

    irq->status |= XICS_STATUS_REJECTED; /* Irrelevant but harmless for LSI */
    irq->status &= ~XICS_STATUS_SENT; /* Irrelevant but harmless for MSI */
}

static void ics_resend(struct ics_state *ics)
{
    int i;

    for (i = 0; i < ics->nr_irqs; i++) {
        struct ics_irq_state *irq = ics->irqs + i;

        /* FIXME: filter by server#? */
        if (irq->lsi) {
            resend_lsi(ics, i);
        } else {
            resend_msi(ics, i);
        }
    }
}

static void ics_eoi(struct ics_state *ics, int nr)
{
    int srcno = nr - ics->offset;
    struct ics_irq_state *irq = ics->irqs + srcno;

    if (irq->lsi) {
        irq->status &= ~XICS_STATUS_SENT;
    }
}

/*
 * Exported functions
 */

qemu_irq xics_get_qirq(struct icp_state *icp, int irq)
{
    if ((irq < icp->ics->offset)
        || (irq >= (icp->ics->offset + icp->ics->nr_irqs))) {
        return NULL;
    }

    return icp->ics->qirqs[irq - icp->ics->offset];
}

void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi)
{
    assert((irq >= icp->ics->offset)
           && (irq < (icp->ics->offset + icp->ics->nr_irqs)));

    icp->ics->irqs[irq - icp->ics->offset].lsi = lsi;
}

static target_ulong h_cppr(CPUPPCState *env, sPAPREnvironment *spapr,
                           target_ulong opcode, target_ulong *args)
{
    target_ulong cppr = args[0];

    icp_set_cppr(spapr->icp, env->cpu_index, cppr);
    return H_SUCCESS;
}

static target_ulong h_ipi(CPUPPCState *env, sPAPREnvironment *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong server = args[0];
    target_ulong mfrr = args[1];

    if (server >= spapr->icp->nr_servers) {
        return H_PARAMETER;
    }

    icp_set_mfrr(spapr->icp, server, mfrr);
    return H_SUCCESS;

}

static target_ulong h_xirr(CPUPPCState *env, sPAPREnvironment *spapr,
                           target_ulong opcode, target_ulong *args)
{
    uint32_t xirr = icp_accept(spapr->icp->ss + env->cpu_index);

    args[0] = xirr;
    return H_SUCCESS;
}

static target_ulong h_eoi(CPUPPCState *env, sPAPREnvironment *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong xirr = args[0];

    icp_eoi(spapr->icp, env->cpu_index, xirr);
    return H_SUCCESS;
}

static void rtas_set_xive(sPAPREnvironment *spapr, uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr, server, priority;

    if ((nargs != 3) || (nret != 1)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);
    server = rtas_ld(args, 1);
    priority = rtas_ld(args, 2);

    if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)
        || (priority > 0xff)) {
        rtas_st(rets, 0, -3);
        return;
    }

    ics_write_xive(ics, nr, server, priority, priority);

    rtas_st(rets, 0, 0); /* Success */
}

static void rtas_get_xive(sPAPREnvironment *spapr, uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr;

    if ((nargs != 1) || (nret != 3)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, -3);
        return;
    }

    rtas_st(rets, 0, 0); /* Success */
    rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
    rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
}

static void rtas_int_off(sPAPREnvironment *spapr, uint32_t token,
                         uint32_t nargs, target_ulong args,
                         uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr;

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, -3);
        return;
    }

    ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,
                   ics->irqs[nr - ics->offset].priority);

    rtas_st(rets, 0, 0); /* Success */
}

static void rtas_int_on(sPAPREnvironment *spapr, uint32_t token,
                        uint32_t nargs, target_ulong args,
                        uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr;

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, -3);
        return;
    }

    ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,
                   ics->irqs[nr - ics->offset].saved_priority,
                   ics->irqs[nr - ics->offset].saved_priority);

    rtas_st(rets, 0, 0); /* Success */
}

static void xics_reset(void *opaque)
{
    struct icp_state *icp = (struct icp_state *)opaque;
    struct ics_state *ics = icp->ics;
    int i;

    for (i = 0; i < icp->nr_servers; i++) {
        icp->ss[i].xirr = 0;
        icp->ss[i].pending_priority = 0;
        icp->ss[i].mfrr = 0xff;
        /* Make all outputs are deasserted */
        qemu_set_irq(icp->ss[i].output, 0);
    }

    for (i = 0; i < ics->nr_irqs; i++) {
        /* Reset everything *except* the type */
        ics->irqs[i].server = 0;
        ics->irqs[i].status = 0;
        ics->irqs[i].priority = 0xff;
        ics->irqs[i].saved_priority = 0xff;
    }
}

struct icp_state *xics_system_init(int nr_irqs)
{
    CPUPPCState *env;
    int max_server_num;
    struct icp_state *icp;
    struct ics_state *ics;

    max_server_num = -1;
    for (env = first_cpu; env != NULL; env = env->next_cpu) {
        if (env->cpu_index > max_server_num) {
            max_server_num = env->cpu_index;
        }
    }

    icp = g_malloc0(sizeof(*icp));
    icp->nr_servers = max_server_num + 1;
    icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state));

    for (env = first_cpu; env != NULL; env = env->next_cpu) {
        struct icp_server_state *ss = &icp->ss[env->cpu_index];

        switch (PPC_INPUT(env)) {
        case PPC_FLAGS_INPUT_POWER7:
            ss->output = env->irq_inputs[POWER7_INPUT_INT];
            break;

        case PPC_FLAGS_INPUT_970:
            ss->output = env->irq_inputs[PPC970_INPUT_INT];
            break;

        default:
            hw_error("XICS interrupt model does not support this CPU bus "
                     "model\n");
            exit(1);
        }
    }

    ics = g_malloc0(sizeof(*ics));
    ics->nr_irqs = nr_irqs;
    ics->offset = 16;
    ics->irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state));

    icp->ics = ics;
    ics->icp = icp;

    ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, nr_irqs);

    spapr_register_hypercall(H_CPPR, h_cppr);
    spapr_register_hypercall(H_IPI, h_ipi);
    spapr_register_hypercall(H_XIRR, h_xirr);
    spapr_register_hypercall(H_EOI, h_eoi);

    spapr_rtas_register("ibm,set-xive", rtas_set_xive);
    spapr_rtas_register("ibm,get-xive", rtas_get_xive);
    spapr_rtas_register("ibm,int-off", rtas_int_off);
    spapr_rtas_register("ibm,int-on", rtas_int_on);

    qemu_register_reset(xics_reset, icp);

    return icp;
}
Commit	Line	Data
b5cec4c5 DG	1	/*
	2	* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
	3	*
	4	* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
	5	*
	6	* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*
	26	*/
	27
	28	#include "hw.h"
	29	#include "hw/spapr.h"
	30	#include "hw/xics.h"
	31
b5cec4c5 DG	32	/*
	33	* ICP: Presentation layer
	34	*/
	35
	36	struct icp_server_state {
	37	uint32_t xirr;
	38	uint8_t pending_priority;
	39	uint8_t mfrr;
	40	qemu_irq output;
	41	};
	42
	43	#define XISR_MASK 0x00ffffff
	44	#define CPPR_MASK 0xff000000
	45
	46	#define XISR(ss) (((ss)->xirr) & XISR_MASK)
	47	#define CPPR(ss) (((ss)->xirr) >> 24)
	48
	49	struct ics_state;
	50
	51	struct icp_state {
	52	long nr_servers;
	53	struct icp_server_state *ss;
	54	struct ics_state *ics;
	55	};
	56
	57	static void ics_reject(struct ics_state *ics, int nr);
	58	static void ics_resend(struct ics_state *ics);
	59	static void ics_eoi(struct ics_state *ics, int nr);
	60
	61	static void icp_check_ipi(struct icp_state *icp, int server)
	62	{
	63	struct icp_server_state *ss = icp->ss + server;
	64
	65	if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
	66	return;
	67	}
	68
	69	if (XISR(ss)) {
	70	ics_reject(icp->ics, XISR(ss));
	71	}
	72
	73	ss->xirr = (ss->xirr & ~XISR_MASK) \| XICS_IPI;
	74	ss->pending_priority = ss->mfrr;
	75	qemu_irq_raise(ss->output);
	76	}
	77
	78	static void icp_resend(struct icp_state *icp, int server)
	79	{
	80	struct icp_server_state *ss = icp->ss + server;
	81
	82	if (ss->mfrr < CPPR(ss)) {
	83	icp_check_ipi(icp, server);
	84	}
	85	ics_resend(icp->ics);
	86	}
	87
	88	static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
	89	{
	90	struct icp_server_state *ss = icp->ss + server;
	91	uint8_t old_cppr;
	92	uint32_t old_xisr;
	93
	94	old_cppr = CPPR(ss);
	95	ss->xirr = (ss->xirr & ~CPPR_MASK) \| (cppr << 24);
96
97	if (cppr < old_cppr) {
98	if (XISR(ss) && (cppr <= ss->pending_priority)) {
99	old_xisr = XISR(ss);
100	ss->xirr &= ~XISR_MASK; /* Clear XISR */
101	qemu_irq_lower(ss->output);
102	ics_reject(icp->ics, old_xisr);
103	}
104	} else {
105	if (!XISR(ss)) {
106	icp_resend(icp, server);
107	}
108	}
109	}
110
bf0175de	111	static void icp_set_mfrr(struct icp_state *icp, int server, uint8_t mfrr)
b5cec4c5	112	{
bf0175de	113	struct icp_server_state *ss = icp->ss + server;
b5cec4c5 DG	114
	115	ss->mfrr = mfrr;
	116	if (mfrr < CPPR(ss)) {
bf0175de	117	icp_check_ipi(icp, server);
b5cec4c5 DG	118	}
	119	}
	120
	121	static uint32_t icp_accept(struct icp_server_state *ss)
	122	{
	123	uint32_t xirr;
	124
	125	qemu_irq_lower(ss->output);
	126	xirr = ss->xirr;
	127	ss->xirr = ss->pending_priority << 24;
	128	return xirr;
	129	}
	130
	131	static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr)
	132	{
	133	struct icp_server_state *ss = icp->ss + server;
	134
b5cec4c5 DG	135	/* Send EOI -> ICS */
b5cec4c5 DG	136	ss->xirr = (ss->xirr & ~CPPR_MASK) \| (xirr & CPPR_MASK);
d07fee7e	137	ics_eoi(icp->ics, xirr & XISR_MASK);
b5cec4c5 DG	138	if (!XISR(ss)) {
	139	icp_resend(icp, server);
	140	}
	141	}
	142
	143	static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority)
	144	{
	145	struct icp_server_state *ss = icp->ss + server;
	146
	147	if ((priority >= CPPR(ss))
	148	\|\| (XISR(ss) && (ss->pending_priority <= priority))) {
	149	ics_reject(icp->ics, nr);
	150	} else {
	151	if (XISR(ss)) {
	152	ics_reject(icp->ics, XISR(ss));
	153	}
	154	ss->xirr = (ss->xirr & ~XISR_MASK) \| (nr & XISR_MASK);
	155	ss->pending_priority = priority;
	156	qemu_irq_raise(ss->output);
	157	}
	158	}
	159
	160	/*
	161	* ICS: Source layer
	162	*/
	163
	164	struct ics_irq_state {
	165	int server;
	166	uint8_t priority;
	167	uint8_t saved_priority;
98ca8c02 DG	168	#define XICS_STATUS_ASSERTED 0x1
	169	#define XICS_STATUS_SENT 0x2
	170	#define XICS_STATUS_REJECTED 0x4
	171	#define XICS_STATUS_MASKED_PENDING 0x8
	172	uint8_t status;
ff9d2afa	173	bool lsi;
b5cec4c5 DG	174	};
	175
	176	struct ics_state {
	177	int nr_irqs;
	178	int offset;
	179	qemu_irq *qirqs;
	180	struct ics_irq_state *irqs;
	181	struct icp_state *icp;
	182	};
	183
	184	static int ics_valid_irq(struct ics_state *ics, uint32_t nr)
	185	{
	186	return (nr >= ics->offset)
	187	&& (nr < (ics->offset + ics->nr_irqs));
	188	}
	189
d07fee7e DG	190	static void resend_msi(struct ics_state *ics, int srcno)
	191	{
	192	struct ics_irq_state *irq = ics->irqs + srcno;
	193
	194	/* FIXME: filter by server#? */
98ca8c02 DG	195	if (irq->status & XICS_STATUS_REJECTED) {
98ca8c02 DG	196	irq->status &= ~XICS_STATUS_REJECTED;
d07fee7e DG	197	if (irq->priority != 0xff) {
	198	icp_irq(ics->icp, irq->server, srcno + ics->offset,
	199	irq->priority);
	200	}
	201	}
	202	}
	203
	204	static void resend_lsi(struct ics_state *ics, int srcno)
	205	{
	206	struct ics_irq_state *irq = ics->irqs + srcno;
	207
98ca8c02 DG	208	if ((irq->priority != 0xff)
	209	&& (irq->status & XICS_STATUS_ASSERTED)
	210	&& !(irq->status & XICS_STATUS_SENT)) {
	211	irq->status \|= XICS_STATUS_SENT;
d07fee7e DG	212	icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
	213	}
	214	}
	215
	216	static void set_irq_msi(struct ics_state *ics, int srcno, int val)
b5cec4c5	217	{
cc67b9c8	218	struct ics_irq_state *irq = ics->irqs + srcno;
b5cec4c5 DG	219
	220	if (val) {
	221	if (irq->priority == 0xff) {
98ca8c02	222	irq->status \|= XICS_STATUS_MASKED_PENDING;
b5cec4c5 DG	223	/* masked pending */ ;
b5cec4c5 DG	224	} else {
cc67b9c8	225	icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
b5cec4c5 DG	226	}
	227	}
	228	}
	229
d07fee7e	230	static void set_irq_lsi(struct ics_state *ics, int srcno, int val)
b5cec4c5	231	{
d07fee7e	232	struct ics_irq_state *irq = ics->irqs + srcno;
b5cec4c5	233
98ca8c02 DG	234	if (val) {
	235	irq->status \|= XICS_STATUS_ASSERTED;
	236	} else {
	237	irq->status &= ~XICS_STATUS_ASSERTED;
	238	}
d07fee7e	239	resend_lsi(ics, srcno);
b5cec4c5 DG	240	}
b5cec4c5 DG	241
d07fee7e	242	static void ics_set_irq(void *opaque, int srcno, int val)
b5cec4c5	243	{
d07fee7e DG	244	struct ics_state ics = (struct ics_state )opaque;
d07fee7e DG	245	struct ics_irq_state *irq = ics->irqs + srcno;
b5cec4c5	246
ff9d2afa	247	if (irq->lsi) {
d07fee7e DG	248	set_irq_lsi(ics, srcno, val);
	249	} else {
	250	set_irq_msi(ics, srcno, val);
	251	}
	252	}
b5cec4c5	253
d07fee7e DG	254	static void write_xive_msi(struct ics_state *ics, int srcno)
	255	{
	256	struct ics_irq_state *irq = ics->irqs + srcno;
	257
98ca8c02 DG	258	if (!(irq->status & XICS_STATUS_MASKED_PENDING)
98ca8c02 DG	259	\|\| (irq->priority == 0xff)) {
d07fee7e	260	return;
b5cec4c5	261	}
d07fee7e	262
98ca8c02	263	irq->status &= ~XICS_STATUS_MASKED_PENDING;
d07fee7e	264	icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
b5cec4c5 DG	265	}
b5cec4c5 DG	266
d07fee7e	267	static void write_xive_lsi(struct ics_state *ics, int srcno)
b5cec4c5	268	{
d07fee7e DG	269	resend_lsi(ics, srcno);
	270	}
	271
	272	static void ics_write_xive(struct ics_state *ics, int nr, int server,
3fe719f4	273	uint8_t priority, uint8_t saved_priority)
d07fee7e DG	274	{
	275	int srcno = nr - ics->offset;
	276	struct ics_irq_state *irq = ics->irqs + srcno;
b5cec4c5 DG	277
	278	irq->server = server;
	279	irq->priority = priority;
3fe719f4	280	irq->saved_priority = saved_priority;
b5cec4c5	281
ff9d2afa	282	if (irq->lsi) {
d07fee7e DG	283	write_xive_lsi(ics, srcno);
	284	} else {
	285	write_xive_msi(ics, srcno);
b5cec4c5	286	}
b5cec4c5 DG	287	}
	288
	289	static void ics_reject(struct ics_state *ics, int nr)
	290	{
d07fee7e DG	291	struct ics_irq_state *irq = ics->irqs + nr - ics->offset;
d07fee7e DG	292
98ca8c02 DG	293	irq->status \|= XICS_STATUS_REJECTED; /* Irrelevant but harmless for LSI */
98ca8c02 DG	294	irq->status &= ~XICS_STATUS_SENT; /* Irrelevant but harmless for MSI */
b5cec4c5 DG	295	}
	296
	297	static void ics_resend(struct ics_state *ics)
	298	{
d07fee7e DG	299	int i;
	300
	301	for (i = 0; i < ics->nr_irqs; i++) {
	302	struct ics_irq_state *irq = ics->irqs + i;
	303
	304	/* FIXME: filter by server#? */
ff9d2afa	305	if (irq->lsi) {
d07fee7e DG	306	resend_lsi(ics, i);
	307	} else {
	308	resend_msi(ics, i);
	309	}
	310	}
b5cec4c5 DG	311	}
	312
	313	static void ics_eoi(struct ics_state *ics, int nr)
	314	{
d07fee7e DG	315	int srcno = nr - ics->offset;
	316	struct ics_irq_state *irq = ics->irqs + srcno;
	317
ff9d2afa	318	if (irq->lsi) {
98ca8c02	319	irq->status &= ~XICS_STATUS_SENT;
d07fee7e	320	}
b5cec4c5 DG	321	}
	322
	323	/*
	324	* Exported functions
	325	*/
	326
a307d594	327	qemu_irq xics_get_qirq(struct icp_state *icp, int irq)
b5cec4c5 DG	328	{
	329	if ((irq < icp->ics->offset)
	330	\|\| (irq >= (icp->ics->offset + icp->ics->nr_irqs))) {
	331	return NULL;
	332	}
	333
a307d594 AK	334	return icp->ics->qirqs[irq - icp->ics->offset];
	335	}
	336
ff9d2afa	337	void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi)
a307d594 AK	338	{
	339	assert((irq >= icp->ics->offset)
	340	&& (irq < (icp->ics->offset + icp->ics->nr_irqs)));
d07fee7e	341
ff9d2afa	342	icp->ics->irqs[irq - icp->ics->offset].lsi = lsi;
b5cec4c5 DG	343	}
b5cec4c5 DG	344
e2684c0b	345	static target_ulong h_cppr(CPUPPCState env, sPAPREnvironment spapr,
b5cec4c5 DG	346	target_ulong opcode, target_ulong *args)
	347	{
	348	target_ulong cppr = args[0];
	349
	350	icp_set_cppr(spapr->icp, env->cpu_index, cppr);
	351	return H_SUCCESS;
	352	}
	353
e2684c0b	354	static target_ulong h_ipi(CPUPPCState env, sPAPREnvironment spapr,
b5cec4c5 DG	355	target_ulong opcode, target_ulong *args)
	356	{
	357	target_ulong server = args[0];
	358	target_ulong mfrr = args[1];
	359
	360	if (server >= spapr->icp->nr_servers) {
	361	return H_PARAMETER;
	362	}
	363
	364	icp_set_mfrr(spapr->icp, server, mfrr);
	365	return H_SUCCESS;
	366
	367	}
	368
e2684c0b	369	static target_ulong h_xirr(CPUPPCState env, sPAPREnvironment spapr,
b5cec4c5 DG	370	target_ulong opcode, target_ulong *args)
	371	{
	372	uint32_t xirr = icp_accept(spapr->icp->ss + env->cpu_index);
	373
	374	args[0] = xirr;
	375	return H_SUCCESS;
	376	}
	377
e2684c0b	378	static target_ulong h_eoi(CPUPPCState env, sPAPREnvironment spapr,
b5cec4c5 DG	379	target_ulong opcode, target_ulong *args)
	380	{
	381	target_ulong xirr = args[0];
	382
	383	icp_eoi(spapr->icp, env->cpu_index, xirr);
	384	return H_SUCCESS;
	385	}
	386
	387	static void rtas_set_xive(sPAPREnvironment *spapr, uint32_t token,
	388	uint32_t nargs, target_ulong args,
	389	uint32_t nret, target_ulong rets)
	390	{
	391	struct ics_state *ics = spapr->icp->ics;
	392	uint32_t nr, server, priority;
	393
	394	if ((nargs != 3) \|\| (nret != 1)) {
	395	rtas_st(rets, 0, -3);
	396	return;
	397	}
	398
	399	nr = rtas_ld(args, 0);
	400	server = rtas_ld(args, 1);
	401	priority = rtas_ld(args, 2);
	402
	403	if (!ics_valid_irq(ics, nr) \|\| (server >= ics->icp->nr_servers)
	404	\|\| (priority > 0xff)) {
	405	rtas_st(rets, 0, -3);
	406	return;
	407	}
	408
3fe719f4	409	ics_write_xive(ics, nr, server, priority, priority);
b5cec4c5 DG	410
	411	rtas_st(rets, 0, 0); /* Success */
	412	}
	413
	414	static void rtas_get_xive(sPAPREnvironment *spapr, uint32_t token,
	415	uint32_t nargs, target_ulong args,
	416	uint32_t nret, target_ulong rets)
	417	{
	418	struct ics_state *ics = spapr->icp->ics;
	419	uint32_t nr;
	420
	421	if ((nargs != 1) \|\| (nret != 3)) {
	422	rtas_st(rets, 0, -3);
	423	return;
	424	}
	425
	426	nr = rtas_ld(args, 0);
	427
	428	if (!ics_valid_irq(ics, nr)) {
	429	rtas_st(rets, 0, -3);
	430	return;
	431	}
	432
	433	rtas_st(rets, 0, 0); /* Success */
	434	rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
	435	rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
	436	}
	437
	438	static void rtas_int_off(sPAPREnvironment *spapr, uint32_t token,
	439	uint32_t nargs, target_ulong args,
	440	uint32_t nret, target_ulong rets)
	441	{
	442	struct ics_state *ics = spapr->icp->ics;
	443	uint32_t nr;
	444
	445	if ((nargs != 1) \|\| (nret != 1)) {
	446	rtas_st(rets, 0, -3);
	447	return;
	448	}
	449
	450	nr = rtas_ld(args, 0);
	451
	452	if (!ics_valid_irq(ics, nr)) {
	453	rtas_st(rets, 0, -3);
	454	return;
	455	}
	456
3fe719f4 DG	457	ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,
3fe719f4 DG	458	ics->irqs[nr - ics->offset].priority);
b5cec4c5 DG	459
	460	rtas_st(rets, 0, 0); /* Success */
	461	}
	462
	463	static void rtas_int_on(sPAPREnvironment *spapr, uint32_t token,
	464	uint32_t nargs, target_ulong args,
	465	uint32_t nret, target_ulong rets)
	466	{
	467	struct ics_state *ics = spapr->icp->ics;
	468	uint32_t nr;
	469
	470	if ((nargs != 1) \|\| (nret != 1)) {
	471	rtas_st(rets, 0, -3);
	472	return;
	473	}
	474
	475	nr = rtas_ld(args, 0);
	476
	477	if (!ics_valid_irq(ics, nr)) {
	478	rtas_st(rets, 0, -3);
	479	return;
	480	}
	481
3fe719f4 DG	482	ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,
	483	ics->irqs[nr - ics->offset].saved_priority,
	484	ics->irqs[nr - ics->offset].saved_priority);
b5cec4c5 DG	485
	486	rtas_st(rets, 0, 0); /* Success */
	487	}
	488
256b408a DG	489	static void xics_reset(void *opaque)
	490	{
	491	struct icp_state icp = (struct icp_state )opaque;
	492	struct ics_state *ics = icp->ics;
	493	int i;
	494
	495	for (i = 0; i < icp->nr_servers; i++) {
	496	icp->ss[i].xirr = 0;
	497	icp->ss[i].pending_priority = 0;
	498	icp->ss[i].mfrr = 0xff;
	499	/* Make all outputs are deasserted */
	500	qemu_set_irq(icp->ss[i].output, 0);
	501	}
	502
	503	for (i = 0; i < ics->nr_irqs; i++) {
	504	/* Reset everything except the type */
	505	ics->irqs[i].server = 0;
98ca8c02	506	ics->irqs[i].status = 0;
256b408a DG	507	ics->irqs[i].priority = 0xff;
	508	ics->irqs[i].saved_priority = 0xff;
	509	}
	510	}
	511
c7a5c0c9	512	struct icp_state *xics_system_init(int nr_irqs)
b5cec4c5	513	{
e2684c0b	514	CPUPPCState *env;
c7a5c0c9	515	int max_server_num;
b5cec4c5 DG	516	struct icp_state *icp;
	517	struct ics_state *ics;
	518
c7a5c0c9 DG	519	max_server_num = -1;
	520	for (env = first_cpu; env != NULL; env = env->next_cpu) {
	521	if (env->cpu_index > max_server_num) {
	522	max_server_num = env->cpu_index;
	523	}
	524	}
	525
7267c094	526	icp = g_malloc0(sizeof(*icp));
c7a5c0c9	527	icp->nr_servers = max_server_num + 1;
7267c094	528	icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state));
c7a5c0c9	529
c7a5c0c9 DG	530	for (env = first_cpu; env != NULL; env = env->next_cpu) {
c7a5c0c9 DG	531	struct icp_server_state *ss = &icp->ss[env->cpu_index];
b5cec4c5	532
c7a5c0c9	533	switch (PPC_INPUT(env)) {
b5cec4c5	534	case PPC_FLAGS_INPUT_POWER7:
c7a5c0c9	535	ss->output = env->irq_inputs[POWER7_INPUT_INT];
b5cec4c5 DG	536	break;
	537
	538	case PPC_FLAGS_INPUT_970:
c7a5c0c9	539	ss->output = env->irq_inputs[PPC970_INPUT_INT];
b5cec4c5 DG	540	break;
	541
	542	default:
	543	hw_error("XICS interrupt model does not support this CPU bus "
	544	"model\n");
	545	exit(1);
	546	}
b5cec4c5 DG	547	}
b5cec4c5 DG	548
7267c094	549	ics = g_malloc0(sizeof(*ics));
b5cec4c5 DG	550	ics->nr_irqs = nr_irqs;
b5cec4c5 DG	551	ics->offset = 16;
7267c094	552	ics->irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state));
b5cec4c5 DG	553
	554	icp->ics = ics;
	555	ics->icp = icp;
	556
d07fee7e	557	ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, nr_irqs);
b5cec4c5 DG	558
	559	spapr_register_hypercall(H_CPPR, h_cppr);
	560	spapr_register_hypercall(H_IPI, h_ipi);
	561	spapr_register_hypercall(H_XIRR, h_xirr);
	562	spapr_register_hypercall(H_EOI, h_eoi);
	563
	564	spapr_rtas_register("ibm,set-xive", rtas_set_xive);
	565	spapr_rtas_register("ibm,get-xive", rtas_get_xive);
	566	spapr_rtas_register("ibm,int-off", rtas_int_off);
	567	spapr_rtas_register("ibm,int-on", rtas_int_on);
	568
256b408a DG	569	qemu_register_reset(xics_reset, icp);
256b408a DG	570
b5cec4c5 DG	571	return icp;
b5cec4c5 DG	572	}