[qemu.git] / hw / xics.c

/*
 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
 *
 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
 *
 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */

#include "hw.h"
#include "hw/spapr.h"
#include "hw/xics.h"

/*
 * ICP: Presentation layer
 */

struct icp_server_state {
    uint32_t xirr;
    uint8_t pending_priority;
    uint8_t mfrr;
    qemu_irq output;
};

#define XISR_MASK  0x00ffffff
#define CPPR_MASK  0xff000000

#define XISR(ss)   (((ss)->xirr) & XISR_MASK)
#define CPPR(ss)   (((ss)->xirr) >> 24)

struct ics_state;

struct icp_state {
    long nr_servers;
    struct icp_server_state *ss;
    struct ics_state *ics;
};

static void ics_reject(struct ics_state *ics, int nr);
static void ics_resend(struct ics_state *ics);
static void ics_eoi(struct ics_state *ics, int nr);

static void icp_check_ipi(struct icp_state *icp, int server)
{
    struct icp_server_state *ss = icp->ss + server;

    if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
        return;
    }

    if (XISR(ss)) {
        ics_reject(icp->ics, XISR(ss));
    }

    ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
    ss->pending_priority = ss->mfrr;
    qemu_irq_raise(ss->output);
}

static void icp_resend(struct icp_state *icp, int server)
{
    struct icp_server_state *ss = icp->ss + server;

    if (ss->mfrr < CPPR(ss)) {
        icp_check_ipi(icp, server);
    }
    ics_resend(icp->ics);
}

static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
{
    struct icp_server_state *ss = icp->ss + server;
    uint8_t old_cppr;
    uint32_t old_xisr;

    old_cppr = CPPR(ss);
    ss->xirr = (ss->xirr & ~CPPR_MASK) | (cppr << 24);

    if (cppr < old_cppr) {
        if (XISR(ss) && (cppr <= ss->pending_priority)) {
            old_xisr = XISR(ss);
            ss->xirr &= ~XISR_MASK; /* Clear XISR */
            qemu_irq_lower(ss->output);
            ics_reject(icp->ics, old_xisr);
        }
    } else {
        if (!XISR(ss)) {
            icp_resend(icp, server);
        }
    }
}

static void icp_set_mfrr(struct icp_state *icp, int nr, uint8_t mfrr)
{
    struct icp_server_state *ss = icp->ss + nr;

    ss->mfrr = mfrr;
    if (mfrr < CPPR(ss)) {
        icp_check_ipi(icp, nr);
    }
}

static uint32_t icp_accept(struct icp_server_state *ss)
{
    uint32_t xirr;

    qemu_irq_lower(ss->output);
    xirr = ss->xirr;
    ss->xirr = ss->pending_priority << 24;
    return xirr;
}

static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr)
{
    struct icp_server_state *ss = icp->ss + server;

    ics_eoi(icp->ics, xirr & XISR_MASK);
    /* Send EOI -> ICS */
    ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
    if (!XISR(ss)) {
        icp_resend(icp, server);
    }
}

static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority)
{
    struct icp_server_state *ss = icp->ss + server;

    if ((priority >= CPPR(ss))
        || (XISR(ss) && (ss->pending_priority <= priority))) {
        ics_reject(icp->ics, nr);
    } else {
        if (XISR(ss)) {
            ics_reject(icp->ics, XISR(ss));
        }
        ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
        ss->pending_priority = priority;
        qemu_irq_raise(ss->output);
    }
}

/*
 * ICS: Source layer
 */

struct ics_irq_state {
    int server;
    uint8_t priority;
    uint8_t saved_priority;
    /* int pending:1; */
    /* int presented:1; */
    int rejected:1;
    int masked_pending:1;
};

struct ics_state {
    int nr_irqs;
    int offset;
    qemu_irq *qirqs;
    struct ics_irq_state *irqs;
    struct icp_state *icp;
};

static int ics_valid_irq(struct ics_state *ics, uint32_t nr)
{
    return (nr >= ics->offset)
        && (nr < (ics->offset + ics->nr_irqs));
}

static void ics_set_irq_msi(void *opaque, int nr, int val)
{
    struct ics_state *ics = (struct ics_state *)opaque;
    struct ics_irq_state *irq = ics->irqs + nr;

    if (val) {
        if (irq->priority == 0xff) {
            irq->masked_pending = 1;
            /* masked pending */ ;
        } else  {
            icp_irq(ics->icp, irq->server, nr + ics->offset, irq->priority);
        }
    }
}

static void ics_reject_msi(struct ics_state *ics, int nr)
{
    struct ics_irq_state *irq = ics->irqs + nr - ics->offset;

    irq->rejected = 1;
}

static void ics_resend_msi(struct ics_state *ics)
{
    int i;

    for (i = 0; i < ics->nr_irqs; i++) {
        struct ics_irq_state *irq = ics->irqs + i;

        /* FIXME: filter by server#? */
        if (irq->rejected) {
            irq->rejected = 0;
            if (irq->priority != 0xff) {
                icp_irq(ics->icp, irq->server, i + ics->offset, irq->priority);
            }
        }
    }
}

static void ics_write_xive_msi(struct ics_state *ics, int nr, int server,
                               uint8_t priority)
{
    struct ics_irq_state *irq = ics->irqs + nr;

    irq->server = server;
    irq->priority = priority;

    if (!irq->masked_pending || (priority == 0xff)) {
        return;
    }

    irq->masked_pending = 0;
    icp_irq(ics->icp, server, nr + ics->offset, priority);
}

static void ics_reject(struct ics_state *ics, int nr)
{
    ics_reject_msi(ics, nr);
}

static void ics_resend(struct ics_state *ics)
{
    ics_resend_msi(ics);
}

static void ics_eoi(struct ics_state *ics, int nr)
{
}

/*
 * Exported functions
 */

qemu_irq xics_find_qirq(struct icp_state *icp, int irq)
{
    if ((irq < icp->ics->offset)
        || (irq >= (icp->ics->offset + icp->ics->nr_irqs))) {
        return NULL;
    }

    return icp->ics->qirqs[irq - icp->ics->offset];
}

static target_ulong h_cppr(CPUState *env, sPAPREnvironment *spapr,
                           target_ulong opcode, target_ulong *args)
{
    target_ulong cppr = args[0];

    icp_set_cppr(spapr->icp, env->cpu_index, cppr);
    return H_SUCCESS;
}

static target_ulong h_ipi(CPUState *env, sPAPREnvironment *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong server = args[0];
    target_ulong mfrr = args[1];

    if (server >= spapr->icp->nr_servers) {
        return H_PARAMETER;
    }

    icp_set_mfrr(spapr->icp, server, mfrr);
    return H_SUCCESS;

}

static target_ulong h_xirr(CPUState *env, sPAPREnvironment *spapr,
                           target_ulong opcode, target_ulong *args)
{
    uint32_t xirr = icp_accept(spapr->icp->ss + env->cpu_index);

    args[0] = xirr;
    return H_SUCCESS;
}

static target_ulong h_eoi(CPUState *env, sPAPREnvironment *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong xirr = args[0];

    icp_eoi(spapr->icp, env->cpu_index, xirr);
    return H_SUCCESS;
}

static void rtas_set_xive(sPAPREnvironment *spapr, uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr, server, priority;

    if ((nargs != 3) || (nret != 1)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);
    server = rtas_ld(args, 1);
    priority = rtas_ld(args, 2);

    if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)
        || (priority > 0xff)) {
        rtas_st(rets, 0, -3);
        return;
    }

    ics_write_xive_msi(ics, nr - ics->offset, server, priority);

    rtas_st(rets, 0, 0); /* Success */
}

static void rtas_get_xive(sPAPREnvironment *spapr, uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr;

    if ((nargs != 1) || (nret != 3)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, -3);
        return;
    }

    rtas_st(rets, 0, 0); /* Success */
    rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
    rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
}

static void rtas_int_off(sPAPREnvironment *spapr, uint32_t token,
                         uint32_t nargs, target_ulong args,
                         uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr;

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, -3);
        return;
    }

    /* This is a NOP for now, since the described PAPR semantics don't
     * seem to gel with what Linux does */
#if 0
    struct ics_irq_state *irq = xics->irqs + (nr - xics->offset);

    irq->saved_priority = irq->priority;
    ics_write_xive_msi(xics, nr - xics->offset, irq->server, 0xff);
#endif

    rtas_st(rets, 0, 0); /* Success */
}

static void rtas_int_on(sPAPREnvironment *spapr, uint32_t token,
                        uint32_t nargs, target_ulong args,
                        uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr;

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, -3);
        return;
    }

    /* This is a NOP for now, since the described PAPR semantics don't
     * seem to gel with what Linux does */
#if 0
    struct ics_irq_state *irq = xics->irqs + (nr - xics->offset);

    ics_write_xive_msi(xics, nr - xics->offset,
                       irq->server, irq->saved_priority);
#endif

    rtas_st(rets, 0, 0); /* Success */
}

struct icp_state *xics_system_init(int nr_irqs)
{
    CPUState *env;
    int max_server_num;
    int i;
    struct icp_state *icp;
    struct ics_state *ics;

    max_server_num = -1;
    for (env = first_cpu; env != NULL; env = env->next_cpu) {
        if (env->cpu_index > max_server_num) {
            max_server_num = env->cpu_index;
        }
    }

    icp = g_malloc0(sizeof(*icp));
    icp->nr_servers = max_server_num + 1;
    icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state));

    for (i = 0; i < icp->nr_servers; i++) {
        icp->ss[i].mfrr = 0xff;
    }

    for (env = first_cpu; env != NULL; env = env->next_cpu) {
        struct icp_server_state *ss = &icp->ss[env->cpu_index];

        switch (PPC_INPUT(env)) {
        case PPC_FLAGS_INPUT_POWER7:
            ss->output = env->irq_inputs[POWER7_INPUT_INT];
            break;

        case PPC_FLAGS_INPUT_970:
            ss->output = env->irq_inputs[PPC970_INPUT_INT];
            break;

        default:
            hw_error("XICS interrupt model does not support this CPU bus "
                     "model\n");
            exit(1);
        }
    }

    ics = g_malloc0(sizeof(*ics));
    ics->nr_irqs = nr_irqs;
    ics->offset = 16;
    ics->irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state));

    icp->ics = ics;
    ics->icp = icp;

    for (i = 0; i < nr_irqs; i++) {
        ics->irqs[i].priority = 0xff;
        ics->irqs[i].saved_priority = 0xff;
    }

    ics->qirqs = qemu_allocate_irqs(ics_set_irq_msi, ics, nr_irqs);

    spapr_register_hypercall(H_CPPR, h_cppr);
    spapr_register_hypercall(H_IPI, h_ipi);
    spapr_register_hypercall(H_XIRR, h_xirr);
    spapr_register_hypercall(H_EOI, h_eoi);

    spapr_rtas_register("ibm,set-xive", rtas_set_xive);
    spapr_rtas_register("ibm,get-xive", rtas_get_xive);
    spapr_rtas_register("ibm,int-off", rtas_int_off);
    spapr_rtas_register("ibm,int-on", rtas_int_on);

    return icp;
}
Commit	Line	Data
b5cec4c5 DG	1	/*
	2	* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
	3	*
	4	* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
	5	*
	6	* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*
	26	*/
	27
	28	#include "hw.h"
	29	#include "hw/spapr.h"
	30	#include "hw/xics.h"
	31
b5cec4c5 DG	32	/*
	33	* ICP: Presentation layer
	34	*/
	35
	36	struct icp_server_state {
	37	uint32_t xirr;
	38	uint8_t pending_priority;
	39	uint8_t mfrr;
	40	qemu_irq output;
	41	};
	42
	43	#define XISR_MASK 0x00ffffff
	44	#define CPPR_MASK 0xff000000
	45
	46	#define XISR(ss) (((ss)->xirr) & XISR_MASK)
	47	#define CPPR(ss) (((ss)->xirr) >> 24)
	48
	49	struct ics_state;
	50
	51	struct icp_state {
	52	long nr_servers;
	53	struct icp_server_state *ss;
	54	struct ics_state *ics;
	55	};
	56
	57	static void ics_reject(struct ics_state *ics, int nr);
	58	static void ics_resend(struct ics_state *ics);
	59	static void ics_eoi(struct ics_state *ics, int nr);
	60
	61	static void icp_check_ipi(struct icp_state *icp, int server)
	62	{
	63	struct icp_server_state *ss = icp->ss + server;
	64
	65	if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
	66	return;
	67	}
	68
	69	if (XISR(ss)) {
	70	ics_reject(icp->ics, XISR(ss));
	71	}
	72
	73	ss->xirr = (ss->xirr & ~XISR_MASK) \| XICS_IPI;
	74	ss->pending_priority = ss->mfrr;
	75	qemu_irq_raise(ss->output);
	76	}
	77
	78	static void icp_resend(struct icp_state *icp, int server)
	79	{
	80	struct icp_server_state *ss = icp->ss + server;
	81
	82	if (ss->mfrr < CPPR(ss)) {
	83	icp_check_ipi(icp, server);
	84	}
	85	ics_resend(icp->ics);
	86	}
	87
	88	static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
	89	{
	90	struct icp_server_state *ss = icp->ss + server;
	91	uint8_t old_cppr;
	92	uint32_t old_xisr;
	93
	94	old_cppr = CPPR(ss);
	95	ss->xirr = (ss->xirr & ~CPPR_MASK) \| (cppr << 24);
96
97	if (cppr < old_cppr) {
98	if (XISR(ss) && (cppr <= ss->pending_priority)) {
99	old_xisr = XISR(ss);
100	ss->xirr &= ~XISR_MASK; /* Clear XISR */
101	qemu_irq_lower(ss->output);
102	ics_reject(icp->ics, old_xisr);
103	}
104	} else {
105	if (!XISR(ss)) {
106	icp_resend(icp, server);
107	}
108	}
109	}
110
111	static void icp_set_mfrr(struct icp_state *icp, int nr, uint8_t mfrr)
112	{
113	struct icp_server_state *ss = icp->ss + nr;
114
115	ss->mfrr = mfrr;
116	if (mfrr < CPPR(ss)) {
117	icp_check_ipi(icp, nr);
118	}
119	}
120
121	static uint32_t icp_accept(struct icp_server_state *ss)
122	{
123	uint32_t xirr;
124
125	qemu_irq_lower(ss->output);
126	xirr = ss->xirr;
127	ss->xirr = ss->pending_priority << 24;
128	return xirr;
129	}
130
131	static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr)
132	{
133	struct icp_server_state *ss = icp->ss + server;
134
135	ics_eoi(icp->ics, xirr & XISR_MASK);
136	/* Send EOI -> ICS */
137	ss->xirr = (ss->xirr & ~CPPR_MASK) \| (xirr & CPPR_MASK);
138	if (!XISR(ss)) {
139	icp_resend(icp, server);
140	}
141	}
142
143	static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority)
144	{
145	struct icp_server_state *ss = icp->ss + server;
146
147	if ((priority >= CPPR(ss))
148	\|\| (XISR(ss) && (ss->pending_priority <= priority))) {
149	ics_reject(icp->ics, nr);
150	} else {
151	if (XISR(ss)) {
152	ics_reject(icp->ics, XISR(ss));
153	}
154	ss->xirr = (ss->xirr & ~XISR_MASK) \| (nr & XISR_MASK);
155	ss->pending_priority = priority;
156	qemu_irq_raise(ss->output);
157	}
158	}
159
160	/*
161	* ICS: Source layer
162	*/
163
164	struct ics_irq_state {
165	int server;
166	uint8_t priority;
167	uint8_t saved_priority;
168	/* int pending:1; */
169	/* int presented:1; */
170	int rejected:1;
171	int masked_pending:1;
172	};
173
174	struct ics_state {
175	int nr_irqs;
176	int offset;
177	qemu_irq *qirqs;
178	struct ics_irq_state *irqs;
179	struct icp_state *icp;
180	};
181
182	static int ics_valid_irq(struct ics_state *ics, uint32_t nr)
183	{
184	return (nr >= ics->offset)
185	&& (nr < (ics->offset + ics->nr_irqs));
186	}
187
188	static void ics_set_irq_msi(void *opaque, int nr, int val)
189	{
190	struct ics_state ics = (struct ics_state )opaque;
191	struct ics_irq_state *irq = ics->irqs + nr;
192
193	if (val) {
194	if (irq->priority == 0xff) {
195	irq->masked_pending = 1;
196	/* masked pending */ ;
197	} else {
198	icp_irq(ics->icp, irq->server, nr + ics->offset, irq->priority);
199	}
200	}
201	}
202
203	static void ics_reject_msi(struct ics_state *ics, int nr)
204	{
205	struct ics_irq_state *irq = ics->irqs + nr - ics->offset;
206
207	irq->rejected = 1;
208	}
209
210	static void ics_resend_msi(struct ics_state *ics)
211	{
212	int i;
213
214	for (i = 0; i < ics->nr_irqs; i++) {
215	struct ics_irq_state *irq = ics->irqs + i;
216
217	/* FIXME: filter by server#? */
218	if (irq->rejected) {
219	irq->rejected = 0;
220	if (irq->priority != 0xff) {
221	icp_irq(ics->icp, irq->server, i + ics->offset, irq->priority);
222	}
223	}
224	}
225	}
226
227	static void ics_write_xive_msi(struct ics_state *ics, int nr, int server,
228	uint8_t priority)
229	{
230	struct ics_irq_state *irq = ics->irqs + nr;
231
232	irq->server = server;
233	irq->priority = priority;
234
235	if (!irq->masked_pending \|\| (priority == 0xff)) {
236	return;
237	}
238
239	irq->masked_pending = 0;
240	icp_irq(ics->icp, server, nr + ics->offset, priority);
241	}
242
243	static void ics_reject(struct ics_state *ics, int nr)
244	{
245	ics_reject_msi(ics, nr);
246	}
247
248	static void ics_resend(struct ics_state *ics)
249	{
250	ics_resend_msi(ics);
251	}
252
253	static void ics_eoi(struct ics_state *ics, int nr)
254	{
255	}
256
257	/*
258	* Exported functions
259	*/
260
261	qemu_irq xics_find_qirq(struct icp_state *icp, int irq)
262	{
263	if ((irq < icp->ics->offset)
264	\|\| (irq >= (icp->ics->offset + icp->ics->nr_irqs))) {
265	return NULL;
266	}
267
268	return icp->ics->qirqs[irq - icp->ics->offset];
269	}
270
271	static target_ulong h_cppr(CPUState env, sPAPREnvironment spapr,
272	target_ulong opcode, target_ulong *args)
273	{
274	target_ulong cppr = args[0];
275
276	icp_set_cppr(spapr->icp, env->cpu_index, cppr);
277	return H_SUCCESS;
278	}
279
280	static target_ulong h_ipi(CPUState env, sPAPREnvironment spapr,
281	target_ulong opcode, target_ulong *args)
282	{
283	target_ulong server = args[0];
284	target_ulong mfrr = args[1];
285
286	if (server >= spapr->icp->nr_servers) {
287	return H_PARAMETER;
288	}
289
290	icp_set_mfrr(spapr->icp, server, mfrr);
291	return H_SUCCESS;
292
293	}
294
295	static target_ulong h_xirr(CPUState env, sPAPREnvironment spapr,
296	target_ulong opcode, target_ulong *args)
297	{
298	uint32_t xirr = icp_accept(spapr->icp->ss + env->cpu_index);
299
300	args[0] = xirr;
301	return H_SUCCESS;
302	}
303
304	static target_ulong h_eoi(CPUState env, sPAPREnvironment spapr,
305	target_ulong opcode, target_ulong *args)
306	{
307	target_ulong xirr = args[0];
308
309	icp_eoi(spapr->icp, env->cpu_index, xirr);
310	return H_SUCCESS;
311	}
312
313	static void rtas_set_xive(sPAPREnvironment *spapr, uint32_t token,
314	uint32_t nargs, target_ulong args,
315	uint32_t nret, target_ulong rets)
316	{
317	struct ics_state *ics = spapr->icp->ics;
318	uint32_t nr, server, priority;
319
320	if ((nargs != 3) \|\| (nret != 1)) {
321	rtas_st(rets, 0, -3);
322	return;
323	}
324
325	nr = rtas_ld(args, 0);
326	server = rtas_ld(args, 1);
327	priority = rtas_ld(args, 2);
328
329	if (!ics_valid_irq(ics, nr) \|\| (server >= ics->icp->nr_servers)
330	\|\| (priority > 0xff)) {
331	rtas_st(rets, 0, -3);
332	return;
333	}
334
335	ics_write_xive_msi(ics, nr - ics->offset, server, priority);
336
337	rtas_st(rets, 0, 0); /* Success */
338	}
339
340	static void rtas_get_xive(sPAPREnvironment *spapr, uint32_t token,
341	uint32_t nargs, target_ulong args,
342	uint32_t nret, target_ulong rets)
343	{
344	struct ics_state *ics = spapr->icp->ics;
345	uint32_t nr;
346
347	if ((nargs != 1) \|\| (nret != 3)) {
348	rtas_st(rets, 0, -3);
349	return;
350	}
351
352	nr = rtas_ld(args, 0);
353
354	if (!ics_valid_irq(ics, nr)) {
355	rtas_st(rets, 0, -3);
356	return;
357	}
358
359	rtas_st(rets, 0, 0); /* Success */
360	rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
361	rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
362	}
363
364	static void rtas_int_off(sPAPREnvironment *spapr, uint32_t token,
365	uint32_t nargs, target_ulong args,
366	uint32_t nret, target_ulong rets)
367	{
368	struct ics_state *ics = spapr->icp->ics;
369	uint32_t nr;
370
371	if ((nargs != 1) \|\| (nret != 1)) {
372	rtas_st(rets, 0, -3);
373	return;
374	}
375
376	nr = rtas_ld(args, 0);
377
378	if (!ics_valid_irq(ics, nr)) {
379	rtas_st(rets, 0, -3);
380	return;
381	}
382
383	/* This is a NOP for now, since the described PAPR semantics don't
384	* seem to gel with what Linux does */
385	#if 0
386	struct ics_irq_state *irq = xics->irqs + (nr - xics->offset);
387
388	irq->saved_priority = irq->priority;
389	ics_write_xive_msi(xics, nr - xics->offset, irq->server, 0xff);
390	#endif
391
392	rtas_st(rets, 0, 0); /* Success */
393	}
394
395	static void rtas_int_on(sPAPREnvironment *spapr, uint32_t token,
396	uint32_t nargs, target_ulong args,
397	uint32_t nret, target_ulong rets)
398	{
399	struct ics_state *ics = spapr->icp->ics;
400	uint32_t nr;
401
402	if ((nargs != 1) \|\| (nret != 1)) {
403	rtas_st(rets, 0, -3);
404	return;
405	}
406
407	nr = rtas_ld(args, 0);
408
409	if (!ics_valid_irq(ics, nr)) {
410	rtas_st(rets, 0, -3);
411	return;
412	}
413
414	/* This is a NOP for now, since the described PAPR semantics don't
415	* seem to gel with what Linux does */
416	#if 0
417	struct ics_irq_state *irq = xics->irqs + (nr - xics->offset);
418
419	ics_write_xive_msi(xics, nr - xics->offset,
420	irq->server, irq->saved_priority);
421	#endif
422
423	rtas_st(rets, 0, 0); /* Success */
424	}
425
c7a5c0c9	426	struct icp_state *xics_system_init(int nr_irqs)
b5cec4c5	427	{
c7a5c0c9 DG	428	CPUState *env;
c7a5c0c9 DG	429	int max_server_num;
b5cec4c5 DG	430	int i;
	431	struct icp_state *icp;
	432	struct ics_state *ics;
	433
c7a5c0c9 DG	434	max_server_num = -1;
	435	for (env = first_cpu; env != NULL; env = env->next_cpu) {
	436	if (env->cpu_index > max_server_num) {
	437	max_server_num = env->cpu_index;
	438	}
	439	}
	440
7267c094	441	icp = g_malloc0(sizeof(*icp));
c7a5c0c9	442	icp->nr_servers = max_server_num + 1;
7267c094	443	icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state));
c7a5c0c9 DG	444
	445	for (i = 0; i < icp->nr_servers; i++) {
	446	icp->ss[i].mfrr = 0xff;
	447	}
b5cec4c5	448
c7a5c0c9 DG	449	for (env = first_cpu; env != NULL; env = env->next_cpu) {
c7a5c0c9 DG	450	struct icp_server_state *ss = &icp->ss[env->cpu_index];
b5cec4c5	451
c7a5c0c9	452	switch (PPC_INPUT(env)) {
b5cec4c5	453	case PPC_FLAGS_INPUT_POWER7:
c7a5c0c9	454	ss->output = env->irq_inputs[POWER7_INPUT_INT];
b5cec4c5 DG	455	break;
	456
	457	case PPC_FLAGS_INPUT_970:
c7a5c0c9	458	ss->output = env->irq_inputs[PPC970_INPUT_INT];
b5cec4c5 DG	459	break;
	460
	461	default:
	462	hw_error("XICS interrupt model does not support this CPU bus "
	463	"model\n");
	464	exit(1);
	465	}
b5cec4c5 DG	466	}
b5cec4c5 DG	467
7267c094	468	ics = g_malloc0(sizeof(*ics));
b5cec4c5 DG	469	ics->nr_irqs = nr_irqs;
b5cec4c5 DG	470	ics->offset = 16;
7267c094	471	ics->irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state));
b5cec4c5 DG	472
	473	icp->ics = ics;
	474	ics->icp = icp;
	475
	476	for (i = 0; i < nr_irqs; i++) {
	477	ics->irqs[i].priority = 0xff;
	478	ics->irqs[i].saved_priority = 0xff;
	479	}
	480
	481	ics->qirqs = qemu_allocate_irqs(ics_set_irq_msi, ics, nr_irqs);
	482
	483	spapr_register_hypercall(H_CPPR, h_cppr);
	484	spapr_register_hypercall(H_IPI, h_ipi);
	485	spapr_register_hypercall(H_XIRR, h_xirr);
	486	spapr_register_hypercall(H_EOI, h_eoi);
	487
	488	spapr_rtas_register("ibm,set-xive", rtas_set_xive);
	489	spapr_rtas_register("ibm,get-xive", rtas_get_xive);
	490	spapr_rtas_register("ibm,int-off", rtas_int_off);
	491	spapr_rtas_register("ibm,int-on", rtas_int_on);
	492
	493	return icp;
	494	}