[qemu.git] / hw / piix_pci.c

/*
 * QEMU i440FX/PIIX3 PCI Bridge Emulation
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw.h"
#include "pc.h"
#include "pci.h"
#include "pci_host.h"
#include "isa.h"
#include "sysbus.h"
#include "range.h"
#include "xen.h"

/*
 * I440FX chipset data sheet.
 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
 */

typedef PCIHostState I440FXState;

#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
#define XEN_PIIX_NUM_PIRQS      128ULL
#define PIIX_PIRQC              0x60

typedef struct PIIX3State {
    PCIDevice dev;

    /*
     * bitmap to track pic levels.
     * The pic level is the logical OR of all the PCI irqs mapped to it
     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
     *
     * PIRQ is mapped to PIC pins, we track it by
     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
     * pic_irq * PIIX_NUM_PIRQS + pirq
     */
#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
#error "unable to encode pic state in 64bit in pic_levels."
#endif
    uint64_t pic_levels;

    qemu_irq *pic;

    /* This member isn't used. Just for save/load compatibility */
    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
} PIIX3State;

struct PCII440FXState {
    PCIDevice dev;
    target_phys_addr_t isa_page_descs[384 / 4];
    uint8_t smm_enabled;
    PIIX3State *piix3;
};


#define I440FX_PAM      0x59
#define I440FX_PAM_SIZE 7
#define I440FX_SMRAM    0x72

static void piix3_set_irq(void *opaque, int pirq, int level);
static void piix3_write_config_xen(PCIDevice *dev,
                               uint32_t address, uint32_t val, int len);

/* return the global irq number corresponding to a given device irq
   pin. We could also use the bus number to have a more precise
   mapping. */
static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
{
    int slot_addend;
    slot_addend = (pci_dev->devfn >> 3) - 1;
    return (pci_intx + slot_addend) & 3;
}

static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
{
    uint32_t addr;

    //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
    switch(r) {
    case 3:
        /* RAM */
        cpu_register_physical_memory(start, end - start,
                                     start);
        break;
    case 1:
        /* ROM (XXX: not quite correct) */
        cpu_register_physical_memory(start, end - start,
                                     start | IO_MEM_ROM);
        break;
    case 2:
    case 0:
        /* XXX: should distinguish read/write cases */
        for(addr = start; addr < end; addr += 4096) {
            cpu_register_physical_memory(addr, 4096,
                                         d->isa_page_descs[(addr - 0xa0000) >> 12]);
        }
        break;
    }
}

static void i440fx_update_memory_mappings(PCII440FXState *d)
{
    int i, r;
    uint32_t smram, addr;

    update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
    for(i = 0; i < 12; i++) {
        r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
        update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
    }
    smram = d->dev.config[I440FX_SMRAM];
    if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
        cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
    } else {
        for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
            cpu_register_physical_memory(addr, 4096,
                                         d->isa_page_descs[(addr - 0xa0000) >> 12]);
        }
    }
}

static void i440fx_set_smm(int val, void *arg)
{
    PCII440FXState *d = arg;

    val = (val != 0);
    if (d->smm_enabled != val) {
        d->smm_enabled = val;
        i440fx_update_memory_mappings(d);
    }
}


/* XXX: suppress when better memory API. We make the assumption that
   no device (in particular the VGA) changes the memory mappings in
   the 0xa0000-0x100000 range */
void i440fx_init_memory_mappings(PCII440FXState *d)
{
    int i;
    for(i = 0; i < 96; i++) {
        d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
    }
}

static void i440fx_write_config(PCIDevice *dev,
                                uint32_t address, uint32_t val, int len)
{
    PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);

    /* XXX: implement SMRAM.D_LOCK */
    pci_default_write_config(dev, address, val, len);
    if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
        range_covers_byte(address, len, I440FX_SMRAM)) {
        i440fx_update_memory_mappings(d);
    }
}

static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
{
    PCII440FXState *d = opaque;
    int ret, i;

    ret = pci_device_load(&d->dev, f);
    if (ret < 0)
        return ret;
    i440fx_update_memory_mappings(d);
    qemu_get_8s(f, &d->smm_enabled);

    if (version_id == 2) {
        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
            qemu_get_be32(f); /* dummy load for compatibility */
        }
    }

    return 0;
}

static int i440fx_post_load(void *opaque, int version_id)
{
    PCII440FXState *d = opaque;

    i440fx_update_memory_mappings(d);
    return 0;
}

static const VMStateDescription vmstate_i440fx = {
    .name = "I440FX",
    .version_id = 3,
    .minimum_version_id = 3,
    .minimum_version_id_old = 1,
    .load_state_old = i440fx_load_old,
    .post_load = i440fx_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PCII440FXState),
        VMSTATE_UINT8(smm_enabled, PCII440FXState),
        VMSTATE_END_OF_LIST()
    }
};

static int i440fx_pcihost_initfn(SysBusDevice *dev)
{
    I440FXState *s = FROM_SYSBUS(I440FXState, dev);

    pci_host_conf_register_ioport(0xcf8, s);

    pci_host_data_register_ioport(0xcfc, s);
    return 0;
}

static int i440fx_initfn(PCIDevice *dev)
{
    PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);

    d->dev.config[I440FX_SMRAM] = 0x02;

    cpu_smm_register(&i440fx_set_smm, d);
    return 0;
}

static PCIBus *i440fx_common_init(const char *device_name,
                                  PCII440FXState **pi440fx_state,
                                  int *piix3_devfn,
                                  qemu_irq *pic,
                                  MemoryRegion *address_space_mem,
                                  MemoryRegion *address_space_io,
                                  ram_addr_t ram_size)
{
    DeviceState *dev;
    PCIBus *b;
    PCIDevice *d;
    I440FXState *s;
    PIIX3State *piix3;

    dev = qdev_create(NULL, "i440FX-pcihost");
    s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
    s->address_space = address_space_mem;
    b = pci_bus_new(&s->busdev.qdev, NULL, s->address_space,
                    address_space_io, 0);
    s->bus = b;
    qdev_init_nofail(dev);

    d = pci_create_simple(b, 0, device_name);
    *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);

    /* Xen supports additional interrupt routes from the PCI devices to
     * the IOAPIC: the four pins of each PCI device on the bus are also
     * connected to the IOAPIC directly.
     * These additional routes can be discovered through ACPI. */
    if (xen_enabled()) {
        piix3 = DO_UPCAST(PIIX3State, dev,
                pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
        pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
                piix3, XEN_PIIX_NUM_PIRQS);
    } else {
        piix3 = DO_UPCAST(PIIX3State, dev,
                pci_create_simple_multifunction(b, -1, true, "PIIX3"));
        pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
                PIIX_NUM_PIRQS);
    }
    piix3->pic = pic;

    (*pi440fx_state)->piix3 = piix3;

    *piix3_devfn = piix3->dev.devfn;

    ram_size = ram_size / 8 / 1024 / 1024;
    if (ram_size > 255)
        ram_size = 255;
    (*pi440fx_state)->dev.config[0x57]=ram_size;

    return b;
}

PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
                    qemu_irq *pic,
                    MemoryRegion *address_space_mem,
                    MemoryRegion *address_space_io,
                    ram_addr_t ram_size)
{
    PCIBus *b;

    b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic,
                           address_space_mem, address_space_io, ram_size);
    return b;
}

/* PIIX3 PCI to ISA bridge */
static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
{
    qemu_set_irq(piix3->pic[pic_irq],
                 !!(piix3->pic_levels &
                    (((1ULL << PIIX_NUM_PIRQS) - 1) <<
                     (pic_irq * PIIX_NUM_PIRQS))));
}

static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
{
    int pic_irq;
    uint64_t mask;

    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
    if (pic_irq >= PIIX_NUM_PIC_IRQS) {
        return;
    }

    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
    piix3->pic_levels &= ~mask;
    piix3->pic_levels |= mask * !!level;

    piix3_set_irq_pic(piix3, pic_irq);
}

static void piix3_set_irq(void *opaque, int pirq, int level)
{
    PIIX3State *piix3 = opaque;
    piix3_set_irq_level(piix3, pirq, level);
}

/* irq routing is changed. so rebuild bitmap */
static void piix3_update_irq_levels(PIIX3State *piix3)
{
    int pirq;

    piix3->pic_levels = 0;
    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
        piix3_set_irq_level(piix3, pirq,
                            pci_bus_get_irq_level(piix3->dev.bus, pirq));
    }
}

static void piix3_write_config(PCIDevice *dev,
                               uint32_t address, uint32_t val, int len)
{
    pci_default_write_config(dev, address, val, len);
    if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
        PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
        int pic_irq;
        piix3_update_irq_levels(piix3);
        for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
            piix3_set_irq_pic(piix3, pic_irq);
        }
    }
}

static void piix3_write_config_xen(PCIDevice *dev,
                               uint32_t address, uint32_t val, int len)
{
    xen_piix_pci_write_config_client(address, val, len);
    piix3_write_config(dev, address, val, len);
}

static void piix3_reset(void *opaque)
{
    PIIX3State *d = opaque;
    uint8_t *pci_conf = d->dev.config;

    pci_conf[0x04] = 0x07; // master, memory and I/O
    pci_conf[0x05] = 0x00;
    pci_conf[0x06] = 0x00;
    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
    pci_conf[0x4c] = 0x4d;
    pci_conf[0x4e] = 0x03;
    pci_conf[0x4f] = 0x00;
    pci_conf[0x60] = 0x80;
    pci_conf[0x61] = 0x80;
    pci_conf[0x62] = 0x80;
    pci_conf[0x63] = 0x80;
    pci_conf[0x69] = 0x02;
    pci_conf[0x70] = 0x80;
    pci_conf[0x76] = 0x0c;
    pci_conf[0x77] = 0x0c;
    pci_conf[0x78] = 0x02;
    pci_conf[0x79] = 0x00;
    pci_conf[0x80] = 0x00;
    pci_conf[0x82] = 0x00;
    pci_conf[0xa0] = 0x08;
    pci_conf[0xa2] = 0x00;
    pci_conf[0xa3] = 0x00;
    pci_conf[0xa4] = 0x00;
    pci_conf[0xa5] = 0x00;
    pci_conf[0xa6] = 0x00;
    pci_conf[0xa7] = 0x00;
    pci_conf[0xa8] = 0x0f;
    pci_conf[0xaa] = 0x00;
    pci_conf[0xab] = 0x00;
    pci_conf[0xac] = 0x00;
    pci_conf[0xae] = 0x00;

    d->pic_levels = 0;
}

static int piix3_post_load(void *opaque, int version_id)
{
    PIIX3State *piix3 = opaque;
    piix3_update_irq_levels(piix3);
    return 0;
}

static void piix3_pre_save(void *opaque)
{
    int i;
    PIIX3State *piix3 = opaque;

    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
        piix3->pci_irq_levels_vmstate[i] =
            pci_bus_get_irq_level(piix3->dev.bus, i);
    }
}

static const VMStateDescription vmstate_piix3 = {
    .name = "PIIX3",
    .version_id = 3,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .post_load = piix3_post_load,
    .pre_save = piix3_pre_save,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PIIX3State),
        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
                              PIIX_NUM_PIRQS, 3),
        VMSTATE_END_OF_LIST()
    }
};

static int piix3_initfn(PCIDevice *dev)
{
    PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);

    isa_bus_new(&d->dev.qdev);
    qemu_register_reset(piix3_reset, d);
    return 0;
}

static PCIDeviceInfo i440fx_info[] = {
    {
        .qdev.name    = "i440FX",
        .qdev.desc    = "Host bridge",
        .qdev.size    = sizeof(PCII440FXState),
        .qdev.vmsd    = &vmstate_i440fx,
        .qdev.no_user = 1,
        .no_hotplug   = 1,
        .init         = i440fx_initfn,
        .config_write = i440fx_write_config,
        .vendor_id    = PCI_VENDOR_ID_INTEL,
        .device_id    = PCI_DEVICE_ID_INTEL_82441,
        .revision     = 0x02,
        .class_id     = PCI_CLASS_BRIDGE_HOST,
    },{
        .qdev.name    = "PIIX3",
        .qdev.desc    = "ISA bridge",
        .qdev.size    = sizeof(PIIX3State),
        .qdev.vmsd    = &vmstate_piix3,
        .qdev.no_user = 1,
        .no_hotplug   = 1,
        .init         = piix3_initfn,
        .config_write = piix3_write_config,
        .vendor_id    = PCI_VENDOR_ID_INTEL,
        .device_id    = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
        .class_id     = PCI_CLASS_BRIDGE_ISA,
    },{
        .qdev.name    = "PIIX3-xen",
        .qdev.desc    = "ISA bridge",
        .qdev.size    = sizeof(PIIX3State),
        .qdev.vmsd    = &vmstate_piix3,
        .qdev.no_user = 1,
        .no_hotplug   = 1,
        .init         = piix3_initfn,
        .config_write = piix3_write_config_xen,
        .vendor_id    = PCI_VENDOR_ID_INTEL,
        .device_id    = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
        .class_id     = PCI_CLASS_BRIDGE_ISA,
    },{
        /* end of list */
    }
};

static SysBusDeviceInfo i440fx_pcihost_info = {
    .init         = i440fx_pcihost_initfn,
    .qdev.name    = "i440FX-pcihost",
    .qdev.fw_name = "pci",
    .qdev.size    = sizeof(I440FXState),
    .qdev.no_user = 1,
};

static void i440fx_register(void)
{
    sysbus_register_withprop(&i440fx_pcihost_info);
    pci_qdev_register_many(i440fx_info);
}
device_init(i440fx_register);
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU i440FX/PIIX3 PCI Bridge Emulation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
87ecb68b PB	25	#include "hw.h"
	26	#include "pc.h"
	27	#include "pci.h"
4f5e19e6	28	#include "pci_host.h"
f75247f1	29	#include "isa.h"
8a14daa5	30	#include "sysbus.h"
bf1b0071	31	#include "range.h"
41445300	32	#include "xen.h"
87ecb68b	33
56594fe3 IY	34	/*
	35	* I440FX chipset data sheet.
	36	* http://download.intel.com/design/chipsets/datashts/29054901.pdf
	37	*/
	38
502a5395 PB	39	typedef PCIHostState I440FXState;
502a5395 PB	40
ab431c28	41	#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
e735b55a	42	#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
bf09551a	43	#define XEN_PIIX_NUM_PIRQS 128ULL
ab431c28	44	#define PIIX_PIRQC 0x60
e735b55a	45
fd37d881 JQ	46	typedef struct PIIX3State {
fd37d881 JQ	47	PCIDevice dev;
ab431c28 IY	48
	49	/*
	50	* bitmap to track pic levels.
	51	* The pic level is the logical OR of all the PCI irqs mapped to it
	52	* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
	53	*
	54	* PIRQ is mapped to PIC pins, we track it by
	55	* PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
	56	* pic_irq * PIIX_NUM_PIRQS + pirq
	57	*/
	58	#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
	59	#error "unable to encode pic state in 64bit in pic_levels."
	60	#endif
	61	uint64_t pic_levels;
	62
bd7dce87	63	qemu_irq *pic;
e735b55a IY	64
	65	/* This member isn't used. Just for save/load compatibility */
	66	int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
7cd9eee0	67	} PIIX3State;
bd7dce87	68
0a3bacf3 JQ	69	struct PCII440FXState {
0a3bacf3 JQ	70	PCIDevice dev;
c227f099	71	target_phys_addr_t isa_page_descs[384 / 4];
6c009fa4	72	uint8_t smm_enabled;
7cd9eee0	73	PIIX3State *piix3;
0a3bacf3 JQ	74	};
0a3bacf3 JQ	75
f2c688bb IY	76
	77	#define I440FX_PAM 0x59
	78	#define I440FX_PAM_SIZE 7
	79	#define I440FX_SMRAM 0x72
	80
ab431c28	81	static void piix3_set_irq(void *opaque, int pirq, int level);
bf09551a SS	82	static void piix3_write_config_xen(PCIDevice *dev,
bf09551a SS	83	uint32_t address, uint32_t val, int len);
d2b59317 PB	84
	85	/* return the global irq number corresponding to a given device irq
	86	pin. We could also use the bus number to have a more precise
	87	mapping. */
ab431c28	88	static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
d2b59317 PB	89	{
	90	int slot_addend;
	91	slot_addend = (pci_dev->devfn >> 3) - 1;
ab431c28	92	return (pci_intx + slot_addend) & 3;
d2b59317	93	}
502a5395	94
0a3bacf3	95	static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
84631fd7 FB	96	{
	97	uint32_t addr;
	98
	99	// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
	100	switch(r) {
	101	case 3:
	102	/* RAM */
5fafdf24	103	cpu_register_physical_memory(start, end - start,
84631fd7 FB	104	start);
	105	break;
	106	case 1:
	107	/* ROM (XXX: not quite correct) */
5fafdf24	108	cpu_register_physical_memory(start, end - start,
84631fd7 FB	109	start \| IO_MEM_ROM);
	110	break;
	111	case 2:
	112	case 0:
	113	/* XXX: should distinguish read/write cases */
	114	for(addr = start; addr < end; addr += 4096) {
5fafdf24	115	cpu_register_physical_memory(addr, 4096,
6c009fa4	116	d->isa_page_descs[(addr - 0xa0000) >> 12]);
84631fd7 FB	117	}
	118	break;
	119	}
	120	}
ee0ea1d0	121
0a3bacf3	122	static void i440fx_update_memory_mappings(PCII440FXState *d)
ee0ea1d0 FB	123	{
ee0ea1d0 FB	124	int i, r;
84631fd7 FB	125	uint32_t smram, addr;
84631fd7 FB	126
f2c688bb	127	update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
84631fd7	128	for(i = 0; i < 12; i++) {
f2c688bb	129	r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
84631fd7	130	update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
ee0ea1d0	131	}
f2c688bb	132	smram = d->dev.config[I440FX_SMRAM];
6c009fa4	133	if ((d->smm_enabled && (smram & 0x08)) \|\| (smram & 0x40)) {
84631fd7 FB	134	cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
	135	} else {
	136	for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
5fafdf24	137	cpu_register_physical_memory(addr, 4096,
6c009fa4	138	d->isa_page_descs[(addr - 0xa0000) >> 12]);
ee0ea1d0 FB	139	}
	140	}
	141	}
	142
f885f1ea	143	static void i440fx_set_smm(int val, void *arg)
ee0ea1d0	144	{
f885f1ea IY	145	PCII440FXState *d = arg;
f885f1ea IY	146
ee0ea1d0	147	val = (val != 0);
6c009fa4 JQ	148	if (d->smm_enabled != val) {
6c009fa4 JQ	149	d->smm_enabled = val;
ee0ea1d0 FB	150	i440fx_update_memory_mappings(d);
	151	}
	152	}
	153
	154
	155	/* XXX: suppress when better memory API. We make the assumption that
	156	no device (in particular the VGA) changes the memory mappings in
	157	the 0xa0000-0x100000 range */
0a3bacf3	158	void i440fx_init_memory_mappings(PCII440FXState *d)
ee0ea1d0 FB	159	{
	160	int i;
	161	for(i = 0; i < 96; i++) {
6c009fa4	162	d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
ee0ea1d0 FB	163	}
	164	}
	165
0a3bacf3	166	static void i440fx_write_config(PCIDevice *dev,
ee0ea1d0 FB	167	uint32_t address, uint32_t val, int len)
ee0ea1d0 FB	168	{
0a3bacf3 JQ	169	PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
0a3bacf3 JQ	170
ee0ea1d0	171	/* XXX: implement SMRAM.D_LOCK */
0a3bacf3	172	pci_default_write_config(dev, address, val, len);
4da5fcd3 IY	173	if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) \|\|
4da5fcd3 IY	174	range_covers_byte(address, len, I440FX_SMRAM)) {
ee0ea1d0	175	i440fx_update_memory_mappings(d);
4da5fcd3	176	}
ee0ea1d0 FB	177	}
ee0ea1d0 FB	178
0c7d19e5	179	static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
ee0ea1d0	180	{
0a3bacf3	181	PCII440FXState *d = opaque;
52fc1d83	182	int ret, i;
ee0ea1d0	183
0a3bacf3	184	ret = pci_device_load(&d->dev, f);
ee0ea1d0 FB	185	if (ret < 0)
	186	return ret;
	187	i440fx_update_memory_mappings(d);
6c009fa4	188	qemu_get_8s(f, &d->smm_enabled);
52fc1d83	189
e735b55a IY	190	if (version_id == 2) {
	191	for (i = 0; i < PIIX_NUM_PIRQS; i++) {
	192	qemu_get_be32(f); /* dummy load for compatibility */
	193	}
	194	}
52fc1d83	195
ee0ea1d0 FB	196	return 0;
	197	}
	198
e59fb374	199	static int i440fx_post_load(void *opaque, int version_id)
0c7d19e5 JQ	200	{
	201	PCII440FXState *d = opaque;
	202
	203	i440fx_update_memory_mappings(d);
	204	return 0;
	205	}
	206
	207	static const VMStateDescription vmstate_i440fx = {
	208	.name = "I440FX",
	209	.version_id = 3,
	210	.minimum_version_id = 3,
	211	.minimum_version_id_old = 1,
	212	.load_state_old = i440fx_load_old,
752ff2fa	213	.post_load = i440fx_post_load,
0c7d19e5 JQ	214	.fields = (VMStateField []) {
	215	VMSTATE_PCI_DEVICE(dev, PCII440FXState),
	216	VMSTATE_UINT8(smm_enabled, PCII440FXState),
	217	VMSTATE_END_OF_LIST()
	218	}
	219	};
	220
81a322d4	221	static int i440fx_pcihost_initfn(SysBusDevice *dev)
502a5395	222	{
8a14daa5	223	I440FXState *s = FROM_SYSBUS(I440FXState, dev);
502a5395	224
f08b32fe	225	pci_host_conf_register_ioport(0xcf8, s);
502a5395	226
4f5e19e6	227	pci_host_data_register_ioport(0xcfc, s);
81a322d4	228	return 0;
8a14daa5	229	}
502a5395	230
0a3bacf3	231	static int i440fx_initfn(PCIDevice *dev)
8a14daa5	232	{
0a3bacf3	233	PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
ee0ea1d0	234
f2c688bb	235	d->dev.config[I440FX_SMRAM] = 0x02;
ee0ea1d0	236
f885f1ea	237	cpu_smm_register(&i440fx_set_smm, d);
81a322d4	238	return 0;
8a14daa5 GH	239	}
8a14daa5 GH	240
41445300 AP	241	static PCIBus i440fx_common_init(const char device_name,
	242	PCII440FXState **pi440fx_state,
	243	int *piix3_devfn,
1e39101c	244	qemu_irq *pic,
aee97b84 AK	245	MemoryRegion *address_space_mem,
aee97b84 AK	246	MemoryRegion *address_space_io,
1e39101c	247	ram_addr_t ram_size)
8a14daa5 GH	248	{
	249	DeviceState *dev;
	250	PCIBus *b;
	251	PCIDevice *d;
	252	I440FXState *s;
7cd9eee0	253	PIIX3State *piix3;
8a14daa5 GH	254
	255	dev = qdev_create(NULL, "i440FX-pcihost");
	256	s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
aee97b84 AK	257	s->address_space = address_space_mem;
	258	b = pci_bus_new(&s->busdev.qdev, NULL, s->address_space,
	259	address_space_io, 0);
8a14daa5	260	s->bus = b;
e23a1b33	261	qdev_init_nofail(dev);
8a14daa5	262
41445300	263	d = pci_create_simple(b, 0, device_name);
0a3bacf3	264	*pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
8a14daa5	265
bf09551a SS	266	/* Xen supports additional interrupt routes from the PCI devices to
	267	* the IOAPIC: the four pins of each PCI device on the bus are also
	268	* connected to the IOAPIC directly.
	269	* These additional routes can be discovered through ACPI. */
	270	if (xen_enabled()) {
	271	piix3 = DO_UPCAST(PIIX3State, dev,
	272	pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
	273	pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
	274	piix3, XEN_PIIX_NUM_PIRQS);
	275	} else {
	276	piix3 = DO_UPCAST(PIIX3State, dev,
	277	pci_create_simple_multifunction(b, -1, true, "PIIX3"));
	278	pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
	279	PIIX_NUM_PIRQS);
	280	}
7cd9eee0	281	piix3->pic = pic;
41445300	282
7cd9eee0 GH	283	(*pi440fx_state)->piix3 = piix3;
	284
	285	*piix3_devfn = piix3->dev.devfn;
85a750ca	286
ec5f92ce BW	287	ram_size = ram_size / 8 / 1024 / 1024;
	288	if (ram_size > 255)
	289	ram_size = 255;
	290	(*pi440fx_state)->dev.config[0x57]=ram_size;
	291
502a5395 PB	292	return b;
	293	}
	294
41445300	295	PCIBus i440fx_init(PCII440FXState pi440fx_state, int piix3_devfn,
aee97b84 AK	296	qemu_irq *pic,
	297	MemoryRegion *address_space_mem,
	298	MemoryRegion *address_space_io,
1e39101c	299	ram_addr_t ram_size)
41445300 AP	300	{
	301	PCIBus *b;
	302
1e39101c	303	b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic,
aee97b84	304	address_space_mem, address_space_io, ram_size);
41445300 AP	305	return b;
	306	}
	307
502a5395	308	/* PIIX3 PCI to ISA bridge */
ab431c28 IY	309	static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
	310	{
	311	qemu_set_irq(piix3->pic[pic_irq],
	312	!!(piix3->pic_levels &
09de0f46	313	(((1ULL << PIIX_NUM_PIRQS) - 1) <<
ab431c28 IY	314	(pic_irq * PIIX_NUM_PIRQS))));
ab431c28 IY	315	}
502a5395	316
afe3ef1d	317	static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
ab431c28 IY	318	{
	319	int pic_irq;
	320	uint64_t mask;
	321
	322	pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
	323	if (pic_irq >= PIIX_NUM_PIC_IRQS) {
	324	return;
	325	}
	326
	327	mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
	328	piix3->pic_levels &= ~mask;
	329	piix3->pic_levels \|= mask * !!level;
	330
afe3ef1d	331	piix3_set_irq_pic(piix3, pic_irq);
ab431c28 IY	332	}
	333
	334	static void piix3_set_irq(void *opaque, int pirq, int level)
502a5395	335	{
7cd9eee0	336	PIIX3State *piix3 = opaque;
afe3ef1d	337	piix3_set_irq_level(piix3, pirq, level);
ab431c28	338	}
502a5395	339
ab431c28 IY	340	/* irq routing is changed. so rebuild bitmap */
	341	static void piix3_update_irq_levels(PIIX3State *piix3)
	342	{
	343	int pirq;
	344
	345	piix3->pic_levels = 0;
	346	for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
	347	piix3_set_irq_level(piix3, pirq,
afe3ef1d	348	pci_bus_get_irq_level(piix3->dev.bus, pirq));
ab431c28 IY	349	}
	350	}
	351
	352	static void piix3_write_config(PCIDevice *dev,
	353	uint32_t address, uint32_t val, int len)
	354	{
	355	pci_default_write_config(dev, address, val, len);
	356	if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
	357	PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
	358	int pic_irq;
	359	piix3_update_irq_levels(piix3);
	360	for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
	361	piix3_set_irq_pic(piix3, pic_irq);
d2b59317	362	}
502a5395 PB	363	}
	364	}
	365
bf09551a SS	366	static void piix3_write_config_xen(PCIDevice *dev,
	367	uint32_t address, uint32_t val, int len)
	368	{
	369	xen_piix_pci_write_config_client(address, val, len);
	370	piix3_write_config(dev, address, val, len);
	371	}
	372
15a1956a	373	static void piix3_reset(void *opaque)
502a5395	374	{
fd37d881 JQ	375	PIIX3State *d = opaque;
fd37d881 JQ	376	uint8_t *pci_conf = d->dev.config;
502a5395 PB	377
	378	pci_conf[0x04] = 0x07; // master, memory and I/O
	379	pci_conf[0x05] = 0x00;
	380	pci_conf[0x06] = 0x00;
	381	pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
	382	pci_conf[0x4c] = 0x4d;
	383	pci_conf[0x4e] = 0x03;
	384	pci_conf[0x4f] = 0x00;
	385	pci_conf[0x60] = 0x80;
477afee3 AJ	386	pci_conf[0x61] = 0x80;
	387	pci_conf[0x62] = 0x80;
	388	pci_conf[0x63] = 0x80;
502a5395 PB	389	pci_conf[0x69] = 0x02;
	390	pci_conf[0x70] = 0x80;
	391	pci_conf[0x76] = 0x0c;
	392	pci_conf[0x77] = 0x0c;
	393	pci_conf[0x78] = 0x02;
	394	pci_conf[0x79] = 0x00;
	395	pci_conf[0x80] = 0x00;
	396	pci_conf[0x82] = 0x00;
	397	pci_conf[0xa0] = 0x08;
502a5395 PB	398	pci_conf[0xa2] = 0x00;
	399	pci_conf[0xa3] = 0x00;
	400	pci_conf[0xa4] = 0x00;
	401	pci_conf[0xa5] = 0x00;
	402	pci_conf[0xa6] = 0x00;
	403	pci_conf[0xa7] = 0x00;
	404	pci_conf[0xa8] = 0x0f;
	405	pci_conf[0xaa] = 0x00;
	406	pci_conf[0xab] = 0x00;
	407	pci_conf[0xac] = 0x00;
	408	pci_conf[0xae] = 0x00;
ab431c28 IY	409
	410	d->pic_levels = 0;
	411	}
	412
	413	static int piix3_post_load(void *opaque, int version_id)
	414	{
	415	PIIX3State *piix3 = opaque;
	416	piix3_update_irq_levels(piix3);
	417	return 0;
e735b55a	418	}
15a1956a	419
e735b55a IY	420	static void piix3_pre_save(void *opaque)
	421	{
	422	int i;
	423	PIIX3State *piix3 = opaque;
	424
	425	for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
	426	piix3->pci_irq_levels_vmstate[i] =
	427	pci_bus_get_irq_level(piix3->dev.bus, i);
	428	}
502a5395 PB	429	}
502a5395 PB	430
d1f171bd JQ	431	static const VMStateDescription vmstate_piix3 = {
	432	.name = "PIIX3",
	433	.version_id = 3,
	434	.minimum_version_id = 2,
	435	.minimum_version_id_old = 2,
ab431c28	436	.post_load = piix3_post_load,
e735b55a	437	.pre_save = piix3_pre_save,
d1f171bd JQ	438	.fields = (VMStateField []) {
d1f171bd JQ	439	VMSTATE_PCI_DEVICE(dev, PIIX3State),
e735b55a IY	440	VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
e735b55a IY	441	PIIX_NUM_PIRQS, 3),
d1f171bd	442	VMSTATE_END_OF_LIST()
da64182c	443	}
d1f171bd	444	};
1941d19c	445
fd37d881	446	static int piix3_initfn(PCIDevice *dev)
502a5395	447	{
fd37d881	448	PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
502a5395	449
fd37d881	450	isa_bus_new(&d->dev.qdev);
a08d4367	451	qemu_register_reset(piix3_reset, d);
81a322d4	452	return 0;
502a5395	453	}
5c2b87e3	454
8a14daa5 GH	455	static PCIDeviceInfo i440fx_info[] = {
	456	{
	457	.qdev.name = "i440FX",
	458	.qdev.desc = "Host bridge",
0a3bacf3	459	.qdev.size = sizeof(PCII440FXState),
be73cfe2	460	.qdev.vmsd = &vmstate_i440fx,
8a14daa5	461	.qdev.no_user = 1,
0965f12d	462	.no_hotplug = 1,
8a14daa5 GH	463	.init = i440fx_initfn,
8a14daa5 GH	464	.config_write = i440fx_write_config,
3a9d8549 IY	465	.vendor_id = PCI_VENDOR_ID_INTEL,
	466	.device_id = PCI_DEVICE_ID_INTEL_82441,
	467	.revision = 0x02,
	468	.class_id = PCI_CLASS_BRIDGE_HOST,
8a14daa5 GH	469	},{
	470	.qdev.name = "PIIX3",
	471	.qdev.desc = "ISA bridge",
fd37d881	472	.qdev.size = sizeof(PIIX3State),
be73cfe2	473	.qdev.vmsd = &vmstate_piix3,
8a14daa5	474	.qdev.no_user = 1,
0965f12d	475	.no_hotplug = 1,
8a14daa5	476	.init = piix3_initfn,
ab431c28	477	.config_write = piix3_write_config,
3a9d8549 IY	478	.vendor_id = PCI_VENDOR_ID_INTEL,
	479	.device_id = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
	480	.class_id = PCI_CLASS_BRIDGE_ISA,
bf09551a SS	481	},{
	482	.qdev.name = "PIIX3-xen",
	483	.qdev.desc = "ISA bridge",
	484	.qdev.size = sizeof(PIIX3State),
	485	.qdev.vmsd = &vmstate_piix3,
	486	.qdev.no_user = 1,
	487	.no_hotplug = 1,
	488	.init = piix3_initfn,
	489	.config_write = piix3_write_config_xen,
ce4fd422 AP	490	.vendor_id = PCI_VENDOR_ID_INTEL,
	491	.device_id = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
	492	.class_id = PCI_CLASS_BRIDGE_ISA,
8a14daa5 GH	493	},{
	494	/* end of list */
	495	}
	496	};
	497
	498	static SysBusDeviceInfo i440fx_pcihost_info = {
	499	.init = i440fx_pcihost_initfn,
	500	.qdev.name = "i440FX-pcihost",
779206de	501	.qdev.fw_name = "pci",
8a14daa5 GH	502	.qdev.size = sizeof(I440FXState),
	503	.qdev.no_user = 1,
	504	};
	505
	506	static void i440fx_register(void)
	507	{
	508	sysbus_register_withprop(&i440fx_pcihost_info);
	509	pci_qdev_register_many(i440fx_info);
	510	}
	511	device_init(i440fx_register);