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Mainstone keypad support, by Armin Kuster.
[qemu.git] / hw / gt64xxx.c
CommitLineData
fde7d5bd
TS		 1/*
2 * QEMU GT64120 PCI host
3 *
4de9b249 4 * Copyright (c) 2006,2007 Aurelien Jarno
5fafdf24 5 *
fde7d5bd
TS		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
87ecb68b
PB		 25#include "hw.h"
26#include "mips.h"
27#include "pci.h"
28#include "pc.h"
05b4ff43 29
fde7d5bd
TS		 30typedef target_phys_addr_t pci_addr_t;
31#include "pci_host.h"
32
05b4ff43
TS		 33//#define DEBUG
34
35#ifdef DEBUG
36#define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
37#else
38#define dprintf(fmt, ...)
39#endif
40
fde7d5bd
TS		 41#define GT_REGS (0x1000 >> 2)
42
43/* CPU Configuration */
44#define GT_CPU (0x000 >> 2)
45#define GT_MULTI (0x120 >> 2)
46
47/* CPU Address Decode */
48#define GT_SCS10LD (0x008 >> 2)
49#define GT_SCS10HD (0x010 >> 2)
50#define GT_SCS32LD (0x018 >> 2)
51#define GT_SCS32HD (0x020 >> 2)
52#define GT_CS20LD (0x028 >> 2)
53#define GT_CS20HD (0x030 >> 2)
54#define GT_CS3BOOTLD (0x038 >> 2)
55#define GT_CS3BOOTHD (0x040 >> 2)
56#define GT_PCI0IOLD (0x048 >> 2)
57#define GT_PCI0IOHD (0x050 >> 2)
58#define GT_PCI0M0LD (0x058 >> 2)
59#define GT_PCI0M0HD (0x060 >> 2)
fde7d5bd
TS		 60#define GT_PCI0M1LD (0x080 >> 2)
61#define GT_PCI0M1HD (0x088 >> 2)
62#define GT_PCI1IOLD (0x090 >> 2)
63#define GT_PCI1IOHD (0x098 >> 2)
64#define GT_PCI1M0LD (0x0a0 >> 2)
65#define GT_PCI1M0HD (0x0a8 >> 2)
66#define GT_PCI1M1LD (0x0b0 >> 2)
67#define GT_PCI1M1HD (0x0b8 >> 2)
05b4ff43 68#define GT_ISD (0x068 >> 2)
fde7d5bd
TS		 69
70#define GT_SCS10AR (0x0d0 >> 2)
71#define GT_SCS32AR (0x0d8 >> 2)
72#define GT_CS20R (0x0e0 >> 2)
73#define GT_CS3BOOTR (0x0e8 >> 2)
74
75#define GT_PCI0IOREMAP (0x0f0 >> 2)
76#define GT_PCI0M0REMAP (0x0f8 >> 2)
77#define GT_PCI0M1REMAP (0x100 >> 2)
78#define GT_PCI1IOREMAP (0x108 >> 2)
79#define GT_PCI1M0REMAP (0x110 >> 2)
80#define GT_PCI1M1REMAP (0x118 >> 2)
81
82/* CPU Error Report */
83#define GT_CPUERR_ADDRLO (0x070 >> 2)
84#define GT_CPUERR_ADDRHI (0x078 >> 2)
85#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
86#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
87#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
88
89/* CPU Sync Barrier */
90#define GT_PCI0SYNC (0x0c0 >> 2)
91#define GT_PCI1SYNC (0x0c8 >> 2)
92
93/* SDRAM and Device Address Decode */
94#define GT_SCS0LD (0x400 >> 2)
95#define GT_SCS0HD (0x404 >> 2)
96#define GT_SCS1LD (0x408 >> 2)
97#define GT_SCS1HD (0x40c >> 2)
98#define GT_SCS2LD (0x410 >> 2)
99#define GT_SCS2HD (0x414 >> 2)
100#define GT_SCS3LD (0x418 >> 2)
101#define GT_SCS3HD (0x41c >> 2)
102#define GT_CS0LD (0x420 >> 2)
103#define GT_CS0HD (0x424 >> 2)
104#define GT_CS1LD (0x428 >> 2)
105#define GT_CS1HD (0x42c >> 2)
106#define GT_CS2LD (0x430 >> 2)
107#define GT_CS2HD (0x434 >> 2)
108#define GT_CS3LD (0x438 >> 2)
109#define GT_CS3HD (0x43c >> 2)
110#define GT_BOOTLD (0x440 >> 2)
111#define GT_BOOTHD (0x444 >> 2)
112#define GT_ADERR (0x470 >> 2)
113
114/* SDRAM Configuration */
115#define GT_SDRAM_CFG (0x448 >> 2)
116#define GT_SDRAM_OPMODE (0x474 >> 2)
117#define GT_SDRAM_BM (0x478 >> 2)
118#define GT_SDRAM_ADDRDECODE (0x47c >> 2)
119
120/* SDRAM Parameters */
121#define GT_SDRAM_B0 (0x44c >> 2)
122#define GT_SDRAM_B1 (0x450 >> 2)
123#define GT_SDRAM_B2 (0x454 >> 2)
124#define GT_SDRAM_B3 (0x458 >> 2)
125
126/* Device Parameters */
127#define GT_DEV_B0 (0x45c >> 2)
128#define GT_DEV_B1 (0x460 >> 2)
129#define GT_DEV_B2 (0x464 >> 2)
130#define GT_DEV_B3 (0x468 >> 2)
131#define GT_DEV_BOOT (0x46c >> 2)
132
133/* ECC */
134#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
135#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
136#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
137#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
138#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
139
140/* DMA Record */
141#define GT_DMA0_CNT (0x800 >> 2)
142#define GT_DMA1_CNT (0x804 >> 2)
143#define GT_DMA2_CNT (0x808 >> 2)
144#define GT_DMA3_CNT (0x80c >> 2)
145#define GT_DMA0_SA (0x810 >> 2)
146#define GT_DMA1_SA (0x814 >> 2)
147#define GT_DMA2_SA (0x818 >> 2)
148#define GT_DMA3_SA (0x81c >> 2)
149#define GT_DMA0_DA (0x820 >> 2)
150#define GT_DMA1_DA (0x824 >> 2)
151#define GT_DMA2_DA (0x828 >> 2)
152#define GT_DMA3_DA (0x82c >> 2)
153#define GT_DMA0_NEXT (0x830 >> 2)
154#define GT_DMA1_NEXT (0x834 >> 2)
155#define GT_DMA2_NEXT (0x838 >> 2)
156#define GT_DMA3_NEXT (0x83c >> 2)
157#define GT_DMA0_CUR (0x870 >> 2)
158#define GT_DMA1_CUR (0x874 >> 2)
159#define GT_DMA2_CUR (0x878 >> 2)
160#define GT_DMA3_CUR (0x87c >> 2)
161
162/* DMA Channel Control */
163#define GT_DMA0_CTRL (0x840 >> 2)
164#define GT_DMA1_CTRL (0x844 >> 2)
165#define GT_DMA2_CTRL (0x848 >> 2)
166#define GT_DMA3_CTRL (0x84c >> 2)
167
168/* DMA Arbiter */
169#define GT_DMA_ARB (0x860 >> 2)
170
171/* Timer/Counter */
172#define GT_TC0 (0x850 >> 2)
173#define GT_TC1 (0x854 >> 2)
174#define GT_TC2 (0x858 >> 2)
175#define GT_TC3 (0x85c >> 2)
176#define GT_TC_CONTROL (0x864 >> 2)
177
178/* PCI Internal */
179#define GT_PCI0_CMD (0xc00 >> 2)
180#define GT_PCI0_TOR (0xc04 >> 2)
181#define GT_PCI0_BS_SCS10 (0xc08 >> 2)
182#define GT_PCI0_BS_SCS32 (0xc0c >> 2)
183#define GT_PCI0_BS_CS20 (0xc10 >> 2)
184#define GT_PCI0_BS_CS3BT (0xc14 >> 2)
185#define GT_PCI1_IACK (0xc30 >> 2)
186#define GT_PCI0_IACK (0xc34 >> 2)
187#define GT_PCI0_BARE (0xc3c >> 2)
188#define GT_PCI0_PREFMBR (0xc40 >> 2)
189#define GT_PCI0_SCS10_BAR (0xc48 >> 2)
190#define GT_PCI0_SCS32_BAR (0xc4c >> 2)
191#define GT_PCI0_CS20_BAR (0xc50 >> 2)
192#define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
193#define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
194#define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
195#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
196#define GT_PCI1_CMD (0xc80 >> 2)
197#define GT_PCI1_TOR (0xc84 >> 2)
198#define GT_PCI1_BS_SCS10 (0xc88 >> 2)
199#define GT_PCI1_BS_SCS32 (0xc8c >> 2)
200#define GT_PCI1_BS_CS20 (0xc90 >> 2)
201#define GT_PCI1_BS_CS3BT (0xc94 >> 2)
202#define GT_PCI1_BARE (0xcbc >> 2)
203#define GT_PCI1_PREFMBR (0xcc0 >> 2)
204#define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
205#define GT_PCI1_SCS32_BAR (0xccc >> 2)
206#define GT_PCI1_CS20_BAR (0xcd0 >> 2)
207#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
208#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
209#define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
210#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
211#define GT_PCI1_CFGADDR (0xcf0 >> 2)
212#define GT_PCI1_CFGDATA (0xcf4 >> 2)
213#define GT_PCI0_CFGADDR (0xcf8 >> 2)
214#define GT_PCI0_CFGDATA (0xcfc >> 2)
215
216/* Interrupts */
217#define GT_INTRCAUSE (0xc18 >> 2)
218#define GT_INTRMASK (0xc1c >> 2)
219#define GT_PCI0_ICMASK (0xc24 >> 2)
220#define GT_PCI0_SERR0MASK (0xc28 >> 2)
221#define GT_CPU_INTSEL (0xc70 >> 2)
222#define GT_PCI0_INTSEL (0xc74 >> 2)
223#define GT_HINTRCAUSE (0xc98 >> 2)
224#define GT_HINTRMASK (0xc9c >> 2)
225#define GT_PCI0_HICMASK (0xca4 >> 2)
226#define GT_PCI1_SERR1MASK (0xca8 >> 2)
227
228
229typedef PCIHostState GT64120PCIState;
230
a0a8793e
TS		 231#define PCI_MAPPING_ENTRY(regname) \
232 target_phys_addr_t regname ##_start; \
233 target_phys_addr_t regname ##_length; \
234 int regname ##_handle
235
fde7d5bd
TS		 236typedef struct GT64120State {
237 GT64120PCIState *pci;
238 uint32_t regs[GT_REGS];
a0a8793e
TS		 239 PCI_MAPPING_ENTRY(PCI0IO);
240 PCI_MAPPING_ENTRY(ISD);
fde7d5bd
TS		 241} GT64120State;
242
a0a8793e
TS		 243/* Adjust range to avoid touching space which isn't mappable via PCI */
244/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
245 0x1fc00000 - 0x1fd00000 */
246static void check_reserved_space (target_phys_addr_t *start,
247 target_phys_addr_t *length)
248{
249 target_phys_addr_t begin = *start;
250 target_phys_addr_t end = *start + *length;
251
252 if (end >= 0x1e000000LL && end < 0x1f100000LL)
253 end = 0x1e000000LL;
254 if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
255 begin = 0x1f100000LL;
256 if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
257 end = 0x1fc00000LL;
258 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
259 begin = 0x1fd00000LL;
260 /* XXX: This is broken when a reserved range splits the requested range */
261 if (end >= 0x1f100000LL && begin < 0x1e000000LL)
262 end = 0x1e000000LL;
263 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
264 end = 0x1fc00000LL;
265
266 *start = begin;
267 *length = end - begin;
268}
269
270static void gt64120_isd_mapping(GT64120State *s)
271{
272 target_phys_addr_t start = s->regs[GT_ISD] << 21;
273 target_phys_addr_t length = 0x1000;
274
275 if (s->ISD_length)
276 cpu_register_physical_memory(s->ISD_start, s->ISD_length,
277 IO_MEM_UNASSIGNED);
278 check_reserved_space(&start, &length);
279 length = 0x1000;
280 /* Map new address */
281 dprintf("ISD: %x@%x -> %x@%x, %x\n", s->ISD_length, s->ISD_start,
282 length, start, s->ISD_handle);
283 s->ISD_start = start;
284 s->ISD_length = length;
285 cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle);
286}
287
9414cc6f 288static void gt64120_pci_mapping(GT64120State *s)
2a1086d9 289{
9414cc6f
TS		 290 /* Update IO mapping */
291 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
292 {
3b46e624 293 /* Unmap old IO address */
9414cc6f
TS		 294 if (s->PCI0IO_length)
295 {
3b46e624 296 cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
9414cc6f
TS		 297 }
298 /* Map new IO address */
299 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
300 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
301 isa_mem_base = s->PCI0IO_start;
302 isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
303 }
2a1086d9
TS		 304}
305
fde7d5bd
TS		 306static void gt64120_writel (void *opaque, target_phys_addr_t addr,
307 uint32_t val)
308{
309 GT64120State *s = opaque;
310 uint32_t saddr;
311
1931e260
TS		 312 if (!(s->regs[GT_PCI0_CMD] & 1))
313 val = bswap32(val);
0da75eb1 314
fde7d5bd
TS		 315 saddr = (addr & 0xfff) >> 2;
316 switch (saddr) {
0da75eb1
TS		 317
318 /* CPU Configuration */
fde7d5bd
TS		 319 case GT_CPU:
320 s->regs[GT_CPU] = val;
fde7d5bd
TS		 321 break;
322 case GT_MULTI:
0da75eb1 323 /* Read-only register as only one GT64xxx is present on the CPU bus */
fde7d5bd
TS		 324 break;
325
326 /* CPU Address Decode */
327 case GT_PCI0IOLD:
328 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
329 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
9414cc6f 330 gt64120_pci_mapping(s);
fde7d5bd
TS		 331 break;
332 case GT_PCI0M0LD:
333 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
334 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
fde7d5bd
TS		 335 break;
336 case GT_PCI0M1LD:
337 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
338 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
fde7d5bd
TS		 339 break;
340 case GT_PCI1IOLD:
341 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
342 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
fde7d5bd
TS		 343 break;
344 case GT_PCI1M0LD:
345 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
346 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
fde7d5bd
TS		 347 break;
348 case GT_PCI1M1LD:
349 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
350 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
fde7d5bd
TS		 351 break;
352 case GT_PCI0IOHD:
bb433bef
TS		 353 s->regs[saddr] = val & 0x0000007f;
354 gt64120_pci_mapping(s);
355 break;
fde7d5bd
TS		 356 case GT_PCI0M0HD:
357 case GT_PCI0M1HD:
358 case GT_PCI1IOHD:
359 case GT_PCI1M0HD:
360 case GT_PCI1M1HD:
361 s->regs[saddr] = val & 0x0000007f;
fde7d5bd 362 break;
a0a8793e
TS		 363 case GT_ISD:
364 s->regs[saddr] = val & 0x00007fff;
365 gt64120_isd_mapping(s);
366 break;
367
fde7d5bd
TS		 368 case GT_PCI0IOREMAP:
369 case GT_PCI0M0REMAP:
370 case GT_PCI0M1REMAP:
371 case GT_PCI1IOREMAP:
372 case GT_PCI1M0REMAP:
373 case GT_PCI1M1REMAP:
374 s->regs[saddr] = val & 0x000007ff;
fde7d5bd
TS		 375 break;
376
377 /* CPU Error Report */
378 case GT_CPUERR_ADDRLO:
379 case GT_CPUERR_ADDRHI:
380 case GT_CPUERR_DATALO:
381 case GT_CPUERR_DATAHI:
382 case GT_CPUERR_PARITY:
0da75eb1
TS		 383 /* Read-only registers, do nothing */
384 break;
385
386 /* CPU Sync Barrier */
387 case GT_PCI0SYNC:
388 case GT_PCI1SYNC:
389 /* Read-only registers, do nothing */
fde7d5bd
TS		 390 break;
391
05b4ff43
TS		 392 /* SDRAM and Device Address Decode */
393 case GT_SCS0LD:
394 case GT_SCS0HD:
395 case GT_SCS1LD:
396 case GT_SCS1HD:
397 case GT_SCS2LD:
398 case GT_SCS2HD:
399 case GT_SCS3LD:
400 case GT_SCS3HD:
401 case GT_CS0LD:
402 case GT_CS0HD:
403 case GT_CS1LD:
404 case GT_CS1HD:
405 case GT_CS2LD:
406 case GT_CS2HD:
407 case GT_CS3LD:
408 case GT_CS3HD:
409 case GT_BOOTLD:
410 case GT_BOOTHD:
411 case GT_ADERR:
412 /* SDRAM Configuration */
413 case GT_SDRAM_CFG:
414 case GT_SDRAM_OPMODE:
415 case GT_SDRAM_BM:
416 case GT_SDRAM_ADDRDECODE:
417 /* Accept and ignore SDRAM interleave configuration */
418 s->regs[saddr] = val;
419 break;
420
421 /* Device Parameters */
422 case GT_DEV_B0:
423 case GT_DEV_B1:
424 case GT_DEV_B2:
425 case GT_DEV_B3:
426 case GT_DEV_BOOT:
427 /* Not implemented */
428 dprintf ("Unimplemented device register offset 0x%x\n", saddr << 2);
429 break;
430
fde7d5bd
TS		 431 /* ECC */
432 case GT_ECC_ERRDATALO:
433 case GT_ECC_ERRDATAHI:
434 case GT_ECC_MEM:
435 case GT_ECC_CALC:
436 case GT_ECC_ERRADDR:
0da75eb1 437 /* Read-only registers, do nothing */
fde7d5bd
TS		 438 break;
439
05b4ff43
TS		 440 /* DMA Record */
441 case GT_DMA0_CNT:
442 case GT_DMA1_CNT:
443 case GT_DMA2_CNT:
444 case GT_DMA3_CNT:
445 case GT_DMA0_SA:
446 case GT_DMA1_SA:
447 case GT_DMA2_SA:
448 case GT_DMA3_SA:
449 case GT_DMA0_DA:
450 case GT_DMA1_DA:
451 case GT_DMA2_DA:
452 case GT_DMA3_DA:
453 case GT_DMA0_NEXT:
454 case GT_DMA1_NEXT:
455 case GT_DMA2_NEXT:
456 case GT_DMA3_NEXT:
457 case GT_DMA0_CUR:
458 case GT_DMA1_CUR:
459 case GT_DMA2_CUR:
460 case GT_DMA3_CUR:
461 /* Not implemented */
462 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
463 break;
464
465 /* DMA Channel Control */
466 case GT_DMA0_CTRL:
467 case GT_DMA1_CTRL:
468 case GT_DMA2_CTRL:
469 case GT_DMA3_CTRL:
470 /* Not implemented */
471 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
472 break;
473
474 /* DMA Arbiter */
475 case GT_DMA_ARB:
476 /* Not implemented */
477 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
478 break;
479
480 /* Timer/Counter */
481 case GT_TC0:
482 case GT_TC1:
483 case GT_TC2:
484 case GT_TC3:
485 case GT_TC_CONTROL:
486 /* Not implemented */
487 dprintf ("Unimplemented timer register offset 0x%x\n", saddr << 2);
488 break;
489
fde7d5bd
TS		 490 /* PCI Internal */
491 case GT_PCI0_CMD:
492 case GT_PCI1_CMD:
493 s->regs[saddr] = val & 0x0401fc0f;
494 break;
05b4ff43
TS		 495 case GT_PCI0_TOR:
496 case GT_PCI0_BS_SCS10:
497 case GT_PCI0_BS_SCS32:
498 case GT_PCI0_BS_CS20:
499 case GT_PCI0_BS_CS3BT:
500 case GT_PCI1_IACK:
501 case GT_PCI0_IACK:
502 case GT_PCI0_BARE:
503 case GT_PCI0_PREFMBR:
504 case GT_PCI0_SCS10_BAR:
505 case GT_PCI0_SCS32_BAR:
506 case GT_PCI0_CS20_BAR:
507 case GT_PCI0_CS3BT_BAR:
508 case GT_PCI0_SSCS10_BAR:
509 case GT_PCI0_SSCS32_BAR:
510 case GT_PCI0_SCS3BT_BAR:
511 case GT_PCI1_TOR:
512 case GT_PCI1_BS_SCS10:
513 case GT_PCI1_BS_SCS32:
514 case GT_PCI1_BS_CS20:
515 case GT_PCI1_BS_CS3BT:
516 case GT_PCI1_BARE:
517 case GT_PCI1_PREFMBR:
518 case GT_PCI1_SCS10_BAR:
519 case GT_PCI1_SCS32_BAR:
520 case GT_PCI1_CS20_BAR:
521 case GT_PCI1_CS3BT_BAR:
522 case GT_PCI1_SSCS10_BAR:
523 case GT_PCI1_SSCS32_BAR:
524 case GT_PCI1_SCS3BT_BAR:
525 case GT_PCI1_CFGADDR:
526 case GT_PCI1_CFGDATA:
527 /* not implemented */
528 break;
fde7d5bd
TS		 529 case GT_PCI0_CFGADDR:
530 s->pci->config_reg = val & 0x80fffffc;
531 break;
532 case GT_PCI0_CFGDATA:
1931e260 533 pci_host_data_writel(s->pci, 0, val);
05b4ff43
TS		 534 break;
535
536 /* Interrupts */
537 case GT_INTRCAUSE:
538 /* not really implemented */
539 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
540 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
541 dprintf("INTRCAUSE %x\n", val);
542 break;
543 case GT_INTRMASK:
544 s->regs[saddr] = val & 0x3c3ffffe;
545 dprintf("INTRMASK %x\n", val);
546 break;
547 case GT_PCI0_ICMASK:
548 s->regs[saddr] = val & 0x03fffffe;
549 dprintf("ICMASK %x\n", val);
550 break;
551 case GT_PCI0_SERR0MASK:
552 s->regs[saddr] = val & 0x0000003f;
553 dprintf("SERR0MASK %x\n", val);
554 break;
555
556 /* Reserved when only PCI_0 is configured. */
557 case GT_HINTRCAUSE:
558 case GT_CPU_INTSEL:
559 case GT_PCI0_INTSEL:
560 case GT_HINTRMASK:
561 case GT_PCI0_HICMASK:
562 case GT_PCI1_SERR1MASK:
563 /* not implemented */
fde7d5bd
TS		 564 break;
565
0da75eb1
TS		 566 /* SDRAM Parameters */
567 case GT_SDRAM_B0:
568 case GT_SDRAM_B1:
569 case GT_SDRAM_B2:
570 case GT_SDRAM_B3:
571 /* We don't simulate electrical parameters of the SDRAM.
572 Accept, but ignore the values. */
573 s->regs[saddr] = val;
574 break;
575
fde7d5bd 576 default:
05b4ff43 577 dprintf ("Bad register offset 0x%x\n", (int)addr);
fde7d5bd
TS		 578 break;
579 }
580}
581
582static uint32_t gt64120_readl (void *opaque,
583 target_phys_addr_t addr)
584{
585 GT64120State *s = opaque;
586 uint32_t val;
587 uint32_t saddr;
588
fde7d5bd 589 saddr = (addr & 0xfff) >> 2;
fde7d5bd
TS		 590 switch (saddr) {
591
0da75eb1
TS		 592 /* CPU Configuration */
593 case GT_MULTI:
594 /* Only one GT64xxx is present on the CPU bus, return
595 the initial value */
596 val = s->regs[saddr];
597 break;
598
fde7d5bd
TS		 599 /* CPU Error Report */
600 case GT_CPUERR_ADDRLO:
601 case GT_CPUERR_ADDRHI:
602 case GT_CPUERR_DATALO:
603 case GT_CPUERR_DATAHI:
604 case GT_CPUERR_PARITY:
0da75eb1 605 /* Emulated memory has no error, always return the initial
5fafdf24 606 values */
0da75eb1
TS		 607 val = s->regs[saddr];
608 break;
609
610 /* CPU Sync Barrier */
611 case GT_PCI0SYNC:
612 case GT_PCI1SYNC:
613 /* Reading those register should empty all FIFO on the PCI
614 bus, which are not emulated. The return value should be
615 a random value that should be ignored. */
5fafdf24 616 val = 0xc000ffee;
fde7d5bd
TS		 617 break;
618
619 /* ECC */
620 case GT_ECC_ERRDATALO:
621 case GT_ECC_ERRDATAHI:
622 case GT_ECC_MEM:
623 case GT_ECC_CALC:
624 case GT_ECC_ERRADDR:
0da75eb1 625 /* Emulated memory has no error, always return the initial
5fafdf24 626 values */
0da75eb1 627 val = s->regs[saddr];
fde7d5bd
TS		 628 break;
629
630 case GT_CPU:
05b4ff43
TS		 631 case GT_SCS10LD:
632 case GT_SCS10HD:
633 case GT_SCS32LD:
634 case GT_SCS32HD:
635 case GT_CS20LD:
636 case GT_CS20HD:
637 case GT_CS3BOOTLD:
638 case GT_CS3BOOTHD:
639 case GT_SCS10AR:
640 case GT_SCS32AR:
641 case GT_CS20R:
642 case GT_CS3BOOTR:
fde7d5bd
TS		 643 case GT_PCI0IOLD:
644 case GT_PCI0M0LD:
645 case GT_PCI0M1LD:
646 case GT_PCI1IOLD:
647 case GT_PCI1M0LD:
648 case GT_PCI1M1LD:
649 case GT_PCI0IOHD:
650 case GT_PCI0M0HD:
651 case GT_PCI0M1HD:
652 case GT_PCI1IOHD:
653 case GT_PCI1M0HD:
654 case GT_PCI1M1HD:
fde7d5bd
TS		 655 case GT_PCI0IOREMAP:
656 case GT_PCI0M0REMAP:
657 case GT_PCI0M1REMAP:
658 case GT_PCI1IOREMAP:
659 case GT_PCI1M0REMAP:
660 case GT_PCI1M1REMAP:
05b4ff43 661 case GT_ISD:
fde7d5bd
TS		 662 val = s->regs[saddr];
663 break;
664 case GT_PCI0_IACK:
5fafdf24 665 /* Read the IRQ number */
4de9b249 666 val = pic_read_irq(isa_pic);
fde7d5bd
TS		 667 break;
668
05b4ff43
TS		 669 /* SDRAM and Device Address Decode */
670 case GT_SCS0LD:
671 case GT_SCS0HD:
672 case GT_SCS1LD:
673 case GT_SCS1HD:
674 case GT_SCS2LD:
675 case GT_SCS2HD:
676 case GT_SCS3LD:
677 case GT_SCS3HD:
678 case GT_CS0LD:
679 case GT_CS0HD:
680 case GT_CS1LD:
681 case GT_CS1HD:
682 case GT_CS2LD:
683 case GT_CS2HD:
684 case GT_CS3LD:
685 case GT_CS3HD:
686 case GT_BOOTLD:
687 case GT_BOOTHD:
688 case GT_ADERR:
689 val = s->regs[saddr];
690 break;
691
692 /* SDRAM Configuration */
693 case GT_SDRAM_CFG:
694 case GT_SDRAM_OPMODE:
695 case GT_SDRAM_BM:
696 case GT_SDRAM_ADDRDECODE:
697 val = s->regs[saddr];
698 break;
699
0da75eb1
TS		 700 /* SDRAM Parameters */
701 case GT_SDRAM_B0:
702 case GT_SDRAM_B1:
703 case GT_SDRAM_B2:
704 case GT_SDRAM_B3:
705 /* We don't simulate electrical parameters of the SDRAM.
706 Just return the last written value. */
707 val = s->regs[saddr];
708 break;
709
05b4ff43
TS		 710 /* Device Parameters */
711 case GT_DEV_B0:
712 case GT_DEV_B1:
713 case GT_DEV_B2:
714 case GT_DEV_B3:
715 case GT_DEV_BOOT:
716 val = s->regs[saddr];
717 break;
718
719 /* DMA Record */
720 case GT_DMA0_CNT:
721 case GT_DMA1_CNT:
722 case GT_DMA2_CNT:
723 case GT_DMA3_CNT:
724 case GT_DMA0_SA:
725 case GT_DMA1_SA:
726 case GT_DMA2_SA:
727 case GT_DMA3_SA:
728 case GT_DMA0_DA:
729 case GT_DMA1_DA:
730 case GT_DMA2_DA:
731 case GT_DMA3_DA:
732 case GT_DMA0_NEXT:
733 case GT_DMA1_NEXT:
734 case GT_DMA2_NEXT:
735 case GT_DMA3_NEXT:
736 case GT_DMA0_CUR:
737 case GT_DMA1_CUR:
738 case GT_DMA2_CUR:
739 case GT_DMA3_CUR:
740 val = s->regs[saddr];
741 break;
742
743 /* DMA Channel Control */
744 case GT_DMA0_CTRL:
745 case GT_DMA1_CTRL:
746 case GT_DMA2_CTRL:
747 case GT_DMA3_CTRL:
748 val = s->regs[saddr];
749 break;
750
751 /* DMA Arbiter */
752 case GT_DMA_ARB:
753 val = s->regs[saddr];
754 break;
755
756 /* Timer/Counter */
757 case GT_TC0:
758 case GT_TC1:
759 case GT_TC2:
760 case GT_TC3:
761 case GT_TC_CONTROL:
762 val = s->regs[saddr];
763 break;
764
fde7d5bd
TS		 765 /* PCI Internal */
766 case GT_PCI0_CFGADDR:
767 val = s->pci->config_reg;
768 break;
769 case GT_PCI0_CFGDATA:
1931e260 770 val = pci_host_data_readl(s->pci, 0);
05b4ff43
TS		 771 break;
772
773 case GT_PCI0_CMD:
774 case GT_PCI0_TOR:
775 case GT_PCI0_BS_SCS10:
776 case GT_PCI0_BS_SCS32:
777 case GT_PCI0_BS_CS20:
778 case GT_PCI0_BS_CS3BT:
779 case GT_PCI1_IACK:
780 case GT_PCI0_BARE:
781 case GT_PCI0_PREFMBR:
782 case GT_PCI0_SCS10_BAR:
783 case GT_PCI0_SCS32_BAR:
784 case GT_PCI0_CS20_BAR:
785 case GT_PCI0_CS3BT_BAR:
786 case GT_PCI0_SSCS10_BAR:
787 case GT_PCI0_SSCS32_BAR:
788 case GT_PCI0_SCS3BT_BAR:
789 case GT_PCI1_CMD:
790 case GT_PCI1_TOR:
791 case GT_PCI1_BS_SCS10:
792 case GT_PCI1_BS_SCS32:
793 case GT_PCI1_BS_CS20:
794 case GT_PCI1_BS_CS3BT:
795 case GT_PCI1_BARE:
796 case GT_PCI1_PREFMBR:
797 case GT_PCI1_SCS10_BAR:
798 case GT_PCI1_SCS32_BAR:
799 case GT_PCI1_CS20_BAR:
800 case GT_PCI1_CS3BT_BAR:
801 case GT_PCI1_SSCS10_BAR:
802 case GT_PCI1_SSCS32_BAR:
803 case GT_PCI1_SCS3BT_BAR:
804 case GT_PCI1_CFGADDR:
805 case GT_PCI1_CFGDATA:
806 val = s->regs[saddr];
807 break;
808
809 /* Interrupts */
810 case GT_INTRCAUSE:
811 val = s->regs[saddr];
812 dprintf("INTRCAUSE %x\n", val);
813 break;
814 case GT_INTRMASK:
815 val = s->regs[saddr];
816 dprintf("INTRMASK %x\n", val);
817 break;
818 case GT_PCI0_ICMASK:
819 val = s->regs[saddr];
820 dprintf("ICMASK %x\n", val);
821 break;
822 case GT_PCI0_SERR0MASK:
823 val = s->regs[saddr];
824 dprintf("SERR0MASK %x\n", val);
825 break;
826
827 /* Reserved when only PCI_0 is configured. */
828 case GT_HINTRCAUSE:
829 case GT_CPU_INTSEL:
830 case GT_PCI0_INTSEL:
831 case GT_HINTRMASK:
832 case GT_PCI0_HICMASK:
833 case GT_PCI1_SERR1MASK:
834 val = s->regs[saddr];
fde7d5bd
TS		 835 break;
836
837 default:
838 val = s->regs[saddr];
05b4ff43 839 dprintf ("Bad register offset 0x%x\n", (int)addr);
fde7d5bd
TS		 840 break;
841 }
842
1931e260
TS		 843 if (!(s->regs[GT_PCI0_CMD] & 1))
844 val = bswap32(val);
845
05b4ff43 846 return val;
fde7d5bd
TS		 847}
848
849static CPUWriteMemoryFunc *gt64120_write[] = {
850 &gt64120_writel,
851 &gt64120_writel,
852 &gt64120_writel,
853};
854
855static CPUReadMemoryFunc *gt64120_read[] = {
856 &gt64120_readl,
857 &gt64120_readl,
858 &gt64120_readl,
859};
860
861static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
862{
863 int slot;
864
865 slot = (pci_dev->devfn >> 3);
866
867 switch (slot) {
868 /* PIIX4 USB */
869 case 10:
870 return 3;
871 /* AMD 79C973 Ethernet */
872 case 11:
d4a4d056 873 return 1;
fde7d5bd
TS		 874 /* Crystal 4281 Sound */
875 case 12:
d4a4d056 876 return 2;
fde7d5bd
TS		 877 /* PCI slot 1 to 4 */
878 case 18 ... 21:
879 return ((slot - 18) + irq_num) & 0x03;
880 /* Unknown device, don't do any translation */
881 default:
882 return irq_num;
883 }
884}
885
886extern PCIDevice *piix4_dev;
887static int pci_irq_levels[4];
888
d537cf6c 889static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level)
fde7d5bd
TS		 890{
891 int i, pic_irq, pic_level;
892
893 pci_irq_levels[irq_num] = level;
894
895 /* now we change the pic irq level according to the piix irq mappings */
896 /* XXX: optimize */
897 pic_irq = piix4_dev->config[0x60 + irq_num];
898 if (pic_irq < 16) {
899 /* The pic level is the logical OR of all the PCI irqs mapped
900 to it */
901 pic_level = 0;
902 for (i = 0; i < 4; i++) {
903 if (pic_irq == piix4_dev->config[0x60 + i])
904 pic_level |= pci_irq_levels[i];
905 }
d537cf6c 906 qemu_set_irq(pic[pic_irq], pic_level);
fde7d5bd
TS		 907 }
908}
909
910
9596ebb7 911static void gt64120_reset(void *opaque)
fde7d5bd
TS		 912{
913 GT64120State *s = opaque;
914
30b6f3a8
TS		 915 /* FIXME: Malta specific hw assumptions ahead */
916
fde7d5bd
TS		 917 /* CPU Configuration */
918#ifdef TARGET_WORDS_BIGENDIAN
919 s->regs[GT_CPU] = 0x00000000;
920#else
bc687ec9 921 s->regs[GT_CPU] = 0x00001000;
fde7d5bd 922#endif
30b6f3a8
TS		 923 s->regs[GT_MULTI] = 0x00000003;
924
925 /* CPU Address decode */
926 s->regs[GT_SCS10LD] = 0x00000000;
927 s->regs[GT_SCS10HD] = 0x00000007;
928 s->regs[GT_SCS32LD] = 0x00000008;
929 s->regs[GT_SCS32HD] = 0x0000000f;
930 s->regs[GT_CS20LD] = 0x000000e0;
931 s->regs[GT_CS20HD] = 0x00000070;
932 s->regs[GT_CS3BOOTLD] = 0x000000f8;
933 s->regs[GT_CS3BOOTHD] = 0x0000007f;
fde7d5bd 934
fde7d5bd
TS		 935 s->regs[GT_PCI0IOLD] = 0x00000080;
936 s->regs[GT_PCI0IOHD] = 0x0000000f;
937 s->regs[GT_PCI0M0LD] = 0x00000090;
938 s->regs[GT_PCI0M0HD] = 0x0000001f;
30b6f3a8 939 s->regs[GT_ISD] = 0x000000a0;
fde7d5bd
TS		 940 s->regs[GT_PCI0M1LD] = 0x00000790;
941 s->regs[GT_PCI0M1HD] = 0x0000001f;
942 s->regs[GT_PCI1IOLD] = 0x00000100;
943 s->regs[GT_PCI1IOHD] = 0x0000000f;
944 s->regs[GT_PCI1M0LD] = 0x00000110;
945 s->regs[GT_PCI1M0HD] = 0x0000001f;
946 s->regs[GT_PCI1M1LD] = 0x00000120;
947 s->regs[GT_PCI1M1HD] = 0x0000002f;
30b6f3a8
TS		 948
949 s->regs[GT_SCS10AR] = 0x00000000;
950 s->regs[GT_SCS32AR] = 0x00000008;
951 s->regs[GT_CS20R] = 0x000000e0;
952 s->regs[GT_CS3BOOTR] = 0x000000f8;
953
fde7d5bd
TS		 954 s->regs[GT_PCI0IOREMAP] = 0x00000080;
955 s->regs[GT_PCI0M0REMAP] = 0x00000090;
956 s->regs[GT_PCI0M1REMAP] = 0x00000790;
957 s->regs[GT_PCI1IOREMAP] = 0x00000100;
958 s->regs[GT_PCI1M0REMAP] = 0x00000110;
959 s->regs[GT_PCI1M1REMAP] = 0x00000120;
960
961 /* CPU Error Report */
962 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
963 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
964 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
965 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
966 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
967
30b6f3a8
TS		 968 /* CPU Sync Barrier */
969 s->regs[GT_PCI0SYNC] = 0x00000000;
970 s->regs[GT_PCI1SYNC] = 0x00000000;
971
972 /* SDRAM and Device Address Decode */
973 s->regs[GT_SCS0LD] = 0x00000000;
974 s->regs[GT_SCS0HD] = 0x00000007;
975 s->regs[GT_SCS1LD] = 0x00000008;
976 s->regs[GT_SCS1HD] = 0x0000000f;
977 s->regs[GT_SCS2LD] = 0x00000010;
978 s->regs[GT_SCS2HD] = 0x00000017;
979 s->regs[GT_SCS3LD] = 0x00000018;
980 s->regs[GT_SCS3HD] = 0x0000001f;
981 s->regs[GT_CS0LD] = 0x000000c0;
982 s->regs[GT_CS0HD] = 0x000000c7;
983 s->regs[GT_CS1LD] = 0x000000c8;
984 s->regs[GT_CS1HD] = 0x000000cf;
985 s->regs[GT_CS2LD] = 0x000000d0;
986 s->regs[GT_CS2HD] = 0x000000df;
987 s->regs[GT_CS3LD] = 0x000000f0;
988 s->regs[GT_CS3HD] = 0x000000fb;
989 s->regs[GT_BOOTLD] = 0x000000fc;
990 s->regs[GT_BOOTHD] = 0x000000ff;
991 s->regs[GT_ADERR] = 0xffffffff;
992
993 /* SDRAM Configuration */
994 s->regs[GT_SDRAM_CFG] = 0x00000200;
995 s->regs[GT_SDRAM_OPMODE] = 0x00000000;
996 s->regs[GT_SDRAM_BM] = 0x00000007;
997 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
998
999 /* SDRAM Parameters */
1000 s->regs[GT_SDRAM_B0] = 0x00000005;
1001 s->regs[GT_SDRAM_B1] = 0x00000005;
1002 s->regs[GT_SDRAM_B2] = 0x00000005;
1003 s->regs[GT_SDRAM_B3] = 0x00000005;
1004
fde7d5bd
TS		 1005 /* ECC */
1006 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1007 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1008 s->regs[GT_ECC_MEM] = 0x00000000;
1009 s->regs[GT_ECC_CALC] = 0x00000000;
1010 s->regs[GT_ECC_ERRADDR] = 0x00000000;
1011
30b6f3a8
TS		 1012 /* Device Parameters */
1013 s->regs[GT_DEV_B0] = 0x386fffff;
1014 s->regs[GT_DEV_B1] = 0x386fffff;
1015 s->regs[GT_DEV_B2] = 0x386fffff;
1016 s->regs[GT_DEV_B3] = 0x386fffff;
1017 s->regs[GT_DEV_BOOT] = 0x146fffff;
0da75eb1 1018
30b6f3a8
TS		 1019 /* DMA registers are all zeroed at reset */
1020
1021 /* Timer/Counter */
1022 s->regs[GT_TC0] = 0xffffffff;
1023 s->regs[GT_TC1] = 0x00ffffff;
1024 s->regs[GT_TC2] = 0x00ffffff;
1025 s->regs[GT_TC3] = 0x00ffffff;
1026 s->regs[GT_TC_CONTROL] = 0x00000000;
1027
1028 /* PCI Internal */
fde7d5bd
TS		 1029#ifdef TARGET_WORDS_BIGENDIAN
1030 s->regs[GT_PCI0_CMD] = 0x00000000;
fde7d5bd
TS		 1031#else
1032 s->regs[GT_PCI0_CMD] = 0x00010001;
fde7d5bd 1033#endif
30b6f3a8
TS		 1034 s->regs[GT_PCI0_TOR] = 0x0000070f;
1035 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1036 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1037 s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1038 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
fde7d5bd 1039 s->regs[GT_PCI1_IACK] = 0x00000000;
30b6f3a8
TS		 1040 s->regs[GT_PCI0_IACK] = 0x00000000;
1041 s->regs[GT_PCI0_BARE] = 0x0000000f;
1042 s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1043 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1044 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1045 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1046 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1047 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1048 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1049 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1050#ifdef TARGET_WORDS_BIGENDIAN
1051 s->regs[GT_PCI1_CMD] = 0x00000000;
1052#else
1053 s->regs[GT_PCI1_CMD] = 0x00010001;
1054#endif
1055 s->regs[GT_PCI1_TOR] = 0x0000070f;
1056 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1057 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1058 s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1059 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1060 s->regs[GT_PCI1_BARE] = 0x0000000f;
1061 s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1062 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1063 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1064 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1065 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1066 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1067 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1068 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1069 s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1070 s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1071 s->regs[GT_PCI0_CFGADDR] = 0x00000000;
1072 s->regs[GT_PCI0_CFGDATA] = 0x00000000;
1073
1074 /* Interrupt registers are all zeroed at reset */
fde7d5bd 1075
a0a8793e 1076 gt64120_isd_mapping(s);
9414cc6f 1077 gt64120_pci_mapping(s);
fde7d5bd
TS		 1078}
1079
bc687ec9
TS		 1080static uint32_t gt64120_read_config(PCIDevice *d, uint32_t address, int len)
1081{
1931e260 1082 return pci_default_read_config(d, address, len);
bc687ec9
TS		 1083}
1084
1085static void gt64120_write_config(PCIDevice *d, uint32_t address, uint32_t val,
1086 int len)
1087{
bc687ec9
TS		 1088 pci_default_write_config(d, address, val, len);
1089}
1090
1823082c
TS		 1091static void gt64120_save(QEMUFile* f, void *opaque)
1092{
1093 PCIDevice *d = opaque;
1094 pci_device_save(d, f);
1095}
1096
1097static int gt64120_load(QEMUFile* f, void *opaque, int version_id)
1098{
1099 PCIDevice *d = opaque;
1100 int ret;
1101
1102 if (version_id != 1)
1103 return -EINVAL;
1104 ret = pci_device_load(d, f);
1105 if (ret < 0)
1106 return ret;
1107 return 0;
1108}
1109
d537cf6c 1110PCIBus *pci_gt64120_init(qemu_irq *pic)
fde7d5bd
TS		 1111{
1112 GT64120State *s;
1113 PCIDevice *d;
fde7d5bd 1114
bd37ec21
FB		 1115 (void)&pci_host_data_writeb; /* avoid warning */
1116 (void)&pci_host_data_writew; /* avoid warning */
1117 (void)&pci_host_data_readb; /* avoid warning */
1118 (void)&pci_host_data_readw; /* avoid warning */
1119
fde7d5bd
TS		 1120 s = qemu_mallocz(sizeof(GT64120State));
1121 s->pci = qemu_mallocz(sizeof(GT64120PCIState));
9414cc6f 1122
fde7d5bd
TS		 1123 s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq,
1124 pic, 144, 4);
a0a8793e 1125 s->ISD_handle = cpu_register_io_memory(0, gt64120_read, gt64120_write, s);
fde7d5bd 1126 d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
bc687ec9 1127 0, gt64120_read_config, gt64120_write_config);
fde7d5bd 1128
0f78cf0c
TS		 1129 /* FIXME: Malta specific hw assumptions ahead */
1130
a0a8793e 1131 d->config[0x00] = 0xab; /* vendor_id */
fde7d5bd 1132 d->config[0x01] = 0x11;
a0a8793e 1133 d->config[0x02] = 0x20; /* device_id */
bc687ec9 1134 d->config[0x03] = 0x46;
0f78cf0c
TS		 1135
1136 d->config[0x04] = 0x00;
fde7d5bd
TS		 1137 d->config[0x05] = 0x00;
1138 d->config[0x06] = 0x80;
0f78cf0c
TS		 1139 d->config[0x07] = 0x02;
1140
fde7d5bd
TS		 1141 d->config[0x08] = 0x10;
1142 d->config[0x09] = 0x00;
0f78cf0c
TS		 1143 d->config[0x0A] = 0x00;
1144 d->config[0x0B] = 0x06;
1145
1146 d->config[0x10] = 0x08;
1147 d->config[0x14] = 0x08;
1148 d->config[0x17] = 0x01;
fde7d5bd
TS		 1149 d->config[0x1B] = 0x1c;
1150 d->config[0x1F] = 0x1f;
1151 d->config[0x23] = 0x14;
0f78cf0c 1152 d->config[0x24] = 0x01;
fde7d5bd
TS		 1153 d->config[0x27] = 0x14;
1154 d->config[0x3D] = 0x01;
1155
a0a8793e
TS		 1156 gt64120_reset(s);
1157
1823082c
TS		 1158 register_savevm("GT64120 PCI Bus", 0, 1, gt64120_save, gt64120_load, d);
1159
fde7d5bd
TS		 1160 return s->pci->bus;
1161}
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