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Handle IBE on MIPS properly.
[qemu.git] / hw / gt64xxx.c
CommitLineData
fde7d5bd
TS		 1/*
2 * QEMU GT64120 PCI host
3 *
4de9b249 4 * Copyright (c) 2006,2007 Aurelien Jarno
5fafdf24 5 *
fde7d5bd
TS		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#include "vl.h"
05b4ff43 26
fde7d5bd
TS		 27typedef target_phys_addr_t pci_addr_t;
28#include "pci_host.h"
29
05b4ff43
TS		 30//#define DEBUG
31
32#ifdef DEBUG
33#define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
34#else
35#define dprintf(fmt, ...)
36#endif
37
fde7d5bd
TS		 38#define GT_REGS (0x1000 >> 2)
39
40/* CPU Configuration */
41#define GT_CPU (0x000 >> 2)
42#define GT_MULTI (0x120 >> 2)
43
44/* CPU Address Decode */
45#define GT_SCS10LD (0x008 >> 2)
46#define GT_SCS10HD (0x010 >> 2)
47#define GT_SCS32LD (0x018 >> 2)
48#define GT_SCS32HD (0x020 >> 2)
49#define GT_CS20LD (0x028 >> 2)
50#define GT_CS20HD (0x030 >> 2)
51#define GT_CS3BOOTLD (0x038 >> 2)
52#define GT_CS3BOOTHD (0x040 >> 2)
53#define GT_PCI0IOLD (0x048 >> 2)
54#define GT_PCI0IOHD (0x050 >> 2)
55#define GT_PCI0M0LD (0x058 >> 2)
56#define GT_PCI0M0HD (0x060 >> 2)
fde7d5bd
TS		 57#define GT_PCI0M1LD (0x080 >> 2)
58#define GT_PCI0M1HD (0x088 >> 2)
59#define GT_PCI1IOLD (0x090 >> 2)
60#define GT_PCI1IOHD (0x098 >> 2)
61#define GT_PCI1M0LD (0x0a0 >> 2)
62#define GT_PCI1M0HD (0x0a8 >> 2)
63#define GT_PCI1M1LD (0x0b0 >> 2)
64#define GT_PCI1M1HD (0x0b8 >> 2)
05b4ff43 65#define GT_ISD (0x068 >> 2)
fde7d5bd
TS		 66
67#define GT_SCS10AR (0x0d0 >> 2)
68#define GT_SCS32AR (0x0d8 >> 2)
69#define GT_CS20R (0x0e0 >> 2)
70#define GT_CS3BOOTR (0x0e8 >> 2)
71
72#define GT_PCI0IOREMAP (0x0f0 >> 2)
73#define GT_PCI0M0REMAP (0x0f8 >> 2)
74#define GT_PCI0M1REMAP (0x100 >> 2)
75#define GT_PCI1IOREMAP (0x108 >> 2)
76#define GT_PCI1M0REMAP (0x110 >> 2)
77#define GT_PCI1M1REMAP (0x118 >> 2)
78
79/* CPU Error Report */
80#define GT_CPUERR_ADDRLO (0x070 >> 2)
81#define GT_CPUERR_ADDRHI (0x078 >> 2)
82#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
83#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
84#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
85
86/* CPU Sync Barrier */
87#define GT_PCI0SYNC (0x0c0 >> 2)
88#define GT_PCI1SYNC (0x0c8 >> 2)
89
90/* SDRAM and Device Address Decode */
91#define GT_SCS0LD (0x400 >> 2)
92#define GT_SCS0HD (0x404 >> 2)
93#define GT_SCS1LD (0x408 >> 2)
94#define GT_SCS1HD (0x40c >> 2)
95#define GT_SCS2LD (0x410 >> 2)
96#define GT_SCS2HD (0x414 >> 2)
97#define GT_SCS3LD (0x418 >> 2)
98#define GT_SCS3HD (0x41c >> 2)
99#define GT_CS0LD (0x420 >> 2)
100#define GT_CS0HD (0x424 >> 2)
101#define GT_CS1LD (0x428 >> 2)
102#define GT_CS1HD (0x42c >> 2)
103#define GT_CS2LD (0x430 >> 2)
104#define GT_CS2HD (0x434 >> 2)
105#define GT_CS3LD (0x438 >> 2)
106#define GT_CS3HD (0x43c >> 2)
107#define GT_BOOTLD (0x440 >> 2)
108#define GT_BOOTHD (0x444 >> 2)
109#define GT_ADERR (0x470 >> 2)
110
111/* SDRAM Configuration */
112#define GT_SDRAM_CFG (0x448 >> 2)
113#define GT_SDRAM_OPMODE (0x474 >> 2)
114#define GT_SDRAM_BM (0x478 >> 2)
115#define GT_SDRAM_ADDRDECODE (0x47c >> 2)
116
117/* SDRAM Parameters */
118#define GT_SDRAM_B0 (0x44c >> 2)
119#define GT_SDRAM_B1 (0x450 >> 2)
120#define GT_SDRAM_B2 (0x454 >> 2)
121#define GT_SDRAM_B3 (0x458 >> 2)
122
123/* Device Parameters */
124#define GT_DEV_B0 (0x45c >> 2)
125#define GT_DEV_B1 (0x460 >> 2)
126#define GT_DEV_B2 (0x464 >> 2)
127#define GT_DEV_B3 (0x468 >> 2)
128#define GT_DEV_BOOT (0x46c >> 2)
129
130/* ECC */
131#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
132#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
133#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
134#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
135#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
136
137/* DMA Record */
138#define GT_DMA0_CNT (0x800 >> 2)
139#define GT_DMA1_CNT (0x804 >> 2)
140#define GT_DMA2_CNT (0x808 >> 2)
141#define GT_DMA3_CNT (0x80c >> 2)
142#define GT_DMA0_SA (0x810 >> 2)
143#define GT_DMA1_SA (0x814 >> 2)
144#define GT_DMA2_SA (0x818 >> 2)
145#define GT_DMA3_SA (0x81c >> 2)
146#define GT_DMA0_DA (0x820 >> 2)
147#define GT_DMA1_DA (0x824 >> 2)
148#define GT_DMA2_DA (0x828 >> 2)
149#define GT_DMA3_DA (0x82c >> 2)
150#define GT_DMA0_NEXT (0x830 >> 2)
151#define GT_DMA1_NEXT (0x834 >> 2)
152#define GT_DMA2_NEXT (0x838 >> 2)
153#define GT_DMA3_NEXT (0x83c >> 2)
154#define GT_DMA0_CUR (0x870 >> 2)
155#define GT_DMA1_CUR (0x874 >> 2)
156#define GT_DMA2_CUR (0x878 >> 2)
157#define GT_DMA3_CUR (0x87c >> 2)
158
159/* DMA Channel Control */
160#define GT_DMA0_CTRL (0x840 >> 2)
161#define GT_DMA1_CTRL (0x844 >> 2)
162#define GT_DMA2_CTRL (0x848 >> 2)
163#define GT_DMA3_CTRL (0x84c >> 2)
164
165/* DMA Arbiter */
166#define GT_DMA_ARB (0x860 >> 2)
167
168/* Timer/Counter */
169#define GT_TC0 (0x850 >> 2)
170#define GT_TC1 (0x854 >> 2)
171#define GT_TC2 (0x858 >> 2)
172#define GT_TC3 (0x85c >> 2)
173#define GT_TC_CONTROL (0x864 >> 2)
174
175/* PCI Internal */
176#define GT_PCI0_CMD (0xc00 >> 2)
177#define GT_PCI0_TOR (0xc04 >> 2)
178#define GT_PCI0_BS_SCS10 (0xc08 >> 2)
179#define GT_PCI0_BS_SCS32 (0xc0c >> 2)
180#define GT_PCI0_BS_CS20 (0xc10 >> 2)
181#define GT_PCI0_BS_CS3BT (0xc14 >> 2)
182#define GT_PCI1_IACK (0xc30 >> 2)
183#define GT_PCI0_IACK (0xc34 >> 2)
184#define GT_PCI0_BARE (0xc3c >> 2)
185#define GT_PCI0_PREFMBR (0xc40 >> 2)
186#define GT_PCI0_SCS10_BAR (0xc48 >> 2)
187#define GT_PCI0_SCS32_BAR (0xc4c >> 2)
188#define GT_PCI0_CS20_BAR (0xc50 >> 2)
189#define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
190#define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
191#define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
192#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
193#define GT_PCI1_CMD (0xc80 >> 2)
194#define GT_PCI1_TOR (0xc84 >> 2)
195#define GT_PCI1_BS_SCS10 (0xc88 >> 2)
196#define GT_PCI1_BS_SCS32 (0xc8c >> 2)
197#define GT_PCI1_BS_CS20 (0xc90 >> 2)
198#define GT_PCI1_BS_CS3BT (0xc94 >> 2)
199#define GT_PCI1_BARE (0xcbc >> 2)
200#define GT_PCI1_PREFMBR (0xcc0 >> 2)
201#define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
202#define GT_PCI1_SCS32_BAR (0xccc >> 2)
203#define GT_PCI1_CS20_BAR (0xcd0 >> 2)
204#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
205#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
206#define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
207#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
208#define GT_PCI1_CFGADDR (0xcf0 >> 2)
209#define GT_PCI1_CFGDATA (0xcf4 >> 2)
210#define GT_PCI0_CFGADDR (0xcf8 >> 2)
211#define GT_PCI0_CFGDATA (0xcfc >> 2)
212
213/* Interrupts */
214#define GT_INTRCAUSE (0xc18 >> 2)
215#define GT_INTRMASK (0xc1c >> 2)
216#define GT_PCI0_ICMASK (0xc24 >> 2)
217#define GT_PCI0_SERR0MASK (0xc28 >> 2)
218#define GT_CPU_INTSEL (0xc70 >> 2)
219#define GT_PCI0_INTSEL (0xc74 >> 2)
220#define GT_HINTRCAUSE (0xc98 >> 2)
221#define GT_HINTRMASK (0xc9c >> 2)
222#define GT_PCI0_HICMASK (0xca4 >> 2)
223#define GT_PCI1_SERR1MASK (0xca8 >> 2)
224
225
226typedef PCIHostState GT64120PCIState;
227
a0a8793e
TS		 228#define PCI_MAPPING_ENTRY(regname) \
229 target_phys_addr_t regname ##_start; \
230 target_phys_addr_t regname ##_length; \
231 int regname ##_handle
232
fde7d5bd
TS		 233typedef struct GT64120State {
234 GT64120PCIState *pci;
235 uint32_t regs[GT_REGS];
a0a8793e
TS		 236 PCI_MAPPING_ENTRY(PCI0IO);
237 PCI_MAPPING_ENTRY(ISD);
fde7d5bd
TS		 238} GT64120State;
239
a0a8793e
TS		 240/* Adjust range to avoid touching space which isn't mappable via PCI */
241/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
242 0x1fc00000 - 0x1fd00000 */
243static void check_reserved_space (target_phys_addr_t *start,
244 target_phys_addr_t *length)
245{
246 target_phys_addr_t begin = *start;
247 target_phys_addr_t end = *start + *length;
248
249 if (end >= 0x1e000000LL && end < 0x1f100000LL)
250 end = 0x1e000000LL;
251 if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
252 begin = 0x1f100000LL;
253 if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
254 end = 0x1fc00000LL;
255 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
256 begin = 0x1fd00000LL;
257 /* XXX: This is broken when a reserved range splits the requested range */
258 if (end >= 0x1f100000LL && begin < 0x1e000000LL)
259 end = 0x1e000000LL;
260 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
261 end = 0x1fc00000LL;
262
263 *start = begin;
264 *length = end - begin;
265}
266
267static void gt64120_isd_mapping(GT64120State *s)
268{
269 target_phys_addr_t start = s->regs[GT_ISD] << 21;
270 target_phys_addr_t length = 0x1000;
271
272 if (s->ISD_length)
273 cpu_register_physical_memory(s->ISD_start, s->ISD_length,
274 IO_MEM_UNASSIGNED);
275 check_reserved_space(&start, &length);
276 length = 0x1000;
277 /* Map new address */
278 dprintf("ISD: %x@%x -> %x@%x, %x\n", s->ISD_length, s->ISD_start,
279 length, start, s->ISD_handle);
280 s->ISD_start = start;
281 s->ISD_length = length;
282 cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle);
283}
284
9414cc6f 285static void gt64120_pci_mapping(GT64120State *s)
2a1086d9 286{
9414cc6f
TS		 287 /* Update IO mapping */
288 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
289 {
3b46e624 290 /* Unmap old IO address */
9414cc6f
TS		 291 if (s->PCI0IO_length)
292 {
3b46e624 293 cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
9414cc6f
TS		 294 }
295 /* Map new IO address */
296 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
297 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
298 isa_mem_base = s->PCI0IO_start;
299 isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
300 }
2a1086d9
TS		 301}
302
fde7d5bd
TS		 303static void gt64120_writel (void *opaque, target_phys_addr_t addr,
304 uint32_t val)
305{
306 GT64120State *s = opaque;
307 uint32_t saddr;
308
0da75eb1
TS		 309#ifdef TARGET_WORDS_BIGENDIAN
310 val = bswap32(val);
311#endif
312
fde7d5bd
TS		 313 saddr = (addr & 0xfff) >> 2;
314 switch (saddr) {
0da75eb1
TS		 315
316 /* CPU Configuration */
fde7d5bd
TS		 317 case GT_CPU:
318 s->regs[GT_CPU] = val;
fde7d5bd
TS		 319 break;
320 case GT_MULTI:
0da75eb1 321 /* Read-only register as only one GT64xxx is present on the CPU bus */
fde7d5bd
TS		 322 break;
323
324 /* CPU Address Decode */
325 case GT_PCI0IOLD:
326 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
327 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
9414cc6f 328 gt64120_pci_mapping(s);
fde7d5bd
TS		 329 break;
330 case GT_PCI0M0LD:
331 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
332 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
fde7d5bd
TS		 333 break;
334 case GT_PCI0M1LD:
335 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
336 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
fde7d5bd
TS		 337 break;
338 case GT_PCI1IOLD:
339 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
340 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
fde7d5bd
TS		 341 break;
342 case GT_PCI1M0LD:
343 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
344 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
fde7d5bd
TS		 345 break;
346 case GT_PCI1M1LD:
347 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
348 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
fde7d5bd
TS		 349 break;
350 case GT_PCI0IOHD:
bb433bef
TS		 351 s->regs[saddr] = val & 0x0000007f;
352 gt64120_pci_mapping(s);
353 break;
fde7d5bd
TS		 354 case GT_PCI0M0HD:
355 case GT_PCI0M1HD:
356 case GT_PCI1IOHD:
357 case GT_PCI1M0HD:
358 case GT_PCI1M1HD:
359 s->regs[saddr] = val & 0x0000007f;
fde7d5bd 360 break;
a0a8793e
TS		 361 case GT_ISD:
362 s->regs[saddr] = val & 0x00007fff;
363 gt64120_isd_mapping(s);
364 break;
365
fde7d5bd
TS		 366 case GT_PCI0IOREMAP:
367 case GT_PCI0M0REMAP:
368 case GT_PCI0M1REMAP:
369 case GT_PCI1IOREMAP:
370 case GT_PCI1M0REMAP:
371 case GT_PCI1M1REMAP:
372 s->regs[saddr] = val & 0x000007ff;
fde7d5bd
TS		 373 break;
374
375 /* CPU Error Report */
376 case GT_CPUERR_ADDRLO:
377 case GT_CPUERR_ADDRHI:
378 case GT_CPUERR_DATALO:
379 case GT_CPUERR_DATAHI:
380 case GT_CPUERR_PARITY:
0da75eb1
TS		 381 /* Read-only registers, do nothing */
382 break;
383
384 /* CPU Sync Barrier */
385 case GT_PCI0SYNC:
386 case GT_PCI1SYNC:
387 /* Read-only registers, do nothing */
fde7d5bd
TS		 388 break;
389
05b4ff43
TS		 390 /* SDRAM and Device Address Decode */
391 case GT_SCS0LD:
392 case GT_SCS0HD:
393 case GT_SCS1LD:
394 case GT_SCS1HD:
395 case GT_SCS2LD:
396 case GT_SCS2HD:
397 case GT_SCS3LD:
398 case GT_SCS3HD:
399 case GT_CS0LD:
400 case GT_CS0HD:
401 case GT_CS1LD:
402 case GT_CS1HD:
403 case GT_CS2LD:
404 case GT_CS2HD:
405 case GT_CS3LD:
406 case GT_CS3HD:
407 case GT_BOOTLD:
408 case GT_BOOTHD:
409 case GT_ADERR:
410 /* SDRAM Configuration */
411 case GT_SDRAM_CFG:
412 case GT_SDRAM_OPMODE:
413 case GT_SDRAM_BM:
414 case GT_SDRAM_ADDRDECODE:
415 /* Accept and ignore SDRAM interleave configuration */
416 s->regs[saddr] = val;
417 break;
418
419 /* Device Parameters */
420 case GT_DEV_B0:
421 case GT_DEV_B1:
422 case GT_DEV_B2:
423 case GT_DEV_B3:
424 case GT_DEV_BOOT:
425 /* Not implemented */
426 dprintf ("Unimplemented device register offset 0x%x\n", saddr << 2);
427 break;
428
fde7d5bd
TS		 429 /* ECC */
430 case GT_ECC_ERRDATALO:
431 case GT_ECC_ERRDATAHI:
432 case GT_ECC_MEM:
433 case GT_ECC_CALC:
434 case GT_ECC_ERRADDR:
0da75eb1 435 /* Read-only registers, do nothing */
fde7d5bd
TS		 436 break;
437
05b4ff43
TS		 438 /* DMA Record */
439 case GT_DMA0_CNT:
440 case GT_DMA1_CNT:
441 case GT_DMA2_CNT:
442 case GT_DMA3_CNT:
443 case GT_DMA0_SA:
444 case GT_DMA1_SA:
445 case GT_DMA2_SA:
446 case GT_DMA3_SA:
447 case GT_DMA0_DA:
448 case GT_DMA1_DA:
449 case GT_DMA2_DA:
450 case GT_DMA3_DA:
451 case GT_DMA0_NEXT:
452 case GT_DMA1_NEXT:
453 case GT_DMA2_NEXT:
454 case GT_DMA3_NEXT:
455 case GT_DMA0_CUR:
456 case GT_DMA1_CUR:
457 case GT_DMA2_CUR:
458 case GT_DMA3_CUR:
459 /* Not implemented */
460 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
461 break;
462
463 /* DMA Channel Control */
464 case GT_DMA0_CTRL:
465 case GT_DMA1_CTRL:
466 case GT_DMA2_CTRL:
467 case GT_DMA3_CTRL:
468 /* Not implemented */
469 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
470 break;
471
472 /* DMA Arbiter */
473 case GT_DMA_ARB:
474 /* Not implemented */
475 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
476 break;
477
478 /* Timer/Counter */
479 case GT_TC0:
480 case GT_TC1:
481 case GT_TC2:
482 case GT_TC3:
483 case GT_TC_CONTROL:
484 /* Not implemented */
485 dprintf ("Unimplemented timer register offset 0x%x\n", saddr << 2);
486 break;
487
fde7d5bd
TS		 488 /* PCI Internal */
489 case GT_PCI0_CMD:
490 case GT_PCI1_CMD:
491 s->regs[saddr] = val & 0x0401fc0f;
492 break;
05b4ff43
TS		 493 case GT_PCI0_TOR:
494 case GT_PCI0_BS_SCS10:
495 case GT_PCI0_BS_SCS32:
496 case GT_PCI0_BS_CS20:
497 case GT_PCI0_BS_CS3BT:
498 case GT_PCI1_IACK:
499 case GT_PCI0_IACK:
500 case GT_PCI0_BARE:
501 case GT_PCI0_PREFMBR:
502 case GT_PCI0_SCS10_BAR:
503 case GT_PCI0_SCS32_BAR:
504 case GT_PCI0_CS20_BAR:
505 case GT_PCI0_CS3BT_BAR:
506 case GT_PCI0_SSCS10_BAR:
507 case GT_PCI0_SSCS32_BAR:
508 case GT_PCI0_SCS3BT_BAR:
509 case GT_PCI1_TOR:
510 case GT_PCI1_BS_SCS10:
511 case GT_PCI1_BS_SCS32:
512 case GT_PCI1_BS_CS20:
513 case GT_PCI1_BS_CS3BT:
514 case GT_PCI1_BARE:
515 case GT_PCI1_PREFMBR:
516 case GT_PCI1_SCS10_BAR:
517 case GT_PCI1_SCS32_BAR:
518 case GT_PCI1_CS20_BAR:
519 case GT_PCI1_CS3BT_BAR:
520 case GT_PCI1_SSCS10_BAR:
521 case GT_PCI1_SSCS32_BAR:
522 case GT_PCI1_SCS3BT_BAR:
523 case GT_PCI1_CFGADDR:
524 case GT_PCI1_CFGDATA:
525 /* not implemented */
526 break;
fde7d5bd
TS		 527 case GT_PCI0_CFGADDR:
528 s->pci->config_reg = val & 0x80fffffc;
529 break;
530 case GT_PCI0_CFGDATA:
05b4ff43
TS		 531 if (s->pci->config_reg & (1u << 31))
532 pci_host_data_writel(s->pci, 0, val);
533 break;
534
535 /* Interrupts */
536 case GT_INTRCAUSE:
537 /* not really implemented */
538 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
539 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
540 dprintf("INTRCAUSE %x\n", val);
541 break;
542 case GT_INTRMASK:
543 s->regs[saddr] = val & 0x3c3ffffe;
544 dprintf("INTRMASK %x\n", val);
545 break;
546 case GT_PCI0_ICMASK:
547 s->regs[saddr] = val & 0x03fffffe;
548 dprintf("ICMASK %x\n", val);
549 break;
550 case GT_PCI0_SERR0MASK:
551 s->regs[saddr] = val & 0x0000003f;
552 dprintf("SERR0MASK %x\n", val);
553 break;
554
555 /* Reserved when only PCI_0 is configured. */
556 case GT_HINTRCAUSE:
557 case GT_CPU_INTSEL:
558 case GT_PCI0_INTSEL:
559 case GT_HINTRMASK:
560 case GT_PCI0_HICMASK:
561 case GT_PCI1_SERR1MASK:
562 /* not implemented */
fde7d5bd
TS		 563 break;
564
0da75eb1
TS		 565 /* SDRAM Parameters */
566 case GT_SDRAM_B0:
567 case GT_SDRAM_B1:
568 case GT_SDRAM_B2:
569 case GT_SDRAM_B3:
570 /* We don't simulate electrical parameters of the SDRAM.
571 Accept, but ignore the values. */
572 s->regs[saddr] = val;
573 break;
574
fde7d5bd 575 default:
05b4ff43 576 dprintf ("Bad register offset 0x%x\n", (int)addr);
fde7d5bd
TS		 577 break;
578 }
579}
580
581static uint32_t gt64120_readl (void *opaque,
582 target_phys_addr_t addr)
583{
584 GT64120State *s = opaque;
585 uint32_t val;
586 uint32_t saddr;
587
588 val = 0;
589 saddr = (addr & 0xfff) >> 2;
590
591 switch (saddr) {
592
0da75eb1
TS		 593 /* CPU Configuration */
594 case GT_MULTI:
595 /* Only one GT64xxx is present on the CPU bus, return
596 the initial value */
597 val = s->regs[saddr];
598 break;
599
fde7d5bd
TS		 600 /* CPU Error Report */
601 case GT_CPUERR_ADDRLO:
602 case GT_CPUERR_ADDRHI:
603 case GT_CPUERR_DATALO:
604 case GT_CPUERR_DATAHI:
605 case GT_CPUERR_PARITY:
0da75eb1 606 /* Emulated memory has no error, always return the initial
5fafdf24 607 values */
0da75eb1
TS		 608 val = s->regs[saddr];
609 break;
610
611 /* CPU Sync Barrier */
612 case GT_PCI0SYNC:
613 case GT_PCI1SYNC:
614 /* Reading those register should empty all FIFO on the PCI
615 bus, which are not emulated. The return value should be
616 a random value that should be ignored. */
5fafdf24 617 val = 0xc000ffee;
fde7d5bd
TS		 618 break;
619
620 /* ECC */
621 case GT_ECC_ERRDATALO:
622 case GT_ECC_ERRDATAHI:
623 case GT_ECC_MEM:
624 case GT_ECC_CALC:
625 case GT_ECC_ERRADDR:
0da75eb1 626 /* Emulated memory has no error, always return the initial
5fafdf24 627 values */
0da75eb1 628 val = s->regs[saddr];
fde7d5bd
TS		 629 break;
630
631 case GT_CPU:
05b4ff43
TS		 632 case GT_SCS10LD:
633 case GT_SCS10HD:
634 case GT_SCS32LD:
635 case GT_SCS32HD:
636 case GT_CS20LD:
637 case GT_CS20HD:
638 case GT_CS3BOOTLD:
639 case GT_CS3BOOTHD:
640 case GT_SCS10AR:
641 case GT_SCS32AR:
642 case GT_CS20R:
643 case GT_CS3BOOTR:
fde7d5bd
TS		 644 case GT_PCI0IOLD:
645 case GT_PCI0M0LD:
646 case GT_PCI0M1LD:
647 case GT_PCI1IOLD:
648 case GT_PCI1M0LD:
649 case GT_PCI1M1LD:
650 case GT_PCI0IOHD:
651 case GT_PCI0M0HD:
652 case GT_PCI0M1HD:
653 case GT_PCI1IOHD:
654 case GT_PCI1M0HD:
655 case GT_PCI1M1HD:
fde7d5bd
TS		 656 case GT_PCI0IOREMAP:
657 case GT_PCI0M0REMAP:
658 case GT_PCI0M1REMAP:
659 case GT_PCI1IOREMAP:
660 case GT_PCI1M0REMAP:
661 case GT_PCI1M1REMAP:
05b4ff43 662 case GT_ISD:
fde7d5bd
TS		 663 val = s->regs[saddr];
664 break;
665 case GT_PCI0_IACK:
5fafdf24 666 /* Read the IRQ number */
4de9b249 667 val = pic_read_irq(isa_pic);
fde7d5bd
TS		 668 break;
669
05b4ff43
TS		 670 /* SDRAM and Device Address Decode */
671 case GT_SCS0LD:
672 case GT_SCS0HD:
673 case GT_SCS1LD:
674 case GT_SCS1HD:
675 case GT_SCS2LD:
676 case GT_SCS2HD:
677 case GT_SCS3LD:
678 case GT_SCS3HD:
679 case GT_CS0LD:
680 case GT_CS0HD:
681 case GT_CS1LD:
682 case GT_CS1HD:
683 case GT_CS2LD:
684 case GT_CS2HD:
685 case GT_CS3LD:
686 case GT_CS3HD:
687 case GT_BOOTLD:
688 case GT_BOOTHD:
689 case GT_ADERR:
690 val = s->regs[saddr];
691 break;
692
693 /* SDRAM Configuration */
694 case GT_SDRAM_CFG:
695 case GT_SDRAM_OPMODE:
696 case GT_SDRAM_BM:
697 case GT_SDRAM_ADDRDECODE:
698 val = s->regs[saddr];
699 break;
700
0da75eb1
TS		 701 /* SDRAM Parameters */
702 case GT_SDRAM_B0:
703 case GT_SDRAM_B1:
704 case GT_SDRAM_B2:
705 case GT_SDRAM_B3:
706 /* We don't simulate electrical parameters of the SDRAM.
707 Just return the last written value. */
708 val = s->regs[saddr];
709 break;
710
05b4ff43
TS		 711 /* Device Parameters */
712 case GT_DEV_B0:
713 case GT_DEV_B1:
714 case GT_DEV_B2:
715 case GT_DEV_B3:
716 case GT_DEV_BOOT:
717 val = s->regs[saddr];
718 break;
719
720 /* DMA Record */
721 case GT_DMA0_CNT:
722 case GT_DMA1_CNT:
723 case GT_DMA2_CNT:
724 case GT_DMA3_CNT:
725 case GT_DMA0_SA:
726 case GT_DMA1_SA:
727 case GT_DMA2_SA:
728 case GT_DMA3_SA:
729 case GT_DMA0_DA:
730 case GT_DMA1_DA:
731 case GT_DMA2_DA:
732 case GT_DMA3_DA:
733 case GT_DMA0_NEXT:
734 case GT_DMA1_NEXT:
735 case GT_DMA2_NEXT:
736 case GT_DMA3_NEXT:
737 case GT_DMA0_CUR:
738 case GT_DMA1_CUR:
739 case GT_DMA2_CUR:
740 case GT_DMA3_CUR:
741 val = s->regs[saddr];
742 break;
743
744 /* DMA Channel Control */
745 case GT_DMA0_CTRL:
746 case GT_DMA1_CTRL:
747 case GT_DMA2_CTRL:
748 case GT_DMA3_CTRL:
749 val = s->regs[saddr];
750 break;
751
752 /* DMA Arbiter */
753 case GT_DMA_ARB:
754 val = s->regs[saddr];
755 break;
756
757 /* Timer/Counter */
758 case GT_TC0:
759 case GT_TC1:
760 case GT_TC2:
761 case GT_TC3:
762 case GT_TC_CONTROL:
763 val = s->regs[saddr];
764 break;
765
fde7d5bd
TS		 766 /* PCI Internal */
767 case GT_PCI0_CFGADDR:
768 val = s->pci->config_reg;
769 break;
770 case GT_PCI0_CFGDATA:
05b4ff43
TS		 771 if (!(s->pci->config_reg & (1u << 31)))
772 val = 0xffffffff;
773 else
f00cb701 774 val = pci_host_data_readl(s->pci, 0);
05b4ff43
TS		 775 break;
776
777 case GT_PCI0_CMD:
778 case GT_PCI0_TOR:
779 case GT_PCI0_BS_SCS10:
780 case GT_PCI0_BS_SCS32:
781 case GT_PCI0_BS_CS20:
782 case GT_PCI0_BS_CS3BT:
783 case GT_PCI1_IACK:
784 case GT_PCI0_BARE:
785 case GT_PCI0_PREFMBR:
786 case GT_PCI0_SCS10_BAR:
787 case GT_PCI0_SCS32_BAR:
788 case GT_PCI0_CS20_BAR:
789 case GT_PCI0_CS3BT_BAR:
790 case GT_PCI0_SSCS10_BAR:
791 case GT_PCI0_SSCS32_BAR:
792 case GT_PCI0_SCS3BT_BAR:
793 case GT_PCI1_CMD:
794 case GT_PCI1_TOR:
795 case GT_PCI1_BS_SCS10:
796 case GT_PCI1_BS_SCS32:
797 case GT_PCI1_BS_CS20:
798 case GT_PCI1_BS_CS3BT:
799 case GT_PCI1_BARE:
800 case GT_PCI1_PREFMBR:
801 case GT_PCI1_SCS10_BAR:
802 case GT_PCI1_SCS32_BAR:
803 case GT_PCI1_CS20_BAR:
804 case GT_PCI1_CS3BT_BAR:
805 case GT_PCI1_SSCS10_BAR:
806 case GT_PCI1_SSCS32_BAR:
807 case GT_PCI1_SCS3BT_BAR:
808 case GT_PCI1_CFGADDR:
809 case GT_PCI1_CFGDATA:
810 val = s->regs[saddr];
811 break;
812
813 /* Interrupts */
814 case GT_INTRCAUSE:
815 val = s->regs[saddr];
816 dprintf("INTRCAUSE %x\n", val);
817 break;
818 case GT_INTRMASK:
819 val = s->regs[saddr];
820 dprintf("INTRMASK %x\n", val);
821 break;
822 case GT_PCI0_ICMASK:
823 val = s->regs[saddr];
824 dprintf("ICMASK %x\n", val);
825 break;
826 case GT_PCI0_SERR0MASK:
827 val = s->regs[saddr];
828 dprintf("SERR0MASK %x\n", val);
829 break;
830
831 /* Reserved when only PCI_0 is configured. */
832 case GT_HINTRCAUSE:
833 case GT_CPU_INTSEL:
834 case GT_PCI0_INTSEL:
835 case GT_HINTRMASK:
836 case GT_PCI0_HICMASK:
837 case GT_PCI1_SERR1MASK:
838 val = s->regs[saddr];
fde7d5bd
TS		 839 break;
840
841 default:
842 val = s->regs[saddr];
05b4ff43 843 dprintf ("Bad register offset 0x%x\n", (int)addr);
fde7d5bd
TS		 844 break;
845 }
846
0da75eb1 847#ifdef TARGET_WORDS_BIGENDIAN
05b4ff43 848 val = bswap32(val);
0da75eb1 849#endif
05b4ff43 850 return val;
fde7d5bd
TS		 851}
852
853static CPUWriteMemoryFunc *gt64120_write[] = {
854 &gt64120_writel,
855 &gt64120_writel,
856 &gt64120_writel,
857};
858
859static CPUReadMemoryFunc *gt64120_read[] = {
860 &gt64120_readl,
861 &gt64120_readl,
862 &gt64120_readl,
863};
864
865static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
866{
867 int slot;
868
869 slot = (pci_dev->devfn >> 3);
870
871 switch (slot) {
872 /* PIIX4 USB */
873 case 10:
874 return 3;
875 /* AMD 79C973 Ethernet */
876 case 11:
d4a4d056 877 return 1;
fde7d5bd
TS		 878 /* Crystal 4281 Sound */
879 case 12:
d4a4d056 880 return 2;
fde7d5bd
TS		 881 /* PCI slot 1 to 4 */
882 case 18 ... 21:
883 return ((slot - 18) + irq_num) & 0x03;
884 /* Unknown device, don't do any translation */
885 default:
886 return irq_num;
887 }
888}
889
890extern PCIDevice *piix4_dev;
891static int pci_irq_levels[4];
892
d537cf6c 893static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level)
fde7d5bd
TS		 894{
895 int i, pic_irq, pic_level;
896
897 pci_irq_levels[irq_num] = level;
898
899 /* now we change the pic irq level according to the piix irq mappings */
900 /* XXX: optimize */
901 pic_irq = piix4_dev->config[0x60 + irq_num];
902 if (pic_irq < 16) {
903 /* The pic level is the logical OR of all the PCI irqs mapped
904 to it */
905 pic_level = 0;
906 for (i = 0; i < 4; i++) {
907 if (pic_irq == piix4_dev->config[0x60 + i])
908 pic_level |= pci_irq_levels[i];
909 }
d537cf6c 910 qemu_set_irq(pic[pic_irq], pic_level);
fde7d5bd
TS		 911 }
912}
913
914
915void gt64120_reset(void *opaque)
916{
917 GT64120State *s = opaque;
918
30b6f3a8
TS		 919 /* FIXME: Malta specific hw assumptions ahead */
920
fde7d5bd
TS		 921 /* CPU Configuration */
922#ifdef TARGET_WORDS_BIGENDIAN
923 s->regs[GT_CPU] = 0x00000000;
924#else
bc687ec9 925 s->regs[GT_CPU] = 0x00001000;
fde7d5bd 926#endif
30b6f3a8
TS		 927 s->regs[GT_MULTI] = 0x00000003;
928
929 /* CPU Address decode */
930 s->regs[GT_SCS10LD] = 0x00000000;
931 s->regs[GT_SCS10HD] = 0x00000007;
932 s->regs[GT_SCS32LD] = 0x00000008;
933 s->regs[GT_SCS32HD] = 0x0000000f;
934 s->regs[GT_CS20LD] = 0x000000e0;
935 s->regs[GT_CS20HD] = 0x00000070;
936 s->regs[GT_CS3BOOTLD] = 0x000000f8;
937 s->regs[GT_CS3BOOTHD] = 0x0000007f;
fde7d5bd 938
fde7d5bd
TS		 939 s->regs[GT_PCI0IOLD] = 0x00000080;
940 s->regs[GT_PCI0IOHD] = 0x0000000f;
941 s->regs[GT_PCI0M0LD] = 0x00000090;
942 s->regs[GT_PCI0M0HD] = 0x0000001f;
30b6f3a8 943 s->regs[GT_ISD] = 0x000000a0;
fde7d5bd
TS		 944 s->regs[GT_PCI0M1LD] = 0x00000790;
945 s->regs[GT_PCI0M1HD] = 0x0000001f;
946 s->regs[GT_PCI1IOLD] = 0x00000100;
947 s->regs[GT_PCI1IOHD] = 0x0000000f;
948 s->regs[GT_PCI1M0LD] = 0x00000110;
949 s->regs[GT_PCI1M0HD] = 0x0000001f;
950 s->regs[GT_PCI1M1LD] = 0x00000120;
951 s->regs[GT_PCI1M1HD] = 0x0000002f;
30b6f3a8
TS		 952
953 s->regs[GT_SCS10AR] = 0x00000000;
954 s->regs[GT_SCS32AR] = 0x00000008;
955 s->regs[GT_CS20R] = 0x000000e0;
956 s->regs[GT_CS3BOOTR] = 0x000000f8;
957
fde7d5bd
TS		 958 s->regs[GT_PCI0IOREMAP] = 0x00000080;
959 s->regs[GT_PCI0M0REMAP] = 0x00000090;
960 s->regs[GT_PCI0M1REMAP] = 0x00000790;
961 s->regs[GT_PCI1IOREMAP] = 0x00000100;
962 s->regs[GT_PCI1M0REMAP] = 0x00000110;
963 s->regs[GT_PCI1M1REMAP] = 0x00000120;
964
965 /* CPU Error Report */
966 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
967 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
968 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
969 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
970 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
971
30b6f3a8
TS		 972 /* CPU Sync Barrier */
973 s->regs[GT_PCI0SYNC] = 0x00000000;
974 s->regs[GT_PCI1SYNC] = 0x00000000;
975
976 /* SDRAM and Device Address Decode */
977 s->regs[GT_SCS0LD] = 0x00000000;
978 s->regs[GT_SCS0HD] = 0x00000007;
979 s->regs[GT_SCS1LD] = 0x00000008;
980 s->regs[GT_SCS1HD] = 0x0000000f;
981 s->regs[GT_SCS2LD] = 0x00000010;
982 s->regs[GT_SCS2HD] = 0x00000017;
983 s->regs[GT_SCS3LD] = 0x00000018;
984 s->regs[GT_SCS3HD] = 0x0000001f;
985 s->regs[GT_CS0LD] = 0x000000c0;
986 s->regs[GT_CS0HD] = 0x000000c7;
987 s->regs[GT_CS1LD] = 0x000000c8;
988 s->regs[GT_CS1HD] = 0x000000cf;
989 s->regs[GT_CS2LD] = 0x000000d0;
990 s->regs[GT_CS2HD] = 0x000000df;
991 s->regs[GT_CS3LD] = 0x000000f0;
992 s->regs[GT_CS3HD] = 0x000000fb;
993 s->regs[GT_BOOTLD] = 0x000000fc;
994 s->regs[GT_BOOTHD] = 0x000000ff;
995 s->regs[GT_ADERR] = 0xffffffff;
996
997 /* SDRAM Configuration */
998 s->regs[GT_SDRAM_CFG] = 0x00000200;
999 s->regs[GT_SDRAM_OPMODE] = 0x00000000;
1000 s->regs[GT_SDRAM_BM] = 0x00000007;
1001 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1002
1003 /* SDRAM Parameters */
1004 s->regs[GT_SDRAM_B0] = 0x00000005;
1005 s->regs[GT_SDRAM_B1] = 0x00000005;
1006 s->regs[GT_SDRAM_B2] = 0x00000005;
1007 s->regs[GT_SDRAM_B3] = 0x00000005;
1008
fde7d5bd
TS		 1009 /* ECC */
1010 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1011 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1012 s->regs[GT_ECC_MEM] = 0x00000000;
1013 s->regs[GT_ECC_CALC] = 0x00000000;
1014 s->regs[GT_ECC_ERRADDR] = 0x00000000;
1015
30b6f3a8
TS		 1016 /* Device Parameters */
1017 s->regs[GT_DEV_B0] = 0x386fffff;
1018 s->regs[GT_DEV_B1] = 0x386fffff;
1019 s->regs[GT_DEV_B2] = 0x386fffff;
1020 s->regs[GT_DEV_B3] = 0x386fffff;
1021 s->regs[GT_DEV_BOOT] = 0x146fffff;
0da75eb1 1022
30b6f3a8
TS		 1023 /* DMA registers are all zeroed at reset */
1024
1025 /* Timer/Counter */
1026 s->regs[GT_TC0] = 0xffffffff;
1027 s->regs[GT_TC1] = 0x00ffffff;
1028 s->regs[GT_TC2] = 0x00ffffff;
1029 s->regs[GT_TC3] = 0x00ffffff;
1030 s->regs[GT_TC_CONTROL] = 0x00000000;
1031
1032 /* PCI Internal */
fde7d5bd
TS		 1033#ifdef TARGET_WORDS_BIGENDIAN
1034 s->regs[GT_PCI0_CMD] = 0x00000000;
fde7d5bd
TS		 1035#else
1036 s->regs[GT_PCI0_CMD] = 0x00010001;
fde7d5bd 1037#endif
30b6f3a8
TS		 1038 s->regs[GT_PCI0_TOR] = 0x0000070f;
1039 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1040 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1041 s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1042 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
fde7d5bd 1043 s->regs[GT_PCI1_IACK] = 0x00000000;
30b6f3a8
TS		 1044 s->regs[GT_PCI0_IACK] = 0x00000000;
1045 s->regs[GT_PCI0_BARE] = 0x0000000f;
1046 s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1047 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1048 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1049 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1050 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1051 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1052 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1053 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1054#ifdef TARGET_WORDS_BIGENDIAN
1055 s->regs[GT_PCI1_CMD] = 0x00000000;
1056#else
1057 s->regs[GT_PCI1_CMD] = 0x00010001;
1058#endif
1059 s->regs[GT_PCI1_TOR] = 0x0000070f;
1060 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1061 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1062 s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1063 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1064 s->regs[GT_PCI1_BARE] = 0x0000000f;
1065 s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1066 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1067 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1068 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1069 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1070 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1071 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1072 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1073 s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1074 s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1075 s->regs[GT_PCI0_CFGADDR] = 0x00000000;
1076 s->regs[GT_PCI0_CFGDATA] = 0x00000000;
1077
1078 /* Interrupt registers are all zeroed at reset */
fde7d5bd 1079
a0a8793e 1080 gt64120_isd_mapping(s);
9414cc6f 1081 gt64120_pci_mapping(s);
fde7d5bd
TS		 1082}
1083
bc687ec9
TS		 1084static uint32_t gt64120_read_config(PCIDevice *d, uint32_t address, int len)
1085{
1086 uint32_t val = pci_default_read_config(d, address, len);
1087#ifdef TARGET_WORDS_BIGENDIAN
1088 val = bswap32(val);
1089#endif
1090 return val;
1091}
1092
1093static void gt64120_write_config(PCIDevice *d, uint32_t address, uint32_t val,
1094 int len)
1095{
1096#ifdef TARGET_WORDS_BIGENDIAN
1097 val = bswap32(val);
1098#endif
1099 pci_default_write_config(d, address, val, len);
1100}
1101
1823082c
TS		 1102static void gt64120_save(QEMUFile* f, void *opaque)
1103{
1104 PCIDevice *d = opaque;
1105 pci_device_save(d, f);
1106}
1107
1108static int gt64120_load(QEMUFile* f, void *opaque, int version_id)
1109{
1110 PCIDevice *d = opaque;
1111 int ret;
1112
1113 if (version_id != 1)
1114 return -EINVAL;
1115 ret = pci_device_load(d, f);
1116 if (ret < 0)
1117 return ret;
1118 return 0;
1119}
1120
d537cf6c 1121PCIBus *pci_gt64120_init(qemu_irq *pic)
fde7d5bd
TS		 1122{
1123 GT64120State *s;
1124 PCIDevice *d;
fde7d5bd
TS		 1125
1126 s = qemu_mallocz(sizeof(GT64120State));
1127 s->pci = qemu_mallocz(sizeof(GT64120PCIState));
9414cc6f 1128
fde7d5bd
TS		 1129 s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq,
1130 pic, 144, 4);
a0a8793e 1131 s->ISD_handle = cpu_register_io_memory(0, gt64120_read, gt64120_write, s);
fde7d5bd 1132 d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
bc687ec9 1133 0, gt64120_read_config, gt64120_write_config);
fde7d5bd 1134
0f78cf0c
TS		 1135 /* FIXME: Malta specific hw assumptions ahead */
1136
a0a8793e 1137 d->config[0x00] = 0xab; /* vendor_id */
fde7d5bd 1138 d->config[0x01] = 0x11;
a0a8793e 1139 d->config[0x02] = 0x20; /* device_id */
bc687ec9 1140 d->config[0x03] = 0x46;
0f78cf0c
TS		 1141
1142 d->config[0x04] = 0x00;
fde7d5bd
TS		 1143 d->config[0x05] = 0x00;
1144 d->config[0x06] = 0x80;
0f78cf0c
TS		 1145 d->config[0x07] = 0x02;
1146
fde7d5bd
TS		 1147 d->config[0x08] = 0x10;
1148 d->config[0x09] = 0x00;
0f78cf0c
TS		 1149 d->config[0x0A] = 0x00;
1150 d->config[0x0B] = 0x06;
1151
1152 d->config[0x10] = 0x08;
1153 d->config[0x14] = 0x08;
1154 d->config[0x17] = 0x01;
fde7d5bd
TS		 1155 d->config[0x1B] = 0x1c;
1156 d->config[0x1F] = 0x1f;
1157 d->config[0x23] = 0x14;
0f78cf0c 1158 d->config[0x24] = 0x01;
fde7d5bd
TS		 1159 d->config[0x27] = 0x14;
1160 d->config[0x3D] = 0x01;
1161
a0a8793e
TS		 1162 gt64120_reset(s);
1163
1823082c
TS		 1164 register_savevm("GT64120 PCI Bus", 0, 1, gt64120_save, gt64120_load, d);
1165
fde7d5bd
TS		 1166 return s->pci->bus;
1167}
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