[qemu.git] / hw / arm / versatilepb.c

/*
 * ARM Versatile Platform/Application Baseboard System emulation.
 *
 * Copyright (c) 2005-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "hw/sysbus.h"
#include "hw/arm/arm.h"
#include "hw/devices.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
#include "hw/pci/pci.h"
#include "hw/i2c/i2c.h"
#include "hw/boards.h"
#include "sysemu/blockdev.h"
#include "exec/address-spaces.h"
#include "hw/block/flash.h"

#define VERSATILE_FLASH_ADDR 0x34000000
#define VERSATILE_FLASH_SIZE (64 * 1024 * 1024)
#define VERSATILE_FLASH_SECT_SIZE (256 * 1024)

/* Primary interrupt controller.  */

typedef struct vpb_sic_state
{
  SysBusDevice busdev;
  MemoryRegion iomem;
  uint32_t level;
  uint32_t mask;
  uint32_t pic_enable;
  qemu_irq parent[32];
  int irq;
} vpb_sic_state;

static const VMStateDescription vmstate_vpb_sic = {
    .name = "versatilepb_sic",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(level, vpb_sic_state),
        VMSTATE_UINT32(mask, vpb_sic_state),
        VMSTATE_UINT32(pic_enable, vpb_sic_state),
        VMSTATE_END_OF_LIST()
    }
};

static void vpb_sic_update(vpb_sic_state *s)
{
    uint32_t flags;

    flags = s->level & s->mask;
    qemu_set_irq(s->parent[s->irq], flags != 0);
}

static void vpb_sic_update_pic(vpb_sic_state *s)
{
    int i;
    uint32_t mask;

    for (i = 21; i <= 30; i++) {
        mask = 1u << i;
        if (!(s->pic_enable & mask))
            continue;
        qemu_set_irq(s->parent[i], (s->level & mask) != 0);
    }
}

static void vpb_sic_set_irq(void *opaque, int irq, int level)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;
    if (level)
        s->level |= 1u << irq;
    else
        s->level &= ~(1u << irq);
    if (s->pic_enable & (1u << irq))
        qemu_set_irq(s->parent[irq], level);
    vpb_sic_update(s);
}

static uint64_t vpb_sic_read(void *opaque, hwaddr offset,
                             unsigned size)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;

    switch (offset >> 2) {
    case 0: /* STATUS */
        return s->level & s->mask;
    case 1: /* RAWSTAT */
        return s->level;
    case 2: /* ENABLE */
        return s->mask;
    case 4: /* SOFTINT */
        return s->level & 1;
    case 8: /* PICENABLE */
        return s->pic_enable;
    default:
        printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
        return 0;
    }
}

static void vpb_sic_write(void *opaque, hwaddr offset,
                          uint64_t value, unsigned size)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;

    switch (offset >> 2) {
    case 2: /* ENSET */
        s->mask |= value;
        break;
    case 3: /* ENCLR */
        s->mask &= ~value;
        break;
    case 4: /* SOFTINTSET */
        if (value)
            s->mask |= 1;
        break;
    case 5: /* SOFTINTCLR */
        if (value)
            s->mask &= ~1u;
        break;
    case 8: /* PICENSET */
        s->pic_enable |= (value & 0x7fe00000);
        vpb_sic_update_pic(s);
        break;
    case 9: /* PICENCLR */
        s->pic_enable &= ~value;
        vpb_sic_update_pic(s);
        break;
    default:
        printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
        return;
    }
    vpb_sic_update(s);
}

static const MemoryRegionOps vpb_sic_ops = {
    .read = vpb_sic_read,
    .write = vpb_sic_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int vpb_sic_init(SysBusDevice *dev)
{
    vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
    int i;

    qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
    for (i = 0; i < 32; i++) {
        sysbus_init_irq(dev, &s->parent[i]);
    }
    s->irq = 31;
    memory_region_init_io(&s->iomem, &vpb_sic_ops, s, "vpb-sic", 0x1000);
    sysbus_init_mmio(dev, &s->iomem);
    return 0;
}

/* Board init.  */

/* The AB and PB boards both use the same core, just with different
   peripherals and expansion busses.  For now we emulate a subset of the
   PB peripherals and just change the board ID.  */

static struct arm_boot_info versatile_binfo;

static void versatile_init(QEMUMachineInitArgs *args, int board_id)
{
    ARMCPU *cpu;
    MemoryRegion *sysmem = get_system_memory();
    MemoryRegion *ram = g_new(MemoryRegion, 1);
    qemu_irq *cpu_pic;
    qemu_irq pic[32];
    qemu_irq sic[32];
    DeviceState *dev, *sysctl;
    SysBusDevice *busdev;
    DeviceState *pl041;
    PCIBus *pci_bus;
    NICInfo *nd;
    i2c_bus *i2c;
    int n;
    int done_smc = 0;
    DriveInfo *dinfo;

    if (!args->cpu_model) {
        args->cpu_model = "arm926";
    }
    cpu = cpu_arm_init(args->cpu_model);
    if (!cpu) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }
    memory_region_init_ram(ram, "versatile.ram", args->ram_size);
    vmstate_register_ram_global(ram);
    /* ??? RAM should repeat to fill physical memory space.  */
    /* SDRAM at address zero.  */
    memory_region_add_subregion(sysmem, 0, ram);

    sysctl = qdev_create(NULL, "realview_sysctl");
    qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
    qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
    qdev_init_nofail(sysctl);
    sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);

    cpu_pic = arm_pic_init_cpu(cpu);
    dev = sysbus_create_varargs("pl190", 0x10140000,
                                cpu_pic[ARM_PIC_CPU_IRQ],
                                cpu_pic[ARM_PIC_CPU_FIQ], NULL);
    for (n = 0; n < 32; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }
    dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
    for (n = 0; n < 32; n++) {
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]);
        sic[n] = qdev_get_gpio_in(dev, n);
    }

    sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
    sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);

    dev = qdev_create(NULL, "versatile_pci");
    busdev = SYS_BUS_DEVICE(dev);
    qdev_init_nofail(dev);
    sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */
    sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */
    sysbus_connect_irq(busdev, 0, sic[27]);
    sysbus_connect_irq(busdev, 1, sic[28]);
    sysbus_connect_irq(busdev, 2, sic[29]);
    sysbus_connect_irq(busdev, 3, sic[30]);
    pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");

    /* The Versatile PCI bridge does not provide access to PCI IO space,
       so many of the qemu PCI devices are not useable.  */
    for(n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];

        if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) {
            smc91c111_init(nd, 0x10010000, sic[25]);
            done_smc = 1;
        } else {
            pci_nic_init_nofail(nd, "rtl8139", NULL);
        }
    }
    if (usb_enabled(false)) {
        pci_create_simple(pci_bus, -1, "pci-ohci");
    }
    n = drive_get_max_bus(IF_SCSI);
    while (n >= 0) {
        pci_create_simple(pci_bus, -1, "lsi53c895a");
        n--;
    }

    sysbus_create_simple("pl011", 0x101f1000, pic[12]);
    sysbus_create_simple("pl011", 0x101f2000, pic[13]);
    sysbus_create_simple("pl011", 0x101f3000, pic[14]);
    sysbus_create_simple("pl011", 0x10009000, sic[6]);

    sysbus_create_simple("pl080", 0x10130000, pic[17]);
    sysbus_create_simple("sp804", 0x101e2000, pic[4]);
    sysbus_create_simple("sp804", 0x101e3000, pic[5]);

    sysbus_create_simple("pl061", 0x101e4000, pic[6]);
    sysbus_create_simple("pl061", 0x101e5000, pic[7]);
    sysbus_create_simple("pl061", 0x101e6000, pic[8]);
    sysbus_create_simple("pl061", 0x101e7000, pic[9]);

    /* The versatile/PB actually has a modified Color LCD controller
       that includes hardware cursor support from the PL111.  */
    dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
    /* Wire up the mux control signals from the SYS_CLCD register */
    qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));

    sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
    sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);

    /* Add PL031 Real Time Clock. */
    sysbus_create_simple("pl031", 0x101e8000, pic[10]);

    dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
    i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
    i2c_create_slave(i2c, "ds1338", 0x68);

    /* Add PL041 AACI Interface to the LM4549 codec */
    pl041 = qdev_create(NULL, "pl041");
    qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
    qdev_init_nofail(pl041);
    sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
    sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]);

    /* Memory map for Versatile/PB:  */
    /* 0x10000000 System registers.  */
    /* 0x10001000 PCI controller config registers.  */
    /* 0x10002000 Serial bus interface.  */
    /*  0x10003000 Secondary interrupt controller.  */
    /* 0x10004000 AACI (audio).  */
    /*  0x10005000 MMCI0.  */
    /*  0x10006000 KMI0 (keyboard).  */
    /*  0x10007000 KMI1 (mouse).  */
    /* 0x10008000 Character LCD Interface.  */
    /*  0x10009000 UART3.  */
    /* 0x1000a000 Smart card 1.  */
    /*  0x1000b000 MMCI1.  */
    /*  0x10010000 Ethernet.  */
    /* 0x10020000 USB.  */
    /* 0x10100000 SSMC.  */
    /* 0x10110000 MPMC.  */
    /*  0x10120000 CLCD Controller.  */
    /*  0x10130000 DMA Controller.  */
    /*  0x10140000 Vectored interrupt controller.  */
    /* 0x101d0000 AHB Monitor Interface.  */
    /* 0x101e0000 System Controller.  */
    /* 0x101e1000 Watchdog Interface.  */
    /* 0x101e2000 Timer 0/1.  */
    /* 0x101e3000 Timer 2/3.  */
    /* 0x101e4000 GPIO port 0.  */
    /* 0x101e5000 GPIO port 1.  */
    /* 0x101e6000 GPIO port 2.  */
    /* 0x101e7000 GPIO port 3.  */
    /* 0x101e8000 RTC.  */
    /* 0x101f0000 Smart card 0.  */
    /*  0x101f1000 UART0.  */
    /*  0x101f2000 UART1.  */
    /*  0x101f3000 UART2.  */
    /* 0x101f4000 SSPI.  */
    /* 0x34000000 NOR Flash */

    dinfo = drive_get(IF_PFLASH, 0, 0);
    if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, NULL, "versatile.flash",
                          VERSATILE_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
                          VERSATILE_FLASH_SECT_SIZE,
                          VERSATILE_FLASH_SIZE / VERSATILE_FLASH_SECT_SIZE,
                          4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
        fprintf(stderr, "qemu: Error registering flash memory.\n");
    }

    versatile_binfo.ram_size = args->ram_size;
    versatile_binfo.kernel_filename = args->kernel_filename;
    versatile_binfo.kernel_cmdline = args->kernel_cmdline;
    versatile_binfo.initrd_filename = args->initrd_filename;
    versatile_binfo.board_id = board_id;
    arm_load_kernel(cpu, &versatile_binfo);
}

static void vpb_init(QEMUMachineInitArgs *args)
{
    versatile_init(args, 0x183);
}

static void vab_init(QEMUMachineInitArgs *args)
{
    versatile_init(args, 0x25e);
}

static QEMUMachine versatilepb_machine = {
    .name = "versatilepb",
    .desc = "ARM Versatile/PB (ARM926EJ-S)",
    .init = vpb_init,
    .block_default_type = IF_SCSI,
    DEFAULT_MACHINE_OPTIONS,
};

static QEMUMachine versatileab_machine = {
    .name = "versatileab",
    .desc = "ARM Versatile/AB (ARM926EJ-S)",
    .init = vab_init,
    .block_default_type = IF_SCSI,
    DEFAULT_MACHINE_OPTIONS,
};

static void versatile_machine_init(void)
{
    qemu_register_machine(&versatilepb_machine);
    qemu_register_machine(&versatileab_machine);
}

machine_init(versatile_machine_init);

static void vpb_sic_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = vpb_sic_init;
    dc->no_user = 1;
    dc->vmsd = &vmstate_vpb_sic;
}

static const TypeInfo vpb_sic_info = {
    .name          = "versatilepb_sic",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(vpb_sic_state),
    .class_init    = vpb_sic_class_init,
};

static void versatilepb_register_types(void)
{
    type_register_static(&vpb_sic_info);
}

type_init(versatilepb_register_types)
Commit	Line	Data
5fafdf24	1	/*
16406950	2	* ARM Versatile Platform/Application Baseboard System emulation.
cdbdb648	3	*
a1bb27b1	4	* Copyright (c) 2005-2007 CodeSourcery.
cdbdb648 PB	5	* Written by Paul Brook
cdbdb648 PB	6	*
8e31bf38	7	* This code is licensed under the GPL.
cdbdb648 PB	8	*/
cdbdb648 PB	9
83c9f4ca	10	#include "hw/sysbus.h"
bd2be150 PM	11	#include "hw/arm/arm.h"
bd2be150 PM	12	#include "hw/devices.h"
1422e32d	13	#include "net/net.h"
9c17d615	14	#include "sysemu/sysemu.h"
83c9f4ca	15	#include "hw/pci/pci.h"
0d09e41a	16	#include "hw/i2c/i2c.h"
83c9f4ca	17	#include "hw/boards.h"
9c17d615	18	#include "sysemu/blockdev.h"
022c62cb	19	#include "exec/address-spaces.h"
0d09e41a	20	#include "hw/block/flash.h"
964c695a EB	21
	22	#define VERSATILE_FLASH_ADDR 0x34000000
	23	#define VERSATILE_FLASH_SIZE (64 * 1024 * 1024)
	24	#define VERSATILE_FLASH_SECT_SIZE (256 * 1024)
cdbdb648	25
cdbdb648 PB	26	/* Primary interrupt controller. */
	27
	28	typedef struct vpb_sic_state
	29	{
3950f18b	30	SysBusDevice busdev;
62ceeb2c	31	MemoryRegion iomem;
cdbdb648 PB	32	uint32_t level;
	33	uint32_t mask;
	34	uint32_t pic_enable;
97aff481	35	qemu_irq parent[32];
cdbdb648 PB	36	int irq;
	37	} vpb_sic_state;
	38
a796d0ac PM	39	static const VMStateDescription vmstate_vpb_sic = {
	40	.name = "versatilepb_sic",
	41	.version_id = 1,
	42	.minimum_version_id = 1,
	43	.fields = (VMStateField[]) {
	44	VMSTATE_UINT32(level, vpb_sic_state),
	45	VMSTATE_UINT32(mask, vpb_sic_state),
	46	VMSTATE_UINT32(pic_enable, vpb_sic_state),
	47	VMSTATE_END_OF_LIST()
	48	}
	49	};
	50
cdbdb648 PB	51	static void vpb_sic_update(vpb_sic_state *s)
	52	{
	53	uint32_t flags;
	54
	55	flags = s->level & s->mask;
d537cf6c	56	qemu_set_irq(s->parent[s->irq], flags != 0);
cdbdb648 PB	57	}
	58
	59	static void vpb_sic_update_pic(vpb_sic_state *s)
	60	{
	61	int i;
	62	uint32_t mask;
	63
	64	for (i = 21; i <= 30; i++) {
	65	mask = 1u << i;
	66	if (!(s->pic_enable & mask))
	67	continue;
d537cf6c	68	qemu_set_irq(s->parent[i], (s->level & mask) != 0);
cdbdb648 PB	69	}
	70	}
	71
	72	static void vpb_sic_set_irq(void *opaque, int irq, int level)
	73	{
	74	vpb_sic_state s = (vpb_sic_state )opaque;
	75	if (level)
	76	s->level \|= 1u << irq;
	77	else
	78	s->level &= ~(1u << irq);
	79	if (s->pic_enable & (1u << irq))
d537cf6c	80	qemu_set_irq(s->parent[irq], level);
cdbdb648 PB	81	vpb_sic_update(s);
	82	}
	83
a8170e5e	84	static uint64_t vpb_sic_read(void *opaque, hwaddr offset,
62ceeb2c	85	unsigned size)
cdbdb648 PB	86	{
	87	vpb_sic_state s = (vpb_sic_state )opaque;
	88
cdbdb648 PB	89	switch (offset >> 2) {
	90	case 0: /* STATUS */
	91	return s->level & s->mask;
	92	case 1: /* RAWSTAT */
	93	return s->level;
	94	case 2: /* ENABLE */
	95	return s->mask;
	96	case 4: /* SOFTINT */
	97	return s->level & 1;
	98	case 8: /* PICENABLE */
	99	return s->pic_enable;
	100	default:
e69954b9	101	printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
cdbdb648 PB	102	return 0;
	103	}
	104	}
	105
a8170e5e	106	static void vpb_sic_write(void *opaque, hwaddr offset,
62ceeb2c	107	uint64_t value, unsigned size)
cdbdb648 PB	108	{
cdbdb648 PB	109	vpb_sic_state s = (vpb_sic_state )opaque;
cdbdb648 PB	110
	111	switch (offset >> 2) {
	112	case 2: /* ENSET */
	113	s->mask \|= value;
	114	break;
	115	case 3: /* ENCLR */
	116	s->mask &= ~value;
	117	break;
	118	case 4: /* SOFTINTSET */
	119	if (value)
	120	s->mask \|= 1;
	121	break;
	122	case 5: /* SOFTINTCLR */
	123	if (value)
	124	s->mask &= ~1u;
	125	break;
	126	case 8: /* PICENSET */
	127	s->pic_enable \|= (value & 0x7fe00000);
	128	vpb_sic_update_pic(s);
	129	break;
	130	case 9: /* PICENCLR */
	131	s->pic_enable &= ~value;
	132	vpb_sic_update_pic(s);
	133	break;
	134	default:
e69954b9	135	printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
cdbdb648 PB	136	return;
	137	}
	138	vpb_sic_update(s);
	139	}
	140
62ceeb2c AK	141	static const MemoryRegionOps vpb_sic_ops = {
	142	.read = vpb_sic_read,
	143	.write = vpb_sic_write,
	144	.endianness = DEVICE_NATIVE_ENDIAN,
cdbdb648 PB	145	};
cdbdb648 PB	146
81a322d4	147	static int vpb_sic_init(SysBusDevice *dev)
cdbdb648	148	{
3950f18b	149	vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
97aff481	150	int i;
cdbdb648	151
067a3ddc	152	qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
97aff481	153	for (i = 0; i < 32; i++) {
3950f18b	154	sysbus_init_irq(dev, &s->parent[i]);
97aff481	155	}
3950f18b	156	s->irq = 31;
62ceeb2c	157	memory_region_init_io(&s->iomem, &vpb_sic_ops, s, "vpb-sic", 0x1000);
750ecd44	158	sysbus_init_mmio(dev, &s->iomem);
81a322d4	159	return 0;
cdbdb648 PB	160	}
	161
	162	/* Board init. */
	163
16406950	164	/* The AB and PB boards both use the same core, just with different
370de023	165	peripherals and expansion busses. For now we emulate a subset of the
16406950	166	PB peripherals and just change the board ID. */
cdbdb648	167
f93eb9ff AZ	168	static struct arm_boot_info versatile_binfo;
f93eb9ff AZ	169
1b523b5b	170	static void versatile_init(QEMUMachineInitArgs *args, int board_id)
cdbdb648	171	{
20e93374	172	ARMCPU *cpu;
62ceeb2c AK	173	MemoryRegion *sysmem = get_system_memory();
62ceeb2c AK	174	MemoryRegion *ram = g_new(MemoryRegion, 1);
97aff481 PB	175	qemu_irq *cpu_pic;
97aff481 PB	176	qemu_irq pic[32];
3950f18b	177	qemu_irq sic[32];
242ea2c6	178	DeviceState dev, sysctl;
7d6e771f	179	SysBusDevice *busdev;
d028d02d	180	DeviceState *pl041;
502a5395 PB	181	PCIBus *pci_bus;
502a5395 PB	182	NICInfo *nd;
b1f05696	183	i2c_bus *i2c;
502a5395 PB	184	int n;
502a5395 PB	185	int done_smc = 0;
964c695a	186	DriveInfo *dinfo;
cdbdb648	187
1b523b5b PM	188	if (!args->cpu_model) {
1b523b5b PM	189	args->cpu_model = "arm926";
20e93374	190	}
1b523b5b	191	cpu = cpu_arm_init(args->cpu_model);
20e93374	192	if (!cpu) {
aaed909a FB	193	fprintf(stderr, "Unable to find CPU definition\n");
	194	exit(1);
	195	}
1b523b5b	196	memory_region_init_ram(ram, "versatile.ram", args->ram_size);
c5705a77	197	vmstate_register_ram_global(ram);
1235fc06	198	/* ??? RAM should repeat to fill physical memory space. */
cdbdb648	199	/* SDRAM at address zero. */
62ceeb2c	200	memory_region_add_subregion(sysmem, 0, ram);
cdbdb648	201
242ea2c6 PM	202	sysctl = qdev_create(NULL, "realview_sysctl");
242ea2c6 PM	203	qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
242ea2c6	204	qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
7a65c8cc	205	qdev_init_nofail(sysctl);
1356b98d	206	sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
242ea2c6	207
4bd74661	208	cpu_pic = arm_pic_init_cpu(cpu);
97aff481	209	dev = sysbus_create_varargs("pl190", 0x10140000,
02cd521f SW	210	cpu_pic[ARM_PIC_CPU_IRQ],
02cd521f SW	211	cpu_pic[ARM_PIC_CPU_FIQ], NULL);
97aff481	212	for (n = 0; n < 32; n++) {
067a3ddc	213	pic[n] = qdev_get_gpio_in(dev, n);
97aff481	214	}
3950f18b PB	215	dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
3950f18b PB	216	for (n = 0; n < 32; n++) {
1356b98d	217	sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]);
067a3ddc	218	sic[n] = qdev_get_gpio_in(dev, n);
3950f18b	219	}
86394e96 PB	220
	221	sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
	222	sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
cdbdb648	223
7d6e771f	224	dev = qdev_create(NULL, "versatile_pci");
1356b98d	225	busdev = SYS_BUS_DEVICE(dev);
7d6e771f PM	226	qdev_init_nofail(dev);
	227	sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */
	228	sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */
	229	sysbus_connect_irq(busdev, 0, sic[27]);
	230	sysbus_connect_irq(busdev, 1, sic[28]);
	231	sysbus_connect_irq(busdev, 2, sic[29]);
	232	sysbus_connect_irq(busdev, 3, sic[30]);
02e2da45	233	pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
0027b06d	234
502a5395 PB	235	/* The Versatile PCI bridge does not provide access to PCI IO space,
	236	so many of the qemu PCI devices are not useable. */
	237	for(n = 0; n < nb_nics; n++) {
	238	nd = &nd_table[n];
0ae18cee	239
e6b3c8ca	240	if (!done_smc && (!nd->model \|\| strcmp(nd->model, "smc91c111") == 0)) {
d537cf6c	241	smc91c111_init(nd, 0x10010000, sic[25]);
0ae18cee	242	done_smc = 1;
cdbdb648	243	} else {
07caea31	244	pci_nic_init_nofail(nd, "rtl8139", NULL);
cdbdb648 PB	245	}
cdbdb648 PB	246	}
094b287f	247	if (usb_enabled(false)) {
afb9a60e	248	pci_create_simple(pci_bus, -1, "pci-ohci");
0d92ed30	249	}
9be5dafe PB	250	n = drive_get_max_bus(IF_SCSI);
	251	while (n >= 0) {
	252	pci_create_simple(pci_bus, -1, "lsi53c895a");
	253	n--;
7d8406be	254	}
cdbdb648	255
a7d518a6 PB	256	sysbus_create_simple("pl011", 0x101f1000, pic[12]);
	257	sysbus_create_simple("pl011", 0x101f2000, pic[13]);
	258	sysbus_create_simple("pl011", 0x101f3000, pic[14]);
	259	sysbus_create_simple("pl011", 0x10009000, sic[6]);
cdbdb648	260
b4496b13	261	sysbus_create_simple("pl080", 0x10130000, pic[17]);
6a824ec3 PB	262	sysbus_create_simple("sp804", 0x101e2000, pic[4]);
6a824ec3 PB	263	sysbus_create_simple("sp804", 0x101e3000, pic[5]);
cdbdb648	264
853e65e0 JCPV	265	sysbus_create_simple("pl061", 0x101e4000, pic[6]);
	266	sysbus_create_simple("pl061", 0x101e5000, pic[7]);
	267	sysbus_create_simple("pl061", 0x101e6000, pic[8]);
	268	sysbus_create_simple("pl061", 0x101e7000, pic[9]);
	269
cdbdb648 PB	270	/* The versatile/PB actually has a modified Color LCD controller
cdbdb648 PB	271	that includes hardware cursor support from the PL111. */
242ea2c6 PM	272	dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
	273	/* Wire up the mux control signals from the SYS_CLCD register */
	274	qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));
cdbdb648	275
aa9311d8 PB	276	sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
aa9311d8 PB	277	sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
a1bb27b1	278
7e1543c2	279	/* Add PL031 Real Time Clock. */
a63bdb31	280	sysbus_create_simple("pl031", 0x101e8000, pic[10]);
7e1543c2	281
b1f05696 OA	282	dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
	283	i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
	284	i2c_create_slave(i2c, "ds1338", 0x68);
	285
d028d02d MS	286	/* Add PL041 AACI Interface to the LM4549 codec */
	287	pl041 = qdev_create(NULL, "pl041");
	288	qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
	289	qdev_init_nofail(pl041);
1356b98d AF	290	sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
1356b98d AF	291	sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]);
d028d02d	292
16406950	293	/* Memory map for Versatile/PB: */
cdbdb648 PB	294	/* 0x10000000 System registers. */
	295	/* 0x10001000 PCI controller config registers. */
	296	/* 0x10002000 Serial bus interface. */
	297	/* 0x10003000 Secondary interrupt controller. */
	298	/* 0x10004000 AACI (audio). */
a1bb27b1	299	/* 0x10005000 MMCI0. */
cdbdb648 PB	300	/* 0x10006000 KMI0 (keyboard). */
	301	/* 0x10007000 KMI1 (mouse). */
	302	/* 0x10008000 Character LCD Interface. */
	303	/* 0x10009000 UART3. */
	304	/* 0x1000a000 Smart card 1. */
a1bb27b1	305	/* 0x1000b000 MMCI1. */
cdbdb648 PB	306	/* 0x10010000 Ethernet. */
	307	/* 0x10020000 USB. */
	308	/* 0x10100000 SSMC. */
	309	/* 0x10110000 MPMC. */
	310	/* 0x10120000 CLCD Controller. */
	311	/* 0x10130000 DMA Controller. */
	312	/* 0x10140000 Vectored interrupt controller. */
	313	/* 0x101d0000 AHB Monitor Interface. */
	314	/* 0x101e0000 System Controller. */
	315	/* 0x101e1000 Watchdog Interface. */
	316	/* 0x101e2000 Timer 0/1. */
	317	/* 0x101e3000 Timer 2/3. */
	318	/* 0x101e4000 GPIO port 0. */
	319	/* 0x101e5000 GPIO port 1. */
	320	/* 0x101e6000 GPIO port 2. */
	321	/* 0x101e7000 GPIO port 3. */
	322	/* 0x101e8000 RTC. */
	323	/* 0x101f0000 Smart card 0. */
	324	/* 0x101f1000 UART0. */
	325	/* 0x101f2000 UART1. */
	326	/* 0x101f3000 UART2. */
	327	/* 0x101f4000 SSPI. */
964c695a EB	328	/* 0x34000000 NOR Flash */
	329
	330	dinfo = drive_get(IF_PFLASH, 0, 0);
	331	if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, NULL, "versatile.flash",
	332	VERSATILE_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
	333	VERSATILE_FLASH_SECT_SIZE,
	334	VERSATILE_FLASH_SIZE / VERSATILE_FLASH_SECT_SIZE,
	335	4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
	336	fprintf(stderr, "qemu: Error registering flash memory.\n");
	337	}
cdbdb648	338
1b523b5b PM	339	versatile_binfo.ram_size = args->ram_size;
	340	versatile_binfo.kernel_filename = args->kernel_filename;
	341	versatile_binfo.kernel_cmdline = args->kernel_cmdline;
	342	versatile_binfo.initrd_filename = args->initrd_filename;
f93eb9ff	343	versatile_binfo.board_id = board_id;
3aaa8dfa	344	arm_load_kernel(cpu, &versatile_binfo);
16406950 PB	345	}
16406950 PB	346
5f072e1f	347	static void vpb_init(QEMUMachineInitArgs *args)
16406950	348	{
1b523b5b	349	versatile_init(args, 0x183);
16406950 PB	350	}
16406950 PB	351
5f072e1f	352	static void vab_init(QEMUMachineInitArgs *args)
16406950	353	{
1b523b5b	354	versatile_init(args, 0x25e);
cdbdb648 PB	355	}
cdbdb648 PB	356
f80f9ec9	357	static QEMUMachine versatilepb_machine = {
c9b1ae2c BS	358	.name = "versatilepb",
	359	.desc = "ARM Versatile/PB (ARM926EJ-S)",
	360	.init = vpb_init,
2d0d2837	361	.block_default_type = IF_SCSI,
e4ada29e	362	DEFAULT_MACHINE_OPTIONS,
cdbdb648	363	};
16406950	364
f80f9ec9	365	static QEMUMachine versatileab_machine = {
c9b1ae2c BS	366	.name = "versatileab",
	367	.desc = "ARM Versatile/AB (ARM926EJ-S)",
	368	.init = vab_init,
2d0d2837	369	.block_default_type = IF_SCSI,
e4ada29e	370	DEFAULT_MACHINE_OPTIONS,
16406950	371	};
3950f18b	372
f80f9ec9 AL	373	static void versatile_machine_init(void)
	374	{
	375	qemu_register_machine(&versatilepb_machine);
	376	qemu_register_machine(&versatileab_machine);
	377	}
	378
	379	machine_init(versatile_machine_init);
	380
999e12bb AL	381	static void vpb_sic_class_init(ObjectClass klass, void data)
999e12bb AL	382	{
39bffca2	383	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	384	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	385
	386	k->init = vpb_sic_init;
39bffca2 AL	387	dc->no_user = 1;
39bffca2 AL	388	dc->vmsd = &vmstate_vpb_sic;
999e12bb AL	389	}
999e12bb AL	390
8c43a6f0	391	static const TypeInfo vpb_sic_info = {
39bffca2 AL	392	.name = "versatilepb_sic",
	393	.parent = TYPE_SYS_BUS_DEVICE,
	394	.instance_size = sizeof(vpb_sic_state),
	395	.class_init = vpb_sic_class_init,
a796d0ac PM	396	};
a796d0ac PM	397
83f7d43a	398	static void versatilepb_register_types(void)
3950f18b	399	{
39bffca2	400	type_register_static(&vpb_sic_info);
3950f18b PB	401	}
3950f18b PB	402
83f7d43a	403	type_init(versatilepb_register_types)