[qemu.git] / hw / versatilepb.c

/* 
 * ARM Versatile Platform Baseboard System emulation.
 *
 * Copyright (c) 2005-2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */

#include "vl.h"
#include "arm_pic.h"

#define KERNEL_ARGS_ADDR 0x100
#define KERNEL_LOAD_ADDR 0x00010000
#define INITRD_LOAD_ADDR 0x00800000

/* Primary interrupt controller.  */

typedef struct vpb_sic_state
{
  arm_pic_handler handler;
  uint32_t base;
  uint32_t level;
  uint32_t mask;
  uint32_t pic_enable;
  void *parent;
  int irq;
} vpb_sic_state;

static void vpb_sic_update(vpb_sic_state *s)
{
    uint32_t flags;

    flags = s->level & s->mask;
    pic_set_irq_new(s->parent, s->irq, flags != 0);
}

static void vpb_sic_update_pic(vpb_sic_state *s)
{
    int i;
    uint32_t mask;

    for (i = 21; i <= 30; i++) {
        mask = 1u << i;
        if (!(s->pic_enable & mask))
            continue;
        pic_set_irq_new(s->parent, i, (s->level & mask) != 0);
    }
}

static void vpb_sic_set_irq(void *opaque, int irq, int level)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;
    if (level)
        s->level |= 1u << irq;
    else
        s->level &= ~(1u << irq);
    if (s->pic_enable & (1u << irq))
        pic_set_irq_new(s->parent, irq, level);
    vpb_sic_update(s);
}

static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;

    offset -= s->base;
    switch (offset >> 2) {
    case 0: /* STATUS */
        return s->level & s->mask;
    case 1: /* RAWSTAT */
        return s->level;
    case 2: /* ENABLE */
        return s->mask;
    case 4: /* SOFTINT */
        return s->level & 1;
    case 8: /* PICENABLE */
        return s->pic_enable;
    default:
        printf ("vpb_sic_read: Bad register offset 0x%x\n", offset);
        return 0;
    }
}

static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
                          uint32_t value)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;
    offset -= s->base;

    switch (offset >> 2) {
    case 2: /* ENSET */
        s->mask |= value;
        break;
    case 3: /* ENCLR */
        s->mask &= ~value;
        break;
    case 4: /* SOFTINTSET */
        if (value)
            s->mask |= 1;
        break;
    case 5: /* SOFTINTCLR */
        if (value)
            s->mask &= ~1u;
        break;
    case 8: /* PICENSET */
        s->pic_enable |= (value & 0x7fe00000);
        vpb_sic_update_pic(s);
        break;
    case 9: /* PICENCLR */
        s->pic_enable &= ~value;
        vpb_sic_update_pic(s);
        break;
    default:
        printf ("vpb_sic_write: Bad register offset 0x%x\n", offset);
        return;
    }
    vpb_sic_update(s);
}

static CPUReadMemoryFunc *vpb_sic_readfn[] = {
   vpb_sic_read,
   vpb_sic_read,
   vpb_sic_read
};

static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
   vpb_sic_write,
   vpb_sic_write,
   vpb_sic_write
};

static vpb_sic_state *vpb_sic_init(uint32_t base, void *parent, int irq)
{
    vpb_sic_state *s;
    int iomemtype;

    s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
    if (!s)
        return NULL;
    s->handler = vpb_sic_set_irq;
    s->base = base;
    s->parent = parent;
    s->irq = irq;
    iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
                                       vpb_sic_writefn, s);
    cpu_register_physical_memory(base, 0x00000fff, iomemtype);
    /* ??? Save/restore.  */
    return s;
}

/* Board init.  */

/* The worlds second smallest bootloader.  Set r0-r2, then jump to kernel.  */
static uint32_t bootloader[] = {
  0xe3a00000, /* mov     r0, #0 */
  0xe3a01083, /* mov     r1, #0x83 */
  0xe3811c01, /* orr     r1, r1, #0x100 */
  0xe59f2000, /* ldr     r2, [pc, #0] */
  0xe59ff000, /* ldr     pc, [pc, #0] */
  0, /* Address of kernel args.  Set by integratorcp_init.  */
  0  /* Kernel entry point.  Set by integratorcp_init.  */
};

static void set_kernel_args(uint32_t ram_size, int initrd_size,
                            const char *kernel_cmdline)
{
    uint32_t *p;

    p = (uint32_t *)(phys_ram_base + KERNEL_ARGS_ADDR);
    /* ATAG_CORE */
    stl_raw(p++, 5);
    stl_raw(p++, 0x54410001);
    stl_raw(p++, 1);
    stl_raw(p++, 0x1000);
    stl_raw(p++, 0);
    /* ATAG_MEM */
    stl_raw(p++, 4);
    stl_raw(p++, 0x54410002);
    stl_raw(p++, ram_size);
    stl_raw(p++, 0);
    if (initrd_size) {
        /* ATAG_INITRD2 */
        stl_raw(p++, 4);
        stl_raw(p++, 0x54420005);
        stl_raw(p++, INITRD_LOAD_ADDR);
        stl_raw(p++, initrd_size);
    }
    if (kernel_cmdline && *kernel_cmdline) {
        /* ATAG_CMDLINE */
        int cmdline_size;

        cmdline_size = strlen(kernel_cmdline);
        memcpy (p + 2, kernel_cmdline, cmdline_size + 1);
        cmdline_size = (cmdline_size >> 2) + 1;
        stl_raw(p++, cmdline_size + 2);
        stl_raw(p++, 0x54410009);
        p += cmdline_size;
    }
    /* ATAG_END */
    stl_raw(p++, 0);
    stl_raw(p++, 0);
}

static void vpb_init(int ram_size, int vga_ram_size, int boot_device,
                     DisplayState *ds, const char **fd_filename, int snapshot,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename)
{
    CPUState *env;
    int kernel_size;
    int initrd_size;
    int n;
    void *pic;
    void *sic;

    env = cpu_init();
    cpu_arm_set_model(env, ARM_CPUID_ARM926);
    /* ??? RAM shoud repeat to fill physical memory space.  */
    /* SDRAM at address zero.  */
    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);

    pic = arm_pic_init_cpu(env);
    pic = pl190_init(0x10140000, pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ);
    sic = vpb_sic_init(0x10003000, pic, 31);
    pl050_init(0x10006000, sic, 3, 0);
    pl050_init(0x10007000, sic, 4, 1);

    /* TODO: Init PCI NICs.  */
    if (nd_table[0].vlan) {
        if (nd_table[0].model == NULL
            || strcmp(nd_table[0].model, "smc91c111") == 0) {
            smc91c111_init(&nd_table[0], 0x10010000, sic, 25);
        } else {
            fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
            exit (1);
        }
    }

    pl011_init(0x101f1000, pic, 12, serial_hds[0]);
    pl011_init(0x101f2000, pic, 13, serial_hds[1]);
    pl011_init(0x101f3000, pic, 14, serial_hds[2]);
    pl011_init(0x10009000, sic, 6, serial_hds[3]);

    pl080_init(0x10130000, pic, 17);
    sp804_init(0x101e2000, pic, 4);
    sp804_init(0x101e3000, pic, 5);

    /* The versatile/PB actually has a modified Color LCD controller
       that includes hardware cursor support from the PL111.  */
    pl110_init(ds, 0x10120000, pic, 16, 1);

    /* 0x10000000 System registers.  */
    /* 0x10001000 PCI controller config registers.  */
    /* 0x10002000 Serial bus interface.  */
    /*  0x10003000 Secondary interrupt controller.  */
    /* 0x10004000 AACI (audio).  */
    /* 0x10005000 MMCI0.  */
    /*  0x10006000 KMI0 (keyboard).  */
    /*  0x10007000 KMI1 (mouse).  */
    /* 0x10008000 Character LCD Interface.  */
    /*  0x10009000 UART3.  */
    /* 0x1000a000 Smart card 1.  */
    /* 0x1000b000 MMCI1.  */
    /*  0x10010000 Ethernet.  */
    /* 0x10020000 USB.  */
    /* 0x10100000 SSMC.  */
    /* 0x10110000 MPMC.  */
    /*  0x10120000 CLCD Controller.  */
    /*  0x10130000 DMA Controller.  */
    /*  0x10140000 Vectored interrupt controller.  */
    /* 0x101d0000 AHB Monitor Interface.  */
    /* 0x101e0000 System Controller.  */
    /* 0x101e1000 Watchdog Interface.  */
    /* 0x101e2000 Timer 0/1.  */
    /* 0x101e3000 Timer 2/3.  */
    /* 0x101e4000 GPIO port 0.  */
    /* 0x101e5000 GPIO port 1.  */
    /* 0x101e6000 GPIO port 2.  */
    /* 0x101e7000 GPIO port 3.  */
    /* 0x101e8000 RTC.  */
    /* 0x101f0000 Smart card 0.  */
    /*  0x101f1000 UART0.  */
    /*  0x101f2000 UART1.  */
    /*  0x101f3000 UART2.  */
    /* 0x101f4000 SSPI.  */

    /* Load the kernel.  */
    if (!kernel_filename) {
        fprintf(stderr, "Kernel image must be specified\n");
        exit(1);
    }
    kernel_size = load_image(kernel_filename,
                             phys_ram_base + KERNEL_LOAD_ADDR);
    if (kernel_size < 0) {
        fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
        exit(1);
    }
    if (initrd_filename) {
        initrd_size = load_image(initrd_filename,
                                 phys_ram_base + INITRD_LOAD_ADDR);
        if (initrd_size < 0) {
            fprintf(stderr, "qemu: could not load initrd '%s'\n",
                    initrd_filename);
            exit(1);
        }
    } else {
        initrd_size = 0;
    }
    bootloader[5] = KERNEL_ARGS_ADDR;
    bootloader[6] = KERNEL_LOAD_ADDR;
    for (n = 0; n < sizeof(bootloader) / 4; n++)
        stl_raw(phys_ram_base + (n * 4), bootloader[n]);
    set_kernel_args(ram_size, initrd_size, kernel_cmdline);
}

QEMUMachine versatilepb_machine = {
    "versatilepb",
    "ARM Versatile/PB (ARM926EJ-S)",
    vpb_init,
};
Commit	Line	Data
cdbdb648 PB	1	/*
	2	* ARM Versatile Platform Baseboard System emulation.
	3	*
	4	* Copyright (c) 2005-2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
	10	#include "vl.h"
	11	#include "arm_pic.h"
	12
	13	#define KERNEL_ARGS_ADDR 0x100
	14	#define KERNEL_LOAD_ADDR 0x00010000
	15	#define INITRD_LOAD_ADDR 0x00800000
	16
	17	/* Primary interrupt controller. */
	18
	19	typedef struct vpb_sic_state
	20	{
	21	arm_pic_handler handler;
	22	uint32_t base;
	23	uint32_t level;
	24	uint32_t mask;
	25	uint32_t pic_enable;
	26	void *parent;
	27	int irq;
	28	} vpb_sic_state;
	29
	30	static void vpb_sic_update(vpb_sic_state *s)
	31	{
	32	uint32_t flags;
	33
	34	flags = s->level & s->mask;
	35	pic_set_irq_new(s->parent, s->irq, flags != 0);
	36	}
	37
	38	static void vpb_sic_update_pic(vpb_sic_state *s)
	39	{
	40	int i;
	41	uint32_t mask;
	42
	43	for (i = 21; i <= 30; i++) {
	44	mask = 1u << i;
	45	if (!(s->pic_enable & mask))
	46	continue;
	47	pic_set_irq_new(s->parent, i, (s->level & mask) != 0);
	48	}
	49	}
	50
	51	static void vpb_sic_set_irq(void *opaque, int irq, int level)
	52	{
	53	vpb_sic_state s = (vpb_sic_state )opaque;
	54	if (level)
	55	s->level \|= 1u << irq;
	56	else
	57	s->level &= ~(1u << irq);
	58	if (s->pic_enable & (1u << irq))
	59	pic_set_irq_new(s->parent, irq, level);
	60	vpb_sic_update(s);
	61	}
	62
	63	static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
	64	{
65	vpb_sic_state s = (vpb_sic_state )opaque;
66
67	offset -= s->base;
68	switch (offset >> 2) {
69	case 0: /* STATUS */
70	return s->level & s->mask;
71	case 1: /* RAWSTAT */
72	return s->level;
73	case 2: /* ENABLE */
74	return s->mask;
75	case 4: /* SOFTINT */
76	return s->level & 1;
77	case 8: /* PICENABLE */
78	return s->pic_enable;
79	default:
80	printf ("vpb_sic_read: Bad register offset 0x%x\n", offset);
81	return 0;
82	}
83	}
84
85	static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
86	uint32_t value)
87	{
88	vpb_sic_state s = (vpb_sic_state )opaque;
89	offset -= s->base;
90
91	switch (offset >> 2) {
92	case 2: /* ENSET */
93	s->mask \|= value;
94	break;
95	case 3: /* ENCLR */
96	s->mask &= ~value;
97	break;
98	case 4: /* SOFTINTSET */
99	if (value)
100	s->mask \|= 1;
101	break;
102	case 5: /* SOFTINTCLR */
103	if (value)
104	s->mask &= ~1u;
105	break;
106	case 8: /* PICENSET */
107	s->pic_enable \|= (value & 0x7fe00000);
108	vpb_sic_update_pic(s);
109	break;
110	case 9: /* PICENCLR */
111	s->pic_enable &= ~value;
112	vpb_sic_update_pic(s);
113	break;
114	default:
115	printf ("vpb_sic_write: Bad register offset 0x%x\n", offset);
116	return;
117	}
118	vpb_sic_update(s);
119	}
120
121	static CPUReadMemoryFunc *vpb_sic_readfn[] = {
122	vpb_sic_read,
123	vpb_sic_read,
124	vpb_sic_read
125	};
126
127	static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
128	vpb_sic_write,
129	vpb_sic_write,
130	vpb_sic_write
131	};
132
133	static vpb_sic_state vpb_sic_init(uint32_t base, void parent, int irq)
134	{
135	vpb_sic_state *s;
136	int iomemtype;
137
138	s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
139	if (!s)
140	return NULL;
141	s->handler = vpb_sic_set_irq;
142	s->base = base;
143	s->parent = parent;
144	s->irq = irq;
145	iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
146	vpb_sic_writefn, s);
147	cpu_register_physical_memory(base, 0x00000fff, iomemtype);
148	/* ??? Save/restore. */
149	return s;
150	}
151
152	/* Board init. */
153
154	/* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */
155	static uint32_t bootloader[] = {
156	0xe3a00000, /* mov r0, #0 */
157	0xe3a01083, /* mov r1, #0x83 */
158	0xe3811c01, /* orr r1, r1, #0x100 */
159	0xe59f2000, /* ldr r2, [pc, #0] */
160	0xe59ff000, /* ldr pc, [pc, #0] */
161	0, /* Address of kernel args. Set by integratorcp_init. */
162	0 /* Kernel entry point. Set by integratorcp_init. */
163	};
164
165	static void set_kernel_args(uint32_t ram_size, int initrd_size,
166	const char *kernel_cmdline)
167	{
168	uint32_t *p;
169
170	p = (uint32_t *)(phys_ram_base + KERNEL_ARGS_ADDR);
171	/* ATAG_CORE */
172	stl_raw(p++, 5);
173	stl_raw(p++, 0x54410001);
174	stl_raw(p++, 1);
175	stl_raw(p++, 0x1000);
176	stl_raw(p++, 0);
177	/* ATAG_MEM */
178	stl_raw(p++, 4);
179	stl_raw(p++, 0x54410002);
180	stl_raw(p++, ram_size);
181	stl_raw(p++, 0);
182	if (initrd_size) {
183	/* ATAG_INITRD2 */
184	stl_raw(p++, 4);
185	stl_raw(p++, 0x54420005);
186	stl_raw(p++, INITRD_LOAD_ADDR);
187	stl_raw(p++, initrd_size);
188	}
189	if (kernel_cmdline && *kernel_cmdline) {
190	/* ATAG_CMDLINE */
191	int cmdline_size;
192
193	cmdline_size = strlen(kernel_cmdline);
194	memcpy (p + 2, kernel_cmdline, cmdline_size + 1);
195	cmdline_size = (cmdline_size >> 2) + 1;
196	stl_raw(p++, cmdline_size + 2);
197	stl_raw(p++, 0x54410009);
198	p += cmdline_size;
199	}
200	/* ATAG_END */
201	stl_raw(p++, 0);
202	stl_raw(p++, 0);
203	}
204
205	static void vpb_init(int ram_size, int vga_ram_size, int boot_device,
206	DisplayState ds, const char *fd_filename, int snapshot,
207	const char kernel_filename, const char kernel_cmdline,
208	const char *initrd_filename)
209	{
210	CPUState *env;
211	int kernel_size;
212	int initrd_size;
213	int n;
214	void *pic;
215	void *sic;
216
217	env = cpu_init();
218	cpu_arm_set_model(env, ARM_CPUID_ARM926);
219	/* ??? RAM shoud repeat to fill physical memory space. */
220	/* SDRAM at address zero. */
221	cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
222
223	pic = arm_pic_init_cpu(env);
224	pic = pl190_init(0x10140000, pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ);
225	sic = vpb_sic_init(0x10003000, pic, 31);
226	pl050_init(0x10006000, sic, 3, 0);
227	pl050_init(0x10007000, sic, 4, 1);
228
229	/* TODO: Init PCI NICs. */
230	if (nd_table[0].vlan) {
231	if (nd_table[0].model == NULL
232	\|\| strcmp(nd_table[0].model, "smc91c111") == 0) {
233	smc91c111_init(&nd_table[0], 0x10010000, sic, 25);
234	} else {
235	fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
236	exit (1);
237	}
238	}
239
240	pl011_init(0x101f1000, pic, 12, serial_hds[0]);
241	pl011_init(0x101f2000, pic, 13, serial_hds[1]);
242	pl011_init(0x101f3000, pic, 14, serial_hds[2]);
243	pl011_init(0x10009000, sic, 6, serial_hds[3]);
244
245	pl080_init(0x10130000, pic, 17);
246	sp804_init(0x101e2000, pic, 4);
247	sp804_init(0x101e3000, pic, 5);
248
249	/* The versatile/PB actually has a modified Color LCD controller
250	that includes hardware cursor support from the PL111. */
251	pl110_init(ds, 0x10120000, pic, 16, 1);
252
253	/* 0x10000000 System registers. */
254	/* 0x10001000 PCI controller config registers. */
255	/* 0x10002000 Serial bus interface. */
256	/* 0x10003000 Secondary interrupt controller. */
257	/* 0x10004000 AACI (audio). */
258	/* 0x10005000 MMCI0. */
259	/* 0x10006000 KMI0 (keyboard). */
260	/* 0x10007000 KMI1 (mouse). */
261	/* 0x10008000 Character LCD Interface. */
262	/* 0x10009000 UART3. */
263	/* 0x1000a000 Smart card 1. */
264	/* 0x1000b000 MMCI1. */
265	/* 0x10010000 Ethernet. */
266	/* 0x10020000 USB. */
267	/* 0x10100000 SSMC. */
268	/* 0x10110000 MPMC. */
269	/* 0x10120000 CLCD Controller. */
270	/* 0x10130000 DMA Controller. */
271	/* 0x10140000 Vectored interrupt controller. */
272	/* 0x101d0000 AHB Monitor Interface. */
273	/* 0x101e0000 System Controller. */
274	/* 0x101e1000 Watchdog Interface. */
275	/* 0x101e2000 Timer 0/1. */
276	/* 0x101e3000 Timer 2/3. */
277	/* 0x101e4000 GPIO port 0. */
278	/* 0x101e5000 GPIO port 1. */
279	/* 0x101e6000 GPIO port 2. */
280	/* 0x101e7000 GPIO port 3. */
281	/* 0x101e8000 RTC. */
282	/* 0x101f0000 Smart card 0. */
283	/* 0x101f1000 UART0. */
284	/* 0x101f2000 UART1. */
285	/* 0x101f3000 UART2. */
286	/* 0x101f4000 SSPI. */
287
288	/* Load the kernel. */
289	if (!kernel_filename) {
290	fprintf(stderr, "Kernel image must be specified\n");
291	exit(1);
292	}
293	kernel_size = load_image(kernel_filename,
294	phys_ram_base + KERNEL_LOAD_ADDR);
295	if (kernel_size < 0) {
296	fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
297	exit(1);
298	}
299	if (initrd_filename) {
300	initrd_size = load_image(initrd_filename,
301	phys_ram_base + INITRD_LOAD_ADDR);
302	if (initrd_size < 0) {
303	fprintf(stderr, "qemu: could not load initrd '%s'\n",
304	initrd_filename);
305	exit(1);
306	}
307	} else {
308	initrd_size = 0;
309	}
310	bootloader[5] = KERNEL_ARGS_ADDR;
311	bootloader[6] = KERNEL_LOAD_ADDR;
312	for (n = 0; n < sizeof(bootloader) / 4; n++)
313	stl_raw(phys_ram_base + (n * 4), bootloader[n]);
314	set_kernel_args(ram_size, initrd_size, kernel_cmdline);
315	}
316
317	QEMUMachine versatilepb_machine = {
318	"versatilepb",
319	"ARM Versatile/PB (ARM926EJ-S)",
320	vpb_init,
321	};