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Fix windows build after virtio changes
[qemu.git] / hw / pxa2xx.c
CommitLineData
c1713132
AZ		 1/*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <[email protected]>
6 *
7 * This code is licenced under the GPL.
8 */
9
87ecb68b
PB		 10#include "hw.h"
11#include "pxa.h"
12#include "sysemu.h"
13#include "pc.h"
14#include "i2c.h"
15#include "qemu-timer.h"
16#include "qemu-char.h"
c1713132
AZ		 17
18static struct {
19 target_phys_addr_t io_base;
20 int irqn;
21} pxa255_serial[] = {
22 { 0x40100000, PXA2XX_PIC_FFUART },
23 { 0x40200000, PXA2XX_PIC_BTUART },
24 { 0x40700000, PXA2XX_PIC_STUART },
25 { 0x41600000, PXA25X_PIC_HWUART },
26 { 0, 0 }
27}, pxa270_serial[] = {
28 { 0x40100000, PXA2XX_PIC_FFUART },
29 { 0x40200000, PXA2XX_PIC_BTUART },
30 { 0x40700000, PXA2XX_PIC_STUART },
31 { 0, 0 }
32};
33
fa58c156 34typedef struct PXASSPDef {
c1713132
AZ		 35 target_phys_addr_t io_base;
36 int irqn;
fa58c156
FB		 37} PXASSPDef;
38
39#if 0
40static PXASSPDef pxa250_ssp[] = {
c1713132
AZ		 41 { 0x41000000, PXA2XX_PIC_SSP },
42 { 0, 0 }
fa58c156
FB		 43};
44#endif
45
46static PXASSPDef pxa255_ssp[] = {
c1713132
AZ		 47 { 0x41000000, PXA2XX_PIC_SSP },
48 { 0x41400000, PXA25X_PIC_NSSP },
49 { 0, 0 }
fa58c156
FB		 50};
51
52#if 0
53static PXASSPDef pxa26x_ssp[] = {
c1713132
AZ		 54 { 0x41000000, PXA2XX_PIC_SSP },
55 { 0x41400000, PXA25X_PIC_NSSP },
56 { 0x41500000, PXA26X_PIC_ASSP },
57 { 0, 0 }
fa58c156
FB		 58};
59#endif
60
61static PXASSPDef pxa27x_ssp[] = {
c1713132
AZ		 62 { 0x41000000, PXA2XX_PIC_SSP },
63 { 0x41700000, PXA27X_PIC_SSP2 },
64 { 0x41900000, PXA2XX_PIC_SSP3 },
65 { 0, 0 }
66};
67
68#define PMCR 0x00 /* Power Manager Control register */
69#define PSSR 0x04 /* Power Manager Sleep Status register */
70#define PSPR 0x08 /* Power Manager Scratch-Pad register */
71#define PWER 0x0c /* Power Manager Wake-Up Enable register */
72#define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
73#define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
74#define PEDR 0x18 /* Power Manager Edge-Detect Status register */
75#define PCFR 0x1c /* Power Manager General Configuration register */
76#define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
77#define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
78#define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
79#define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
80#define RCSR 0x30 /* Reset Controller Status register */
81#define PSLR 0x34 /* Power Manager Sleep Configuration register */
82#define PTSR 0x38 /* Power Manager Standby Configuration register */
83#define PVCR 0x40 /* Power Manager Voltage Change Control register */
84#define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
85#define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
86#define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
87#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
88#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
89
90static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
91{
92 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
c1713132
AZ		 93
94 switch (addr) {
95 case PMCR ... PCMD31:
96 if (addr & 3)
97 goto fail;
98
99 return s->pm_regs[addr >> 2];
100 default:
101 fail:
102 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
103 break;
104 }
105 return 0;
106}
107
108static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
109 uint32_t value)
110{
111 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
c1713132
AZ		 112
113 switch (addr) {
114 case PMCR:
115 s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
116 s->pm_regs[addr >> 2] |= value & 0x15;
117 break;
118
119 case PSSR: /* Read-clean registers */
120 case RCSR:
121 case PKSR:
122 s->pm_regs[addr >> 2] &= ~value;
123 break;
124
125 default: /* Read-write registers */
126 if (addr >= PMCR && addr <= PCMD31 && !(addr & 3)) {
127 s->pm_regs[addr >> 2] = value;
128 break;
129 }
130
131 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
132 break;
133 }
134}
135
136static CPUReadMemoryFunc *pxa2xx_pm_readfn[] = {
137 pxa2xx_pm_read,
138 pxa2xx_pm_read,
139 pxa2xx_pm_read,
140};
141
142static CPUWriteMemoryFunc *pxa2xx_pm_writefn[] = {
143 pxa2xx_pm_write,
144 pxa2xx_pm_write,
145 pxa2xx_pm_write,
146};
147
aa941b94
AZ		 148static void pxa2xx_pm_save(QEMUFile *f, void *opaque)
149{
150 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
151 int i;
152
153 for (i = 0; i < 0x40; i ++)
154 qemu_put_be32s(f, &s->pm_regs[i]);
155}
156
157static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
158{
159 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
160 int i;
161
162 for (i = 0; i < 0x40; i ++)
163 qemu_get_be32s(f, &s->pm_regs[i]);
164
165 return 0;
166}
167
c1713132
AZ		 168#define CCCR 0x00 /* Core Clock Configuration register */
169#define CKEN 0x04 /* Clock Enable register */
170#define OSCC 0x08 /* Oscillator Configuration register */
171#define CCSR 0x0c /* Core Clock Status register */
172
173static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
174{
175 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
c1713132
AZ		 176
177 switch (addr) {
178 case CCCR:
179 case CKEN:
180 case OSCC:
181 return s->cm_regs[addr >> 2];
182
183 case CCSR:
184 return s->cm_regs[CCCR >> 2] | (3 << 28);
185
186 default:
187 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
188 break;
189 }
190 return 0;
191}
192
193static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
194 uint32_t value)
195{
196 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
c1713132
AZ		 197
198 switch (addr) {
199 case CCCR:
200 case CKEN:
201 s->cm_regs[addr >> 2] = value;
202 break;
203
204 case OSCC:
565d2895 205 s->cm_regs[addr >> 2] &= ~0x6c;
c1713132 206 s->cm_regs[addr >> 2] |= value & 0x6e;
565d2895
AZ		 207 if ((value >> 1) & 1) /* OON */
208 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
c1713132
AZ		 209 break;
210
211 default:
212 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
213 break;
214 }
215}
216
217static CPUReadMemoryFunc *pxa2xx_cm_readfn[] = {
218 pxa2xx_cm_read,
219 pxa2xx_cm_read,
220 pxa2xx_cm_read,
221};
222
223static CPUWriteMemoryFunc *pxa2xx_cm_writefn[] = {
224 pxa2xx_cm_write,
225 pxa2xx_cm_write,
226 pxa2xx_cm_write,
227};
228
aa941b94
AZ		 229static void pxa2xx_cm_save(QEMUFile *f, void *opaque)
230{
231 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
232 int i;
233
234 for (i = 0; i < 4; i ++)
235 qemu_put_be32s(f, &s->cm_regs[i]);
236 qemu_put_be32s(f, &s->clkcfg);
237 qemu_put_be32s(f, &s->pmnc);
238}
239
240static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id)
241{
242 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
243 int i;
244
245 for (i = 0; i < 4; i ++)
246 qemu_get_be32s(f, &s->cm_regs[i]);
247 qemu_get_be32s(f, &s->clkcfg);
248 qemu_get_be32s(f, &s->pmnc);
249
250 return 0;
251}
252
c1713132
AZ		 253static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
254{
255 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
256
257 switch (reg) {
258 case 6: /* Clock Configuration register */
259 return s->clkcfg;
260
261 case 7: /* Power Mode register */
262 return 0;
263
264 default:
265 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
266 break;
267 }
268 return 0;
269}
270
271static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
272 uint32_t value)
273{
274 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
275 static const char *pwrmode[8] = {
276 "Normal", "Idle", "Deep-idle", "Standby",
277 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
278 };
279
280 switch (reg) {
281 case 6: /* Clock Configuration register */
282 s->clkcfg = value & 0xf;
283 if (value & 2)
284 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
285 break;
286
287 case 7: /* Power Mode register */
288 if (value & 8)
289 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
290 switch (value & 7) {
291 case 0:
292 /* Do nothing */
293 break;
294
295 case 1:
296 /* Idle */
82d17978 297 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
c1713132
AZ		 298 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
299 break;
300 }
301 /* Fall through. */
302
303 case 2:
304 /* Deep-Idle */
305 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
306 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
307 goto message;
308
309 case 3:
a90b7318
AZ		 310 s->env->uncached_cpsr =
311 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
c1713132
AZ		 312 s->env->cp15.c1_sys = 0;
313 s->env->cp15.c1_coproc = 0;
9ee6e8bb 314 s->env->cp15.c2_base0 = 0;
c1713132
AZ		 315 s->env->cp15.c3 = 0;
316 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
317 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
318
319 /*
320 * The scratch-pad register is almost universally used
321 * for storing the return address on suspend. For the
322 * lack of a resuming bootloader, perform a jump
323 * directly to that address.
324 */
325 memset(s->env->regs, 0, 4 * 15);
326 s->env->regs[15] = s->pm_regs[PSPR >> 2];
327
328#if 0
329 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
330 cpu_physical_memory_write(0, &buffer, 4);
331 buffer = s->pm_regs[PSPR >> 2];
332 cpu_physical_memory_write(8, &buffer, 4);
333#endif
334
335 /* Suspend */
336 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
337
338 goto message;
339
340 default:
341 message:
342 printf("%s: machine entered %s mode\n", __FUNCTION__,
343 pwrmode[value & 7]);
344 }
345 break;
346
347 default:
348 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
349 break;
350 }
351}
352
353/* Performace Monitoring Registers */
354#define CPPMNC 0 /* Performance Monitor Control register */
355#define CPCCNT 1 /* Clock Counter register */
356#define CPINTEN 4 /* Interrupt Enable register */
357#define CPFLAG 5 /* Overflow Flag register */
358#define CPEVTSEL 8 /* Event Selection register */
359
360#define CPPMN0 0 /* Performance Count register 0 */
361#define CPPMN1 1 /* Performance Count register 1 */
362#define CPPMN2 2 /* Performance Count register 2 */
363#define CPPMN3 3 /* Performance Count register 3 */
364
365static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
366{
367 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
368
369 switch (reg) {
370 case CPPMNC:
371 return s->pmnc;
372 case CPCCNT:
373 if (s->pmnc & 1)
374 return qemu_get_clock(vm_clock);
375 else
376 return 0;
377 case CPINTEN:
378 case CPFLAG:
379 case CPEVTSEL:
380 return 0;
381
382 default:
383 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
384 break;
385 }
386 return 0;
387}
388
389static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
390 uint32_t value)
391{
392 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
393
394 switch (reg) {
395 case CPPMNC:
396 s->pmnc = value;
397 break;
398
399 case CPCCNT:
400 case CPINTEN:
401 case CPFLAG:
402 case CPEVTSEL:
403 break;
404
405 default:
406 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
407 break;
408 }
409}
410
411static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
412{
413 switch (crm) {
414 case 0:
415 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
416 case 1:
417 return pxa2xx_perf_read(opaque, op2, reg, crm);
418 case 2:
419 switch (reg) {
420 case CPPMN0:
421 case CPPMN1:
422 case CPPMN2:
423 case CPPMN3:
424 return 0;
425 }
426 /* Fall through */
427 default:
428 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
429 break;
430 }
431 return 0;
432}
433
434static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
435 uint32_t value)
436{
437 switch (crm) {
438 case 0:
439 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
440 break;
441 case 1:
442 pxa2xx_perf_write(opaque, op2, reg, crm, value);
443 break;
444 case 2:
445 switch (reg) {
446 case CPPMN0:
447 case CPPMN1:
448 case CPPMN2:
449 case CPPMN3:
450 return;
451 }
452 /* Fall through */
453 default:
454 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
455 break;
456 }
457}
458
459#define MDCNFG 0x00 /* SDRAM Configuration register */
460#define MDREFR 0x04 /* SDRAM Refresh Control register */
461#define MSC0 0x08 /* Static Memory Control register 0 */
462#define MSC1 0x0c /* Static Memory Control register 1 */
463#define MSC2 0x10 /* Static Memory Control register 2 */
464#define MECR 0x14 /* Expansion Memory Bus Config register */
465#define SXCNFG 0x1c /* Synchronous Static Memory Config register */
466#define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
467#define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
468#define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
469#define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
470#define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
471#define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
472#define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
473#define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
474#define ARB_CNTL 0x48 /* Arbiter Control register */
475#define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
476#define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
477#define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
478#define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
479#define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
480#define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
481#define SA1110 0x64 /* SA-1110 Memory Compatibility register */
482
483static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
484{
485 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
c1713132
AZ		 486
487 switch (addr) {
488 case MDCNFG ... SA1110:
489 if ((addr & 3) == 0)
490 return s->mm_regs[addr >> 2];
491
492 default:
493 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
494 break;
495 }
496 return 0;
497}
498
499static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
500 uint32_t value)
501{
502 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
c1713132
AZ		 503
504 switch (addr) {
505 case MDCNFG ... SA1110:
506 if ((addr & 3) == 0) {
507 s->mm_regs[addr >> 2] = value;
508 break;
509 }
510
511 default:
512 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
513 break;
514 }
515}
516
517static CPUReadMemoryFunc *pxa2xx_mm_readfn[] = {
518 pxa2xx_mm_read,
519 pxa2xx_mm_read,
520 pxa2xx_mm_read,
521};
522
523static CPUWriteMemoryFunc *pxa2xx_mm_writefn[] = {
524 pxa2xx_mm_write,
525 pxa2xx_mm_write,
526 pxa2xx_mm_write,
527};
528
aa941b94
AZ		 529static void pxa2xx_mm_save(QEMUFile *f, void *opaque)
530{
531 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
532 int i;
533
534 for (i = 0; i < 0x1a; i ++)
535 qemu_put_be32s(f, &s->mm_regs[i]);
536}
537
538static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)
539{
540 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
541 int i;
542
543 for (i = 0; i < 0x1a; i ++)
544 qemu_get_be32s(f, &s->mm_regs[i]);
545
546 return 0;
547}
548
c1713132
AZ		 549/* Synchronous Serial Ports */
550struct pxa2xx_ssp_s {
c1713132
AZ		 551 qemu_irq irq;
552 int enable;
553
554 uint32_t sscr[2];
555 uint32_t sspsp;
556 uint32_t ssto;
557 uint32_t ssitr;
558 uint32_t sssr;
559 uint8_t sstsa;
560 uint8_t ssrsa;
561 uint8_t ssacd;
562
563 uint32_t rx_fifo[16];
564 int rx_level;
565 int rx_start;
566
567 uint32_t (*readfn)(void *opaque);
568 void (*writefn)(void *opaque, uint32_t value);
569 void *opaque;
570};
571
572#define SSCR0 0x00 /* SSP Control register 0 */
573#define SSCR1 0x04 /* SSP Control register 1 */
574#define SSSR 0x08 /* SSP Status register */
575#define SSITR 0x0c /* SSP Interrupt Test register */
576#define SSDR 0x10 /* SSP Data register */
577#define SSTO 0x28 /* SSP Time-Out register */
578#define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
579#define SSTSA 0x30 /* SSP TX Time Slot Active register */
580#define SSRSA 0x34 /* SSP RX Time Slot Active register */
581#define SSTSS 0x38 /* SSP Time Slot Status register */
582#define SSACD 0x3c /* SSP Audio Clock Divider register */
583
584/* Bitfields for above registers */
585#define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
586#define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
587#define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
588#define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
589#define SSCR0_SSE (1 << 7)
590#define SSCR0_RIM (1 << 22)
591#define SSCR0_TIM (1 << 23)
592#define SSCR0_MOD (1 << 31)
593#define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
594#define SSCR1_RIE (1 << 0)
595#define SSCR1_TIE (1 << 1)
596#define SSCR1_LBM (1 << 2)
597#define SSCR1_MWDS (1 << 5)
598#define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
599#define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
600#define SSCR1_EFWR (1 << 14)
601#define SSCR1_PINTE (1 << 18)
602#define SSCR1_TINTE (1 << 19)
603#define SSCR1_RSRE (1 << 20)
604#define SSCR1_TSRE (1 << 21)
605#define SSCR1_EBCEI (1 << 29)
606#define SSITR_INT (7 << 5)
607#define SSSR_TNF (1 << 2)
608#define SSSR_RNE (1 << 3)
609#define SSSR_TFS (1 << 5)
610#define SSSR_RFS (1 << 6)
611#define SSSR_ROR (1 << 7)
612#define SSSR_PINT (1 << 18)
613#define SSSR_TINT (1 << 19)
614#define SSSR_EOC (1 << 20)
615#define SSSR_TUR (1 << 21)
616#define SSSR_BCE (1 << 23)
617#define SSSR_RW 0x00bc0080
618
619static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s)
620{
621 int level = 0;
622
623 level |= s->ssitr & SSITR_INT;
624 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
625 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
626 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
627 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
628 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
629 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
630 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
631 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
632 qemu_set_irq(s->irq, !!level);
633}
634
635static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s)
636{
637 s->sssr &= ~(0xf << 12); /* Clear RFL */
638 s->sssr &= ~(0xf << 8); /* Clear TFL */
639 s->sssr &= ~SSSR_TNF;
640 if (s->enable) {
641 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
642 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
643 s->sssr |= SSSR_RFS;
644 else
645 s->sssr &= ~SSSR_RFS;
646 if (0 <= SSCR1_TFT(s->sscr[1]))
647 s->sssr |= SSSR_TFS;
648 else
649 s->sssr &= ~SSSR_TFS;
650 if (s->rx_level)
651 s->sssr |= SSSR_RNE;
652 else
653 s->sssr &= ~SSSR_RNE;
654 s->sssr |= SSSR_TNF;
655 }
656
657 pxa2xx_ssp_int_update(s);
658}
659
660static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
661{
662 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
663 uint32_t retval;
c1713132
AZ		 664
665 switch (addr) {
666 case SSCR0:
667 return s->sscr[0];
668 case SSCR1:
669 return s->sscr[1];
670 case SSPSP:
671 return s->sspsp;
672 case SSTO:
673 return s->ssto;
674 case SSITR:
675 return s->ssitr;
676 case SSSR:
677 return s->sssr | s->ssitr;
678 case SSDR:
679 if (!s->enable)
680 return 0xffffffff;
681 if (s->rx_level < 1) {
682 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
683 return 0xffffffff;
684 }
685 s->rx_level --;
686 retval = s->rx_fifo[s->rx_start ++];
687 s->rx_start &= 0xf;
688 pxa2xx_ssp_fifo_update(s);
689 return retval;
690 case SSTSA:
691 return s->sstsa;
692 case SSRSA:
693 return s->ssrsa;
694 case SSTSS:
695 return 0;
696 case SSACD:
697 return s->ssacd;
698 default:
699 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
700 break;
701 }
702 return 0;
703}
704
705static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
706 uint32_t value)
707{
708 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
c1713132
AZ		 709
710 switch (addr) {
711 case SSCR0:
712 s->sscr[0] = value & 0xc7ffffff;
713 s->enable = value & SSCR0_SSE;
714 if (value & SSCR0_MOD)
715 printf("%s: Attempt to use network mode\n", __FUNCTION__);
716 if (s->enable && SSCR0_DSS(value) < 4)
717 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
718 SSCR0_DSS(value));
719 if (!(value & SSCR0_SSE)) {
720 s->sssr = 0;
721 s->ssitr = 0;
722 s->rx_level = 0;
723 }
724 pxa2xx_ssp_fifo_update(s);
725 break;
726
727 case SSCR1:
728 s->sscr[1] = value;
729 if (value & (SSCR1_LBM | SSCR1_EFWR))
730 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
731 pxa2xx_ssp_fifo_update(s);
732 break;
733
734 case SSPSP:
735 s->sspsp = value;
736 break;
737
738 case SSTO:
739 s->ssto = value;
740 break;
741
742 case SSITR:
743 s->ssitr = value & SSITR_INT;
744 pxa2xx_ssp_int_update(s);
745 break;
746
747 case SSSR:
748 s->sssr &= ~(value & SSSR_RW);
749 pxa2xx_ssp_int_update(s);
750 break;
751
752 case SSDR:
753 if (SSCR0_UWIRE(s->sscr[0])) {
754 if (s->sscr[1] & SSCR1_MWDS)
755 value &= 0xffff;
756 else
757 value &= 0xff;
758 } else
759 /* Note how 32bits overflow does no harm here */
760 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
761
762 /* Data goes from here to the Tx FIFO and is shifted out from
763 * there directly to the slave, no need to buffer it.
764 */
765 if (s->enable) {
766 if (s->writefn)
767 s->writefn(s->opaque, value);
768
769 if (s->rx_level < 0x10) {
770 if (s->readfn)
771 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] =
772 s->readfn(s->opaque);
773 else
774 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = 0x0;
775 } else
776 s->sssr |= SSSR_ROR;
777 }
778 pxa2xx_ssp_fifo_update(s);
779 break;
780
781 case SSTSA:
782 s->sstsa = value;
783 break;
784
785 case SSRSA:
786 s->ssrsa = value;
787 break;
788
789 case SSACD:
790 s->ssacd = value;
791 break;
792
793 default:
794 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
795 break;
796 }
797}
798
799void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
800 uint32_t (*readfn)(void *opaque),
801 void (*writefn)(void *opaque, uint32_t value), void *opaque)
802{
803 if (!port) {
804 printf("%s: no such SSP\n", __FUNCTION__);
805 exit(-1);
806 }
807
808 port->opaque = opaque;
809 port->readfn = readfn;
810 port->writefn = writefn;
811}
812
813static CPUReadMemoryFunc *pxa2xx_ssp_readfn[] = {
814 pxa2xx_ssp_read,
815 pxa2xx_ssp_read,
816 pxa2xx_ssp_read,
817};
818
819static CPUWriteMemoryFunc *pxa2xx_ssp_writefn[] = {
820 pxa2xx_ssp_write,
821 pxa2xx_ssp_write,
822 pxa2xx_ssp_write,
823};
824
aa941b94
AZ		 825static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
826{
827 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
828 int i;
829
830 qemu_put_be32(f, s->enable);
831
832 qemu_put_be32s(f, &s->sscr[0]);
833 qemu_put_be32s(f, &s->sscr[1]);
834 qemu_put_be32s(f, &s->sspsp);
835 qemu_put_be32s(f, &s->ssto);
836 qemu_put_be32s(f, &s->ssitr);
837 qemu_put_be32s(f, &s->sssr);
838 qemu_put_8s(f, &s->sstsa);
839 qemu_put_8s(f, &s->ssrsa);
840 qemu_put_8s(f, &s->ssacd);
841
842 qemu_put_byte(f, s->rx_level);
843 for (i = 0; i < s->rx_level; i ++)
844 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
845}
846
847static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
848{
849 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
850 int i;
851
852 s->enable = qemu_get_be32(f);
853
854 qemu_get_be32s(f, &s->sscr[0]);
855 qemu_get_be32s(f, &s->sscr[1]);
856 qemu_get_be32s(f, &s->sspsp);
857 qemu_get_be32s(f, &s->ssto);
858 qemu_get_be32s(f, &s->ssitr);
859 qemu_get_be32s(f, &s->sssr);
860 qemu_get_8s(f, &s->sstsa);
861 qemu_get_8s(f, &s->ssrsa);
862 qemu_get_8s(f, &s->ssacd);
863
864 s->rx_level = qemu_get_byte(f);
865 s->rx_start = 0;
866 for (i = 0; i < s->rx_level; i ++)
867 s->rx_fifo[i] = qemu_get_byte(f);
868
869 return 0;
870}
871
c1713132
AZ		 872/* Real-Time Clock */
873#define RCNR 0x00 /* RTC Counter register */
874#define RTAR 0x04 /* RTC Alarm register */
875#define RTSR 0x08 /* RTC Status register */
876#define RTTR 0x0c /* RTC Timer Trim register */
877#define RDCR 0x10 /* RTC Day Counter register */
878#define RYCR 0x14 /* RTC Year Counter register */
879#define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
880#define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
881#define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
882#define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
883#define SWCR 0x28 /* RTC Stopwatch Counter register */
884#define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
885#define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
886#define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
887#define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
888
889static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s *s)
890{
891 qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
892}
893
894static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s)
895{
896 int64_t rt = qemu_get_clock(rt_clock);
897 s->last_rcnr += ((rt - s->last_hz) << 15) /
898 (1000 * ((s->rttr & 0xffff) + 1));
899 s->last_rdcr += ((rt - s->last_hz) << 15) /
900 (1000 * ((s->rttr & 0xffff) + 1));
901 s->last_hz = rt;
902}
903
904static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s)
905{
906 int64_t rt = qemu_get_clock(rt_clock);
907 if (s->rtsr & (1 << 12))
908 s->last_swcr += (rt - s->last_sw) / 10;
909 s->last_sw = rt;
910}
911
912static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s)
913{
914 int64_t rt = qemu_get_clock(rt_clock);
915 if (s->rtsr & (1 << 15))
916 s->last_swcr += rt - s->last_pi;
917 s->last_pi = rt;
918}
919
920static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s,
921 uint32_t rtsr)
922{
923 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
924 qemu_mod_timer(s->rtc_hz, s->last_hz +
925 (((s->rtar - s->last_rcnr) * 1000 *
926 ((s->rttr & 0xffff) + 1)) >> 15));
927 else
928 qemu_del_timer(s->rtc_hz);
929
930 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
931 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
932 (((s->rdar1 - s->last_rdcr) * 1000 *
933 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
934 else
935 qemu_del_timer(s->rtc_rdal1);
936
937 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
938 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
939 (((s->rdar2 - s->last_rdcr) * 1000 *
940 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
941 else
942 qemu_del_timer(s->rtc_rdal2);
943
944 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
945 qemu_mod_timer(s->rtc_swal1, s->last_sw +
946 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
947 else
948 qemu_del_timer(s->rtc_swal1);
949
950 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
951 qemu_mod_timer(s->rtc_swal2, s->last_sw +
952 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
953 else
954 qemu_del_timer(s->rtc_swal2);
955
956 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
957 qemu_mod_timer(s->rtc_pi, s->last_pi +
958 (s->piar & 0xffff) - s->last_rtcpicr);
959 else
960 qemu_del_timer(s->rtc_pi);
961}
962
963static inline void pxa2xx_rtc_hz_tick(void *opaque)
964{
965 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
966 s->rtsr |= (1 << 0);
967 pxa2xx_rtc_alarm_update(s, s->rtsr);
968 pxa2xx_rtc_int_update(s);
969}
970
971static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
972{
973 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
974 s->rtsr |= (1 << 4);
975 pxa2xx_rtc_alarm_update(s, s->rtsr);
976 pxa2xx_rtc_int_update(s);
977}
978
979static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
980{
981 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
982 s->rtsr |= (1 << 6);
983 pxa2xx_rtc_alarm_update(s, s->rtsr);
984 pxa2xx_rtc_int_update(s);
985}
986
987static inline void pxa2xx_rtc_swal1_tick(void *opaque)
988{
989 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
990 s->rtsr |= (1 << 8);
991 pxa2xx_rtc_alarm_update(s, s->rtsr);
992 pxa2xx_rtc_int_update(s);
993}
994
995static inline void pxa2xx_rtc_swal2_tick(void *opaque)
996{
997 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
998 s->rtsr |= (1 << 10);
999 pxa2xx_rtc_alarm_update(s, s->rtsr);
1000 pxa2xx_rtc_int_update(s);
1001}
1002
1003static inline void pxa2xx_rtc_pi_tick(void *opaque)
1004{
1005 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1006 s->rtsr |= (1 << 13);
1007 pxa2xx_rtc_piupdate(s);
1008 s->last_rtcpicr = 0;
1009 pxa2xx_rtc_alarm_update(s, s->rtsr);
1010 pxa2xx_rtc_int_update(s);
1011}
1012
1013static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
1014{
1015 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
c1713132
AZ		 1016
1017 switch (addr) {
1018 case RTTR:
1019 return s->rttr;
1020 case RTSR:
1021 return s->rtsr;
1022 case RTAR:
1023 return s->rtar;
1024 case RDAR1:
1025 return s->rdar1;
1026 case RDAR2:
1027 return s->rdar2;
1028 case RYAR1:
1029 return s->ryar1;
1030 case RYAR2:
1031 return s->ryar2;
1032 case SWAR1:
1033 return s->swar1;
1034 case SWAR2:
1035 return s->swar2;
1036 case PIAR:
1037 return s->piar;
1038 case RCNR:
1039 return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1040 (1000 * ((s->rttr & 0xffff) + 1));
1041 case RDCR:
1042 return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1043 (1000 * ((s->rttr & 0xffff) + 1));
1044 case RYCR:
1045 return s->last_rycr;
1046 case SWCR:
1047 if (s->rtsr & (1 << 12))
1048 return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10;
1049 else
1050 return s->last_swcr;
1051 default:
1052 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1053 break;
1054 }
1055 return 0;
1056}
1057
1058static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1059 uint32_t value)
1060{
1061 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
c1713132
AZ		 1062
1063 switch (addr) {
1064 case RTTR:
1065 if (!(s->rttr & (1 << 31))) {
1066 pxa2xx_rtc_hzupdate(s);
1067 s->rttr = value;
1068 pxa2xx_rtc_alarm_update(s, s->rtsr);
1069 }
1070 break;
1071
1072 case RTSR:
1073 if ((s->rtsr ^ value) & (1 << 15))
1074 pxa2xx_rtc_piupdate(s);
1075
1076 if ((s->rtsr ^ value) & (1 << 12))
1077 pxa2xx_rtc_swupdate(s);
1078
1079 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1080 pxa2xx_rtc_alarm_update(s, value);
1081
1082 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1083 pxa2xx_rtc_int_update(s);
1084 break;
1085
1086 case RTAR:
1087 s->rtar = value;
1088 pxa2xx_rtc_alarm_update(s, s->rtsr);
1089 break;
1090
1091 case RDAR1:
1092 s->rdar1 = value;
1093 pxa2xx_rtc_alarm_update(s, s->rtsr);
1094 break;
1095
1096 case RDAR2:
1097 s->rdar2 = value;
1098 pxa2xx_rtc_alarm_update(s, s->rtsr);
1099 break;
1100
1101 case RYAR1:
1102 s->ryar1 = value;
1103 pxa2xx_rtc_alarm_update(s, s->rtsr);
1104 break;
1105
1106 case RYAR2:
1107 s->ryar2 = value;
1108 pxa2xx_rtc_alarm_update(s, s->rtsr);
1109 break;
1110
1111 case SWAR1:
1112 pxa2xx_rtc_swupdate(s);
1113 s->swar1 = value;
1114 s->last_swcr = 0;
1115 pxa2xx_rtc_alarm_update(s, s->rtsr);
1116 break;
1117
1118 case SWAR2:
1119 s->swar2 = value;
1120 pxa2xx_rtc_alarm_update(s, s->rtsr);
1121 break;
1122
1123 case PIAR:
1124 s->piar = value;
1125 pxa2xx_rtc_alarm_update(s, s->rtsr);
1126 break;
1127
1128 case RCNR:
1129 pxa2xx_rtc_hzupdate(s);
1130 s->last_rcnr = value;
1131 pxa2xx_rtc_alarm_update(s, s->rtsr);
1132 break;
1133
1134 case RDCR:
1135 pxa2xx_rtc_hzupdate(s);
1136 s->last_rdcr = value;
1137 pxa2xx_rtc_alarm_update(s, s->rtsr);
1138 break;
1139
1140 case RYCR:
1141 s->last_rycr = value;
1142 break;
1143
1144 case SWCR:
1145 pxa2xx_rtc_swupdate(s);
1146 s->last_swcr = value;
1147 pxa2xx_rtc_alarm_update(s, s->rtsr);
1148 break;
1149
1150 case RTCPICR:
1151 pxa2xx_rtc_piupdate(s);
1152 s->last_rtcpicr = value & 0xffff;
1153 pxa2xx_rtc_alarm_update(s, s->rtsr);
1154 break;
1155
1156 default:
1157 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1158 }
1159}
1160
aa941b94
AZ		 1161static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
1162 pxa2xx_rtc_read,
1163 pxa2xx_rtc_read,
1164 pxa2xx_rtc_read,
1165};
1166
1167static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
1168 pxa2xx_rtc_write,
1169 pxa2xx_rtc_write,
1170 pxa2xx_rtc_write,
1171};
1172
1173static void pxa2xx_rtc_init(struct pxa2xx_state_s *s)
c1713132 1174{
f6503059 1175 struct tm tm;
c1713132
AZ		 1176 int wom;
1177
1178 s->rttr = 0x7fff;
1179 s->rtsr = 0;
1180
f6503059
AZ		 1181 qemu_get_timedate(&tm, 0);
1182 wom = ((tm.tm_mday - 1) / 7) + 1;
1183
1184 s->last_rcnr = (uint32_t) mktime(&tm);
1185 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1186 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1187 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1188 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1189 s->last_swcr = (tm.tm_hour << 19) |
1190 (tm.tm_min << 13) | (tm.tm_sec << 7);
c1713132
AZ		 1191 s->last_rtcpicr = 0;
1192 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock);
1193
1194 s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s);
1195 s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1196 s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1197 s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s);
1198 s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s);
1199 s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s);
1200}
1201
aa941b94
AZ		 1202static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
1203{
1204 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
c1713132 1205
aa941b94
AZ		 1206 pxa2xx_rtc_hzupdate(s);
1207 pxa2xx_rtc_piupdate(s);
1208 pxa2xx_rtc_swupdate(s);
1209
1210 qemu_put_be32s(f, &s->rttr);
1211 qemu_put_be32s(f, &s->rtsr);
1212 qemu_put_be32s(f, &s->rtar);
1213 qemu_put_be32s(f, &s->rdar1);
1214 qemu_put_be32s(f, &s->rdar2);
1215 qemu_put_be32s(f, &s->ryar1);
1216 qemu_put_be32s(f, &s->ryar2);
1217 qemu_put_be32s(f, &s->swar1);
1218 qemu_put_be32s(f, &s->swar2);
1219 qemu_put_be32s(f, &s->piar);
1220 qemu_put_be32s(f, &s->last_rcnr);
1221 qemu_put_be32s(f, &s->last_rdcr);
1222 qemu_put_be32s(f, &s->last_rycr);
1223 qemu_put_be32s(f, &s->last_swcr);
1224 qemu_put_be32s(f, &s->last_rtcpicr);
b6c4f71f
BS		 1225 qemu_put_sbe64s(f, &s->last_hz);
1226 qemu_put_sbe64s(f, &s->last_sw);
1227 qemu_put_sbe64s(f, &s->last_pi);
aa941b94
AZ		 1228}
1229
1230static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id)
1231{
1232 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1233
1234 qemu_get_be32s(f, &s->rttr);
1235 qemu_get_be32s(f, &s->rtsr);
1236 qemu_get_be32s(f, &s->rtar);
1237 qemu_get_be32s(f, &s->rdar1);
1238 qemu_get_be32s(f, &s->rdar2);
1239 qemu_get_be32s(f, &s->ryar1);
1240 qemu_get_be32s(f, &s->ryar2);
1241 qemu_get_be32s(f, &s->swar1);
1242 qemu_get_be32s(f, &s->swar2);
1243 qemu_get_be32s(f, &s->piar);
1244 qemu_get_be32s(f, &s->last_rcnr);
1245 qemu_get_be32s(f, &s->last_rdcr);
1246 qemu_get_be32s(f, &s->last_rycr);
1247 qemu_get_be32s(f, &s->last_swcr);
1248 qemu_get_be32s(f, &s->last_rtcpicr);
b6c4f71f
BS		 1249 qemu_get_sbe64s(f, &s->last_hz);
1250 qemu_get_sbe64s(f, &s->last_sw);
1251 qemu_get_sbe64s(f, &s->last_pi);
aa941b94
AZ		 1252
1253 pxa2xx_rtc_alarm_update(s, s->rtsr);
1254
1255 return 0;
1256}
c1713132 1257
3f582262
AZ		 1258/* I2C Interface */
1259struct pxa2xx_i2c_s {
1260 i2c_slave slave;
1261 i2c_bus *bus;
3f582262
AZ		 1262 qemu_irq irq;
1263
1264 uint16_t control;
1265 uint16_t status;
1266 uint8_t ibmr;
1267 uint8_t data;
1268};
1269
1270#define IBMR 0x80 /* I2C Bus Monitor register */
1271#define IDBR 0x88 /* I2C Data Buffer register */
1272#define ICR 0x90 /* I2C Control register */
1273#define ISR 0x98 /* I2C Status register */
1274#define ISAR 0xa0 /* I2C Slave Address register */
1275
1276static void pxa2xx_i2c_update(struct pxa2xx_i2c_s *s)
1277{
1278 uint16_t level = 0;
1279 level |= s->status & s->control & (1 << 10); /* BED */
1280 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1281 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1282 level |= s->status & (1 << 9); /* SAD */
1283 qemu_set_irq(s->irq, !!level);
1284}
1285
1286/* These are only stubs now. */
1287static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1288{
1289 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1290
1291 switch (event) {
1292 case I2C_START_SEND:
1293 s->status |= (1 << 9); /* set SAD */
1294 s->status &= ~(1 << 0); /* clear RWM */
1295 break;
1296 case I2C_START_RECV:
1297 s->status |= (1 << 9); /* set SAD */
1298 s->status |= 1 << 0; /* set RWM */
1299 break;
1300 case I2C_FINISH:
1301 s->status |= (1 << 4); /* set SSD */
1302 break;
1303 case I2C_NACK:
1304 s->status |= 1 << 1; /* set ACKNAK */
1305 break;
1306 }
1307 pxa2xx_i2c_update(s);
1308}
1309
1310static int pxa2xx_i2c_rx(i2c_slave *i2c)
1311{
1312 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1313 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1314 return 0;
1315
1316 if (s->status & (1 << 0)) { /* RWM */
1317 s->status |= 1 << 6; /* set ITE */
1318 }
1319 pxa2xx_i2c_update(s);
1320
1321 return s->data;
1322}
1323
1324static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1325{
1326 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1327 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1328 return 1;
1329
1330 if (!(s->status & (1 << 0))) { /* RWM */
1331 s->status |= 1 << 7; /* set IRF */
1332 s->data = data;
1333 }
1334 pxa2xx_i2c_update(s);
1335
1336 return 1;
1337}
1338
1339static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1340{
1341 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
3f582262 1342
8da3ff18 1343 addr &= 0xff;
3f582262
AZ		 1344 switch (addr) {
1345 case ICR:
1346 return s->control;
1347 case ISR:
1348 return s->status | (i2c_bus_busy(s->bus) << 2);
1349 case ISAR:
1350 return s->slave.address;
1351 case IDBR:
1352 return s->data;
1353 case IBMR:
1354 if (s->status & (1 << 2))
1355 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1356 else
1357 s->ibmr = 0;
1358 return s->ibmr;
1359 default:
1360 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1361 break;
1362 }
1363 return 0;
1364}
1365
1366static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1367 uint32_t value)
1368{
1369 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1370 int ack;
3f582262 1371
8da3ff18 1372 addr &= 0xff;
3f582262
AZ		 1373 switch (addr) {
1374 case ICR:
1375 s->control = value & 0xfff7;
1376 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1377 /* TODO: slave mode */
1378 if (value & (1 << 0)) { /* START condition */
1379 if (s->data & 1)
1380 s->status |= 1 << 0; /* set RWM */
1381 else
1382 s->status &= ~(1 << 0); /* clear RWM */
1383 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1384 } else {
1385 if (s->status & (1 << 0)) { /* RWM */
1386 s->data = i2c_recv(s->bus);
1387 if (value & (1 << 2)) /* ACKNAK */
1388 i2c_nack(s->bus);
1389 ack = 1;
1390 } else
1391 ack = !i2c_send(s->bus, s->data);
1392 }
1393
1394 if (value & (1 << 1)) /* STOP condition */
1395 i2c_end_transfer(s->bus);
1396
1397 if (ack) {
1398 if (value & (1 << 0)) /* START condition */
1399 s->status |= 1 << 6; /* set ITE */
1400 else
1401 if (s->status & (1 << 0)) /* RWM */
1402 s->status |= 1 << 7; /* set IRF */
1403 else
1404 s->status |= 1 << 6; /* set ITE */
1405 s->status &= ~(1 << 1); /* clear ACKNAK */
1406 } else {
1407 s->status |= 1 << 6; /* set ITE */
1408 s->status |= 1 << 10; /* set BED */
1409 s->status |= 1 << 1; /* set ACKNAK */
1410 }
1411 }
1412 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1413 if (value & (1 << 4)) /* MA */
1414 i2c_end_transfer(s->bus);
1415 pxa2xx_i2c_update(s);
1416 break;
1417
1418 case ISR:
1419 s->status &= ~(value & 0x07f0);
1420 pxa2xx_i2c_update(s);
1421 break;
1422
1423 case ISAR:
1424 i2c_set_slave_address(&s->slave, value & 0x7f);
1425 break;
1426
1427 case IDBR:
1428 s->data = value & 0xff;
1429 break;
1430
1431 default:
1432 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1433 }
1434}
1435
1436static CPUReadMemoryFunc *pxa2xx_i2c_readfn[] = {
1437 pxa2xx_i2c_read,
1438 pxa2xx_i2c_read,
1439 pxa2xx_i2c_read,
1440};
1441
1442static CPUWriteMemoryFunc *pxa2xx_i2c_writefn[] = {
1443 pxa2xx_i2c_write,
1444 pxa2xx_i2c_write,
1445 pxa2xx_i2c_write,
1446};
1447
aa941b94
AZ		 1448static void pxa2xx_i2c_save(QEMUFile *f, void *opaque)
1449{
1450 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1451
1452 qemu_put_be16s(f, &s->control);
1453 qemu_put_be16s(f, &s->status);
1454 qemu_put_8s(f, &s->ibmr);
1455 qemu_put_8s(f, &s->data);
1456
aa941b94
AZ		 1457 i2c_slave_save(f, &s->slave);
1458}
1459
1460static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
1461{
1462 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1463
c701b35b
PB		 1464 if (version_id != 1)
1465 return -EINVAL;
1466
aa941b94
AZ		 1467 qemu_get_be16s(f, &s->control);
1468 qemu_get_be16s(f, &s->status);
1469 qemu_get_8s(f, &s->ibmr);
1470 qemu_get_8s(f, &s->data);
1471
aa941b94
AZ		 1472 i2c_slave_load(f, &s->slave);
1473 return 0;
1474}
1475
3f582262 1476struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
2a163929 1477 qemu_irq irq, uint32_t page_size)
3f582262
AZ		 1478{
1479 int iomemtype;
c701b35b 1480 /* FIXME: Should the slave device really be on a separate bus? */
3f582262 1481 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *)
3f6c925f 1482 i2c_slave_init(i2c_init_bus(), 0, sizeof(struct pxa2xx_i2c_s));
3f582262 1483
3f582262
AZ		 1484 s->irq = irq;
1485 s->slave.event = pxa2xx_i2c_event;
1486 s->slave.recv = pxa2xx_i2c_rx;
1487 s->slave.send = pxa2xx_i2c_tx;
1488 s->bus = i2c_init_bus();
1489
2a163929
AZ		 1490 iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
1491 pxa2xx_i2c_writefn, s);
8da3ff18 1492 cpu_register_physical_memory(base & ~page_size, page_size + 1, iomemtype);
3f582262 1493
c701b35b 1494 register_savevm("pxa2xx_i2c", base, 1,
aa941b94
AZ		 1495 pxa2xx_i2c_save, pxa2xx_i2c_load, s);
1496
3f582262
AZ		 1497 return s;
1498}
1499
1500i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s)
1501{
1502 return s->bus;
1503}
1504
c1713132
AZ		 1505/* PXA Inter-IC Sound Controller */
1506static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s)
1507{
1508 i2s->rx_len = 0;
1509 i2s->tx_len = 0;
1510 i2s->fifo_len = 0;
1511 i2s->clk = 0x1a;
1512 i2s->control[0] = 0x00;
1513 i2s->control[1] = 0x00;
1514 i2s->status = 0x00;
1515 i2s->mask = 0x00;
1516}
1517
1518#define SACR_TFTH(val) ((val >> 8) & 0xf)
1519#define SACR_RFTH(val) ((val >> 12) & 0xf)
1520#define SACR_DREC(val) (val & (1 << 3))
1521#define SACR_DPRL(val) (val & (1 << 4))
1522
1523static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s)
1524{
1525 int rfs, tfs;
1526 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1527 !SACR_DREC(i2s->control[1]);
1528 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1529 i2s->enable && !SACR_DPRL(i2s->control[1]);
1530
1531 pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs);
1532 pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
1533
1534 i2s->status &= 0xe0;
59c0149b
AZ		 1535 if (i2s->fifo_len < 16 || !i2s->enable)
1536 i2s->status |= 1 << 0; /* TNF */
c1713132
AZ		 1537 if (i2s->rx_len)
1538 i2s->status |= 1 << 1; /* RNE */
1539 if (i2s->enable)
1540 i2s->status |= 1 << 2; /* BSY */
1541 if (tfs)
1542 i2s->status |= 1 << 3; /* TFS */
1543 if (rfs)
1544 i2s->status |= 1 << 4; /* RFS */
1545 if (!(i2s->tx_len && i2s->enable))
1546 i2s->status |= i2s->fifo_len << 8; /* TFL */
1547 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1548
1549 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1550}
1551
1552#define SACR0 0x00 /* Serial Audio Global Control register */
1553#define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1554#define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1555#define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1556#define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1557#define SADIV 0x60 /* Serial Audio Clock Divider register */
1558#define SADR 0x80 /* Serial Audio Data register */
1559
1560static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1561{
1562 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
c1713132
AZ		 1563
1564 switch (addr) {
1565 case SACR0:
1566 return s->control[0];
1567 case SACR1:
1568 return s->control[1];
1569 case SASR0:
1570 return s->status;
1571 case SAIMR:
1572 return s->mask;
1573 case SAICR:
1574 return 0;
1575 case SADIV:
1576 return s->clk;
1577 case SADR:
1578 if (s->rx_len > 0) {
1579 s->rx_len --;
1580 pxa2xx_i2s_update(s);
1581 return s->codec_in(s->opaque);
1582 }
1583 return 0;
1584 default:
1585 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1586 break;
1587 }
1588 return 0;
1589}
1590
1591static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1592 uint32_t value)
1593{
1594 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1595 uint32_t *sample;
c1713132
AZ		 1596
1597 switch (addr) {
1598 case SACR0:
1599 if (value & (1 << 3)) /* RST */
1600 pxa2xx_i2s_reset(s);
1601 s->control[0] = value & 0xff3d;
1602 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1603 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1604 s->codec_out(s->opaque, *sample);
1605 s->status &= ~(1 << 7); /* I2SOFF */
1606 }
1607 if (value & (1 << 4)) /* EFWR */
1608 printf("%s: Attempt to use special function\n", __FUNCTION__);
1609 s->enable = ((value ^ 4) & 5) == 5; /* ENB && !RST*/
1610 pxa2xx_i2s_update(s);
1611 break;
1612 case SACR1:
1613 s->control[1] = value & 0x0039;
1614 if (value & (1 << 5)) /* ENLBF */
1615 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1616 if (value & (1 << 4)) /* DPRL */
1617 s->fifo_len = 0;
1618 pxa2xx_i2s_update(s);
1619 break;
1620 case SAIMR:
1621 s->mask = value & 0x0078;
1622 pxa2xx_i2s_update(s);
1623 break;
1624 case SAICR:
1625 s->status &= ~(value & (3 << 5));
1626 pxa2xx_i2s_update(s);
1627 break;
1628 case SADIV:
1629 s->clk = value & 0x007f;
1630 break;
1631 case SADR:
1632 if (s->tx_len && s->enable) {
1633 s->tx_len --;
1634 pxa2xx_i2s_update(s);
1635 s->codec_out(s->opaque, value);
1636 } else if (s->fifo_len < 16) {
1637 s->fifo[s->fifo_len ++] = value;
1638 pxa2xx_i2s_update(s);
1639 }
1640 break;
1641 default:
1642 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1643 }
1644}
1645
1646static CPUReadMemoryFunc *pxa2xx_i2s_readfn[] = {
1647 pxa2xx_i2s_read,
1648 pxa2xx_i2s_read,
1649 pxa2xx_i2s_read,
1650};
1651
1652static CPUWriteMemoryFunc *pxa2xx_i2s_writefn[] = {
1653 pxa2xx_i2s_write,
1654 pxa2xx_i2s_write,
1655 pxa2xx_i2s_write,
1656};
1657
aa941b94
AZ		 1658static void pxa2xx_i2s_save(QEMUFile *f, void *opaque)
1659{
1660 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1661
1662 qemu_put_be32s(f, &s->control[0]);
1663 qemu_put_be32s(f, &s->control[1]);
1664 qemu_put_be32s(f, &s->status);
1665 qemu_put_be32s(f, &s->mask);
1666 qemu_put_be32s(f, &s->clk);
1667
1668 qemu_put_be32(f, s->enable);
1669 qemu_put_be32(f, s->rx_len);
1670 qemu_put_be32(f, s->tx_len);
1671 qemu_put_be32(f, s->fifo_len);
1672}
1673
1674static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id)
1675{
1676 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1677
1678 qemu_get_be32s(f, &s->control[0]);
1679 qemu_get_be32s(f, &s->control[1]);
1680 qemu_get_be32s(f, &s->status);
1681 qemu_get_be32s(f, &s->mask);
1682 qemu_get_be32s(f, &s->clk);
1683
1684 s->enable = qemu_get_be32(f);
1685 s->rx_len = qemu_get_be32(f);
1686 s->tx_len = qemu_get_be32(f);
1687 s->fifo_len = qemu_get_be32(f);
1688
1689 return 0;
1690}
1691
c1713132
AZ		 1692static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1693{
1694 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1695 uint32_t *sample;
1696
1697 /* Signal FIFO errors */
1698 if (s->enable && s->tx_len)
1699 s->status |= 1 << 5; /* TUR */
1700 if (s->enable && s->rx_len)
1701 s->status |= 1 << 6; /* ROR */
1702
1703 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1704 * handle the cases where it makes a difference. */
1705 s->tx_len = tx - s->fifo_len;
1706 s->rx_len = rx;
1707 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1708 if (s->enable)
1709 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1710 s->codec_out(s->opaque, *sample);
1711 pxa2xx_i2s_update(s);
1712}
1713
1714static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base,
1715 qemu_irq irq, struct pxa2xx_dma_state_s *dma)
1716{
1717 int iomemtype;
1718 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *)
1719 qemu_mallocz(sizeof(struct pxa2xx_i2s_s));
1720
c1713132
AZ		 1721 s->irq = irq;
1722 s->dma = dma;
1723 s->data_req = pxa2xx_i2s_data_req;
1724
1725 pxa2xx_i2s_reset(s);
1726
1727 iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
1728 pxa2xx_i2s_writefn, s);
8da3ff18 1729 cpu_register_physical_memory(base, 0x100000, iomemtype);
c1713132 1730
aa941b94
AZ		 1731 register_savevm("pxa2xx_i2s", base, 0,
1732 pxa2xx_i2s_save, pxa2xx_i2s_load, s);
1733
c1713132
AZ		 1734 return s;
1735}
1736
1737/* PXA Fast Infra-red Communications Port */
1738struct pxa2xx_fir_s {
c1713132
AZ		 1739 qemu_irq irq;
1740 struct pxa2xx_dma_state_s *dma;
1741 int enable;
1742 CharDriverState *chr;
1743
1744 uint8_t control[3];
1745 uint8_t status[2];
1746
1747 int rx_len;
1748 int rx_start;
1749 uint8_t rx_fifo[64];
1750};
1751
1752static void pxa2xx_fir_reset(struct pxa2xx_fir_s *s)
1753{
1754 s->control[0] = 0x00;
1755 s->control[1] = 0x00;
1756 s->control[2] = 0x00;
1757 s->status[0] = 0x00;
1758 s->status[1] = 0x00;
1759 s->enable = 0;
1760}
1761
1762static inline void pxa2xx_fir_update(struct pxa2xx_fir_s *s)
1763{
1764 static const int tresh[4] = { 8, 16, 32, 0 };
1765 int intr = 0;
1766 if ((s->control[0] & (1 << 4)) && /* RXE */
1767 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1768 s->status[0] |= 1 << 4; /* RFS */
1769 else
1770 s->status[0] &= ~(1 << 4); /* RFS */
1771 if (s->control[0] & (1 << 3)) /* TXE */
1772 s->status[0] |= 1 << 3; /* TFS */
1773 else
1774 s->status[0] &= ~(1 << 3); /* TFS */
1775 if (s->rx_len)
1776 s->status[1] |= 1 << 2; /* RNE */
1777 else
1778 s->status[1] &= ~(1 << 2); /* RNE */
1779 if (s->control[0] & (1 << 4)) /* RXE */
1780 s->status[1] |= 1 << 0; /* RSY */
1781 else
1782 s->status[1] &= ~(1 << 0); /* RSY */
1783
1784 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1785 (s->status[0] & (1 << 4)); /* RFS */
1786 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1787 (s->status[0] & (1 << 3)); /* TFS */
1788 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1789 (s->status[0] & (1 << 6)); /* EOC */
1790 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1791 (s->status[0] & (1 << 1)); /* TUR */
1792 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1793
1794 pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1);
1795 pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1);
1796
1797 qemu_set_irq(s->irq, intr && s->enable);
1798}
1799
1800#define ICCR0 0x00 /* FICP Control register 0 */
1801#define ICCR1 0x04 /* FICP Control register 1 */
1802#define ICCR2 0x08 /* FICP Control register 2 */
1803#define ICDR 0x0c /* FICP Data register */
1804#define ICSR0 0x14 /* FICP Status register 0 */
1805#define ICSR1 0x18 /* FICP Status register 1 */
1806#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1807
1808static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1809{
1810 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1811 uint8_t ret;
c1713132
AZ		 1812
1813 switch (addr) {
1814 case ICCR0:
1815 return s->control[0];
1816 case ICCR1:
1817 return s->control[1];
1818 case ICCR2:
1819 return s->control[2];
1820 case ICDR:
1821 s->status[0] &= ~0x01;
1822 s->status[1] &= ~0x72;
1823 if (s->rx_len) {
1824 s->rx_len --;
1825 ret = s->rx_fifo[s->rx_start ++];
1826 s->rx_start &= 63;
1827 pxa2xx_fir_update(s);
1828 return ret;
1829 }
1830 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1831 break;
1832 case ICSR0:
1833 return s->status[0];
1834 case ICSR1:
1835 return s->status[1] | (1 << 3); /* TNF */
1836 case ICFOR:
1837 return s->rx_len;
1838 default:
1839 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1840 break;
1841 }
1842 return 0;
1843}
1844
1845static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1846 uint32_t value)
1847{
1848 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1849 uint8_t ch;
c1713132
AZ		 1850
1851 switch (addr) {
1852 case ICCR0:
1853 s->control[0] = value;
1854 if (!(value & (1 << 4))) /* RXE */
1855 s->rx_len = s->rx_start = 0;
1856 if (!(value & (1 << 3))) /* TXE */
1857 /* Nop */;
1858 s->enable = value & 1; /* ITR */
1859 if (!s->enable)
1860 s->status[0] = 0;
1861 pxa2xx_fir_update(s);
1862 break;
1863 case ICCR1:
1864 s->control[1] = value;
1865 break;
1866 case ICCR2:
1867 s->control[2] = value & 0x3f;
1868 pxa2xx_fir_update(s);
1869 break;
1870 case ICDR:
1871 if (s->control[2] & (1 << 2)) /* TXP */
1872 ch = value;
1873 else
1874 ch = ~value;
1875 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1876 qemu_chr_write(s->chr, &ch, 1);
1877 break;
1878 case ICSR0:
1879 s->status[0] &= ~(value & 0x66);
1880 pxa2xx_fir_update(s);
1881 break;
1882 case ICFOR:
1883 break;
1884 default:
1885 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1886 }
1887}
1888
1889static CPUReadMemoryFunc *pxa2xx_fir_readfn[] = {
1890 pxa2xx_fir_read,
1891 pxa2xx_fir_read,
1892 pxa2xx_fir_read,
1893};
1894
1895static CPUWriteMemoryFunc *pxa2xx_fir_writefn[] = {
1896 pxa2xx_fir_write,
1897 pxa2xx_fir_write,
1898 pxa2xx_fir_write,
1899};
1900
1901static int pxa2xx_fir_is_empty(void *opaque)
1902{
1903 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1904 return (s->rx_len < 64);
1905}
1906
1907static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1908{
1909 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1910 if (!(s->control[0] & (1 << 4))) /* RXE */
1911 return;
1912
1913 while (size --) {
1914 s->status[1] |= 1 << 4; /* EOF */
1915 if (s->rx_len >= 64) {
1916 s->status[1] |= 1 << 6; /* ROR */
1917 break;
1918 }
1919
1920 if (s->control[2] & (1 << 3)) /* RXP */
1921 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1922 else
1923 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1924 }
1925
1926 pxa2xx_fir_update(s);
1927}
1928
1929static void pxa2xx_fir_event(void *opaque, int event)
1930{
1931}
1932
aa941b94
AZ		 1933static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1934{
1935 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1936 int i;
1937
1938 qemu_put_be32(f, s->enable);
1939
1940 qemu_put_8s(f, &s->control[0]);
1941 qemu_put_8s(f, &s->control[1]);
1942 qemu_put_8s(f, &s->control[2]);
1943 qemu_put_8s(f, &s->status[0]);
1944 qemu_put_8s(f, &s->status[1]);
1945
1946 qemu_put_byte(f, s->rx_len);
1947 for (i = 0; i < s->rx_len; i ++)
1948 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1949}
1950
1951static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1952{
1953 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1954 int i;
1955
1956 s->enable = qemu_get_be32(f);
1957
1958 qemu_get_8s(f, &s->control[0]);
1959 qemu_get_8s(f, &s->control[1]);
1960 qemu_get_8s(f, &s->control[2]);
1961 qemu_get_8s(f, &s->status[0]);
1962 qemu_get_8s(f, &s->status[1]);
1963
1964 s->rx_len = qemu_get_byte(f);
1965 s->rx_start = 0;
1966 for (i = 0; i < s->rx_len; i ++)
1967 s->rx_fifo[i] = qemu_get_byte(f);
1968
1969 return 0;
1970}
1971
c1713132
AZ		 1972static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base,
1973 qemu_irq irq, struct pxa2xx_dma_state_s *dma,
1974 CharDriverState *chr)
1975{
1976 int iomemtype;
1977 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *)
1978 qemu_mallocz(sizeof(struct pxa2xx_fir_s));
1979
c1713132
AZ		 1980 s->irq = irq;
1981 s->dma = dma;
1982 s->chr = chr;
1983
1984 pxa2xx_fir_reset(s);
1985
1986 iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
1987 pxa2xx_fir_writefn, s);
8da3ff18 1988 cpu_register_physical_memory(base, 0x1000, iomemtype);
c1713132
AZ		 1989
1990 if (chr)
1991 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
1992 pxa2xx_fir_rx, pxa2xx_fir_event, s);
1993
aa941b94
AZ		 1994 register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save, pxa2xx_fir_load, s);
1995
c1713132
AZ		 1996 return s;
1997}
1998
38641a52 1999static void pxa2xx_reset(void *opaque, int line, int level)
c1713132
AZ		 2000{
2001 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
38641a52 2002
c1713132
AZ		 2003 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2004 cpu_reset(s->env);
2005 /* TODO: reset peripherals */
2006 }
2007}
2008
2009/* Initialise a PXA270 integrated chip (ARM based core). */
d95b2f8d
AZ		 2010struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
2011 DisplayState *ds, const char *revision)
c1713132
AZ		 2012{
2013 struct pxa2xx_state_s *s;
2014 struct pxa2xx_ssp_s *ssp;
c1713132 2015 int iomemtype, i;
e4bcb14c 2016 int index;
c1713132
AZ		 2017 s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
2018
4207117c
AZ		 2019 if (revision && strncmp(revision, "pxa27", 5)) {
2020 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2021 exit(1);
2022 }
aaed909a
FB		 2023 if (!revision)
2024 revision = "pxa270";
2025
2026 s->env = cpu_init(revision);
2027 if (!s->env) {
2028 fprintf(stderr, "Unable to find CPU definition\n");
2029 exit(1);
2030 }
38641a52
AZ		 2031 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2032
d95b2f8d
AZ		 2033 /* SDRAM & Internal Memory Storage */
2034 cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
2035 sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2036 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
2037 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM);
2038
c1713132
AZ		 2039 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2040
2041 s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2042
a171fe39 2043 pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
3f582262 2044 s->pic[PXA27X_PIC_OST_4_11]);
a171fe39 2045
c1713132
AZ		 2046 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
2047
e4bcb14c
TS		 2048 index = drive_get_index(IF_SD, 0, 0);
2049 if (index == -1) {
2050 fprintf(stderr, "qemu: missing SecureDigital device\n");
2051 exit(1);
2052 }
2053 s->mmc = pxa2xx_mmci_init(0x41100000, drives_table[index].bdrv,
2054 s->pic[PXA2XX_PIC_MMC], s->dma);
a171fe39 2055
c1713132
AZ		 2056 for (i = 0; pxa270_serial[i].io_base; i ++)
2057 if (serial_hds[i])
2058 serial_mm_init(pxa270_serial[i].io_base, 2,
b6cd0ea1
AJ		 2059 s->pic[pxa270_serial[i].irqn], 14857000/16,
2060 serial_hds[i], 1);
c1713132
AZ		 2061 else
2062 break;
2063 if (serial_hds[i])
2064 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2065 s->dma, serial_hds[i]);
2066
a171fe39
AZ		 2067 if (ds)
2068 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
2069
c1713132 2070 s->cm_base = 0x41300000;
82d17978 2071 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
c1713132
AZ		 2072 s->clkcfg = 0x00000009; /* Turbo mode active */
2073 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
2074 pxa2xx_cm_writefn, s);
187337f8 2075 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
aa941b94 2076 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
c1713132
AZ		 2077
2078 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2079
2080 s->mm_base = 0x48000000;
2081 s->mm_regs[MDMRS >> 2] = 0x00020002;
2082 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2083 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2084 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
2085 pxa2xx_mm_writefn, s);
187337f8 2086 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
aa941b94 2087 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
c1713132 2088
2a163929
AZ		 2089 s->pm_base = 0x40f00000;
2090 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
2091 pxa2xx_pm_writefn, s);
187337f8 2092 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2a163929
AZ		 2093 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2094
c1713132
AZ		 2095 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2096 s->ssp = (struct pxa2xx_ssp_s **)
2097 qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
2098 ssp = (struct pxa2xx_ssp_s *)
2099 qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
2100 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
8da3ff18 2101 target_phys_addr_t ssp_base;
c1713132 2102 s->ssp[i] = &ssp[i];
8da3ff18 2103 ssp_base = pxa27x_ssp[i].io_base;
c1713132
AZ		 2104 ssp[i].irq = s->pic[pxa27x_ssp[i].irqn];
2105
2106 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
2107 pxa2xx_ssp_writefn, &ssp[i]);
8da3ff18 2108 cpu_register_physical_memory(ssp_base, 0x1000, iomemtype);
aa941b94
AZ		 2109 register_savevm("pxa2xx_ssp", i, 0,
2110 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
c1713132
AZ		 2111 }
2112
a171fe39
AZ		 2113 if (usb_enabled) {
2114 usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
2115 }
2116
2117 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2118 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2119
c1713132
AZ		 2120 s->rtc_base = 0x40900000;
2121 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
2122 pxa2xx_rtc_writefn, s);
187337f8 2123 cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
aa941b94
AZ		 2124 pxa2xx_rtc_init(s);
2125 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
c1713132 2126
2a163929
AZ		 2127 s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2128 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
c1713132
AZ		 2129
2130 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2131
31b87f2e
AZ		 2132 s->kp = pxa27x_keypad_init(0x41500000, s->pic[PXA2XX_PIC_KEYPAD]);
2133
c1713132 2134 /* GPIO1 resets the processor */
fe8f096b 2135 /* The handler can be overridden by board-specific code */
38641a52 2136 pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
c1713132
AZ		 2137 return s;
2138}
2139
2140/* Initialise a PXA255 integrated chip (ARM based core). */
d95b2f8d
AZ		 2141struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
2142 DisplayState *ds)
c1713132
AZ		 2143{
2144 struct pxa2xx_state_s *s;
2145 struct pxa2xx_ssp_s *ssp;
2146 int iomemtype, i;
e4bcb14c 2147 int index;
aaed909a 2148
c1713132
AZ		 2149 s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
2150
aaed909a
FB		 2151 s->env = cpu_init("pxa255");
2152 if (!s->env) {
2153 fprintf(stderr, "Unable to find CPU definition\n");
2154 exit(1);
2155 }
38641a52
AZ		 2156 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2157
d95b2f8d 2158 /* SDRAM & Internal Memory Storage */
a07dec22
AZ		 2159 cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
2160 qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2161 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
2162 qemu_ram_alloc(PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
d95b2f8d 2163
c1713132
AZ		 2164 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2165
2166 s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2167
3f582262 2168 pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
a171fe39 2169
3bdd58a4 2170 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
c1713132 2171
e4bcb14c
TS		 2172 index = drive_get_index(IF_SD, 0, 0);
2173 if (index == -1) {
2174 fprintf(stderr, "qemu: missing SecureDigital device\n");
2175 exit(1);
2176 }
2177 s->mmc = pxa2xx_mmci_init(0x41100000, drives_table[index].bdrv,
2178 s->pic[PXA2XX_PIC_MMC], s->dma);
a171fe39 2179
c1713132
AZ		 2180 for (i = 0; pxa255_serial[i].io_base; i ++)
2181 if (serial_hds[i])
2182 serial_mm_init(pxa255_serial[i].io_base, 2,
b6cd0ea1
AJ		 2183 s->pic[pxa255_serial[i].irqn], 14745600/16,
2184 serial_hds[i], 1);
c1713132
AZ		 2185 else
2186 break;
2187 if (serial_hds[i])
2188 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2189 s->dma, serial_hds[i]);
2190
a171fe39
AZ		 2191 if (ds)
2192 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
2193
c1713132 2194 s->cm_base = 0x41300000;
82d17978 2195 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
c1713132
AZ		 2196 s->clkcfg = 0x00000009; /* Turbo mode active */
2197 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
2198 pxa2xx_cm_writefn, s);
187337f8 2199 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
aa941b94 2200 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
c1713132
AZ		 2201
2202 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2203
2204 s->mm_base = 0x48000000;
2205 s->mm_regs[MDMRS >> 2] = 0x00020002;
2206 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2207 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2208 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
2209 pxa2xx_mm_writefn, s);
187337f8 2210 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
aa941b94 2211 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
c1713132 2212
2a163929
AZ		 2213 s->pm_base = 0x40f00000;
2214 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
2215 pxa2xx_pm_writefn, s);
187337f8 2216 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2a163929
AZ		 2217 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2218
c1713132
AZ		 2219 for (i = 0; pxa255_ssp[i].io_base; i ++);
2220 s->ssp = (struct pxa2xx_ssp_s **)
2221 qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
2222 ssp = (struct pxa2xx_ssp_s *)
2223 qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
2224 for (i = 0; pxa255_ssp[i].io_base; i ++) {
8da3ff18 2225 target_phys_addr_t ssp_base;
c1713132 2226 s->ssp[i] = &ssp[i];
8da3ff18 2227 ssp_base = pxa255_ssp[i].io_base;
c1713132
AZ		 2228 ssp[i].irq = s->pic[pxa255_ssp[i].irqn];
2229
2230 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
2231 pxa2xx_ssp_writefn, &ssp[i]);
8da3ff18 2232 cpu_register_physical_memory(ssp_base, 0x1000, iomemtype);
aa941b94
AZ		 2233 register_savevm("pxa2xx_ssp", i, 0,
2234 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
c1713132
AZ		 2235 }
2236
a171fe39
AZ		 2237 if (usb_enabled) {
2238 usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
2239 }
2240
2241 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2242 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2243
c1713132
AZ		 2244 s->rtc_base = 0x40900000;
2245 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
2246 pxa2xx_rtc_writefn, s);
187337f8 2247 cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
aa941b94
AZ		 2248 pxa2xx_rtc_init(s);
2249 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
c1713132 2250
2a163929
AZ		 2251 s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2252 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
c1713132
AZ		 2253
2254 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2255
2256 /* GPIO1 resets the processor */
fe8f096b 2257 /* The handler can be overridden by board-specific code */
38641a52 2258 pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
c1713132
AZ		 2259 return s;
2260}
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