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Document ColdFire system emulation.
[qemu.git] / hw / pxa2xx.c
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c1713132
AZ		 1/*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <[email protected]>
6 *
7 * This code is licenced under the GPL.
8 */
9
10# include "vl.h"
11
12static struct {
13 target_phys_addr_t io_base;
14 int irqn;
15} pxa255_serial[] = {
16 { 0x40100000, PXA2XX_PIC_FFUART },
17 { 0x40200000, PXA2XX_PIC_BTUART },
18 { 0x40700000, PXA2XX_PIC_STUART },
19 { 0x41600000, PXA25X_PIC_HWUART },
20 { 0, 0 }
21}, pxa270_serial[] = {
22 { 0x40100000, PXA2XX_PIC_FFUART },
23 { 0x40200000, PXA2XX_PIC_BTUART },
24 { 0x40700000, PXA2XX_PIC_STUART },
25 { 0, 0 }
26};
27
28static struct {
29 target_phys_addr_t io_base;
30 int irqn;
31} pxa250_ssp[] = {
32 { 0x41000000, PXA2XX_PIC_SSP },
33 { 0, 0 }
34}, pxa255_ssp[] = {
35 { 0x41000000, PXA2XX_PIC_SSP },
36 { 0x41400000, PXA25X_PIC_NSSP },
37 { 0, 0 }
38}, pxa26x_ssp[] = {
39 { 0x41000000, PXA2XX_PIC_SSP },
40 { 0x41400000, PXA25X_PIC_NSSP },
41 { 0x41500000, PXA26X_PIC_ASSP },
42 { 0, 0 }
43}, pxa27x_ssp[] = {
44 { 0x41000000, PXA2XX_PIC_SSP },
45 { 0x41700000, PXA27X_PIC_SSP2 },
46 { 0x41900000, PXA2XX_PIC_SSP3 },
47 { 0, 0 }
48};
49
50#define PMCR 0x00 /* Power Manager Control register */
51#define PSSR 0x04 /* Power Manager Sleep Status register */
52#define PSPR 0x08 /* Power Manager Scratch-Pad register */
53#define PWER 0x0c /* Power Manager Wake-Up Enable register */
54#define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
55#define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
56#define PEDR 0x18 /* Power Manager Edge-Detect Status register */
57#define PCFR 0x1c /* Power Manager General Configuration register */
58#define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
59#define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
60#define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
61#define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
62#define RCSR 0x30 /* Reset Controller Status register */
63#define PSLR 0x34 /* Power Manager Sleep Configuration register */
64#define PTSR 0x38 /* Power Manager Standby Configuration register */
65#define PVCR 0x40 /* Power Manager Voltage Change Control register */
66#define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
67#define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
68#define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
69#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
70#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
71
72static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
73{
74 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
75 addr -= s->pm_base;
76
77 switch (addr) {
78 case PMCR ... PCMD31:
79 if (addr & 3)
80 goto fail;
81
82 return s->pm_regs[addr >> 2];
83 default:
84 fail:
85 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
86 break;
87 }
88 return 0;
89}
90
91static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
92 uint32_t value)
93{
94 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
95 addr -= s->pm_base;
96
97 switch (addr) {
98 case PMCR:
99 s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
100 s->pm_regs[addr >> 2] |= value & 0x15;
101 break;
102
103 case PSSR: /* Read-clean registers */
104 case RCSR:
105 case PKSR:
106 s->pm_regs[addr >> 2] &= ~value;
107 break;
108
109 default: /* Read-write registers */
110 if (addr >= PMCR && addr <= PCMD31 && !(addr & 3)) {
111 s->pm_regs[addr >> 2] = value;
112 break;
113 }
114
115 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
116 break;
117 }
118}
119
120static CPUReadMemoryFunc *pxa2xx_pm_readfn[] = {
121 pxa2xx_pm_read,
122 pxa2xx_pm_read,
123 pxa2xx_pm_read,
124};
125
126static CPUWriteMemoryFunc *pxa2xx_pm_writefn[] = {
127 pxa2xx_pm_write,
128 pxa2xx_pm_write,
129 pxa2xx_pm_write,
130};
131
132#define CCCR 0x00 /* Core Clock Configuration register */
133#define CKEN 0x04 /* Clock Enable register */
134#define OSCC 0x08 /* Oscillator Configuration register */
135#define CCSR 0x0c /* Core Clock Status register */
136
137static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
138{
139 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
140 addr -= s->cm_base;
141
142 switch (addr) {
143 case CCCR:
144 case CKEN:
145 case OSCC:
146 return s->cm_regs[addr >> 2];
147
148 case CCSR:
149 return s->cm_regs[CCCR >> 2] | (3 << 28);
150
151 default:
152 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
153 break;
154 }
155 return 0;
156}
157
158static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
159 uint32_t value)
160{
161 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
162 addr -= s->cm_base;
163
164 switch (addr) {
165 case CCCR:
166 case CKEN:
167 s->cm_regs[addr >> 2] = value;
168 break;
169
170 case OSCC:
565d2895 171 s->cm_regs[addr >> 2] &= ~0x6c;
c1713132 172 s->cm_regs[addr >> 2] |= value & 0x6e;
565d2895
AZ		 173 if ((value >> 1) & 1) /* OON */
174 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
c1713132
AZ		 175 break;
176
177 default:
178 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
179 break;
180 }
181}
182
183static CPUReadMemoryFunc *pxa2xx_cm_readfn[] = {
184 pxa2xx_cm_read,
185 pxa2xx_cm_read,
186 pxa2xx_cm_read,
187};
188
189static CPUWriteMemoryFunc *pxa2xx_cm_writefn[] = {
190 pxa2xx_cm_write,
191 pxa2xx_cm_write,
192 pxa2xx_cm_write,
193};
194
195static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
196{
197 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
198
199 switch (reg) {
200 case 6: /* Clock Configuration register */
201 return s->clkcfg;
202
203 case 7: /* Power Mode register */
204 return 0;
205
206 default:
207 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
208 break;
209 }
210 return 0;
211}
212
213static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
214 uint32_t value)
215{
216 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
217 static const char *pwrmode[8] = {
218 "Normal", "Idle", "Deep-idle", "Standby",
219 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
220 };
221
222 switch (reg) {
223 case 6: /* Clock Configuration register */
224 s->clkcfg = value & 0xf;
225 if (value & 2)
226 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
227 break;
228
229 case 7: /* Power Mode register */
230 if (value & 8)
231 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
232 switch (value & 7) {
233 case 0:
234 /* Do nothing */
235 break;
236
237 case 1:
238 /* Idle */
239 if (!(s->cm_regs[CCCR] & (1 << 31))) { /* CPDIS */
240 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
241 break;
242 }
243 /* Fall through. */
244
245 case 2:
246 /* Deep-Idle */
247 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
248 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
249 goto message;
250
251 case 3:
a90b7318
AZ		 252 s->env->uncached_cpsr =
253 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
c1713132
AZ		 254 s->env->cp15.c1_sys = 0;
255 s->env->cp15.c1_coproc = 0;
ce819861 256 s->env->cp15.c2_base = 0;
c1713132
AZ		 257 s->env->cp15.c3 = 0;
258 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
259 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
260
261 /*
262 * The scratch-pad register is almost universally used
263 * for storing the return address on suspend. For the
264 * lack of a resuming bootloader, perform a jump
265 * directly to that address.
266 */
267 memset(s->env->regs, 0, 4 * 15);
268 s->env->regs[15] = s->pm_regs[PSPR >> 2];
269
270#if 0
271 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
272 cpu_physical_memory_write(0, &buffer, 4);
273 buffer = s->pm_regs[PSPR >> 2];
274 cpu_physical_memory_write(8, &buffer, 4);
275#endif
276
277 /* Suspend */
278 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
279
280 goto message;
281
282 default:
283 message:
284 printf("%s: machine entered %s mode\n", __FUNCTION__,
285 pwrmode[value & 7]);
286 }
287 break;
288
289 default:
290 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
291 break;
292 }
293}
294
295/* Performace Monitoring Registers */
296#define CPPMNC 0 /* Performance Monitor Control register */
297#define CPCCNT 1 /* Clock Counter register */
298#define CPINTEN 4 /* Interrupt Enable register */
299#define CPFLAG 5 /* Overflow Flag register */
300#define CPEVTSEL 8 /* Event Selection register */
301
302#define CPPMN0 0 /* Performance Count register 0 */
303#define CPPMN1 1 /* Performance Count register 1 */
304#define CPPMN2 2 /* Performance Count register 2 */
305#define CPPMN3 3 /* Performance Count register 3 */
306
307static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
308{
309 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
310
311 switch (reg) {
312 case CPPMNC:
313 return s->pmnc;
314 case CPCCNT:
315 if (s->pmnc & 1)
316 return qemu_get_clock(vm_clock);
317 else
318 return 0;
319 case CPINTEN:
320 case CPFLAG:
321 case CPEVTSEL:
322 return 0;
323
324 default:
325 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
326 break;
327 }
328 return 0;
329}
330
331static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
332 uint32_t value)
333{
334 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
335
336 switch (reg) {
337 case CPPMNC:
338 s->pmnc = value;
339 break;
340
341 case CPCCNT:
342 case CPINTEN:
343 case CPFLAG:
344 case CPEVTSEL:
345 break;
346
347 default:
348 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
349 break;
350 }
351}
352
353static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
354{
355 switch (crm) {
356 case 0:
357 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
358 case 1:
359 return pxa2xx_perf_read(opaque, op2, reg, crm);
360 case 2:
361 switch (reg) {
362 case CPPMN0:
363 case CPPMN1:
364 case CPPMN2:
365 case CPPMN3:
366 return 0;
367 }
368 /* Fall through */
369 default:
370 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
371 break;
372 }
373 return 0;
374}
375
376static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
377 uint32_t value)
378{
379 switch (crm) {
380 case 0:
381 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
382 break;
383 case 1:
384 pxa2xx_perf_write(opaque, op2, reg, crm, value);
385 break;
386 case 2:
387 switch (reg) {
388 case CPPMN0:
389 case CPPMN1:
390 case CPPMN2:
391 case CPPMN3:
392 return;
393 }
394 /* Fall through */
395 default:
396 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
397 break;
398 }
399}
400
401#define MDCNFG 0x00 /* SDRAM Configuration register */
402#define MDREFR 0x04 /* SDRAM Refresh Control register */
403#define MSC0 0x08 /* Static Memory Control register 0 */
404#define MSC1 0x0c /* Static Memory Control register 1 */
405#define MSC2 0x10 /* Static Memory Control register 2 */
406#define MECR 0x14 /* Expansion Memory Bus Config register */
407#define SXCNFG 0x1c /* Synchronous Static Memory Config register */
408#define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
409#define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
410#define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
411#define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
412#define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
413#define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
414#define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
415#define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
416#define ARB_CNTL 0x48 /* Arbiter Control register */
417#define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
418#define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
419#define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
420#define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
421#define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
422#define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
423#define SA1110 0x64 /* SA-1110 Memory Compatibility register */
424
425static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
426{
427 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
428 addr -= s->mm_base;
429
430 switch (addr) {
431 case MDCNFG ... SA1110:
432 if ((addr & 3) == 0)
433 return s->mm_regs[addr >> 2];
434
435 default:
436 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
437 break;
438 }
439 return 0;
440}
441
442static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
443 uint32_t value)
444{
445 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
446 addr -= s->mm_base;
447
448 switch (addr) {
449 case MDCNFG ... SA1110:
450 if ((addr & 3) == 0) {
451 s->mm_regs[addr >> 2] = value;
452 break;
453 }
454
455 default:
456 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
457 break;
458 }
459}
460
461static CPUReadMemoryFunc *pxa2xx_mm_readfn[] = {
462 pxa2xx_mm_read,
463 pxa2xx_mm_read,
464 pxa2xx_mm_read,
465};
466
467static CPUWriteMemoryFunc *pxa2xx_mm_writefn[] = {
468 pxa2xx_mm_write,
469 pxa2xx_mm_write,
470 pxa2xx_mm_write,
471};
472
473/* Synchronous Serial Ports */
474struct pxa2xx_ssp_s {
475 target_phys_addr_t base;
476 qemu_irq irq;
477 int enable;
478
479 uint32_t sscr[2];
480 uint32_t sspsp;
481 uint32_t ssto;
482 uint32_t ssitr;
483 uint32_t sssr;
484 uint8_t sstsa;
485 uint8_t ssrsa;
486 uint8_t ssacd;
487
488 uint32_t rx_fifo[16];
489 int rx_level;
490 int rx_start;
491
492 uint32_t (*readfn)(void *opaque);
493 void (*writefn)(void *opaque, uint32_t value);
494 void *opaque;
495};
496
497#define SSCR0 0x00 /* SSP Control register 0 */
498#define SSCR1 0x04 /* SSP Control register 1 */
499#define SSSR 0x08 /* SSP Status register */
500#define SSITR 0x0c /* SSP Interrupt Test register */
501#define SSDR 0x10 /* SSP Data register */
502#define SSTO 0x28 /* SSP Time-Out register */
503#define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
504#define SSTSA 0x30 /* SSP TX Time Slot Active register */
505#define SSRSA 0x34 /* SSP RX Time Slot Active register */
506#define SSTSS 0x38 /* SSP Time Slot Status register */
507#define SSACD 0x3c /* SSP Audio Clock Divider register */
508
509/* Bitfields for above registers */
510#define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
511#define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
512#define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
513#define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
514#define SSCR0_SSE (1 << 7)
515#define SSCR0_RIM (1 << 22)
516#define SSCR0_TIM (1 << 23)
517#define SSCR0_MOD (1 << 31)
518#define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
519#define SSCR1_RIE (1 << 0)
520#define SSCR1_TIE (1 << 1)
521#define SSCR1_LBM (1 << 2)
522#define SSCR1_MWDS (1 << 5)
523#define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
524#define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
525#define SSCR1_EFWR (1 << 14)
526#define SSCR1_PINTE (1 << 18)
527#define SSCR1_TINTE (1 << 19)
528#define SSCR1_RSRE (1 << 20)
529#define SSCR1_TSRE (1 << 21)
530#define SSCR1_EBCEI (1 << 29)
531#define SSITR_INT (7 << 5)
532#define SSSR_TNF (1 << 2)
533#define SSSR_RNE (1 << 3)
534#define SSSR_TFS (1 << 5)
535#define SSSR_RFS (1 << 6)
536#define SSSR_ROR (1 << 7)
537#define SSSR_PINT (1 << 18)
538#define SSSR_TINT (1 << 19)
539#define SSSR_EOC (1 << 20)
540#define SSSR_TUR (1 << 21)
541#define SSSR_BCE (1 << 23)
542#define SSSR_RW 0x00bc0080
543
544static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s)
545{
546 int level = 0;
547
548 level |= s->ssitr & SSITR_INT;
549 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
550 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
551 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
552 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
553 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
554 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
555 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
556 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
557 qemu_set_irq(s->irq, !!level);
558}
559
560static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s)
561{
562 s->sssr &= ~(0xf << 12); /* Clear RFL */
563 s->sssr &= ~(0xf << 8); /* Clear TFL */
564 s->sssr &= ~SSSR_TNF;
565 if (s->enable) {
566 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
567 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
568 s->sssr |= SSSR_RFS;
569 else
570 s->sssr &= ~SSSR_RFS;
571 if (0 <= SSCR1_TFT(s->sscr[1]))
572 s->sssr |= SSSR_TFS;
573 else
574 s->sssr &= ~SSSR_TFS;
575 if (s->rx_level)
576 s->sssr |= SSSR_RNE;
577 else
578 s->sssr &= ~SSSR_RNE;
579 s->sssr |= SSSR_TNF;
580 }
581
582 pxa2xx_ssp_int_update(s);
583}
584
585static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
586{
587 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
588 uint32_t retval;
589 addr -= s->base;
590
591 switch (addr) {
592 case SSCR0:
593 return s->sscr[0];
594 case SSCR1:
595 return s->sscr[1];
596 case SSPSP:
597 return s->sspsp;
598 case SSTO:
599 return s->ssto;
600 case SSITR:
601 return s->ssitr;
602 case SSSR:
603 return s->sssr | s->ssitr;
604 case SSDR:
605 if (!s->enable)
606 return 0xffffffff;
607 if (s->rx_level < 1) {
608 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
609 return 0xffffffff;
610 }
611 s->rx_level --;
612 retval = s->rx_fifo[s->rx_start ++];
613 s->rx_start &= 0xf;
614 pxa2xx_ssp_fifo_update(s);
615 return retval;
616 case SSTSA:
617 return s->sstsa;
618 case SSRSA:
619 return s->ssrsa;
620 case SSTSS:
621 return 0;
622 case SSACD:
623 return s->ssacd;
624 default:
625 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
626 break;
627 }
628 return 0;
629}
630
631static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
632 uint32_t value)
633{
634 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
635 addr -= s->base;
636
637 switch (addr) {
638 case SSCR0:
639 s->sscr[0] = value & 0xc7ffffff;
640 s->enable = value & SSCR0_SSE;
641 if (value & SSCR0_MOD)
642 printf("%s: Attempt to use network mode\n", __FUNCTION__);
643 if (s->enable && SSCR0_DSS(value) < 4)
644 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
645 SSCR0_DSS(value));
646 if (!(value & SSCR0_SSE)) {
647 s->sssr = 0;
648 s->ssitr = 0;
649 s->rx_level = 0;
650 }
651 pxa2xx_ssp_fifo_update(s);
652 break;
653
654 case SSCR1:
655 s->sscr[1] = value;
656 if (value & (SSCR1_LBM | SSCR1_EFWR))
657 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
658 pxa2xx_ssp_fifo_update(s);
659 break;
660
661 case SSPSP:
662 s->sspsp = value;
663 break;
664
665 case SSTO:
666 s->ssto = value;
667 break;
668
669 case SSITR:
670 s->ssitr = value & SSITR_INT;
671 pxa2xx_ssp_int_update(s);
672 break;
673
674 case SSSR:
675 s->sssr &= ~(value & SSSR_RW);
676 pxa2xx_ssp_int_update(s);
677 break;
678
679 case SSDR:
680 if (SSCR0_UWIRE(s->sscr[0])) {
681 if (s->sscr[1] & SSCR1_MWDS)
682 value &= 0xffff;
683 else
684 value &= 0xff;
685 } else
686 /* Note how 32bits overflow does no harm here */
687 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
688
689 /* Data goes from here to the Tx FIFO and is shifted out from
690 * there directly to the slave, no need to buffer it.
691 */
692 if (s->enable) {
693 if (s->writefn)
694 s->writefn(s->opaque, value);
695
696 if (s->rx_level < 0x10) {
697 if (s->readfn)
698 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] =
699 s->readfn(s->opaque);
700 else
701 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = 0x0;
702 } else
703 s->sssr |= SSSR_ROR;
704 }
705 pxa2xx_ssp_fifo_update(s);
706 break;
707
708 case SSTSA:
709 s->sstsa = value;
710 break;
711
712 case SSRSA:
713 s->ssrsa = value;
714 break;
715
716 case SSACD:
717 s->ssacd = value;
718 break;
719
720 default:
721 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
722 break;
723 }
724}
725
726void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
727 uint32_t (*readfn)(void *opaque),
728 void (*writefn)(void *opaque, uint32_t value), void *opaque)
729{
730 if (!port) {
731 printf("%s: no such SSP\n", __FUNCTION__);
732 exit(-1);
733 }
734
735 port->opaque = opaque;
736 port->readfn = readfn;
737 port->writefn = writefn;
738}
739
740static CPUReadMemoryFunc *pxa2xx_ssp_readfn[] = {
741 pxa2xx_ssp_read,
742 pxa2xx_ssp_read,
743 pxa2xx_ssp_read,
744};
745
746static CPUWriteMemoryFunc *pxa2xx_ssp_writefn[] = {
747 pxa2xx_ssp_write,
748 pxa2xx_ssp_write,
749 pxa2xx_ssp_write,
750};
751
752/* Real-Time Clock */
753#define RCNR 0x00 /* RTC Counter register */
754#define RTAR 0x04 /* RTC Alarm register */
755#define RTSR 0x08 /* RTC Status register */
756#define RTTR 0x0c /* RTC Timer Trim register */
757#define RDCR 0x10 /* RTC Day Counter register */
758#define RYCR 0x14 /* RTC Year Counter register */
759#define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
760#define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
761#define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
762#define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
763#define SWCR 0x28 /* RTC Stopwatch Counter register */
764#define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
765#define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
766#define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
767#define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
768
769static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s *s)
770{
771 qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
772}
773
774static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s)
775{
776 int64_t rt = qemu_get_clock(rt_clock);
777 s->last_rcnr += ((rt - s->last_hz) << 15) /
778 (1000 * ((s->rttr & 0xffff) + 1));
779 s->last_rdcr += ((rt - s->last_hz) << 15) /
780 (1000 * ((s->rttr & 0xffff) + 1));
781 s->last_hz = rt;
782}
783
784static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s)
785{
786 int64_t rt = qemu_get_clock(rt_clock);
787 if (s->rtsr & (1 << 12))
788 s->last_swcr += (rt - s->last_sw) / 10;
789 s->last_sw = rt;
790}
791
792static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s)
793{
794 int64_t rt = qemu_get_clock(rt_clock);
795 if (s->rtsr & (1 << 15))
796 s->last_swcr += rt - s->last_pi;
797 s->last_pi = rt;
798}
799
800static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s,
801 uint32_t rtsr)
802{
803 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
804 qemu_mod_timer(s->rtc_hz, s->last_hz +
805 (((s->rtar - s->last_rcnr) * 1000 *
806 ((s->rttr & 0xffff) + 1)) >> 15));
807 else
808 qemu_del_timer(s->rtc_hz);
809
810 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
811 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
812 (((s->rdar1 - s->last_rdcr) * 1000 *
813 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
814 else
815 qemu_del_timer(s->rtc_rdal1);
816
817 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
818 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
819 (((s->rdar2 - s->last_rdcr) * 1000 *
820 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
821 else
822 qemu_del_timer(s->rtc_rdal2);
823
824 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
825 qemu_mod_timer(s->rtc_swal1, s->last_sw +
826 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
827 else
828 qemu_del_timer(s->rtc_swal1);
829
830 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
831 qemu_mod_timer(s->rtc_swal2, s->last_sw +
832 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
833 else
834 qemu_del_timer(s->rtc_swal2);
835
836 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
837 qemu_mod_timer(s->rtc_pi, s->last_pi +
838 (s->piar & 0xffff) - s->last_rtcpicr);
839 else
840 qemu_del_timer(s->rtc_pi);
841}
842
843static inline void pxa2xx_rtc_hz_tick(void *opaque)
844{
845 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
846 s->rtsr |= (1 << 0);
847 pxa2xx_rtc_alarm_update(s, s->rtsr);
848 pxa2xx_rtc_int_update(s);
849}
850
851static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
852{
853 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
854 s->rtsr |= (1 << 4);
855 pxa2xx_rtc_alarm_update(s, s->rtsr);
856 pxa2xx_rtc_int_update(s);
857}
858
859static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
860{
861 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
862 s->rtsr |= (1 << 6);
863 pxa2xx_rtc_alarm_update(s, s->rtsr);
864 pxa2xx_rtc_int_update(s);
865}
866
867static inline void pxa2xx_rtc_swal1_tick(void *opaque)
868{
869 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
870 s->rtsr |= (1 << 8);
871 pxa2xx_rtc_alarm_update(s, s->rtsr);
872 pxa2xx_rtc_int_update(s);
873}
874
875static inline void pxa2xx_rtc_swal2_tick(void *opaque)
876{
877 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
878 s->rtsr |= (1 << 10);
879 pxa2xx_rtc_alarm_update(s, s->rtsr);
880 pxa2xx_rtc_int_update(s);
881}
882
883static inline void pxa2xx_rtc_pi_tick(void *opaque)
884{
885 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
886 s->rtsr |= (1 << 13);
887 pxa2xx_rtc_piupdate(s);
888 s->last_rtcpicr = 0;
889 pxa2xx_rtc_alarm_update(s, s->rtsr);
890 pxa2xx_rtc_int_update(s);
891}
892
893static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
894{
895 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
896 addr -= s->rtc_base;
897
898 switch (addr) {
899 case RTTR:
900 return s->rttr;
901 case RTSR:
902 return s->rtsr;
903 case RTAR:
904 return s->rtar;
905 case RDAR1:
906 return s->rdar1;
907 case RDAR2:
908 return s->rdar2;
909 case RYAR1:
910 return s->ryar1;
911 case RYAR2:
912 return s->ryar2;
913 case SWAR1:
914 return s->swar1;
915 case SWAR2:
916 return s->swar2;
917 case PIAR:
918 return s->piar;
919 case RCNR:
920 return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
921 (1000 * ((s->rttr & 0xffff) + 1));
922 case RDCR:
923 return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
924 (1000 * ((s->rttr & 0xffff) + 1));
925 case RYCR:
926 return s->last_rycr;
927 case SWCR:
928 if (s->rtsr & (1 << 12))
929 return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10;
930 else
931 return s->last_swcr;
932 default:
933 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
934 break;
935 }
936 return 0;
937}
938
939static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
940 uint32_t value)
941{
942 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
943 addr -= s->rtc_base;
944
945 switch (addr) {
946 case RTTR:
947 if (!(s->rttr & (1 << 31))) {
948 pxa2xx_rtc_hzupdate(s);
949 s->rttr = value;
950 pxa2xx_rtc_alarm_update(s, s->rtsr);
951 }
952 break;
953
954 case RTSR:
955 if ((s->rtsr ^ value) & (1 << 15))
956 pxa2xx_rtc_piupdate(s);
957
958 if ((s->rtsr ^ value) & (1 << 12))
959 pxa2xx_rtc_swupdate(s);
960
961 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
962 pxa2xx_rtc_alarm_update(s, value);
963
964 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
965 pxa2xx_rtc_int_update(s);
966 break;
967
968 case RTAR:
969 s->rtar = value;
970 pxa2xx_rtc_alarm_update(s, s->rtsr);
971 break;
972
973 case RDAR1:
974 s->rdar1 = value;
975 pxa2xx_rtc_alarm_update(s, s->rtsr);
976 break;
977
978 case RDAR2:
979 s->rdar2 = value;
980 pxa2xx_rtc_alarm_update(s, s->rtsr);
981 break;
982
983 case RYAR1:
984 s->ryar1 = value;
985 pxa2xx_rtc_alarm_update(s, s->rtsr);
986 break;
987
988 case RYAR2:
989 s->ryar2 = value;
990 pxa2xx_rtc_alarm_update(s, s->rtsr);
991 break;
992
993 case SWAR1:
994 pxa2xx_rtc_swupdate(s);
995 s->swar1 = value;
996 s->last_swcr = 0;
997 pxa2xx_rtc_alarm_update(s, s->rtsr);
998 break;
999
1000 case SWAR2:
1001 s->swar2 = value;
1002 pxa2xx_rtc_alarm_update(s, s->rtsr);
1003 break;
1004
1005 case PIAR:
1006 s->piar = value;
1007 pxa2xx_rtc_alarm_update(s, s->rtsr);
1008 break;
1009
1010 case RCNR:
1011 pxa2xx_rtc_hzupdate(s);
1012 s->last_rcnr = value;
1013 pxa2xx_rtc_alarm_update(s, s->rtsr);
1014 break;
1015
1016 case RDCR:
1017 pxa2xx_rtc_hzupdate(s);
1018 s->last_rdcr = value;
1019 pxa2xx_rtc_alarm_update(s, s->rtsr);
1020 break;
1021
1022 case RYCR:
1023 s->last_rycr = value;
1024 break;
1025
1026 case SWCR:
1027 pxa2xx_rtc_swupdate(s);
1028 s->last_swcr = value;
1029 pxa2xx_rtc_alarm_update(s, s->rtsr);
1030 break;
1031
1032 case RTCPICR:
1033 pxa2xx_rtc_piupdate(s);
1034 s->last_rtcpicr = value & 0xffff;
1035 pxa2xx_rtc_alarm_update(s, s->rtsr);
1036 break;
1037
1038 default:
1039 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1040 }
1041}
1042
1043static void pxa2xx_rtc_reset(struct pxa2xx_state_s *s)
1044{
1045 struct tm *tm;
1046 time_t ti;
1047 int wom;
1048
1049 s->rttr = 0x7fff;
1050 s->rtsr = 0;
1051
1052 time(&ti);
1053 if (rtc_utc)
1054 tm = gmtime(&ti);
1055 else
1056 tm = localtime(&ti);
1057 wom = ((tm->tm_mday - 1) / 7) + 1;
1058
1059 s->last_rcnr = (uint32_t) ti;
1060 s->last_rdcr = (wom << 20) | ((tm->tm_wday + 1) << 17) |
1061 (tm->tm_hour << 12) | (tm->tm_min << 6) | tm->tm_sec;
1062 s->last_rycr = ((tm->tm_year + 1900) << 9) |
1063 ((tm->tm_mon + 1) << 5) | tm->tm_mday;
1064 s->last_swcr = (tm->tm_hour << 19) |
1065 (tm->tm_min << 13) | (tm->tm_sec << 7);
1066 s->last_rtcpicr = 0;
1067 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock);
1068
1069 s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s);
1070 s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1071 s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1072 s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s);
1073 s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s);
1074 s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s);
1075}
1076
1077static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
1078 pxa2xx_rtc_read,
1079 pxa2xx_rtc_read,
1080 pxa2xx_rtc_read,
1081};
1082
1083static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
1084 pxa2xx_rtc_write,
1085 pxa2xx_rtc_write,
1086 pxa2xx_rtc_write,
1087};
1088
1089/* PXA Inter-IC Sound Controller */
1090static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s)
1091{
1092 i2s->rx_len = 0;
1093 i2s->tx_len = 0;
1094 i2s->fifo_len = 0;
1095 i2s->clk = 0x1a;
1096 i2s->control[0] = 0x00;
1097 i2s->control[1] = 0x00;
1098 i2s->status = 0x00;
1099 i2s->mask = 0x00;
1100}
1101
1102#define SACR_TFTH(val) ((val >> 8) & 0xf)
1103#define SACR_RFTH(val) ((val >> 12) & 0xf)
1104#define SACR_DREC(val) (val & (1 << 3))
1105#define SACR_DPRL(val) (val & (1 << 4))
1106
1107static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s)
1108{
1109 int rfs, tfs;
1110 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1111 !SACR_DREC(i2s->control[1]);
1112 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1113 i2s->enable && !SACR_DPRL(i2s->control[1]);
1114
1115 pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs);
1116 pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
1117
1118 i2s->status &= 0xe0;
1119 if (i2s->rx_len)
1120 i2s->status |= 1 << 1; /* RNE */
1121 if (i2s->enable)
1122 i2s->status |= 1 << 2; /* BSY */
1123 if (tfs)
1124 i2s->status |= 1 << 3; /* TFS */
1125 if (rfs)
1126 i2s->status |= 1 << 4; /* RFS */
1127 if (!(i2s->tx_len && i2s->enable))
1128 i2s->status |= i2s->fifo_len << 8; /* TFL */
1129 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1130
1131 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1132}
1133
1134#define SACR0 0x00 /* Serial Audio Global Control register */
1135#define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1136#define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1137#define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1138#define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1139#define SADIV 0x60 /* Serial Audio Clock Divider register */
1140#define SADR 0x80 /* Serial Audio Data register */
1141
1142static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1143{
1144 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1145 addr -= s->base;
1146
1147 switch (addr) {
1148 case SACR0:
1149 return s->control[0];
1150 case SACR1:
1151 return s->control[1];
1152 case SASR0:
1153 return s->status;
1154 case SAIMR:
1155 return s->mask;
1156 case SAICR:
1157 return 0;
1158 case SADIV:
1159 return s->clk;
1160 case SADR:
1161 if (s->rx_len > 0) {
1162 s->rx_len --;
1163 pxa2xx_i2s_update(s);
1164 return s->codec_in(s->opaque);
1165 }
1166 return 0;
1167 default:
1168 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1169 break;
1170 }
1171 return 0;
1172}
1173
1174static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1175 uint32_t value)
1176{
1177 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1178 uint32_t *sample;
1179 addr -= s->base;
1180
1181 switch (addr) {
1182 case SACR0:
1183 if (value & (1 << 3)) /* RST */
1184 pxa2xx_i2s_reset(s);
1185 s->control[0] = value & 0xff3d;
1186 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1187 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1188 s->codec_out(s->opaque, *sample);
1189 s->status &= ~(1 << 7); /* I2SOFF */
1190 }
1191 if (value & (1 << 4)) /* EFWR */
1192 printf("%s: Attempt to use special function\n", __FUNCTION__);
1193 s->enable = ((value ^ 4) & 5) == 5; /* ENB && !RST*/
1194 pxa2xx_i2s_update(s);
1195 break;
1196 case SACR1:
1197 s->control[1] = value & 0x0039;
1198 if (value & (1 << 5)) /* ENLBF */
1199 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1200 if (value & (1 << 4)) /* DPRL */
1201 s->fifo_len = 0;
1202 pxa2xx_i2s_update(s);
1203 break;
1204 case SAIMR:
1205 s->mask = value & 0x0078;
1206 pxa2xx_i2s_update(s);
1207 break;
1208 case SAICR:
1209 s->status &= ~(value & (3 << 5));
1210 pxa2xx_i2s_update(s);
1211 break;
1212 case SADIV:
1213 s->clk = value & 0x007f;
1214 break;
1215 case SADR:
1216 if (s->tx_len && s->enable) {
1217 s->tx_len --;
1218 pxa2xx_i2s_update(s);
1219 s->codec_out(s->opaque, value);
1220 } else if (s->fifo_len < 16) {
1221 s->fifo[s->fifo_len ++] = value;
1222 pxa2xx_i2s_update(s);
1223 }
1224 break;
1225 default:
1226 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1227 }
1228}
1229
1230static CPUReadMemoryFunc *pxa2xx_i2s_readfn[] = {
1231 pxa2xx_i2s_read,
1232 pxa2xx_i2s_read,
1233 pxa2xx_i2s_read,
1234};
1235
1236static CPUWriteMemoryFunc *pxa2xx_i2s_writefn[] = {
1237 pxa2xx_i2s_write,
1238 pxa2xx_i2s_write,
1239 pxa2xx_i2s_write,
1240};
1241
1242static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1243{
1244 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1245 uint32_t *sample;
1246
1247 /* Signal FIFO errors */
1248 if (s->enable && s->tx_len)
1249 s->status |= 1 << 5; /* TUR */
1250 if (s->enable && s->rx_len)
1251 s->status |= 1 << 6; /* ROR */
1252
1253 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1254 * handle the cases where it makes a difference. */
1255 s->tx_len = tx - s->fifo_len;
1256 s->rx_len = rx;
1257 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1258 if (s->enable)
1259 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1260 s->codec_out(s->opaque, *sample);
1261 pxa2xx_i2s_update(s);
1262}
1263
1264static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base,
1265 qemu_irq irq, struct pxa2xx_dma_state_s *dma)
1266{
1267 int iomemtype;
1268 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *)
1269 qemu_mallocz(sizeof(struct pxa2xx_i2s_s));
1270
1271 s->base = base;
1272 s->irq = irq;
1273 s->dma = dma;
1274 s->data_req = pxa2xx_i2s_data_req;
1275
1276 pxa2xx_i2s_reset(s);
1277
1278 iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
1279 pxa2xx_i2s_writefn, s);
1280 cpu_register_physical_memory(s->base & 0xfff00000, 0xfffff, iomemtype);
1281
1282 return s;
1283}
1284
1285/* PXA Fast Infra-red Communications Port */
1286struct pxa2xx_fir_s {
1287 target_phys_addr_t base;
1288 qemu_irq irq;
1289 struct pxa2xx_dma_state_s *dma;
1290 int enable;
1291 CharDriverState *chr;
1292
1293 uint8_t control[3];
1294 uint8_t status[2];
1295
1296 int rx_len;
1297 int rx_start;
1298 uint8_t rx_fifo[64];
1299};
1300
1301static void pxa2xx_fir_reset(struct pxa2xx_fir_s *s)
1302{
1303 s->control[0] = 0x00;
1304 s->control[1] = 0x00;
1305 s->control[2] = 0x00;
1306 s->status[0] = 0x00;
1307 s->status[1] = 0x00;
1308 s->enable = 0;
1309}
1310
1311static inline void pxa2xx_fir_update(struct pxa2xx_fir_s *s)
1312{
1313 static const int tresh[4] = { 8, 16, 32, 0 };
1314 int intr = 0;
1315 if ((s->control[0] & (1 << 4)) && /* RXE */
1316 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1317 s->status[0] |= 1 << 4; /* RFS */
1318 else
1319 s->status[0] &= ~(1 << 4); /* RFS */
1320 if (s->control[0] & (1 << 3)) /* TXE */
1321 s->status[0] |= 1 << 3; /* TFS */
1322 else
1323 s->status[0] &= ~(1 << 3); /* TFS */
1324 if (s->rx_len)
1325 s->status[1] |= 1 << 2; /* RNE */
1326 else
1327 s->status[1] &= ~(1 << 2); /* RNE */
1328 if (s->control[0] & (1 << 4)) /* RXE */
1329 s->status[1] |= 1 << 0; /* RSY */
1330 else
1331 s->status[1] &= ~(1 << 0); /* RSY */
1332
1333 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1334 (s->status[0] & (1 << 4)); /* RFS */
1335 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1336 (s->status[0] & (1 << 3)); /* TFS */
1337 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1338 (s->status[0] & (1 << 6)); /* EOC */
1339 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1340 (s->status[0] & (1 << 1)); /* TUR */
1341 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1342
1343 pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1);
1344 pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1);
1345
1346 qemu_set_irq(s->irq, intr && s->enable);
1347}
1348
1349#define ICCR0 0x00 /* FICP Control register 0 */
1350#define ICCR1 0x04 /* FICP Control register 1 */
1351#define ICCR2 0x08 /* FICP Control register 2 */
1352#define ICDR 0x0c /* FICP Data register */
1353#define ICSR0 0x14 /* FICP Status register 0 */
1354#define ICSR1 0x18 /* FICP Status register 1 */
1355#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1356
1357static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1358{
1359 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1360 uint8_t ret;
1361 addr -= s->base;
1362
1363 switch (addr) {
1364 case ICCR0:
1365 return s->control[0];
1366 case ICCR1:
1367 return s->control[1];
1368 case ICCR2:
1369 return s->control[2];
1370 case ICDR:
1371 s->status[0] &= ~0x01;
1372 s->status[1] &= ~0x72;
1373 if (s->rx_len) {
1374 s->rx_len --;
1375 ret = s->rx_fifo[s->rx_start ++];
1376 s->rx_start &= 63;
1377 pxa2xx_fir_update(s);
1378 return ret;
1379 }
1380 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1381 break;
1382 case ICSR0:
1383 return s->status[0];
1384 case ICSR1:
1385 return s->status[1] | (1 << 3); /* TNF */
1386 case ICFOR:
1387 return s->rx_len;
1388 default:
1389 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1390 break;
1391 }
1392 return 0;
1393}
1394
1395static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1396 uint32_t value)
1397{
1398 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1399 uint8_t ch;
1400 addr -= s->base;
1401
1402 switch (addr) {
1403 case ICCR0:
1404 s->control[0] = value;
1405 if (!(value & (1 << 4))) /* RXE */
1406 s->rx_len = s->rx_start = 0;
1407 if (!(value & (1 << 3))) /* TXE */
1408 /* Nop */;
1409 s->enable = value & 1; /* ITR */
1410 if (!s->enable)
1411 s->status[0] = 0;
1412 pxa2xx_fir_update(s);
1413 break;
1414 case ICCR1:
1415 s->control[1] = value;
1416 break;
1417 case ICCR2:
1418 s->control[2] = value & 0x3f;
1419 pxa2xx_fir_update(s);
1420 break;
1421 case ICDR:
1422 if (s->control[2] & (1 << 2)) /* TXP */
1423 ch = value;
1424 else
1425 ch = ~value;
1426 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1427 qemu_chr_write(s->chr, &ch, 1);
1428 break;
1429 case ICSR0:
1430 s->status[0] &= ~(value & 0x66);
1431 pxa2xx_fir_update(s);
1432 break;
1433 case ICFOR:
1434 break;
1435 default:
1436 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1437 }
1438}
1439
1440static CPUReadMemoryFunc *pxa2xx_fir_readfn[] = {
1441 pxa2xx_fir_read,
1442 pxa2xx_fir_read,
1443 pxa2xx_fir_read,
1444};
1445
1446static CPUWriteMemoryFunc *pxa2xx_fir_writefn[] = {
1447 pxa2xx_fir_write,
1448 pxa2xx_fir_write,
1449 pxa2xx_fir_write,
1450};
1451
1452static int pxa2xx_fir_is_empty(void *opaque)
1453{
1454 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1455 return (s->rx_len < 64);
1456}
1457
1458static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1459{
1460 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1461 if (!(s->control[0] & (1 << 4))) /* RXE */
1462 return;
1463
1464 while (size --) {
1465 s->status[1] |= 1 << 4; /* EOF */
1466 if (s->rx_len >= 64) {
1467 s->status[1] |= 1 << 6; /* ROR */
1468 break;
1469 }
1470
1471 if (s->control[2] & (1 << 3)) /* RXP */
1472 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1473 else
1474 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1475 }
1476
1477 pxa2xx_fir_update(s);
1478}
1479
1480static void pxa2xx_fir_event(void *opaque, int event)
1481{
1482}
1483
1484static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base,
1485 qemu_irq irq, struct pxa2xx_dma_state_s *dma,
1486 CharDriverState *chr)
1487{
1488 int iomemtype;
1489 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *)
1490 qemu_mallocz(sizeof(struct pxa2xx_fir_s));
1491
1492 s->base = base;
1493 s->irq = irq;
1494 s->dma = dma;
1495 s->chr = chr;
1496
1497 pxa2xx_fir_reset(s);
1498
1499 iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
1500 pxa2xx_fir_writefn, s);
1501 cpu_register_physical_memory(s->base, 0xfff, iomemtype);
1502
1503 if (chr)
1504 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
1505 pxa2xx_fir_rx, pxa2xx_fir_event, s);
1506
1507 return s;
1508}
1509
1510void pxa2xx_reset(int line, int level, void *opaque)
1511{
1512 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1513 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
1514 cpu_reset(s->env);
1515 /* TODO: reset peripherals */
1516 }
1517}
1518
1519/* Initialise a PXA270 integrated chip (ARM based core). */
d95b2f8d
AZ		 1520struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
1521 DisplayState *ds, const char *revision)
c1713132
AZ		 1522{
1523 struct pxa2xx_state_s *s;
1524 struct pxa2xx_ssp_s *ssp;
c1713132
AZ		 1525 int iomemtype, i;
1526 s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
1527
4207117c
AZ		 1528 if (revision && strncmp(revision, "pxa27", 5)) {
1529 fprintf(stderr, "Machine requires a PXA27x processor.\n");
1530 exit(1);
1531 }
1532
c1713132 1533 s->env = cpu_init();
4207117c 1534 cpu_arm_set_model(s->env, revision ?: "pxa270");
c1713132 1535
d95b2f8d
AZ		 1536 /* SDRAM & Internal Memory Storage */
1537 cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
1538 sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
1539 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
1540 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM);
1541
c1713132
AZ		 1542 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
1543
1544 s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
1545
a171fe39
AZ		 1546 pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
1547 s->pic[PXA27X_PIC_OST_4_11], s->env);
1548
c1713132
AZ		 1549 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
1550
a171fe39
AZ		 1551 s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
1552
c1713132
AZ		 1553 for (i = 0; pxa270_serial[i].io_base; i ++)
1554 if (serial_hds[i])
1555 serial_mm_init(pxa270_serial[i].io_base, 2,
1556 s->pic[pxa270_serial[i].irqn], serial_hds[i], 1);
1557 else
1558 break;
1559 if (serial_hds[i])
1560 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
1561 s->dma, serial_hds[i]);
1562
a171fe39
AZ		 1563 if (ds)
1564 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
1565
c1713132
AZ		 1566 s->cm_base = 0x41300000;
1567 s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */
1568 s->clkcfg = 0x00000009; /* Turbo mode active */
1569 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
1570 pxa2xx_cm_writefn, s);
1571 cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype);
1572
1573 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
1574
1575 s->mm_base = 0x48000000;
1576 s->mm_regs[MDMRS >> 2] = 0x00020002;
1577 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
1578 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
1579 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
1580 pxa2xx_mm_writefn, s);
1581 cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype);
1582
1583 for (i = 0; pxa27x_ssp[i].io_base; i ++);
1584 s->ssp = (struct pxa2xx_ssp_s **)
1585 qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
1586 ssp = (struct pxa2xx_ssp_s *)
1587 qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
1588 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
1589 s->ssp[i] = &ssp[i];
1590 ssp[i].base = pxa27x_ssp[i].io_base;
1591 ssp[i].irq = s->pic[pxa27x_ssp[i].irqn];
1592
1593 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
1594 pxa2xx_ssp_writefn, &ssp[i]);
1595 cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
1596 }
1597
a171fe39
AZ		 1598 if (usb_enabled) {
1599 usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
1600 }
1601
1602 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
1603 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
1604
c1713132
AZ		 1605 s->rtc_base = 0x40900000;
1606 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
1607 pxa2xx_rtc_writefn, s);
1608 cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
1609 pxa2xx_rtc_reset(s);
1610
1611 s->pm_base = 0x40f00000;
1612 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
1613 pxa2xx_pm_writefn, s);
1614 cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype);
1615
1616 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
1617
1618 /* GPIO1 resets the processor */
1619 /* The handler can be overriden by board-specific code */
1620 pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
1621 return s;
1622}
1623
1624/* Initialise a PXA255 integrated chip (ARM based core). */
d95b2f8d
AZ		 1625struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
1626 DisplayState *ds)
c1713132
AZ		 1627{
1628 struct pxa2xx_state_s *s;
1629 struct pxa2xx_ssp_s *ssp;
1630 int iomemtype, i;
1631 s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
1632
1633 s->env = cpu_init();
1634 cpu_arm_set_model(s->env, "pxa255");
1635
d95b2f8d 1636 /* SDRAM & Internal Memory Storage */
a07dec22
AZ		 1637 cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
1638 qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
1639 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
1640 qemu_ram_alloc(PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
d95b2f8d 1641
c1713132
AZ		 1642 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
1643
1644 s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
1645
a171fe39
AZ		 1646 pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0], s->env);
1647
3bdd58a4 1648 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
c1713132 1649
a171fe39
AZ		 1650 s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
1651
c1713132
AZ		 1652 for (i = 0; pxa255_serial[i].io_base; i ++)
1653 if (serial_hds[i])
1654 serial_mm_init(pxa255_serial[i].io_base, 2,
1655 s->pic[pxa255_serial[i].irqn], serial_hds[i], 1);
1656 else
1657 break;
1658 if (serial_hds[i])
1659 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
1660 s->dma, serial_hds[i]);
1661
a171fe39
AZ		 1662 if (ds)
1663 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
1664
c1713132
AZ		 1665 s->cm_base = 0x41300000;
1666 s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */
1667 s->clkcfg = 0x00000009; /* Turbo mode active */
1668 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
1669 pxa2xx_cm_writefn, s);
1670 cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype);
1671
1672 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
1673
1674 s->mm_base = 0x48000000;
1675 s->mm_regs[MDMRS >> 2] = 0x00020002;
1676 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
1677 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
1678 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
1679 pxa2xx_mm_writefn, s);
1680 cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype);
1681
1682 for (i = 0; pxa255_ssp[i].io_base; i ++);
1683 s->ssp = (struct pxa2xx_ssp_s **)
1684 qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
1685 ssp = (struct pxa2xx_ssp_s *)
1686 qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
1687 for (i = 0; pxa255_ssp[i].io_base; i ++) {
1688 s->ssp[i] = &ssp[i];
1689 ssp[i].base = pxa255_ssp[i].io_base;
1690 ssp[i].irq = s->pic[pxa255_ssp[i].irqn];
1691
1692 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
1693 pxa2xx_ssp_writefn, &ssp[i]);
1694 cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
1695 }
1696
a171fe39
AZ		 1697 if (usb_enabled) {
1698 usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
1699 }
1700
1701 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
1702 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
1703
c1713132
AZ		 1704 s->rtc_base = 0x40900000;
1705 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
1706 pxa2xx_rtc_writefn, s);
1707 cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
1708 pxa2xx_rtc_reset(s);
1709
1710 s->pm_base = 0x40f00000;
1711 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
1712 pxa2xx_pm_writefn, s);
1713 cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype);
1714
1715 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
1716
1717 /* GPIO1 resets the processor */
1718 /* The handler can be overriden by board-specific code */
1719 pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
1720 return s;
1721}
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