[qemu.git] / target-i386 / exec.h

/*
 *  i386 execution defines
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include "config.h"
#include "dyngen-exec.h"

/* XXX: factorize this mess */
#ifdef TARGET_X86_64
#define TARGET_LONG_BITS 64
#else
#define TARGET_LONG_BITS 32
#endif

#include "cpu-defs.h"

/* at least 4 register variables are defined */
register struct CPUX86State *env asm(AREG0);

#ifndef CPU_NO_GLOBAL_REGS

#if TARGET_LONG_BITS > HOST_LONG_BITS

/* no registers can be used */
#define T0 (env->t0)
#define T1 (env->t1)
#define T2 (env->t2)

#else

/* XXX: use unsigned long instead of target_ulong - better code will
   be generated for 64 bit CPUs */
register target_ulong T0 asm(AREG1);
register target_ulong T1 asm(AREG2);
register target_ulong T2 asm(AREG3);

#endif /* ! (TARGET_LONG_BITS > HOST_LONG_BITS) */

#endif /* ! CPU_NO_GLOBAL_REGS */

#define A0 T2

extern FILE *logfile;
extern int loglevel;

#ifndef reg_EAX
#define EAX (env->regs[R_EAX])
#endif
#ifndef reg_ECX
#define ECX (env->regs[R_ECX])
#endif
#ifndef reg_EDX
#define EDX (env->regs[R_EDX])
#endif
#ifndef reg_EBX
#define EBX (env->regs[R_EBX])
#endif
#ifndef reg_ESP
#define ESP (env->regs[R_ESP])
#endif
#ifndef reg_EBP
#define EBP (env->regs[R_EBP])
#endif
#ifndef reg_ESI
#define ESI (env->regs[R_ESI])
#endif
#ifndef reg_EDI
#define EDI (env->regs[R_EDI])
#endif
#define EIP  (env->eip)
#define DF  (env->df)

#define CC_SRC (env->cc_src)
#define CC_DST (env->cc_dst)
#define CC_OP  (env->cc_op)

/* float macros */
#define FT0    (env->ft0)
#define ST0    (env->fpregs[env->fpstt].d)
#define ST(n)  (env->fpregs[(env->fpstt + (n)) & 7].d)
#define ST1    ST(1)

#include "cpu.h"
#include "exec-all.h"

void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
void cpu_x86_flush_tlb(CPUX86State *env, target_ulong addr);
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
                             int is_write, int mmu_idx, int is_softmmu);
void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
              void *retaddr);
void __hidden cpu_lock(void);
void __hidden cpu_unlock(void);
void do_interrupt(int intno, int is_int, int error_code,
                  target_ulong next_eip, int is_hw);
void do_interrupt_user(int intno, int is_int, int error_code,
                       target_ulong next_eip);
void raise_interrupt(int intno, int is_int, int error_code,
                     int next_eip_addend);
void raise_exception_err(int exception_index, int error_code);
void raise_exception(int exception_index);
void do_smm_enter(void);
void __hidden cpu_loop_exit(void);

void OPPROTO op_movl_eflags_T0(void);
void OPPROTO op_movl_T0_eflags(void);

/* n must be a constant to be efficient */
static inline target_long lshift(target_long x, int n)
{
    if (n >= 0)
        return x << n;
    else
        return x >> (-n);
}

#include "helper.h"

static inline void svm_check_intercept(uint32_t type)
{
    helper_svm_check_intercept_param(type, 0);
}

#if !defined(CONFIG_USER_ONLY)

#include "softmmu_exec.h"

#endif /* !defined(CONFIG_USER_ONLY) */

#ifdef USE_X86LDOUBLE
/* use long double functions */
#define floatx_to_int32 floatx80_to_int32
#define floatx_to_int64 floatx80_to_int64
#define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
#define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
#define int32_to_floatx int32_to_floatx80
#define int64_to_floatx int64_to_floatx80
#define float32_to_floatx float32_to_floatx80
#define float64_to_floatx float64_to_floatx80
#define floatx_to_float32 floatx80_to_float32
#define floatx_to_float64 floatx80_to_float64
#define floatx_abs floatx80_abs
#define floatx_chs floatx80_chs
#define floatx_round_to_int floatx80_round_to_int
#define floatx_compare floatx80_compare
#define floatx_compare_quiet floatx80_compare_quiet
#define sin sinl
#define cos cosl
#define sqrt sqrtl
#define pow powl
#define log logl
#define tan tanl
#define atan2 atan2l
#define floor floorl
#define ceil ceill
#define ldexp ldexpl
#else
#define floatx_to_int32 float64_to_int32
#define floatx_to_int64 float64_to_int64
#define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
#define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
#define int32_to_floatx int32_to_float64
#define int64_to_floatx int64_to_float64
#define float32_to_floatx float32_to_float64
#define float64_to_floatx(x, e) (x)
#define floatx_to_float32 float64_to_float32
#define floatx_to_float64(x, e) (x)
#define floatx_abs float64_abs
#define floatx_chs float64_chs
#define floatx_round_to_int float64_round_to_int
#define floatx_compare float64_compare
#define floatx_compare_quiet float64_compare_quiet
#endif

extern CPU86_LDouble sin(CPU86_LDouble x);
extern CPU86_LDouble cos(CPU86_LDouble x);
extern CPU86_LDouble sqrt(CPU86_LDouble x);
extern CPU86_LDouble pow(CPU86_LDouble, CPU86_LDouble);
extern CPU86_LDouble log(CPU86_LDouble x);
extern CPU86_LDouble tan(CPU86_LDouble x);
extern CPU86_LDouble atan2(CPU86_LDouble, CPU86_LDouble);
extern CPU86_LDouble floor(CPU86_LDouble x);
extern CPU86_LDouble ceil(CPU86_LDouble x);

#define RC_MASK         0xc00
#define RC_NEAR		0x000
#define RC_DOWN		0x400
#define RC_UP		0x800
#define RC_CHOP		0xc00

#define MAXTAN 9223372036854775808.0

#ifdef USE_X86LDOUBLE

/* only for x86 */
typedef union {
    long double d;
    struct {
        unsigned long long lower;
        unsigned short upper;
    } l;
} CPU86_LDoubleU;

/* the following deal with x86 long double-precision numbers */
#define MAXEXPD 0x7fff
#define EXPBIAS 16383
#define EXPD(fp)	(fp.l.upper & 0x7fff)
#define SIGND(fp)	((fp.l.upper) & 0x8000)
#define MANTD(fp)       (fp.l.lower)
#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS

#else

/* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
typedef union {
    double d;
#if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
    struct {
        uint32_t lower;
        int32_t upper;
    } l;
#else
    struct {
        int32_t upper;
        uint32_t lower;
    } l;
#endif
#ifndef __arm__
    int64_t ll;
#endif
} CPU86_LDoubleU;

/* the following deal with IEEE double-precision numbers */
#define MAXEXPD 0x7ff
#define EXPBIAS 1023
#define EXPD(fp)	(((fp.l.upper) >> 20) & 0x7FF)
#define SIGND(fp)	((fp.l.upper) & 0x80000000)
#ifdef __arm__
#define MANTD(fp)	(fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32))
#else
#define MANTD(fp)	(fp.ll & ((1LL << 52) - 1))
#endif
#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20)
#endif

static inline void fpush(void)
{
    env->fpstt = (env->fpstt - 1) & 7;
    env->fptags[env->fpstt] = 0; /* validate stack entry */
}

static inline void fpop(void)
{
    env->fptags[env->fpstt] = 1; /* invvalidate stack entry */
    env->fpstt = (env->fpstt + 1) & 7;
}

#ifndef USE_X86LDOUBLE
static inline CPU86_LDouble helper_fldt(target_ulong ptr)
{
    CPU86_LDoubleU temp;
    int upper, e;
    uint64_t ll;

    /* mantissa */
    upper = lduw(ptr + 8);
    /* XXX: handle overflow ? */
    e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
    e |= (upper >> 4) & 0x800; /* sign */
    ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1);
#ifdef __arm__
    temp.l.upper = (e << 20) | (ll >> 32);
    temp.l.lower = ll;
#else
    temp.ll = ll | ((uint64_t)e << 52);
#endif
    return temp.d;
}

static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
{
    CPU86_LDoubleU temp;
    int e;

    temp.d = f;
    /* mantissa */
    stq(ptr, (MANTD(temp) << 11) | (1LL << 63));
    /* exponent + sign */
    e = EXPD(temp) - EXPBIAS + 16383;
    e |= SIGND(temp) >> 16;
    stw(ptr + 8, e);
}
#else

/* we use memory access macros */

static inline CPU86_LDouble helper_fldt(target_ulong ptr)
{
    CPU86_LDoubleU temp;

    temp.l.lower = ldq(ptr);
    temp.l.upper = lduw(ptr + 8);
    return temp.d;
}

static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
{
    CPU86_LDoubleU temp;

    temp.d = f;
    stq(ptr, temp.l.lower);
    stw(ptr + 8, temp.l.upper);
}

#endif /* USE_X86LDOUBLE */

#define FPUS_IE (1 << 0)
#define FPUS_DE (1 << 1)
#define FPUS_ZE (1 << 2)
#define FPUS_OE (1 << 3)
#define FPUS_UE (1 << 4)
#define FPUS_PE (1 << 5)
#define FPUS_SF (1 << 6)
#define FPUS_SE (1 << 7)
#define FPUS_B  (1 << 15)

#define FPUC_EM 0x3f

extern const CPU86_LDouble f15rk[7];

void fpu_raise_exception(void);
void restore_native_fp_state(CPUState *env);
void save_native_fp_state(CPUState *env);

extern const uint8_t parity_table[256];
extern const uint8_t rclw_table[32];
extern const uint8_t rclb_table[32];

static inline uint32_t compute_eflags(void)
{
    return env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
}

/* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
static inline void load_eflags(int eflags, int update_mask)
{
    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
    DF = 1 - (2 * ((eflags >> 10) & 1));
    env->eflags = (env->eflags & ~update_mask) |
        (eflags & update_mask);
}

static inline void env_to_regs(void)
{
#ifdef reg_EAX
    EAX = env->regs[R_EAX];
#endif
#ifdef reg_ECX
    ECX = env->regs[R_ECX];
#endif
#ifdef reg_EDX
    EDX = env->regs[R_EDX];
#endif
#ifdef reg_EBX
    EBX = env->regs[R_EBX];
#endif
#ifdef reg_ESP
    ESP = env->regs[R_ESP];
#endif
#ifdef reg_EBP
    EBP = env->regs[R_EBP];
#endif
#ifdef reg_ESI
    ESI = env->regs[R_ESI];
#endif
#ifdef reg_EDI
    EDI = env->regs[R_EDI];
#endif
}

static inline void regs_to_env(void)
{
#ifdef reg_EAX
    env->regs[R_EAX] = EAX;
#endif
#ifdef reg_ECX
    env->regs[R_ECX] = ECX;
#endif
#ifdef reg_EDX
    env->regs[R_EDX] = EDX;
#endif
#ifdef reg_EBX
    env->regs[R_EBX] = EBX;
#endif
#ifdef reg_ESP
    env->regs[R_ESP] = ESP;
#endif
#ifdef reg_EBP
    env->regs[R_EBP] = EBP;
#endif
#ifdef reg_ESI
    env->regs[R_ESI] = ESI;
#endif
#ifdef reg_EDI
    env->regs[R_EDI] = EDI;
#endif
}

static inline int cpu_halted(CPUState *env) {
    /* handle exit of HALTED state */
    if (!(env->hflags & HF_HALTED_MASK))
        return 0;
    /* disable halt condition */
    if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
         (env->eflags & IF_MASK)) ||
        (env->interrupt_request & CPU_INTERRUPT_NMI)) {
        env->hflags &= ~HF_HALTED_MASK;
        return 0;
    }
    return EXCP_HALTED;
}
Commit	Line	Data
2c0262af	1	/*
5fafdf24	2	* i386 execution defines
2c0262af FB	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
7d3505c5	20	#include "config.h"
2c0262af FB	21	#include "dyngen-exec.h"
2c0262af FB	22
14ce26e7	23	/* XXX: factorize this mess */
14ce26e7 FB	24	#ifdef TARGET_X86_64
	25	#define TARGET_LONG_BITS 64
	26	#else
	27	#define TARGET_LONG_BITS 32
	28	#endif
	29
d785e6be FB	30	#include "cpu-defs.h"
d785e6be FB	31
0d1a29f9	32	/* at least 4 register variables are defined */
2c0262af	33	register struct CPUX86State *env asm(AREG0);
14ce26e7	34
edea5f01 FB	35	#ifndef CPU_NO_GLOBAL_REGS
edea5f01 FB	36
d785e6be FB	37	#if TARGET_LONG_BITS > HOST_LONG_BITS
	38
	39	/* no registers can be used */
	40	#define T0 (env->t0)
	41	#define T1 (env->t1)
	42	#define T2 (env->t2)
14ce26e7	43
d785e6be FB	44	#else
	45
	46	/* XXX: use unsigned long instead of target_ulong - better code will
	47	be generated for 64 bit CPUs */
	48	register target_ulong T0 asm(AREG1);
	49	register target_ulong T1 asm(AREG2);
	50	register target_ulong T2 asm(AREG3);
2c0262af	51
d785e6be	52	#endif /* ! (TARGET_LONG_BITS > HOST_LONG_BITS) */
14ce26e7	53
edea5f01 FB	54	#endif /* ! CPU_NO_GLOBAL_REGS */
edea5f01 FB	55
14ce26e7 FB	56	#define A0 T2
14ce26e7 FB	57
2c0262af FB	58	extern FILE *logfile;
	59	extern int loglevel;
	60
	61	#ifndef reg_EAX
	62	#define EAX (env->regs[R_EAX])
	63	#endif
	64	#ifndef reg_ECX
	65	#define ECX (env->regs[R_ECX])
	66	#endif
	67	#ifndef reg_EDX
	68	#define EDX (env->regs[R_EDX])
	69	#endif
	70	#ifndef reg_EBX
	71	#define EBX (env->regs[R_EBX])
	72	#endif
	73	#ifndef reg_ESP
	74	#define ESP (env->regs[R_ESP])
	75	#endif
	76	#ifndef reg_EBP
	77	#define EBP (env->regs[R_EBP])
	78	#endif
	79	#ifndef reg_ESI
	80	#define ESI (env->regs[R_ESI])
	81	#endif
	82	#ifndef reg_EDI
	83	#define EDI (env->regs[R_EDI])
	84	#endif
	85	#define EIP (env->eip)
	86	#define DF (env->df)
	87
	88	#define CC_SRC (env->cc_src)
	89	#define CC_DST (env->cc_dst)
	90	#define CC_OP (env->cc_op)
	91
	92	/* float macros */
	93	#define FT0 (env->ft0)
664e0f19 FB	94	#define ST0 (env->fpregs[env->fpstt].d)
664e0f19 FB	95	#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
2c0262af FB	96	#define ST1 ST(1)
2c0262af FB	97
2c0262af FB	98	#include "cpu.h"
	99	#include "exec-all.h"
	100
1ac157da	101	void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
14ce26e7	102	void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1ac157da	103	void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
8f091a59	104	void cpu_x86_flush_tlb(CPUX86State *env, target_ulong addr);
5fafdf24	105	int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
6ebbf390 JM	106	int is_write, int mmu_idx, int is_softmmu);
6ebbf390 JM	107	void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
61382a50	108	void *retaddr);
2c0262af FB	109	void __hidden cpu_lock(void);
2c0262af FB	110	void __hidden cpu_unlock(void);
5fafdf24	111	void do_interrupt(int intno, int is_int, int error_code,
14ce26e7	112	target_ulong next_eip, int is_hw);
5fafdf24	113	void do_interrupt_user(int intno, int is_int, int error_code,
14ce26e7	114	target_ulong next_eip);
5fafdf24	115	void raise_interrupt(int intno, int is_int, int error_code,
a8ede8ba	116	int next_eip_addend);
2c0262af FB	117	void raise_exception_err(int exception_index, int error_code);
2c0262af FB	118	void raise_exception(int exception_index);
3b21e03e	119	void do_smm_enter(void);
2c0262af	120	void __hidden cpu_loop_exit(void);
2c0262af FB	121
	122	void OPPROTO op_movl_eflags_T0(void);
	123	void OPPROTO op_movl_T0_eflags(void);
57fec1fe	124
b6abf97d FB	125	/* n must be a constant to be efficient */
	126	static inline target_long lshift(target_long x, int n)
	127	{
	128	if (n >= 0)
	129	return x << n;
	130	else
	131	return x >> (-n);
	132	}
	133
57fec1fe FB	134	#include "helper.h"
57fec1fe FB	135
b8b6a50b FB	136	static inline void svm_check_intercept(uint32_t type)
	137	{
	138	helper_svm_check_intercept_param(type, 0);
	139	}
3e25f951	140
9951bf39 FB	141	#if !defined(CONFIG_USER_ONLY)
9951bf39 FB	142
a9049a07	143	#include "softmmu_exec.h"
9951bf39	144
9951bf39 FB	145	#endif /* !defined(CONFIG_USER_ONLY) */
9951bf39 FB	146
2c0262af FB	147	#ifdef USE_X86LDOUBLE
2c0262af FB	148	/* use long double functions */
7a0e1f41 FB	149	#define floatx_to_int32 floatx80_to_int32
7a0e1f41 FB	150	#define floatx_to_int64 floatx80_to_int64
465e9838 FB	151	#define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
465e9838 FB	152	#define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
19e6c4b8 FB	153	#define int32_to_floatx int32_to_floatx80
	154	#define int64_to_floatx int64_to_floatx80
	155	#define float32_to_floatx float32_to_floatx80
	156	#define float64_to_floatx float64_to_floatx80
	157	#define floatx_to_float32 floatx80_to_float32
	158	#define floatx_to_float64 floatx80_to_float64
7a0e1f41 FB	159	#define floatx_abs floatx80_abs
	160	#define floatx_chs floatx80_chs
	161	#define floatx_round_to_int floatx80_round_to_int
8422b113 FB	162	#define floatx_compare floatx80_compare
8422b113 FB	163	#define floatx_compare_quiet floatx80_compare_quiet
2c0262af FB	164	#define sin sinl
	165	#define cos cosl
	166	#define sqrt sqrtl
	167	#define pow powl
	168	#define log logl
	169	#define tan tanl
	170	#define atan2 atan2l
	171	#define floor floorl
	172	#define ceil ceill
57e4c06e	173	#define ldexp ldexpl
7d3505c5	174	#else
7a0e1f41 FB	175	#define floatx_to_int32 float64_to_int32
7a0e1f41 FB	176	#define floatx_to_int64 float64_to_int64
465e9838 FB	177	#define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
465e9838 FB	178	#define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
19e6c4b8 FB	179	#define int32_to_floatx int32_to_float64
	180	#define int64_to_floatx int64_to_float64
	181	#define float32_to_floatx float32_to_float64
	182	#define float64_to_floatx(x, e) (x)
	183	#define floatx_to_float32 float64_to_float32
	184	#define floatx_to_float64(x, e) (x)
7a0e1f41 FB	185	#define floatx_abs float64_abs
	186	#define floatx_chs float64_chs
	187	#define floatx_round_to_int float64_round_to_int
8422b113 FB	188	#define floatx_compare float64_compare
8422b113 FB	189	#define floatx_compare_quiet float64_compare_quiet
7d3505c5	190	#endif
7a0e1f41	191
2c0262af FB	192	extern CPU86_LDouble sin(CPU86_LDouble x);
	193	extern CPU86_LDouble cos(CPU86_LDouble x);
	194	extern CPU86_LDouble sqrt(CPU86_LDouble x);
	195	extern CPU86_LDouble pow(CPU86_LDouble, CPU86_LDouble);
	196	extern CPU86_LDouble log(CPU86_LDouble x);
	197	extern CPU86_LDouble tan(CPU86_LDouble x);
	198	extern CPU86_LDouble atan2(CPU86_LDouble, CPU86_LDouble);
	199	extern CPU86_LDouble floor(CPU86_LDouble x);
	200	extern CPU86_LDouble ceil(CPU86_LDouble x);
2c0262af FB	201
	202	#define RC_MASK 0xc00
	203	#define RC_NEAR 0x000
	204	#define RC_DOWN 0x400
	205	#define RC_UP 0x800
	206	#define RC_CHOP 0xc00
	207
	208	#define MAXTAN 9223372036854775808.0
	209
2c0262af FB	210	#ifdef USE_X86LDOUBLE
	211
	212	/* only for x86 */
	213	typedef union {
	214	long double d;
	215	struct {
	216	unsigned long long lower;
	217	unsigned short upper;
	218	} l;
	219	} CPU86_LDoubleU;
	220
	221	/* the following deal with x86 long double-precision numbers */
	222	#define MAXEXPD 0x7fff
	223	#define EXPBIAS 16383
	224	#define EXPD(fp) (fp.l.upper & 0x7fff)
	225	#define SIGND(fp) ((fp.l.upper) & 0x8000)
	226	#define MANTD(fp) (fp.l.lower)
	227	#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) \| EXPBIAS
	228
	229	#else
	230
	231	/* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
	232	typedef union {
	233	double d;
	234	#if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
	235	struct {
	236	uint32_t lower;
	237	int32_t upper;
	238	} l;
	239	#else
	240	struct {
	241	int32_t upper;
	242	uint32_t lower;
	243	} l;
	244	#endif
	245	#ifndef __arm__
	246	int64_t ll;
	247	#endif
	248	} CPU86_LDoubleU;
	249
	250	/* the following deal with IEEE double-precision numbers */
	251	#define MAXEXPD 0x7ff
	252	#define EXPBIAS 1023
	253	#define EXPD(fp) (((fp.l.upper) >> 20) & 0x7FF)
	254	#define SIGND(fp) ((fp.l.upper) & 0x80000000)
	255	#ifdef __arm__
	256	#define MANTD(fp) (fp.l.lower \| ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32))
	257	#else
	258	#define MANTD(fp) (fp.ll & ((1LL << 52) - 1))
	259	#endif
	260	#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) \| (EXPBIAS << 20)
	261	#endif
	262
	263	static inline void fpush(void)
	264	{
	265	env->fpstt = (env->fpstt - 1) & 7;
	266	env->fptags[env->fpstt] = 0; /* validate stack entry */
	267	}
	268
	269	static inline void fpop(void)
	270	{
	271	env->fptags[env->fpstt] = 1; /* invvalidate stack entry */
	272	env->fpstt = (env->fpstt + 1) & 7;
	273	}
274
275	#ifndef USE_X86LDOUBLE
14ce26e7	276	static inline CPU86_LDouble helper_fldt(target_ulong ptr)
2c0262af FB	277	{
	278	CPU86_LDoubleU temp;
	279	int upper, e;
	280	uint64_t ll;
	281
	282	/* mantissa */
	283	upper = lduw(ptr + 8);
	284	/* XXX: handle overflow ? */
	285	e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
	286	e \|= (upper >> 4) & 0x800; /* sign */
	287	ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1);
	288	#ifdef __arm__
	289	temp.l.upper = (e << 20) \| (ll >> 32);
	290	temp.l.lower = ll;
	291	#else
	292	temp.ll = ll \| ((uint64_t)e << 52);
	293	#endif
	294	return temp.d;
	295	}
	296
664e0f19	297	static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
2c0262af FB	298	{
	299	CPU86_LDoubleU temp;
	300	int e;
	301
	302	temp.d = f;
	303	/* mantissa */
	304	stq(ptr, (MANTD(temp) << 11) \| (1LL << 63));
	305	/* exponent + sign */
	306	e = EXPD(temp) - EXPBIAS + 16383;
	307	e \|= SIGND(temp) >> 16;
	308	stw(ptr + 8, e);
	309	}
9951bf39 FB	310	#else
9951bf39 FB	311
9951bf39 FB	312	/* we use memory access macros */
9951bf39 FB	313
14ce26e7	314	static inline CPU86_LDouble helper_fldt(target_ulong ptr)
9951bf39 FB	315	{
	316	CPU86_LDoubleU temp;
	317
	318	temp.l.lower = ldq(ptr);
	319	temp.l.upper = lduw(ptr + 8);
	320	return temp.d;
	321	}
	322
14ce26e7	323	static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
9951bf39 FB	324	{
9951bf39 FB	325	CPU86_LDoubleU temp;
3b46e624	326
9951bf39 FB	327	temp.d = f;
	328	stq(ptr, temp.l.lower);
	329	stw(ptr + 8, temp.l.upper);
	330	}
	331
9951bf39	332	#endif /* USE_X86LDOUBLE */
2c0262af	333
2ee73ac3 FB	334	#define FPUS_IE (1 << 0)
	335	#define FPUS_DE (1 << 1)
	336	#define FPUS_ZE (1 << 2)
	337	#define FPUS_OE (1 << 3)
	338	#define FPUS_UE (1 << 4)
	339	#define FPUS_PE (1 << 5)
	340	#define FPUS_SF (1 << 6)
	341	#define FPUS_SE (1 << 7)
	342	#define FPUS_B (1 << 15)
	343
	344	#define FPUC_EM 0x3f
	345
83fb7adf	346	extern const CPU86_LDouble f15rk[7];
2c0262af	347
2ee73ac3	348	void fpu_raise_exception(void);
03857e31 FB	349	void restore_native_fp_state(CPUState *env);
03857e31 FB	350	void save_native_fp_state(CPUState *env);
2c0262af	351
83fb7adf FB	352	extern const uint8_t parity_table[256];
	353	extern const uint8_t rclw_table[32];
	354	extern const uint8_t rclb_table[32];
2c0262af FB	355
	356	static inline uint32_t compute_eflags(void)
	357	{
	358	return env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
	359	}
	360
2c0262af FB	361	/* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
	362	static inline void load_eflags(int eflags, int update_mask)
	363	{
	364	CC_SRC = eflags & (CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
	365	DF = 1 - (2 * ((eflags >> 10) & 1));
5fafdf24	366	env->eflags = (env->eflags & ~update_mask) \|
2c0262af FB	367	(eflags & update_mask);
	368	}
	369
0d1a29f9 FB	370	static inline void env_to_regs(void)
	371	{
	372	#ifdef reg_EAX
	373	EAX = env->regs[R_EAX];
	374	#endif
	375	#ifdef reg_ECX
	376	ECX = env->regs[R_ECX];
	377	#endif
	378	#ifdef reg_EDX
	379	EDX = env->regs[R_EDX];
	380	#endif
	381	#ifdef reg_EBX
	382	EBX = env->regs[R_EBX];
	383	#endif
	384	#ifdef reg_ESP
	385	ESP = env->regs[R_ESP];
	386	#endif
	387	#ifdef reg_EBP
	388	EBP = env->regs[R_EBP];
	389	#endif
	390	#ifdef reg_ESI
	391	ESI = env->regs[R_ESI];
	392	#endif
	393	#ifdef reg_EDI
	394	EDI = env->regs[R_EDI];
	395	#endif
	396	}
	397
	398	static inline void regs_to_env(void)
	399	{
	400	#ifdef reg_EAX
	401	env->regs[R_EAX] = EAX;
	402	#endif
	403	#ifdef reg_ECX
	404	env->regs[R_ECX] = ECX;
	405	#endif
	406	#ifdef reg_EDX
	407	env->regs[R_EDX] = EDX;
	408	#endif
	409	#ifdef reg_EBX
	410	env->regs[R_EBX] = EBX;
	411	#endif
	412	#ifdef reg_ESP
	413	env->regs[R_ESP] = ESP;
	414	#endif
	415	#ifdef reg_EBP
	416	env->regs[R_EBP] = EBP;
	417	#endif
	418	#ifdef reg_ESI
	419	env->regs[R_ESI] = ESI;
	420	#endif
	421	#ifdef reg_EDI
	422	env->regs[R_EDI] = EDI;
	423	#endif
	424	}
bfed01fc TS	425
	426	static inline int cpu_halted(CPUState *env) {
	427	/* handle exit of HALTED state */
d0bdf2a2	428	if (!(env->hflags & HF_HALTED_MASK))
bfed01fc TS	429	return 0;
bfed01fc TS	430	/* disable halt condition */
474ea849 AJ	431	if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
	432	(env->eflags & IF_MASK)) \|\|
	433	(env->interrupt_request & CPU_INTERRUPT_NMI)) {
bfed01fc TS	434	env->hflags &= ~HF_HALTED_MASK;
	435	return 0;
	436	}
	437	return EXCP_HALTED;
	438	}
0573fbfc	439