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1cd1031d
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1/*
2 * AHCI test cases
3 *
4 * Copyright (c) 2014 John Snow <[email protected]>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#include <stdint.h>
26#include <string.h>
27#include <stdio.h>
8840a843 28#include <getopt.h>
1cd1031d
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29#include <glib.h>
30
31#include "libqtest.h"
90e5add6 32#include "libqos/libqos-pc.h"
90fc5e09 33#include "libqos/ahci.h"
1cd1031d 34#include "libqos/pci-pc.h"
1cd1031d
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35
36#include "qemu-common.h"
37#include "qemu/host-utils.h"
38
39#include "hw/pci/pci_ids.h"
40#include "hw/pci/pci_regs.h"
41
917158dc
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42/* Test images sizes in MB */
43#define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024)
44#define TEST_IMAGE_SIZE_MB_SMALL 64
1cd1031d 45
1cd1031d 46/*** Globals ***/
1cd1031d 47static char tmp_path[] = "/tmp/qtest.XXXXXX";
cf5aa89e 48static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX";
6d9e7295 49static char mig_socket[] = "/tmp/qtest-migration.XXXXXX";
8840a843 50static bool ahci_pedantic;
b236b610 51static const char *imgfmt;
917158dc 52static unsigned test_image_size_mb;
8840a843 53
1cd1031d 54/*** Function Declarations ***/
8d5eeced 55static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
6100ddb0
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56static void ahci_test_pci_spec(AHCIQState *ahci);
57static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
8840a843 58 uint8_t offset);
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59static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
60static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
61static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset);
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62
63/*** Utilities ***/
64
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65static uint64_t mb_to_sectors(uint64_t image_size_mb)
66{
67 return (image_size_mb * 1024 * 1024) / AHCI_SECTOR_SIZE;
68}
69
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70static void string_bswap16(uint16_t *s, size_t bytes)
71{
72 g_assert_cmphex((bytes & 1), ==, 0);
73 bytes /= 2;
74
75 while (bytes--) {
76 *s = bswap16(*s);
77 s++;
78 }
79}
80
278128ab
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81/**
82 * Verify that the transfer did not corrupt our state at all.
83 */
84static void verify_state(AHCIQState *ahci)
85{
86 int i, j;
87 uint32_t ahci_fingerprint;
88 uint64_t hba_base;
89 uint64_t hba_stored;
90 AHCICommandHeader cmd;
91
92 ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID);
93 g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint);
94
95 /* If we haven't initialized, this is as much as can be validated. */
96 if (!ahci->hba_base) {
97 return;
98 }
99
100 hba_base = (uint64_t)qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
101 hba_stored = (uint64_t)(uintptr_t)ahci->hba_base;
102 g_assert_cmphex(hba_base, ==, hba_stored);
103
104 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap);
105 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP2), ==, ahci->cap2);
106
107 for (i = 0; i < 32; i++) {
108 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_FB), ==,
109 ahci->port[i].fb);
110 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_CLB), ==,
111 ahci->port[i].clb);
112 for (j = 0; j < 32; j++) {
113 ahci_get_command_header(ahci, i, j, &cmd);
114 g_assert_cmphex(cmd.prdtl, ==, ahci->port[i].prdtl[j]);
115 g_assert_cmphex(cmd.ctba, ==, ahci->port[i].ctba[j]);
116 }
117 }
118}
119
120static void ahci_migrate(AHCIQState *from, AHCIQState *to, const char *uri)
121{
122 QOSState *tmp = to->parent;
123 QPCIDevice *dev = to->dev;
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124 char *uri_local = NULL;
125
278128ab 126 if (uri == NULL) {
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127 uri_local = g_strdup_printf("%s%s", "unix:", mig_socket);
128 uri = uri_local;
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129 }
130
131 /* context will be 'to' after completion. */
132 migrate(from->parent, to->parent, uri);
133
134 /* We'd like for the AHCIState objects to still point
135 * to information specific to its specific parent
136 * instance, but otherwise just inherit the new data. */
137 memcpy(to, from, sizeof(AHCIQState));
138 to->parent = tmp;
139 to->dev = dev;
140
141 tmp = from->parent;
142 dev = from->dev;
143 memset(from, 0x00, sizeof(AHCIQState));
144 from->parent = tmp;
145 from->dev = dev;
146
147 verify_state(to);
6d9e7295 148 g_free(uri_local);
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149}
150
1cd1031d
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151/*** Test Setup & Teardown ***/
152
153/**
dd0029c0 154 * Start a Q35 machine and bookmark a handle to the AHCI device.
1cd1031d 155 */
debaaa11 156static AHCIQState *ahci_vboot(const char *cli, va_list ap)
1cd1031d 157{
dd0029c0 158 AHCIQState *s;
1cd1031d 159
dd0029c0 160 s = g_malloc0(sizeof(AHCIQState));
debaaa11 161 s->parent = qtest_pc_vboot(cli, ap);
259342d3 162 alloc_set_flags(s->parent->alloc, ALLOC_LEAK_ASSERT);
1cd1031d 163
dd0029c0 164 /* Verify that we have an AHCI device present. */
8d5eeced 165 s->dev = get_ahci_device(&s->fingerprint);
1cd1031d 166
dd0029c0 167 return s;
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168}
169
debaaa11
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170/**
171 * Start a Q35 machine and bookmark a handle to the AHCI device.
172 */
173static AHCIQState *ahci_boot(const char *cli, ...)
174{
175 AHCIQState *s;
176 va_list ap;
177
178 if (cli) {
179 va_start(ap, cli);
180 s = ahci_vboot(cli, ap);
181 va_end(ap);
182 } else {
183 cli = "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
b236b610 184 ",format=%s"
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185 " -M q35 "
186 "-device ide-hd,drive=drive0 "
187 "-global ide-hd.ver=%s";
b236b610 188 s = ahci_boot(cli, tmp_path, "testdisk", imgfmt, "version");
debaaa11
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189 }
190
191 return s;
192}
193
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194/**
195 * Clean up the PCI device, then terminate the QEMU instance.
196 */
dd0029c0 197static void ahci_shutdown(AHCIQState *ahci)
1cd1031d 198{
dd0029c0 199 QOSState *qs = ahci->parent;
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200
201 set_context(qs);
259342d3 202 ahci_clean_mem(ahci);
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203 free_ahci_device(ahci->dev);
204 g_free(ahci);
205 qtest_shutdown(qs);
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206}
207
d63b4017
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208/**
209 * Boot and fully enable the HBA device.
210 * @see ahci_boot, ahci_pci_enable and ahci_hba_enable.
211 */
debaaa11 212static AHCIQState *ahci_boot_and_enable(const char *cli, ...)
d63b4017
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213{
214 AHCIQState *ahci;
debaaa11 215 va_list ap;
34475239
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216 uint16_t buff[256];
217 uint8_t port;
d0b282a5 218 uint8_t hello;
debaaa11
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219
220 if (cli) {
221 va_start(ap, cli);
222 ahci = ahci_vboot(cli, ap);
223 va_end(ap);
224 } else {
225 ahci = ahci_boot(NULL);
226 }
d63b4017
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227
228 ahci_pci_enable(ahci);
229 ahci_hba_enable(ahci);
34475239
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230 /* Initialize test device */
231 port = ahci_port_select(ahci);
232 ahci_port_clear(ahci, port);
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233 if (is_atapi(ahci, port)) {
234 hello = CMD_PACKET_ID;
235 } else {
236 hello = CMD_IDENTIFY;
237 }
238 ahci_io(ahci, port, hello, &buff, sizeof(buff), 0);
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239
240 return ahci;
241}
242
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243/*** Specification Adherence Tests ***/
244
245/**
246 * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
247 */
6100ddb0 248static void ahci_test_pci_spec(AHCIQState *ahci)
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249{
250 uint8_t datab;
251 uint16_t data;
252 uint32_t datal;
253
254 /* Most of these bits should start cleared until we turn them on. */
6100ddb0 255 data = qpci_config_readw(ahci->dev, PCI_COMMAND);
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256 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
257 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
258 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL); /* Reserved */
259 ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */
260 ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
261 ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT); /* Reserved */
262 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
263 ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
264 ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
265 ASSERT_BIT_CLEAR(data, 0xF800); /* Reserved */
266
6100ddb0 267 data = qpci_config_readw(ahci->dev, PCI_STATUS);
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268 ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04); /* Reserved */
269 ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
270 ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST); /* must be set */
271 ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF); /* Reserved */
272 ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
273 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
274 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
275 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
276 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
277 ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
278
279 /* RID occupies the low byte, CCs occupy the high three. */
6100ddb0 280 datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION);
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281 if (ahci_pedantic) {
282 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
283 * Though in practice this is likely seldom true. */
284 ASSERT_BIT_CLEAR(datal, 0xFF);
285 }
286
287 /* BCC *must* equal 0x01. */
288 g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
289 if (PCI_SCC(datal) == 0x01) {
290 /* IDE */
291 ASSERT_BIT_SET(0x80000000, datal);
292 ASSERT_BIT_CLEAR(0x60000000, datal);
293 } else if (PCI_SCC(datal) == 0x04) {
294 /* RAID */
295 g_assert_cmphex(PCI_PI(datal), ==, 0);
296 } else if (PCI_SCC(datal) == 0x06) {
297 /* AHCI */
298 g_assert_cmphex(PCI_PI(datal), ==, 0x01);
299 } else {
300 g_assert_not_reached();
301 }
302
6100ddb0 303 datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE);
8840a843
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304 g_assert_cmphex(datab, ==, 0);
305
6100ddb0 306 datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER);
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307 g_assert_cmphex(datab, ==, 0);
308
309 /* Only the bottom 7 bits must be off. */
6100ddb0 310 datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE);
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311 ASSERT_BIT_CLEAR(datab, 0x7F);
312
313 /* BIST is optional, but the low 7 bits must always start off regardless. */
6100ddb0 314 datab = qpci_config_readb(ahci->dev, PCI_BIST);
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315 ASSERT_BIT_CLEAR(datab, 0x7F);
316
317 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
6100ddb0 318 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
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319 g_assert_cmphex(datal, ==, 0);
320
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321 qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
322 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
8840a843
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323 /* ABAR must be 32-bit, memory mapped, non-prefetchable and
324 * must be >= 512 bytes. To that end, bits 0-8 must be off. */
325 ASSERT_BIT_CLEAR(datal, 0xFF);
326
327 /* Capability list MUST be present, */
6100ddb0 328 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST);
8840a843
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329 /* But these bits are reserved. */
330 ASSERT_BIT_CLEAR(datal, ~0xFF);
331 g_assert_cmphex(datal, !=, 0);
332
333 /* Check specification adherence for capability extenstions. */
6100ddb0 334 data = qpci_config_readw(ahci->dev, datal);
8840a843 335
8d5eeced 336 switch (ahci->fingerprint) {
8840a843
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337 case AHCI_INTEL_ICH9:
338 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
339 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
340 break;
341 default:
342 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
343 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
344 }
345
346 ahci_test_pci_caps(ahci, data, (uint8_t)datal);
347
348 /* Reserved. */
6100ddb0 349 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4);
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350 g_assert_cmphex(datal, ==, 0);
351
352 /* IPIN might vary, but ILINE must be off. */
6100ddb0 353 datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE);
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354 g_assert_cmphex(datab, ==, 0);
355}
356
357/**
358 * Test PCI capabilities for AHCI specification adherence.
359 */
6100ddb0 360static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
8840a843
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361 uint8_t offset)
362{
363 uint8_t cid = header & 0xFF;
364 uint8_t next = header >> 8;
365
366 g_test_message("CID: %02x; next: %02x", cid, next);
367
368 switch (cid) {
369 case PCI_CAP_ID_PM:
370 ahci_test_pmcap(ahci, offset);
371 break;
372 case PCI_CAP_ID_MSI:
373 ahci_test_msicap(ahci, offset);
374 break;
375 case PCI_CAP_ID_SATA:
376 ahci_test_satacap(ahci, offset);
377 break;
378
379 default:
380 g_test_message("Unknown CAP 0x%02x", cid);
381 }
382
383 if (next) {
6100ddb0 384 ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next);
8840a843
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385 }
386}
387
388/**
389 * Test SATA PCI capabilitity for AHCI specification adherence.
390 */
6100ddb0 391static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset)
8840a843
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392{
393 uint16_t dataw;
394 uint32_t datal;
395
396 g_test_message("Verifying SATACAP");
397
398 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
6100ddb0 399 dataw = qpci_config_readw(ahci->dev, offset + 2);
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400 g_assert_cmphex(dataw, ==, 0x10);
401
402 /* Grab the SATACR1 register. */
6100ddb0 403 datal = qpci_config_readw(ahci->dev, offset + 4);
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404
405 switch (datal & 0x0F) {
406 case 0x04: /* BAR0 */
407 case 0x05: /* BAR1 */
408 case 0x06:
409 case 0x07:
410 case 0x08:
411 case 0x09: /* BAR5 */
412 case 0x0F: /* Immediately following SATACR1 in PCI config space. */
413 break;
414 default:
415 /* Invalid BARLOC for the Index Data Pair. */
416 g_assert_not_reached();
417 }
418
419 /* Reserved. */
420 g_assert_cmphex((datal >> 24), ==, 0x00);
421}
422
423/**
424 * Test MSI PCI capability for AHCI specification adherence.
425 */
6100ddb0 426static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset)
8840a843
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427{
428 uint16_t dataw;
429 uint32_t datal;
430
431 g_test_message("Verifying MSICAP");
432
6100ddb0 433 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS);
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434 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
435 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
436 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
437
6100ddb0 438 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO);
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439 g_assert_cmphex(datal, ==, 0);
440
441 if (dataw & PCI_MSI_FLAGS_64BIT) {
442 g_test_message("MSICAP is 64bit");
6100ddb0 443 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI);
8840a843 444 g_assert_cmphex(datal, ==, 0);
6100ddb0 445 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64);
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446 g_assert_cmphex(dataw, ==, 0);
447 } else {
448 g_test_message("MSICAP is 32bit");
6100ddb0 449 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32);
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450 g_assert_cmphex(dataw, ==, 0);
451 }
452}
453
454/**
455 * Test Power Management PCI capability for AHCI specification adherence.
456 */
6100ddb0 457static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
8840a843
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458{
459 uint16_t dataw;
460
461 g_test_message("Verifying PMCAP");
462
6100ddb0 463 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC);
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464 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
465 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
466 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
467 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
468
6100ddb0 469 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL);
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470 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
471 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
472 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
473 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
474}
475
6100ddb0 476static void ahci_test_hba_spec(AHCIQState *ahci)
c2f3029f 477{
c2f3029f 478 unsigned i;
8d5eeced 479 uint32_t reg;
c2f3029f
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480 uint32_t ports;
481 uint8_t nports_impl;
482 uint8_t maxports;
483
6100ddb0 484 g_assert(ahci != NULL);
c2f3029f
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485
486 /*
487 * Note that the AHCI spec does expect the BIOS to set up a few things:
488 * CAP.SSS - Support for staggered spin-up (t/f)
489 * CAP.SMPS - Support for mechanical presence switches (t/f)
490 * PI - Ports Implemented (1-32)
491 * PxCMD.HPCP - Hot Plug Capable Port
492 * PxCMD.MPSP - Mechanical Presence Switch Present
493 * PxCMD.CPD - Cold Presence Detection support
494 *
495 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
496 * Foreach Port Implemented:
497 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
498 * -PxCLB/U and PxFB/U are set to valid regions in memory
499 * -PxSUD is set to 1.
500 * -PxSSTS.DET is polled for presence; if detected, we continue:
501 * -PxSERR is cleared with 1's.
502 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
503 * the device is ready.
504 */
505
506 /* 1 CAP - Capabilities Register */
1a8bba4d 507 ahci->cap = ahci_rreg(ahci, AHCI_CAP);
8d5eeced 508 ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
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509
510 /* 2 GHC - Global Host Control */
1a8bba4d 511 reg = ahci_rreg(ahci, AHCI_GHC);
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512 ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
513 ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
514 ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
8d5eeced 515 if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
c2f3029f
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516 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
517 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
518 } else {
519 g_test_message("Supports AHCI/Legacy mix.");
520 ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
521 }
522
523 /* 3 IS - Interrupt Status */
1a8bba4d 524 reg = ahci_rreg(ahci, AHCI_IS);
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525 g_assert_cmphex(reg, ==, 0);
526
527 /* 4 PI - Ports Implemented */
1a8bba4d 528 ports = ahci_rreg(ahci, AHCI_PI);
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529 /* Ports Implemented must be non-zero. */
530 g_assert_cmphex(ports, !=, 0);
531 /* Ports Implemented must be <= Number of Ports. */
532 nports_impl = ctpopl(ports);
8d5eeced 533 g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
c2f3029f 534
c2f3029f
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535 /* Ports must be within the proper range. Given a mapping of SIZE,
536 * 256 bytes are used for global HBA control, and the rest is used
537 * for ports data, at 0x80 bytes each. */
8d5eeced
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538 g_assert_cmphex(ahci->barsize, >, 0);
539 maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
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540 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
541 g_assert_cmphex((reg >> maxports), ==, 0);
542
543 /* 5 AHCI Version */
1a8bba4d 544 reg = ahci_rreg(ahci, AHCI_VS);
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545 switch (reg) {
546 case AHCI_VERSION_0_95:
547 case AHCI_VERSION_1_0:
548 case AHCI_VERSION_1_1:
549 case AHCI_VERSION_1_2:
550 case AHCI_VERSION_1_3:
551 break;
552 default:
553 g_assert_not_reached();
554 }
555
556 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
1a8bba4d 557 reg = ahci_rreg(ahci, AHCI_CCCCTL);
8d5eeced 558 if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
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559 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
560 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
561 ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
562 ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
563 } else {
564 g_assert_cmphex(reg, ==, 0);
565 }
566
567 /* 7 CCC_PORTS */
1a8bba4d 568 reg = ahci_rreg(ahci, AHCI_CCCPORTS);
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569 /* Must be zeroes initially regardless of CAP.CCCS */
570 g_assert_cmphex(reg, ==, 0);
571
572 /* 8 EM_LOC */
1a8bba4d 573 reg = ahci_rreg(ahci, AHCI_EMLOC);
8d5eeced 574 if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
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575 g_assert_cmphex(reg, ==, 0);
576 }
577
578 /* 9 EM_CTL */
1a8bba4d 579 reg = ahci_rreg(ahci, AHCI_EMCTL);
8d5eeced 580 if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
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581 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
582 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
583 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
584 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
585 } else {
586 g_assert_cmphex(reg, ==, 0);
587 }
588
589 /* 10 CAP2 -- Capabilities Extended */
1a8bba4d 590 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
8d5eeced 591 ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
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592
593 /* 11 BOHC -- Bios/OS Handoff Control */
1a8bba4d 594 reg = ahci_rreg(ahci, AHCI_BOHC);
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595 g_assert_cmphex(reg, ==, 0);
596
597 /* 12 -- 23: Reserved */
598 g_test_message("Verifying HBA reserved area is empty.");
599 for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
1a8bba4d 600 reg = ahci_rreg(ahci, i);
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601 g_assert_cmphex(reg, ==, 0);
602 }
603
604 /* 24 -- 39: NVMHCI */
8d5eeced 605 if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
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606 g_test_message("Verifying HBA/NVMHCI area is empty.");
607 for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
1a8bba4d 608 reg = ahci_rreg(ahci, i);
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609 g_assert_cmphex(reg, ==, 0);
610 }
611 }
612
613 /* 40 -- 63: Vendor */
614 g_test_message("Verifying HBA/Vendor area is empty.");
615 for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
1a8bba4d 616 reg = ahci_rreg(ahci, i);
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617 g_assert_cmphex(reg, ==, 0);
618 }
619
620 /* 64 -- XX: Port Space */
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621 for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
622 if (BITSET(ports, 0x1)) {
623 g_test_message("Testing port %u for spec", i);
8d5eeced 624 ahci_test_port_spec(ahci, i);
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625 } else {
626 uint16_t j;
627 uint16_t low = AHCI_PORTS + (32 * i);
628 uint16_t high = AHCI_PORTS + (32 * (i + 1));
629 g_test_message("Asserting unimplemented port %u "
630 "(reg [%u-%u]) is empty.",
631 i, low, high - 1);
632 for (j = low; j < high; ++j) {
1a8bba4d 633 reg = ahci_rreg(ahci, j);
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634 g_assert_cmphex(reg, ==, 0);
635 }
636 }
637 }
638}
639
640/**
641 * Test the memory space for one port for specification adherence.
642 */
8d5eeced 643static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
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644{
645 uint32_t reg;
646 unsigned i;
647
648 /* (0) CLB */
1a8bba4d 649 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB);
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650 ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
651
652 /* (1) CLBU */
8d5eeced 653 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
1a8bba4d 654 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU);
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655 g_assert_cmphex(reg, ==, 0);
656 }
657
658 /* (2) FB */
1a8bba4d 659 reg = ahci_px_rreg(ahci, port, AHCI_PX_FB);
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660 ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
661
662 /* (3) FBU */
8d5eeced 663 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
1a8bba4d 664 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU);
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665 g_assert_cmphex(reg, ==, 0);
666 }
667
668 /* (4) IS */
1a8bba4d 669 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
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670 g_assert_cmphex(reg, ==, 0);
671
672 /* (5) IE */
1a8bba4d 673 reg = ahci_px_rreg(ahci, port, AHCI_PX_IE);
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674 g_assert_cmphex(reg, ==, 0);
675
676 /* (6) CMD */
1a8bba4d 677 reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD);
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678 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
679 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
680 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
681 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
682 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
683 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA); /* And RW only if CAP.SPM */
684 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE); /* RW only if CAP2.APST */
685 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
686 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
687 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE); /* RW only if CAP.SALP */
688 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP); /* RW only if CAP.SALP */
689 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
690 /* If CPDetect support does not exist, CPState must be off. */
691 if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
692 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
693 }
694 /* If MPSPresence is not set, MPSState must be off. */
695 if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
696 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
697 }
698 /* If we do not support MPS, MPSS and MPSP must be off. */
8d5eeced 699 if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
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700 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
701 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
702 }
703 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
7e7d49d6 704 if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) {
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705 ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
706 }
707 /* HPCP and ESP cannot both be active. */
708 g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
709 /* If CAP.FBSS is not set, FBSCP must not be set. */
8d5eeced 710 if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
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711 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
712 }
713
714 /* (7) RESERVED */
1a8bba4d 715 reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1);
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716 g_assert_cmphex(reg, ==, 0);
717
718 /* (8) TFD */
1a8bba4d 719 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
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720 /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
721 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
722 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
723 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
724 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
725 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
726 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
727 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
728 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
729
730 /* (9) SIG */
731 /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
732 * Even when GHC.ST is zero, the AHCI HBA may receive the initial
733 * D2H register FIS and update the signature asynchronously,
734 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
735
736 /* (10) SSTS / SCR0: SStatus */
1a8bba4d 737 reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS);
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738 ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
739 /* Even though the register should be 0 at boot, it is asynchronous and
740 * prone to change, so we cannot test any well known value. */
741
742 /* (11) SCTL / SCR2: SControl */
1a8bba4d 743 reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL);
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744 g_assert_cmphex(reg, ==, 0);
745
746 /* (12) SERR / SCR1: SError */
1a8bba4d 747 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
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748 g_assert_cmphex(reg, ==, 0);
749
750 /* (13) SACT / SCR3: SActive */
1a8bba4d 751 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
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752 g_assert_cmphex(reg, ==, 0);
753
754 /* (14) CI */
1a8bba4d 755 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
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756 g_assert_cmphex(reg, ==, 0);
757
758 /* (15) SNTF */
1a8bba4d 759 reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF);
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760 g_assert_cmphex(reg, ==, 0);
761
762 /* (16) FBS */
1a8bba4d 763 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS);
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764 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
765 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
766 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
767 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
768 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
769 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
8d5eeced 770 if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
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771 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
772 g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
773 }
774
775 /* [17 -- 27] RESERVED */
776 for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
1a8bba4d 777 reg = ahci_px_rreg(ahci, port, i);
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778 g_assert_cmphex(reg, ==, 0);
779 }
780
781 /* [28 -- 31] Vendor-Specific */
782 for (i = AHCI_PX_VS; i < 32; ++i) {
1a8bba4d 783 reg = ahci_px_rreg(ahci, port, i);
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784 if (reg) {
785 g_test_message("INFO: Vendor register %u non-empty", i);
786 }
787 }
788}
789
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790/**
791 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
792 * device we see, then read and check the response.
793 */
6100ddb0 794static void ahci_test_identify(AHCIQState *ahci)
0fa781e3 795{
0fa781e3 796 uint16_t buff[256];
ae029620 797 unsigned px;
0fa781e3 798 int rc;
122482a3 799 uint16_t sect_size;
ae029620 800 const size_t buffsize = 512;
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801
802 g_assert(ahci != NULL);
0fa781e3 803
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804 /**
805 * This serves as a bit of a tutorial on AHCI device programming:
806 *
807 * (1) Create a data buffer for the IDENTIFY response to be sent to
808 * (2) Create a Command Table buffer, where we will store the
809 * command and PRDT (Physical Region Descriptor Table)
64a5a272 810 * (3) Construct an FIS host-to-device command structure, and write it to
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811 * the top of the Command Table buffer.
812 * (4) Create one or more Physical Region Descriptors (PRDs) that describe
813 * a location in memory where data may be stored/retrieved.
814 * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
815 * (6) Each AHCI port has up to 32 command slots. Each slot contains a
816 * header that points to a Command Table buffer. Pick an unused slot
817 * and update it to point to the Command Table we have built.
818 * (7) Now: Command #n points to our Command Table, and our Command Table
819 * contains the FIS (that describes our command) and the PRDTL, which
820 * describes our buffer.
821 * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
822 * #n is ready for processing.
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823 */
824
825 /* Pick the first implemented and running port */
ae029620
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826 px = ahci_port_select(ahci);
827 g_test_message("Selected port %u for test", px);
0fa781e3 828
e83fd96b 829 /* Clear out the FIS Receive area and any pending interrupts. */
ae029620 830 ahci_port_clear(ahci, px);
0fa781e3 831
ae029620 832 /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
727be1a7 833 ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize, 0);
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834
835 /* Check serial number/version in the buffer */
836 /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
837 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
838 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
839 * as a consequence, only needs to unchunk the data on LE machines. */
840 string_bswap16(&buff[10], 20);
841 rc = memcmp(&buff[10], "testdisk ", 20);
842 g_assert_cmphex(rc, ==, 0);
843
844 string_bswap16(&buff[23], 8);
845 rc = memcmp(&buff[23], "version ", 8);
846 g_assert_cmphex(rc, ==, 0);
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JS
847
848 sect_size = le16_to_cpu(*((uint16_t *)(&buff[5])));
727be1a7 849 g_assert_cmphex(sect_size, ==, AHCI_SECTOR_SIZE);
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850}
851
bda39dc2 852static void ahci_test_io_rw_simple(AHCIQState *ahci, unsigned bufsize,
727be1a7
JS
853 uint64_t sector, uint8_t read_cmd,
854 uint8_t write_cmd)
81705ee4
JS
855{
856 uint64_t ptr;
857 uint8_t port;
81705ee4
JS
858 unsigned char *tx = g_malloc(bufsize);
859 unsigned char *rx = g_malloc0(bufsize);
860
861 g_assert(ahci != NULL);
862
863 /* Pick the first running port and clear it. */
864 port = ahci_port_select(ahci);
865 ahci_port_clear(ahci, port);
866
867 /*** Create pattern and transfer to guest ***/
868 /* Data buffer in the guest */
869 ptr = ahci_alloc(ahci, bufsize);
870 g_assert(ptr);
871
d6c403ed 872 /* Write some indicative pattern to our buffer. */
54fced03 873 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
91d0374a 874 bufwrite(ptr, tx, bufsize);
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875
876 /* Write this buffer to disk, then read it back to the DMA buffer. */
727be1a7 877 ahci_guest_io(ahci, port, write_cmd, ptr, bufsize, sector);
81705ee4 878 qmemset(ptr, 0x00, bufsize);
727be1a7 879 ahci_guest_io(ahci, port, read_cmd, ptr, bufsize, sector);
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880
881 /*** Read back the Data ***/
91d0374a 882 bufread(ptr, rx, bufsize);
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883 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
884
885 ahci_free(ahci, ptr);
886 g_free(tx);
887 g_free(rx);
888}
889
0d3e9d1f 890static uint8_t ahci_test_nondata(AHCIQState *ahci, uint8_t ide_cmd)
4e217074 891{
0d3e9d1f 892 uint8_t port;
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893
894 /* Sanitize */
0d3e9d1f
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895 port = ahci_port_select(ahci);
896 ahci_port_clear(ahci, port);
4e217074 897
b1b66c3b 898 ahci_io(ahci, port, ide_cmd, NULL, 0, 0);
0d3e9d1f
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899
900 return port;
4e217074
JS
901}
902
903static void ahci_test_flush(AHCIQState *ahci)
904{
905 ahci_test_nondata(ahci, CMD_FLUSH_CACHE);
906}
907
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908static void ahci_test_max(AHCIQState *ahci)
909{
910 RegD2HFIS *d2h = g_malloc0(0x20);
911 uint64_t nsect;
912 uint8_t port;
913 uint8_t cmd;
917158dc 914 uint64_t config_sect = mb_to_sectors(test_image_size_mb) - 1;
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915
916 if (config_sect > 0xFFFFFF) {
917 cmd = CMD_READ_MAX_EXT;
918 } else {
919 cmd = CMD_READ_MAX;
920 }
921
922 port = ahci_test_nondata(ahci, cmd);
923 memread(ahci->port[port].fb + 0x40, d2h, 0x20);
924 nsect = (uint64_t)d2h->lba_hi[2] << 40 |
925 (uint64_t)d2h->lba_hi[1] << 32 |
926 (uint64_t)d2h->lba_hi[0] << 24 |
927 (uint64_t)d2h->lba_lo[2] << 16 |
928 (uint64_t)d2h->lba_lo[1] << 8 |
929 (uint64_t)d2h->lba_lo[0];
930
931 g_assert_cmphex(nsect, ==, config_sect);
932 g_free(d2h);
933}
934
4e217074 935
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936/******************************************************************************/
937/* Test Interfaces */
938/******************************************************************************/
939
940/**
941 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
942 */
943static void test_sanity(void)
944{
dd0029c0 945 AHCIQState *ahci;
debaaa11 946 ahci = ahci_boot(NULL);
1cd1031d
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947 ahci_shutdown(ahci);
948}
949
8840a843
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950/**
951 * Ensure that the PCI configuration space for the AHCI device is in-line with
952 * the AHCI 1.3 specification for initial values.
953 */
954static void test_pci_spec(void)
955{
dd0029c0 956 AHCIQState *ahci;
debaaa11 957 ahci = ahci_boot(NULL);
6100ddb0 958 ahci_test_pci_spec(ahci);
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JS
959 ahci_shutdown(ahci);
960}
961
96d6d3ba
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962/**
963 * Engage the PCI AHCI device and sanity check the response.
964 * Perform additional PCI config space bringup for the HBA.
965 */
966static void test_pci_enable(void)
967{
dd0029c0 968 AHCIQState *ahci;
debaaa11 969 ahci = ahci_boot(NULL);
6100ddb0 970 ahci_pci_enable(ahci);
96d6d3ba
JS
971 ahci_shutdown(ahci);
972}
973
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974/**
975 * Investigate the memory mapped regions of the HBA,
976 * and test them for AHCI specification adherence.
977 */
978static void test_hba_spec(void)
979{
dd0029c0 980 AHCIQState *ahci;
c2f3029f 981
debaaa11 982 ahci = ahci_boot(NULL);
6100ddb0
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983 ahci_pci_enable(ahci);
984 ahci_test_hba_spec(ahci);
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985 ahci_shutdown(ahci);
986}
987
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988/**
989 * Engage the HBA functionality of the AHCI PCI device,
990 * and bring it into a functional idle state.
991 */
992static void test_hba_enable(void)
993{
dd0029c0 994 AHCIQState *ahci;
dbc180e5 995
debaaa11 996 ahci = ahci_boot(NULL);
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997 ahci_pci_enable(ahci);
998 ahci_hba_enable(ahci);
dbc180e5
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999 ahci_shutdown(ahci);
1000}
1001
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1002/**
1003 * Bring up the device and issue an IDENTIFY command.
1004 * Inspect the state of the HBA device and the data returned.
1005 */
1006static void test_identify(void)
1007{
dd0029c0 1008 AHCIQState *ahci;
0fa781e3 1009
debaaa11 1010 ahci = ahci_boot_and_enable(NULL);
6100ddb0 1011 ahci_test_identify(ahci);
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1012 ahci_shutdown(ahci);
1013}
1014
e0c59cc7
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1015/**
1016 * Fragmented DMA test: Perform a standard 4K DMA read/write
1017 * test, but make sure the physical regions are fragmented to
1018 * be very small, each just 32 bytes, to see how AHCI performs
1019 * with chunks defined to be much less than a sector.
1020 */
1021static void test_dma_fragmented(void)
1022{
1023 AHCIQState *ahci;
1024 AHCICommand *cmd;
1025 uint8_t px;
1026 size_t bufsize = 4096;
1027 unsigned char *tx = g_malloc(bufsize);
1028 unsigned char *rx = g_malloc0(bufsize);
e0c59cc7
JS
1029 uint64_t ptr;
1030
debaaa11 1031 ahci = ahci_boot_and_enable(NULL);
e0c59cc7
JS
1032 px = ahci_port_select(ahci);
1033 ahci_port_clear(ahci, px);
1034
1035 /* create pattern */
54fced03 1036 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
e0c59cc7
JS
1037
1038 /* Create a DMA buffer in guest memory, and write our pattern to it. */
1039 ptr = guest_alloc(ahci->parent->alloc, bufsize);
1040 g_assert(ptr);
91d0374a 1041 bufwrite(ptr, tx, bufsize);
e0c59cc7
JS
1042
1043 cmd = ahci_command_create(CMD_WRITE_DMA);
1044 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1045 ahci_command_commit(ahci, cmd, px);
1046 ahci_command_issue(ahci, cmd);
1047 ahci_command_verify(ahci, cmd);
248de4a8 1048 ahci_command_free(cmd);
e0c59cc7
JS
1049
1050 cmd = ahci_command_create(CMD_READ_DMA);
1051 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1052 ahci_command_commit(ahci, cmd, px);
1053 ahci_command_issue(ahci, cmd);
1054 ahci_command_verify(ahci, cmd);
248de4a8 1055 ahci_command_free(cmd);
e0c59cc7
JS
1056
1057 /* Read back the guest's receive buffer into local memory */
91d0374a 1058 bufread(ptr, rx, bufsize);
e0c59cc7
JS
1059 guest_free(ahci->parent->alloc, ptr);
1060
1061 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1062
1063 ahci_shutdown(ahci);
1064
1065 g_free(rx);
1066 g_free(tx);
1067}
1068
4e217074
JS
1069static void test_flush(void)
1070{
1071 AHCIQState *ahci;
1072
debaaa11 1073 ahci = ahci_boot_and_enable(NULL);
4e217074
JS
1074 ahci_test_flush(ahci);
1075 ahci_shutdown(ahci);
1076}
1077
cf5aa89e
JS
1078static void test_flush_retry(void)
1079{
1080 AHCIQState *ahci;
1081 AHCICommand *cmd;
1082 uint8_t port;
1083 const char *s;
1084
1085 prepare_blkdebug_script(debug_path, "flush_to_disk");
1086 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
b236b610 1087 "format=%s,cache=writeback,"
cf5aa89e
JS
1088 "rerror=stop,werror=stop "
1089 "-M q35 "
1090 "-device ide-hd,drive=drive0 ",
1091 debug_path,
b236b610 1092 tmp_path, imgfmt);
cf5aa89e 1093
a606ce50 1094 /* Issue Flush Command and wait for error */
cf5aa89e
JS
1095 port = ahci_port_select(ahci);
1096 ahci_port_clear(ahci, port);
1097 cmd = ahci_command_create(CMD_FLUSH_CACHE);
1098 ahci_command_commit(ahci, cmd, port);
1099 ahci_command_issue_async(ahci, cmd);
1100 qmp_eventwait("STOP");
1101
1102 /* Complete the command */
1103 s = "{'execute':'cont' }";
1104 qmp_async(s);
1105 qmp_eventwait("RESUME");
1106 ahci_command_wait(ahci, cmd);
1107 ahci_command_verify(ahci, cmd);
1108
1109 ahci_command_free(cmd);
1110 ahci_shutdown(ahci);
1111}
1112
278128ab
JS
1113/**
1114 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
1115 */
1116static void test_migrate_sanity(void)
1117{
1118 AHCIQState *src, *dst;
6d9e7295 1119 char *uri = g_strdup_printf("unix:%s", mig_socket);
278128ab
JS
1120
1121 src = ahci_boot("-m 1024 -M q35 "
b236b610 1122 "-drive if=ide,file=%s,format=%s ", tmp_path, imgfmt);
278128ab 1123 dst = ahci_boot("-m 1024 -M q35 "
b236b610
JS
1124 "-drive if=ide,file=%s,format=%s "
1125 "-incoming %s", tmp_path, imgfmt, uri);
278128ab
JS
1126
1127 ahci_migrate(src, dst, uri);
1128
1129 ahci_shutdown(src);
1130 ahci_shutdown(dst);
6d9e7295 1131 g_free(uri);
278128ab
JS
1132}
1133
88e21f94 1134/**
07a1ee79 1135 * Simple migration test: Write a pattern, migrate, then read.
88e21f94 1136 */
07a1ee79 1137static void ahci_migrate_simple(uint8_t cmd_read, uint8_t cmd_write)
88e21f94
JS
1138{
1139 AHCIQState *src, *dst;
1140 uint8_t px;
1141 size_t bufsize = 4096;
1142 unsigned char *tx = g_malloc(bufsize);
1143 unsigned char *rx = g_malloc0(bufsize);
6d9e7295 1144 char *uri = g_strdup_printf("unix:%s", mig_socket);
88e21f94
JS
1145
1146 src = ahci_boot_and_enable("-m 1024 -M q35 "
b236b610
JS
1147 "-drive if=ide,format=%s,file=%s ",
1148 imgfmt, tmp_path);
88e21f94 1149 dst = ahci_boot("-m 1024 -M q35 "
b236b610
JS
1150 "-drive if=ide,format=%s,file=%s "
1151 "-incoming %s", imgfmt, tmp_path, uri);
88e21f94
JS
1152
1153 set_context(src->parent);
1154
1155 /* initialize */
1156 px = ahci_port_select(src);
1157 ahci_port_clear(src, px);
1158
1159 /* create pattern */
d7531638 1160 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
88e21f94
JS
1161
1162 /* Write, migrate, then read. */
07a1ee79 1163 ahci_io(src, px, cmd_write, tx, bufsize, 0);
88e21f94 1164 ahci_migrate(src, dst, uri);
07a1ee79 1165 ahci_io(dst, px, cmd_read, rx, bufsize, 0);
88e21f94
JS
1166
1167 /* Verify pattern */
1168 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1169
1170 ahci_shutdown(src);
1171 ahci_shutdown(dst);
1172 g_free(rx);
1173 g_free(tx);
6d9e7295 1174 g_free(uri);
88e21f94
JS
1175}
1176
07a1ee79
JS
1177static void test_migrate_dma(void)
1178{
1179 ahci_migrate_simple(CMD_READ_DMA, CMD_WRITE_DMA);
1180}
1181
1182static void test_migrate_ncq(void)
1183{
1184 ahci_migrate_simple(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1185}
1186
189d1b61 1187/**
7f6cf5ee 1188 * Halted IO Error Test
189d1b61
JS
1189 *
1190 * Simulate an error on first write, Try to write a pattern,
1191 * Confirm the VM has stopped, resume the VM, verify command
1192 * has completed, then read back the data and verify.
1193 */
7f6cf5ee 1194static void ahci_halted_io_test(uint8_t cmd_read, uint8_t cmd_write)
189d1b61
JS
1195{
1196 AHCIQState *ahci;
1197 uint8_t port;
1198 size_t bufsize = 4096;
1199 unsigned char *tx = g_malloc(bufsize);
1200 unsigned char *rx = g_malloc0(bufsize);
189d1b61
JS
1201 uint64_t ptr;
1202 AHCICommand *cmd;
1203
1204 prepare_blkdebug_script(debug_path, "write_aio");
1205
1206 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
b236b610 1207 "format=%s,cache=writeback,"
189d1b61
JS
1208 "rerror=stop,werror=stop "
1209 "-M q35 "
1210 "-device ide-hd,drive=drive0 ",
1211 debug_path,
b236b610 1212 tmp_path, imgfmt);
189d1b61
JS
1213
1214 /* Initialize and prepare */
1215 port = ahci_port_select(ahci);
1216 ahci_port_clear(ahci, port);
1217
189d1b61 1218 /* create DMA source buffer and write pattern */
d7531638 1219 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
189d1b61
JS
1220 ptr = ahci_alloc(ahci, bufsize);
1221 g_assert(ptr);
1222 memwrite(ptr, tx, bufsize);
1223
1224 /* Attempt to write (and fail) */
7f6cf5ee 1225 cmd = ahci_guest_io_halt(ahci, port, cmd_write,
189d1b61
JS
1226 ptr, bufsize, 0);
1227
1228 /* Attempt to resume the command */
1229 ahci_guest_io_resume(ahci, cmd);
1230 ahci_free(ahci, ptr);
1231
1232 /* Read back and verify */
7f6cf5ee 1233 ahci_io(ahci, port, cmd_read, rx, bufsize, 0);
189d1b61
JS
1234 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1235
1236 /* Cleanup and go home */
1237 ahci_shutdown(ahci);
1238 g_free(rx);
1239 g_free(tx);
1240}
1241
7f6cf5ee
JS
1242static void test_halted_dma(void)
1243{
1244 ahci_halted_io_test(CMD_READ_DMA, CMD_WRITE_DMA);
1245}
1246
1247static void test_halted_ncq(void)
1248{
1249 ahci_halted_io_test(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1250}
1251
5d1cf091 1252/**
8146d7dc 1253 * IO Error Migration Test
5d1cf091
JS
1254 *
1255 * Simulate an error on first write, Try to write a pattern,
1256 * Confirm the VM has stopped, migrate, resume the VM,
1257 * verify command has completed, then read back the data and verify.
1258 */
8146d7dc 1259static void ahci_migrate_halted_io(uint8_t cmd_read, uint8_t cmd_write)
5d1cf091
JS
1260{
1261 AHCIQState *src, *dst;
1262 uint8_t port;
1263 size_t bufsize = 4096;
1264 unsigned char *tx = g_malloc(bufsize);
1265 unsigned char *rx = g_malloc0(bufsize);
5d1cf091
JS
1266 uint64_t ptr;
1267 AHCICommand *cmd;
6d9e7295 1268 char *uri = g_strdup_printf("unix:%s", mig_socket);
5d1cf091
JS
1269
1270 prepare_blkdebug_script(debug_path, "write_aio");
1271
1272 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
b236b610 1273 "format=%s,cache=writeback,"
5d1cf091
JS
1274 "rerror=stop,werror=stop "
1275 "-M q35 "
1276 "-device ide-hd,drive=drive0 ",
1277 debug_path,
b236b610 1278 tmp_path, imgfmt);
5d1cf091
JS
1279
1280 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
b236b610 1281 "format=%s,cache=writeback,"
5d1cf091
JS
1282 "rerror=stop,werror=stop "
1283 "-M q35 "
1284 "-device ide-hd,drive=drive0 "
1285 "-incoming %s",
b236b610 1286 tmp_path, imgfmt, uri);
5d1cf091
JS
1287
1288 set_context(src->parent);
1289
1290 /* Initialize and prepare */
1291 port = ahci_port_select(src);
1292 ahci_port_clear(src, port);
d7531638 1293 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
5d1cf091
JS
1294
1295 /* create DMA source buffer and write pattern */
1296 ptr = ahci_alloc(src, bufsize);
1297 g_assert(ptr);
1298 memwrite(ptr, tx, bufsize);
1299
1300 /* Write, trigger the VM to stop, migrate, then resume. */
8146d7dc 1301 cmd = ahci_guest_io_halt(src, port, cmd_write,
5d1cf091
JS
1302 ptr, bufsize, 0);
1303 ahci_migrate(src, dst, uri);
1304 ahci_guest_io_resume(dst, cmd);
1305 ahci_free(dst, ptr);
1306
1307 /* Read back */
8146d7dc 1308 ahci_io(dst, port, cmd_read, rx, bufsize, 0);
5d1cf091
JS
1309
1310 /* Verify TX and RX are identical */
1311 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1312
1313 /* Cleanup and go home. */
1314 ahci_shutdown(src);
1315 ahci_shutdown(dst);
1316 g_free(rx);
1317 g_free(tx);
6d9e7295 1318 g_free(uri);
5d1cf091
JS
1319}
1320
8146d7dc
JS
1321static void test_migrate_halted_dma(void)
1322{
1323 ahci_migrate_halted_io(CMD_READ_DMA, CMD_WRITE_DMA);
1324}
1325
1326static void test_migrate_halted_ncq(void)
1327{
1328 ahci_migrate_halted_io(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1329}
1330
a606ce50
JS
1331/**
1332 * Migration test: Try to flush, migrate, then resume.
1333 */
1334static void test_flush_migrate(void)
1335{
1336 AHCIQState *src, *dst;
1337 AHCICommand *cmd;
1338 uint8_t px;
1339 const char *s;
6d9e7295 1340 char *uri = g_strdup_printf("unix:%s", mig_socket);
a606ce50
JS
1341
1342 prepare_blkdebug_script(debug_path, "flush_to_disk");
1343
1344 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
b236b610
JS
1345 "cache=writeback,rerror=stop,werror=stop,"
1346 "format=%s "
a606ce50
JS
1347 "-M q35 "
1348 "-device ide-hd,drive=drive0 ",
b236b610 1349 debug_path, tmp_path, imgfmt);
a606ce50 1350 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
b236b610
JS
1351 "cache=writeback,rerror=stop,werror=stop,"
1352 "format=%s "
a606ce50
JS
1353 "-M q35 "
1354 "-device ide-hd,drive=drive0 "
b236b610 1355 "-incoming %s", tmp_path, imgfmt, uri);
a606ce50
JS
1356
1357 set_context(src->parent);
1358
1359 /* Issue Flush Command */
1360 px = ahci_port_select(src);
1361 ahci_port_clear(src, px);
1362 cmd = ahci_command_create(CMD_FLUSH_CACHE);
1363 ahci_command_commit(src, cmd, px);
1364 ahci_command_issue_async(src, cmd);
1365 qmp_eventwait("STOP");
1366
1367 /* Migrate over */
1368 ahci_migrate(src, dst, uri);
1369
1370 /* Complete the command */
1371 s = "{'execute':'cont' }";
1372 qmp_async(s);
1373 qmp_eventwait("RESUME");
1374 ahci_command_wait(dst, cmd);
1375 ahci_command_verify(dst, cmd);
1376
1377 ahci_command_free(cmd);
1378 ahci_shutdown(src);
1379 ahci_shutdown(dst);
6d9e7295 1380 g_free(uri);
a606ce50
JS
1381}
1382
0d3e9d1f
JS
1383static void test_max(void)
1384{
1385 AHCIQState *ahci;
1386
1387 ahci = ahci_boot_and_enable(NULL);
1388 ahci_test_max(ahci);
1389 ahci_shutdown(ahci);
1390}
1391
d31a3ebc
JS
1392static void test_reset(void)
1393{
1394 AHCIQState *ahci;
1395 int i;
1396
1397 ahci = ahci_boot(NULL);
1398 ahci_test_pci_spec(ahci);
1399 ahci_pci_enable(ahci);
1400
1401 for (i = 0; i < 2; i++) {
1402 ahci_test_hba_spec(ahci);
1403 ahci_hba_enable(ahci);
1404 ahci_test_identify(ahci);
1405 ahci_test_io_rw_simple(ahci, 4096, 0,
1406 CMD_READ_DMA_EXT,
1407 CMD_WRITE_DMA_EXT);
1408 ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR);
1409 ahci_clean_mem(ahci);
1410 }
1411
1412 ahci_shutdown(ahci);
1413}
1414
26ad0045
JS
1415static void test_ncq_simple(void)
1416{
1417 AHCIQState *ahci;
1418
1419 ahci = ahci_boot_and_enable(NULL);
1420 ahci_test_io_rw_simple(ahci, 4096, 0,
1421 READ_FPDMA_QUEUED,
1422 WRITE_FPDMA_QUEUED);
1423 ahci_shutdown(ahci);
1424}
1425
bda39dc2
JS
1426/******************************************************************************/
1427/* AHCI I/O Test Matrix Definitions */
1428
1429enum BuffLen {
1430 LEN_BEGIN = 0,
1431 LEN_SIMPLE = LEN_BEGIN,
1432 LEN_DOUBLE,
1433 LEN_LONG,
1434 LEN_SHORT,
1435 NUM_LENGTHS
1436};
1437
1438static const char *buff_len_str[NUM_LENGTHS] = { "simple", "double",
1439 "long", "short" };
1440
1441enum AddrMode {
1442 ADDR_MODE_BEGIN = 0,
1443 ADDR_MODE_LBA28 = ADDR_MODE_BEGIN,
1444 ADDR_MODE_LBA48,
1445 NUM_ADDR_MODES
1446};
1447
1448static const char *addr_mode_str[NUM_ADDR_MODES] = { "lba28", "lba48" };
1449
1450enum IOMode {
1451 MODE_BEGIN = 0,
1452 MODE_PIO = MODE_BEGIN,
1453 MODE_DMA,
1454 NUM_MODES
1455};
1456
1457static const char *io_mode_str[NUM_MODES] = { "pio", "dma" };
1458
1459enum IOOps {
1460 IO_BEGIN = 0,
1461 IO_READ = IO_BEGIN,
1462 IO_WRITE,
1463 NUM_IO_OPS
1464};
1465
727be1a7
JS
1466enum OffsetType {
1467 OFFSET_BEGIN = 0,
1468 OFFSET_ZERO = OFFSET_BEGIN,
1469 OFFSET_LOW,
1470 OFFSET_HIGH,
1471 NUM_OFFSETS
1472};
1473
1474static const char *offset_str[NUM_OFFSETS] = { "zero", "low", "high" };
1475
bda39dc2
JS
1476typedef struct AHCIIOTestOptions {
1477 enum BuffLen length;
1478 enum AddrMode address_type;
1479 enum IOMode io_type;
727be1a7 1480 enum OffsetType offset;
bda39dc2
JS
1481} AHCIIOTestOptions;
1482
727be1a7
JS
1483static uint64_t offset_sector(enum OffsetType ofst,
1484 enum AddrMode addr_type,
1485 uint64_t buffsize)
1486{
1487 uint64_t ceil;
1488 uint64_t nsectors;
1489
1490 switch (ofst) {
1491 case OFFSET_ZERO:
1492 return 0;
1493 case OFFSET_LOW:
1494 return 1;
1495 case OFFSET_HIGH:
1496 ceil = (addr_type == ADDR_MODE_LBA28) ? 0xfffffff : 0xffffffffffff;
917158dc 1497 ceil = MIN(ceil, mb_to_sectors(test_image_size_mb) - 1);
727be1a7
JS
1498 nsectors = buffsize / AHCI_SECTOR_SIZE;
1499 return ceil - nsectors + 1;
1500 default:
1501 g_assert_not_reached();
1502 }
1503}
1504
81705ee4 1505/**
bda39dc2 1506 * Table of possible I/O ATA commands given a set of enumerations.
81705ee4 1507 */
bda39dc2
JS
1508static const uint8_t io_cmds[NUM_MODES][NUM_ADDR_MODES][NUM_IO_OPS] = {
1509 [MODE_PIO] = {
1510 [ADDR_MODE_LBA28] = {
1511 [IO_READ] = CMD_READ_PIO,
1512 [IO_WRITE] = CMD_WRITE_PIO },
1513 [ADDR_MODE_LBA48] = {
1514 [IO_READ] = CMD_READ_PIO_EXT,
1515 [IO_WRITE] = CMD_WRITE_PIO_EXT }
1516 },
1517 [MODE_DMA] = {
1518 [ADDR_MODE_LBA28] = {
1519 [IO_READ] = CMD_READ_DMA,
1520 [IO_WRITE] = CMD_WRITE_DMA },
1521 [ADDR_MODE_LBA48] = {
1522 [IO_READ] = CMD_READ_DMA_EXT,
1523 [IO_WRITE] = CMD_WRITE_DMA_EXT }
1524 }
1525};
1526
1527/**
1528 * Test a Read/Write pattern using various commands, addressing modes,
1529 * transfer modes, and buffer sizes.
1530 */
1531static void test_io_rw_interface(enum AddrMode lba48, enum IOMode dma,
727be1a7 1532 unsigned bufsize, uint64_t sector)
81705ee4
JS
1533{
1534 AHCIQState *ahci;
1535
debaaa11 1536 ahci = ahci_boot_and_enable(NULL);
727be1a7 1537 ahci_test_io_rw_simple(ahci, bufsize, sector,
bda39dc2
JS
1538 io_cmds[dma][lba48][IO_READ],
1539 io_cmds[dma][lba48][IO_WRITE]);
81705ee4
JS
1540 ahci_shutdown(ahci);
1541}
1542
bda39dc2
JS
1543/**
1544 * Demultiplex the test data and invoke the actual test routine.
1545 */
1546static void test_io_interface(gconstpointer opaque)
d6c403ed 1547{
bda39dc2
JS
1548 AHCIIOTestOptions *opts = (AHCIIOTestOptions *)opaque;
1549 unsigned bufsize;
727be1a7 1550 uint64_t sector;
d6c403ed 1551
bda39dc2
JS
1552 switch (opts->length) {
1553 case LEN_SIMPLE:
1554 bufsize = 4096;
1555 break;
1556 case LEN_DOUBLE:
1557 bufsize = 8192;
1558 break;
1559 case LEN_LONG:
1560 bufsize = 4096 * 64;
1561 break;
1562 case LEN_SHORT:
1563 bufsize = 512;
1564 break;
1565 default:
1566 g_assert_not_reached();
1567 }
d6c403ed 1568
727be1a7
JS
1569 sector = offset_sector(opts->offset, opts->address_type, bufsize);
1570 test_io_rw_interface(opts->address_type, opts->io_type, bufsize, sector);
bda39dc2
JS
1571 g_free(opts);
1572 return;
d6c403ed
JS
1573}
1574
bda39dc2 1575static void create_ahci_io_test(enum IOMode type, enum AddrMode addr,
727be1a7 1576 enum BuffLen len, enum OffsetType offset)
d6c403ed 1577{
bda39dc2 1578 char *name;
917158dc 1579 AHCIIOTestOptions *opts;
bda39dc2 1580
917158dc 1581 opts = g_malloc(sizeof(AHCIIOTestOptions));
bda39dc2
JS
1582 opts->length = len;
1583 opts->address_type = addr;
1584 opts->io_type = type;
727be1a7 1585 opts->offset = offset;
bda39dc2 1586
53f77e45 1587 name = g_strdup_printf("ahci/io/%s/%s/%s/%s",
bda39dc2
JS
1588 io_mode_str[type],
1589 addr_mode_str[addr],
727be1a7
JS
1590 buff_len_str[len],
1591 offset_str[offset]);
bda39dc2 1592
917158dc
JS
1593 if ((addr == ADDR_MODE_LBA48) && (offset == OFFSET_HIGH) &&
1594 (mb_to_sectors(test_image_size_mb) <= 0xFFFFFFF)) {
1595 g_test_message("%s: skipped; test image too small", name);
1596 g_free(name);
1597 return;
1598 }
1599
53f77e45 1600 qtest_add_data_func(name, opts, test_io_interface);
bda39dc2 1601 g_free(name);
d6c403ed
JS
1602}
1603
1cd1031d
JS
1604/******************************************************************************/
1605
1606int main(int argc, char **argv)
1607{
1608 const char *arch;
1cd1031d 1609 int ret;
cf5aa89e 1610 int fd;
8840a843 1611 int c;
727be1a7 1612 int i, j, k, m;
8840a843
JS
1613
1614 static struct option long_options[] = {
1615 {"pedantic", no_argument, 0, 'p' },
1616 {0, 0, 0, 0},
1617 };
1cd1031d
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1618
1619 /* Should be first to utilize g_test functionality, So we can see errors. */
1620 g_test_init(&argc, &argv, NULL);
1621
8840a843
JS
1622 while (1) {
1623 c = getopt_long(argc, argv, "", long_options, NULL);
1624 if (c == -1) {
1625 break;
1626 }
1627 switch (c) {
1628 case -1:
1629 break;
1630 case 'p':
1631 ahci_pedantic = 1;
1632 break;
1633 default:
1634 fprintf(stderr, "Unrecognized ahci_test option.\n");
1635 g_assert_not_reached();
1636 }
1637 }
1638
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1639 /* Check architecture */
1640 arch = qtest_get_arch();
1641 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
1642 g_test_message("Skipping test for non-x86");
1643 return 0;
1644 }
1645
b236b610
JS
1646 /* Create a temporary image */
1647 fd = mkstemp(tmp_path);
1648 g_assert(fd >= 0);
917158dc
JS
1649 if (have_qemu_img()) {
1650 imgfmt = "qcow2";
1651 test_image_size_mb = TEST_IMAGE_SIZE_MB_LARGE;
1652 mkqcow2(tmp_path, TEST_IMAGE_SIZE_MB_LARGE);
1653 } else {
1654 g_test_message("QTEST_QEMU_IMG not set or qemu-img missing; "
1655 "skipping LBA48 high-sector tests");
1656 imgfmt = "raw";
1657 test_image_size_mb = TEST_IMAGE_SIZE_MB_SMALL;
1658 ret = ftruncate(fd, test_image_size_mb * 1024 * 1024);
1659 g_assert(ret == 0);
1660 }
b236b610 1661 close(fd);
1cd1031d 1662
cf5aa89e
JS
1663 /* Create temporary blkdebug instructions */
1664 fd = mkstemp(debug_path);
1665 g_assert(fd >= 0);
1666 close(fd);
1667
6d9e7295
JS
1668 /* Reserve a hollow file to use as a socket for migration tests */
1669 fd = mkstemp(mig_socket);
1670 g_assert(fd >= 0);
1671 close(fd);
1672
1cd1031d
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1673 /* Run the tests */
1674 qtest_add_func("/ahci/sanity", test_sanity);
8840a843 1675 qtest_add_func("/ahci/pci_spec", test_pci_spec);
96d6d3ba 1676 qtest_add_func("/ahci/pci_enable", test_pci_enable);
c2f3029f 1677 qtest_add_func("/ahci/hba_spec", test_hba_spec);
dbc180e5 1678 qtest_add_func("/ahci/hba_enable", test_hba_enable);
0fa781e3 1679 qtest_add_func("/ahci/identify", test_identify);
bda39dc2
JS
1680
1681 for (i = MODE_BEGIN; i < NUM_MODES; i++) {
1682 for (j = ADDR_MODE_BEGIN; j < NUM_ADDR_MODES; j++) {
1683 for (k = LEN_BEGIN; k < NUM_LENGTHS; k++) {
727be1a7
JS
1684 for (m = OFFSET_BEGIN; m < NUM_OFFSETS; m++) {
1685 create_ahci_io_test(i, j, k, m);
1686 }
bda39dc2
JS
1687 }
1688 }
1689 }
1cd1031d 1690
e0c59cc7
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1691 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented);
1692
4e217074 1693 qtest_add_func("/ahci/flush/simple", test_flush);
cf5aa89e 1694 qtest_add_func("/ahci/flush/retry", test_flush_retry);
a606ce50 1695 qtest_add_func("/ahci/flush/migrate", test_flush_migrate);
4e217074 1696
278128ab 1697 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity);
5d1cf091 1698 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma);
189d1b61 1699 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma);
5d1cf091 1700 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma);
278128ab 1701
0d3e9d1f 1702 qtest_add_func("/ahci/max", test_max);
d31a3ebc 1703 qtest_add_func("/ahci/reset", test_reset);
0d3e9d1f 1704
26ad0045 1705 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple);
07a1ee79 1706 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq);
7f6cf5ee 1707 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq);
8146d7dc 1708 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq);
26ad0045 1709
1cd1031d
JS
1710 ret = g_test_run();
1711
1712 /* Cleanup */
1713 unlink(tmp_path);
cf5aa89e 1714 unlink(debug_path);
6d9e7295 1715 unlink(mig_socket);
1cd1031d
JS
1716
1717 return ret;
1718}
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