[qemu.git] / softmmu_template.h

/*
 *  Software MMU support
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#define DATA_SIZE (1 << SHIFT)

#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#else
#error unsupported data size
#endif

#ifdef SOFTMMU_CODE_ACCESS
#define READ_ACCESS_TYPE 2
#define ADDR_READ addr_code
#else
#define READ_ACCESS_TYPE 0
#define ADDR_READ addr_read
#endif

static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                        int mmu_idx,
                                                        void *retaddr);
static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
                                              target_ulong addr,
                                              void *retaddr)
{
    DATA_TYPE res;
    int index;
    index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    env->mem_io_pc = (unsigned long)retaddr;
    if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
            && !can_do_io(env)) {
        cpu_io_recompile(env, retaddr);
    }

    env->mem_io_vaddr = addr;
#if SHIFT <= 2
    res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
    res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
#else
    res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
    res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
#endif
#endif /* SHIFT > 2 */
    return res;
}

/* handle all cases except unaligned access which span two pages */
DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                      int mmu_idx)
{
    DATA_TYPE res;
    int index;
    target_ulong tlb_addr;
    target_phys_addr_t addend;
    void *retaddr;

    /* test if there is match for unaligned or IO access */
    /* XXX: could done more in memory macro in a non portable way */
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            addend = env->iotlb[mmu_idx][index];
            res = glue(io_read, SUFFIX)(addend, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
            /* slow unaligned access (it spans two pages or IO) */
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
            res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
                                                         mmu_idx, retaddr);
        } else {
            /* unaligned/aligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
            }
#endif
            addend = env->tlb_table[mmu_idx][index].addend;
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
        tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

/* handle all unaligned cases */
static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                        int mmu_idx,
                                                        void *retaddr)
{
    DATA_TYPE res, res1, res2;
    int index, shift;
    target_phys_addr_t addend;
    target_ulong tlb_addr, addr1, addr2;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            addend = env->iotlb[mmu_idx][index];
            res = glue(io_read, SUFFIX)(addend, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* slow unaligned access (it spans two pages) */
            addr1 = addr & ~(DATA_SIZE - 1);
            addr2 = addr1 + DATA_SIZE;
            res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
                                                          mmu_idx, retaddr);
            res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
                                                          mmu_idx, retaddr);
            shift = (addr & (DATA_SIZE - 1)) * 8;
#ifdef TARGET_WORDS_BIGENDIAN
            res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
#else
            res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
#endif
            res = (DATA_TYPE)res;
        } else {
            /* unaligned/aligned access in the same page */
            addend = env->tlb_table[mmu_idx][index].addend;
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

#ifndef SOFTMMU_CODE_ACCESS

static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   void *retaddr);

static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
                                          DATA_TYPE val,
                                          target_ulong addr,
                                          void *retaddr)
{
    int index;
    index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
            && !can_do_io(env)) {
        cpu_io_recompile(env, retaddr);
    }

    env->mem_io_vaddr = addr;
    env->mem_io_pc = (unsigned long)retaddr;
#if SHIFT <= 2
    io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
#else
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
#endif
#endif /* SHIFT > 2 */
}

void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                 DATA_TYPE val,
                                                 int mmu_idx)
{
    target_phys_addr_t addend;
    target_ulong tlb_addr;
    void *retaddr;
    int index;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            addend = env->iotlb[mmu_idx][index];
            glue(io_write, SUFFIX)(addend, val, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(addr, 1, mmu_idx, retaddr);
#endif
            glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
                                                   mmu_idx, retaddr);
        } else {
            /* aligned/unaligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(addr, 1, mmu_idx, retaddr);
            }
#endif
            addend = env->tlb_table[mmu_idx][index].addend;
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(addr, 1, mmu_idx, retaddr);
#endif
        tlb_fill(addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

/* handles all unaligned cases */
static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   void *retaddr)
{
    target_phys_addr_t addend;
    target_ulong tlb_addr;
    int index, i;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            addend = env->iotlb[mmu_idx][index];
            glue(io_write, SUFFIX)(addend, val, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* XXX: not efficient, but simple */
            /* Note: relies on the fact that tlb_fill() does not remove the
             * previous page from the TLB cache.  */
            for(i = DATA_SIZE - 1; i >= 0; i--) {
#ifdef TARGET_WORDS_BIGENDIAN
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
                                          mmu_idx, retaddr);
#else
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
                                          mmu_idx, retaddr);
#endif
            }
        } else {
            /* aligned/unaligned access in the same page */
            addend = env->tlb_table[mmu_idx][index].addend;
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

#endif /* !defined(SOFTMMU_CODE_ACCESS) */

#undef READ_ACCESS_TYPE
#undef SHIFT
#undef DATA_TYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef ADDR_READ
Commit	Line	Data
b92e5a22 FB	1	/*
b92e5a22 FB	2	* Software MMU support
5fafdf24	3	*
b92e5a22 FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
b92e5a22 FB	18	*/
	19	#define DATA_SIZE (1 << SHIFT)
	20
	21	#if DATA_SIZE == 8
	22	#define SUFFIX q
61382a50	23	#define USUFFIX q
b92e5a22 FB	24	#define DATA_TYPE uint64_t
	25	#elif DATA_SIZE == 4
	26	#define SUFFIX l
61382a50	27	#define USUFFIX l
b92e5a22 FB	28	#define DATA_TYPE uint32_t
	29	#elif DATA_SIZE == 2
	30	#define SUFFIX w
61382a50	31	#define USUFFIX uw
b92e5a22 FB	32	#define DATA_TYPE uint16_t
	33	#elif DATA_SIZE == 1
	34	#define SUFFIX b
61382a50	35	#define USUFFIX ub
b92e5a22 FB	36	#define DATA_TYPE uint8_t
	37	#else
	38	#error unsupported data size
	39	#endif
	40
b769d8fe FB	41	#ifdef SOFTMMU_CODE_ACCESS
b769d8fe FB	42	#define READ_ACCESS_TYPE 2
84b7b8e7	43	#define ADDR_READ addr_code
b769d8fe FB	44	#else
b769d8fe FB	45	#define READ_ACCESS_TYPE 0
84b7b8e7	46	#define ADDR_READ addr_read
b769d8fe FB	47	#endif
b769d8fe FB	48
5fafdf24	49	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
6ebbf390	50	int mmu_idx,
61382a50	51	void *retaddr);
5fafdf24	52	static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
2e70f6ef PB	53	target_ulong addr,
2e70f6ef PB	54	void *retaddr)
b92e5a22 FB	55	{
	56	DATA_TYPE res;
	57	int index;
0f459d16 PB	58	index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
0f459d16 PB	59	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
2e70f6ef PB	60	env->mem_io_pc = (unsigned long)retaddr;
	61	if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
	62	&& !can_do_io(env)) {
	63	cpu_io_recompile(env, retaddr);
	64	}
b92e5a22	65
db8886d3	66	env->mem_io_vaddr = addr;
b92e5a22	67	#if SHIFT <= 2
a4193c8a	68	res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
b92e5a22 FB	69	#else
b92e5a22 FB	70	#ifdef TARGET_WORDS_BIGENDIAN
a4193c8a FB	71	res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
a4193c8a FB	72	res \|= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
b92e5a22	73	#else
a4193c8a FB	74	res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
a4193c8a FB	75	res \|= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
b92e5a22 FB	76	#endif
	77	#endif /* SHIFT > 2 */
	78	return res;
	79	}
	80
b92e5a22	81	/* handle all cases except unaligned access which span two pages */
d656469f FB	82	DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
d656469f FB	83	int mmu_idx)
b92e5a22 FB	84	{
b92e5a22 FB	85	DATA_TYPE res;
61382a50	86	int index;
c27004ec	87	target_ulong tlb_addr;
0f459d16	88	target_phys_addr_t addend;
b92e5a22	89	void *retaddr;
3b46e624	90
b92e5a22 FB	91	/* test if there is match for unaligned or IO access */
b92e5a22 FB	92	/* XXX: could done more in memory macro in a non portable way */
b92e5a22 FB	93	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	94	redo:
6ebbf390	95	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22	96	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	97	if (tlb_addr & ~TARGET_PAGE_MASK) {
	98	/* IO access */
	99	if ((addr & (DATA_SIZE - 1)) != 0)
	100	goto do_unaligned_access;
2e70f6ef	101	retaddr = GETPC();
0f459d16	102	addend = env->iotlb[mmu_idx][index];
2e70f6ef	103	res = glue(io_read, SUFFIX)(addend, addr, retaddr);
98699967	104	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	105	/* slow unaligned access (it spans two pages or IO) */
b92e5a22 FB	106	do_unaligned_access:
61382a50	107	retaddr = GETPC();
a64d4718	108	#ifdef ALIGNED_ONLY
6ebbf390	109	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718	110	#endif
5fafdf24	111	res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
6ebbf390	112	mmu_idx, retaddr);
b92e5a22	113	} else {
a64d4718 FB	114	/* unaligned/aligned access in the same page */
	115	#ifdef ALIGNED_ONLY
	116	if ((addr & (DATA_SIZE - 1)) != 0) {
	117	retaddr = GETPC();
6ebbf390	118	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718 FB	119	}
a64d4718 FB	120	#endif
0f459d16 PB	121	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	122	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
b92e5a22 FB	123	}
	124	} else {
	125	/* the page is not in the TLB : fill it */
61382a50	126	retaddr = GETPC();
a64d4718 FB	127	#ifdef ALIGNED_ONLY
a64d4718 FB	128	if ((addr & (DATA_SIZE - 1)) != 0)
6ebbf390	129	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718	130	#endif
6ebbf390	131	tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22 FB	132	goto redo;
	133	}
	134	return res;
	135	}
	136
	137	/* handle all unaligned cases */
5fafdf24	138	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
6ebbf390	139	int mmu_idx,
61382a50	140	void *retaddr)
b92e5a22 FB	141	{
b92e5a22 FB	142	DATA_TYPE res, res1, res2;
61382a50	143	int index, shift;
0f459d16	144	target_phys_addr_t addend;
c27004ec	145	target_ulong tlb_addr, addr1, addr2;
b92e5a22	146
b92e5a22 FB	147	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	148	redo:
6ebbf390	149	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22	150	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	151	if (tlb_addr & ~TARGET_PAGE_MASK) {
	152	/* IO access */
	153	if ((addr & (DATA_SIZE - 1)) != 0)
	154	goto do_unaligned_access;
2e70f6ef	155	retaddr = GETPC();
0f459d16	156	addend = env->iotlb[mmu_idx][index];
2e70f6ef	157	res = glue(io_read, SUFFIX)(addend, addr, retaddr);
98699967	158	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	159	do_unaligned_access:
	160	/* slow unaligned access (it spans two pages) */
	161	addr1 = addr & ~(DATA_SIZE - 1);
	162	addr2 = addr1 + DATA_SIZE;
5fafdf24	163	res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
6ebbf390	164	mmu_idx, retaddr);
5fafdf24	165	res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
6ebbf390	166	mmu_idx, retaddr);
b92e5a22 FB	167	shift = (addr & (DATA_SIZE - 1)) * 8;
	168	#ifdef TARGET_WORDS_BIGENDIAN
	169	res = (res1 << shift) \| (res2 >> ((DATA_SIZE * 8) - shift));
	170	#else
	171	res = (res1 >> shift) \| (res2 << ((DATA_SIZE * 8) - shift));
	172	#endif
6986f88c	173	res = (DATA_TYPE)res;
b92e5a22 FB	174	} else {
b92e5a22 FB	175	/* unaligned/aligned access in the same page */
0f459d16 PB	176	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	177	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
b92e5a22 FB	178	}
	179	} else {
	180	/* the page is not in the TLB : fill it */
6ebbf390	181	tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22 FB	182	goto redo;
	183	}
	184	return res;
	185	}
	186
b769d8fe FB	187	#ifndef SOFTMMU_CODE_ACCESS
b769d8fe FB	188
5fafdf24 TS	189	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
5fafdf24 TS	190	DATA_TYPE val,
6ebbf390	191	int mmu_idx,
b769d8fe FB	192	void *retaddr);
b769d8fe FB	193
5fafdf24	194	static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
b769d8fe	195	DATA_TYPE val,
0f459d16	196	target_ulong addr,
b769d8fe FB	197	void *retaddr)
	198	{
	199	int index;
0f459d16 PB	200	index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
0f459d16 PB	201	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
2e70f6ef PB	202	if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
	203	&& !can_do_io(env)) {
	204	cpu_io_recompile(env, retaddr);
	205	}
b769d8fe	206
2e70f6ef PB	207	env->mem_io_vaddr = addr;
2e70f6ef PB	208	env->mem_io_pc = (unsigned long)retaddr;
b769d8fe FB	209	#if SHIFT <= 2
	210	io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
	211	#else
	212	#ifdef TARGET_WORDS_BIGENDIAN
	213	io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
	214	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
	215	#else
	216	io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
	217	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
	218	#endif
	219	#endif /* SHIFT > 2 */
	220	}
b92e5a22	221
d656469f FB	222	void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
	223	DATA_TYPE val,
	224	int mmu_idx)
b92e5a22	225	{
0f459d16	226	target_phys_addr_t addend;
c27004ec	227	target_ulong tlb_addr;
b92e5a22	228	void *retaddr;
61382a50	229	int index;
3b46e624	230
b92e5a22 FB	231	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	232	redo:
6ebbf390	233	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22	234	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	235	if (tlb_addr & ~TARGET_PAGE_MASK) {
	236	/* IO access */
	237	if ((addr & (DATA_SIZE - 1)) != 0)
	238	goto do_unaligned_access;
d720b93d	239	retaddr = GETPC();
0f459d16 PB	240	addend = env->iotlb[mmu_idx][index];
0f459d16 PB	241	glue(io_write, SUFFIX)(addend, val, addr, retaddr);
98699967	242	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22	243	do_unaligned_access:
61382a50	244	retaddr = GETPC();
a64d4718	245	#ifdef ALIGNED_ONLY
6ebbf390	246	do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718	247	#endif
5fafdf24	248	glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
6ebbf390	249	mmu_idx, retaddr);
b92e5a22 FB	250	} else {
b92e5a22 FB	251	/* aligned/unaligned access in the same page */
a64d4718 FB	252	#ifdef ALIGNED_ONLY
	253	if ((addr & (DATA_SIZE - 1)) != 0) {
	254	retaddr = GETPC();
6ebbf390	255	do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718 FB	256	}
a64d4718 FB	257	#endif
0f459d16 PB	258	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	259	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
b92e5a22 FB	260	}
	261	} else {
	262	/* the page is not in the TLB : fill it */
61382a50	263	retaddr = GETPC();
a64d4718 FB	264	#ifdef ALIGNED_ONLY
a64d4718 FB	265	if ((addr & (DATA_SIZE - 1)) != 0)
6ebbf390	266	do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718	267	#endif
6ebbf390	268	tlb_fill(addr, 1, mmu_idx, retaddr);
b92e5a22 FB	269	goto redo;
	270	}
	271	}
	272
	273	/* handles all unaligned cases */
5fafdf24	274	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50	275	DATA_TYPE val,
6ebbf390	276	int mmu_idx,
61382a50	277	void *retaddr)
b92e5a22	278	{
0f459d16	279	target_phys_addr_t addend;
c27004ec	280	target_ulong tlb_addr;
61382a50	281	int index, i;
b92e5a22	282
b92e5a22 FB	283	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	284	redo:
6ebbf390	285	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22	286	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	287	if (tlb_addr & ~TARGET_PAGE_MASK) {
	288	/* IO access */
	289	if ((addr & (DATA_SIZE - 1)) != 0)
	290	goto do_unaligned_access;
0f459d16 PB	291	addend = env->iotlb[mmu_idx][index];
0f459d16 PB	292	glue(io_write, SUFFIX)(addend, val, addr, retaddr);
98699967	293	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	294	do_unaligned_access:
b92e5a22 FB	295	/* XXX: not efficient, but simple */
6c41b272 AZ	296	/* Note: relies on the fact that tlb_fill() does not remove the
6c41b272 AZ	297	* previous page from the TLB cache. */
7221fa98	298	for(i = DATA_SIZE - 1; i >= 0; i--) {
b92e5a22	299	#ifdef TARGET_WORDS_BIGENDIAN
5fafdf24	300	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
6ebbf390	301	mmu_idx, retaddr);
b92e5a22	302	#else
5fafdf24	303	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
6ebbf390	304	mmu_idx, retaddr);
b92e5a22 FB	305	#endif
	306	}
	307	} else {
	308	/* aligned/unaligned access in the same page */
0f459d16 PB	309	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	310	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
b92e5a22 FB	311	}
	312	} else {
	313	/* the page is not in the TLB : fill it */
6ebbf390	314	tlb_fill(addr, 1, mmu_idx, retaddr);
b92e5a22 FB	315	goto redo;
	316	}
	317	}
	318
b769d8fe FB	319	#endif /* !defined(SOFTMMU_CODE_ACCESS) */
	320
	321	#undef READ_ACCESS_TYPE
b92e5a22 FB	322	#undef SHIFT
	323	#undef DATA_TYPE
	324	#undef SUFFIX
61382a50	325	#undef USUFFIX
b92e5a22	326	#undef DATA_SIZE
84b7b8e7	327	#undef ADDR_READ