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ppc4xx_i2c: Rewrite to model hardware more closely
[qemu.git] / tcg / tcg-op.h
CommitLineData
c896fe29
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
951c6300 24
c896fe29 25#include "tcg.h"
944eea96 26#include "exec/helper-proto.h"
c017230d
RH		 27#include "exec/helper-gen.h"
28
951c6300 29/* Basic output routines. Not for general consumption. */
c896fe29 30
b7e8b17a
RH		 31void tcg_gen_op1(TCGOpcode, TCGArg);
32void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
33void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
34void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
35void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
36void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
951c6300 37
d2fd745f
RH		 38void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
39void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
40void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
41
951c6300 42static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
c896fe29 43{
ae8b75dc 44 tcg_gen_op1(opc, tcgv_i32_arg(a1));
a7812ae4
PB		 45}
46
951c6300 47static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
a7812ae4 48{
ae8b75dc 49 tcg_gen_op1(opc, tcgv_i64_arg(a1));
c896fe29
FB		 50}
51
951c6300 52static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
c896fe29 53{
b7e8b17a 54 tcg_gen_op1(opc, a1);
c896fe29
FB		 55}
56
951c6300 57static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
a7812ae4 58{
ae8b75dc 59 tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2));
a7812ae4
PB		 60}
61
951c6300 62static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
a7812ae4 63{
ae8b75dc 64 tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2));
a7812ae4
PB		 65}
66
951c6300 67static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
c896fe29 68{
ae8b75dc 69 tcg_gen_op2(opc, tcgv_i32_arg(a1), a2);
c896fe29
FB		 70}
71
951c6300 72static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
c896fe29 73{
ae8b75dc 74 tcg_gen_op2(opc, tcgv_i64_arg(a1), a2);
ac56dd48
PB		 75}
76
951c6300 77static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
bcb0126f 78{
b7e8b17a 79 tcg_gen_op2(opc, a1, a2);
bcb0126f
PB		 80}
81
951c6300
RH		 82static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
83 TCGv_i32 a2, TCGv_i32 a3)
a7812ae4 84{
ae8b75dc 85 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3));
a7812ae4
PB		 86}
87
951c6300
RH		 88static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
89 TCGv_i64 a2, TCGv_i64 a3)
a7812ae4 90{
ae8b75dc 91 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3));
a7812ae4
PB		 92}
93
951c6300
RH		 94static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
95 TCGv_i32 a2, TCGArg a3)
ac56dd48 96{
ae8b75dc 97 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3);
ac56dd48
PB		 98}
99
951c6300
RH		 100static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
101 TCGv_i64 a2, TCGArg a3)
ac56dd48 102{
ae8b75dc 103 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3);
ac56dd48
PB		 104}
105
a9751609
RH		 106static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
107 TCGv_ptr base, TCGArg offset)
a7812ae4 108{
ae8b75dc 109 tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset);
a7812ae4
PB		 110}
111
a9751609
RH		 112static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
113 TCGv_ptr base, TCGArg offset)
a7812ae4 114{
ae8b75dc 115 tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset);
a7812ae4
PB		 116}
117
951c6300
RH		 118static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
119 TCGv_i32 a3, TCGv_i32 a4)
a7812ae4 120{
ae8b75dc
RH		 121 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
122 tcgv_i32_arg(a3), tcgv_i32_arg(a4));
a7812ae4
PB		 123}
124
951c6300
RH		 125static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
126 TCGv_i64 a3, TCGv_i64 a4)
a7812ae4 127{
ae8b75dc
RH		 128 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
129 tcgv_i64_arg(a3), tcgv_i64_arg(a4));
a7812ae4
PB		 130}
131
951c6300
RH		 132static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
133 TCGv_i32 a3, TCGArg a4)
a7812ae4 134{
ae8b75dc
RH		 135 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
136 tcgv_i32_arg(a3), a4);
a7812ae4
PB		 137}
138
951c6300
RH		 139static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
140 TCGv_i64 a3, TCGArg a4)
ac56dd48 141{
ae8b75dc
RH		 142 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
143 tcgv_i64_arg(a3), a4);
ac56dd48
PB		 144}
145
951c6300
RH		 146static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
147 TCGArg a3, TCGArg a4)
ac56dd48 148{
ae8b75dc 149 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4);
c896fe29
FB		 150}
151
951c6300
RH		 152static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
153 TCGArg a3, TCGArg a4)
c896fe29 154{
ae8b75dc 155 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4);
ac56dd48
PB		 156}
157
951c6300
RH		 158static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
159 TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
a7812ae4 160{
ae8b75dc
RH		 161 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
162 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5));
a7812ae4
PB		 163}
164
951c6300
RH		 165static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
166 TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
a7812ae4 167{
ae8b75dc
RH		 168 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
169 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5));
a7812ae4
PB		 170}
171
951c6300
RH		 172static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
173 TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
ac56dd48 174{
ae8b75dc
RH		 175 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
176 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5);
ac56dd48
PB		 177}
178
951c6300
RH		 179static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
180 TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
ac56dd48 181{
ae8b75dc
RH		 182 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
183 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5);
c896fe29
FB		 184}
185
951c6300
RH		 186static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
187 TCGv_i32 a3, TCGArg a4, TCGArg a5)
b7767f0f 188{
ae8b75dc
RH		 189 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
190 tcgv_i32_arg(a3), a4, a5);
b7767f0f
RH		 191}
192
951c6300
RH		 193static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
194 TCGv_i64 a3, TCGArg a4, TCGArg a5)
b7767f0f 195{
ae8b75dc
RH		 196 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
197 tcgv_i64_arg(a3), a4, a5);
b7767f0f
RH		 198}
199
951c6300
RH		 200static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
201 TCGv_i32 a3, TCGv_i32 a4,
202 TCGv_i32 a5, TCGv_i32 a6)
a7812ae4 203{
ae8b75dc
RH		 204 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
205 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5),
206 tcgv_i32_arg(a6));
a7812ae4
PB		 207}
208
951c6300
RH		 209static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
210 TCGv_i64 a3, TCGv_i64 a4,
211 TCGv_i64 a5, TCGv_i64 a6)
c896fe29 212{
ae8b75dc
RH		 213 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
214 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5),
215 tcgv_i64_arg(a6));
ac56dd48
PB		 216}
217
951c6300
RH		 218static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
219 TCGv_i32 a3, TCGv_i32 a4,
220 TCGv_i32 a5, TCGArg a6)
be210acb 221{
ae8b75dc
RH		 222 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
223 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6);
be210acb
RH		 224}
225
951c6300
RH		 226static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
227 TCGv_i64 a3, TCGv_i64 a4,
228 TCGv_i64 a5, TCGArg a6)
be210acb 229{
ae8b75dc
RH		 230 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
231 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6);
be210acb
RH		 232}
233
951c6300
RH		 234static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
235 TCGv_i32 a3, TCGv_i32 a4,
236 TCGArg a5, TCGArg a6)
ac56dd48 237{
ae8b75dc
RH		 238 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
239 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6);
a7812ae4
PB		 240}
241
951c6300
RH		 242static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
243 TCGv_i64 a3, TCGv_i64 a4,
244 TCGArg a5, TCGArg a6)
a7812ae4 245{
ae8b75dc
RH		 246 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
247 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6);
c896fe29
FB		 248}
249
f713d6ad 250
951c6300
RH		 251/* Generic ops. */
252
42a268c2 253static inline void gen_set_label(TCGLabel *l)
c896fe29 254{
b7e8b17a 255 tcg_gen_op1(INDEX_op_set_label, label_arg(l));
c896fe29
FB		 256}
257
42a268c2 258static inline void tcg_gen_br(TCGLabel *l)
fb50d413 259{
b7e8b17a 260 tcg_gen_op1(INDEX_op_br, label_arg(l));
951c6300
RH		 261}
262
f65e19bc
PK		 263void tcg_gen_mb(TCGBar);
264
951c6300
RH		 265/* Helper calls. */
266
267/* 32 bit ops */
268
269void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
270void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
271void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
474b2e8f 272void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300
RH		 273void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
274void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
474b2e8f
RH		 275void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
276void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
277void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300
RH		 278void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
279void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
280void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
281void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
282void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
283void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
284void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
285void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
286void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
287void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
0e28d006
RH		 288void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
289void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
290void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
291void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
086920c2 292void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg);
a768e4e9 293void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2);
951c6300
RH		 294void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
295void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
296void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
297void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
298void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
299 unsigned int ofs, unsigned int len);
07cc68d5
RH		 300void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
301 unsigned int ofs, unsigned int len);
7ec8bab3
RH		 302void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
303 unsigned int ofs, unsigned int len);
304void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
305 unsigned int ofs, unsigned int len);
42a268c2
RH		 306void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
307void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
951c6300
RH		 308void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
309 TCGv_i32 arg1, TCGv_i32 arg2);
310void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
311 TCGv_i32 arg1, int32_t arg2);
312void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
313 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2);
314void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
315 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
316void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
317 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
318void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
319void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
5087abfb 320void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
951c6300
RH		 321void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg);
322void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg);
323void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg);
324void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg);
325void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg);
326void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
b87fb8cd
RH		 327void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
328void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
329void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
330void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
951c6300
RH		 331
332static inline void tcg_gen_discard_i32(TCGv_i32 arg)
333{
334 tcg_gen_op1_i32(INDEX_op_discard, arg);
fb50d413
BS		 335}
336
a7812ae4 337static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 338{
11f4e8f8 339 if (ret != arg) {
a7812ae4 340 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
951c6300 341 }
c896fe29
FB		 342}
343
a7812ae4 344static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
c896fe29 345{
a7812ae4 346 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
c896fe29
FB		 347}
348
951c6300
RH		 349static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2,
350 tcg_target_long offset)
c896fe29 351{
a7812ae4 352 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
c896fe29
FB		 353}
354
951c6300
RH		 355static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2,
356 tcg_target_long offset)
c896fe29 357{
a7812ae4 358 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
c896fe29
FB		 359}
360
951c6300
RH		 361static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2,
362 tcg_target_long offset)
c896fe29 363{
a7812ae4 364 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
c896fe29
FB		 365}
366
951c6300
RH		 367static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2,
368 tcg_target_long offset)
c896fe29 369{
a7812ae4 370 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
c896fe29
FB		 371}
372
951c6300
RH		 373static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2,
374 tcg_target_long offset)
c896fe29 375{
a7812ae4 376 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
c896fe29
FB		 377}
378
951c6300
RH		 379static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2,
380 tcg_target_long offset)
c896fe29 381{
a7812ae4 382 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
c896fe29
FB		 383}
384
951c6300
RH		 385static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2,
386 tcg_target_long offset)
c896fe29 387{
a7812ae4 388 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
c896fe29
FB		 389}
390
951c6300
RH		 391static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2,
392 tcg_target_long offset)
c896fe29 393{
a7812ae4 394 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
c896fe29
FB		 395}
396
a7812ae4 397static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 398{
a7812ae4 399 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
c896fe29
FB		 400}
401
a7812ae4 402static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 403{
a7812ae4 404 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
c896fe29
FB		 405}
406
a7812ae4 407static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 408{
951c6300 409 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
c896fe29
FB		 410}
411
a7812ae4 412static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 413{
951c6300 414 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
c896fe29
FB		 415}
416
a7812ae4 417static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 418{
951c6300 419 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
c896fe29
FB		 420}
421
a7812ae4 422static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 423{
a7812ae4 424 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
c896fe29
FB		 425}
426
a7812ae4 427static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 428{
a7812ae4 429 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
c896fe29
FB		 430}
431
a7812ae4 432static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 433{
a7812ae4 434 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
c896fe29
FB		 435}
436
a7812ae4 437static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 438{
a7812ae4 439 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
c896fe29
FB		 440}
441
951c6300 442static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 443{
951c6300
RH		 444 if (TCG_TARGET_HAS_neg_i32) {
445 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
25c4d9cc 446 } else {
951c6300 447 tcg_gen_subfi_i32(ret, 0, arg);
25c4d9cc 448 }
31d66551
AJ		 449}
450
951c6300 451static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
31d66551 452{
951c6300
RH		 453 if (TCG_TARGET_HAS_not_i32) {
454 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
25c4d9cc 455 } else {
951c6300 456 tcg_gen_xori_i32(ret, arg, -1);
25c4d9cc 457 }
31d66551
AJ		 458}
459
951c6300
RH		 460/* 64 bit ops */
461
462void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
463void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
464void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474b2e8f 465void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300
RH		 466void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
467void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474b2e8f
RH		 468void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
469void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
470void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300
RH		 471void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
472void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
473void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
474void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
475void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
476void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
477void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
478void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
479void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
480void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
0e28d006
RH		 481void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
482void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
483void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
484void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
086920c2 485void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg);
a768e4e9 486void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2);
951c6300
RH		 487void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
488void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
489void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
490void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
491void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
492 unsigned int ofs, unsigned int len);
07cc68d5
RH		 493void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
494 unsigned int ofs, unsigned int len);
7ec8bab3
RH		 495void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
496 unsigned int ofs, unsigned int len);
497void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
498 unsigned int ofs, unsigned int len);
42a268c2
RH		 499void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
500void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
951c6300
RH		 501void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
502 TCGv_i64 arg1, TCGv_i64 arg2);
503void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
504 TCGv_i64 arg1, int64_t arg2);
505void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
506 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2);
507void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
508 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
509void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
510 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
511void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
512void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
5087abfb 513void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
951c6300
RH		 514void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg);
515void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg);
516void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg);
517void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg);
518void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg);
519void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg);
520void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg);
521void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg);
522void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg);
523void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
b87fb8cd
RH		 524void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
525void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
526void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
527void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
c896fe29 528
951c6300
RH		 529#if TCG_TARGET_REG_BITS == 64
530static inline void tcg_gen_discard_i64(TCGv_i64 arg)
531{
532 tcg_gen_op1_i64(INDEX_op_discard, arg);
533}
c896fe29 534
a7812ae4 535static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 536{
11f4e8f8 537 if (ret != arg) {
951c6300 538 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
4d07272d 539 }
c896fe29
FB		 540}
541
a7812ae4 542static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
c896fe29 543{
951c6300 544 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
c896fe29
FB		 545}
546
a7812ae4
PB		 547static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
548 tcg_target_long offset)
c896fe29 549{
951c6300 550 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
c896fe29
FB		 551}
552
a7812ae4
PB		 553static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
554 tcg_target_long offset)
c896fe29 555{
951c6300 556 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
c896fe29
FB		 557}
558
a7812ae4
PB		 559static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
560 tcg_target_long offset)
c896fe29 561{
951c6300 562 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
c896fe29
FB		 563}
564
a7812ae4
PB		 565static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
566 tcg_target_long offset)
c896fe29 567{
951c6300 568 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
c896fe29
FB		 569}
570
a7812ae4
PB		 571static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
572 tcg_target_long offset)
c896fe29 573{
951c6300 574 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
c896fe29
FB		 575}
576
a7812ae4
PB		 577static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
578 tcg_target_long offset)
c896fe29 579{
951c6300 580 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
c896fe29
FB		 581}
582
a7812ae4
PB		 583static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
584 tcg_target_long offset)
c896fe29 585{
951c6300 586 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
c896fe29
FB		 587}
588
a7812ae4
PB		 589static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
590 tcg_target_long offset)
c896fe29 591{
951c6300 592 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
c896fe29
FB		 593}
594
a7812ae4
PB		 595static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
596 tcg_target_long offset)
c896fe29 597{
951c6300 598 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
c896fe29
FB		 599}
600
a7812ae4
PB		 601static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
602 tcg_target_long offset)
c896fe29 603{
951c6300 604 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
c896fe29
FB		 605}
606
a7812ae4
PB		 607static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
608 tcg_target_long offset)
c896fe29 609{
951c6300 610 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
c896fe29
FB		 611}
612
a7812ae4 613static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 614{
951c6300 615 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
c896fe29
FB		 616}
617
a7812ae4 618static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 619{
951c6300 620 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
c896fe29
FB		 621}
622
a7812ae4 623static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 624{
951c6300 625 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
c896fe29
FB		 626}
627
a7812ae4 628static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 629{
951c6300 630 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
c896fe29
FB		 631}
632
a7812ae4 633static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 634{
951c6300 635 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
c896fe29
FB		 636}
637
a7812ae4 638static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 639{
951c6300 640 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
c896fe29
FB		 641}
642
a7812ae4 643static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 644{
951c6300 645 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
c896fe29
FB		 646}
647
a7812ae4 648static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 649{
951c6300 650 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
5105c556
AJ		 651}
652
a7812ae4 653static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 654{
951c6300 655 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
c896fe29 656}
951c6300
RH		 657#else /* TCG_TARGET_REG_BITS == 32 */
658static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
659 tcg_target_long offset)
c896fe29 660{
951c6300 661 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 662}
663
951c6300
RH		 664static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
665 tcg_target_long offset)
c896fe29 666{
951c6300 667 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 668}
669
951c6300
RH		 670static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
671 tcg_target_long offset)
c896fe29 672{
951c6300 673 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 674}
675
951c6300 676static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 677{
951c6300
RH		 678 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
679 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
c896fe29
FB		 680}
681
951c6300 682static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 683{
951c6300
RH		 684 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
685 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
686}
687
688void tcg_gen_discard_i64(TCGv_i64 arg);
689void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg);
690void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg);
691void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
692void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
693void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
694void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
695void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
696void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
697void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
698void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
699void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
700void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
701void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
702void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
703void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
704void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
705void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
706#endif /* TCG_TARGET_REG_BITS */
c896fe29 707
951c6300 708static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 709{
951c6300
RH		 710 if (TCG_TARGET_HAS_neg_i64) {
711 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
712 } else {
713 tcg_gen_subfi_i64(ret, 0, arg);
714 }
c896fe29
FB		 715}
716
951c6300 717/* Size changing operations. */
c896fe29 718
951c6300
RH		 719void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
720void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
721void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high);
609ad705
RH		 722void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
723void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
951c6300
RH		 724void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg);
725void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg);
c896fe29 726
951c6300 727static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
c896fe29 728{
951c6300 729 tcg_gen_deposit_i64(ret, lo, hi, 32, 32);
c896fe29
FB		 730}
731
951c6300 732/* QEMU specific operations. */
c896fe29 733
951c6300
RH		 734#ifndef TARGET_LONG_BITS
735#error must include QEMU headers
736#endif
c896fe29 737
9aef40ed
RH		 738#if TARGET_INSN_START_WORDS == 1
739# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
740static inline void tcg_gen_insn_start(target_ulong pc)
c896fe29 741{
b7e8b17a 742 tcg_gen_op1(INDEX_op_insn_start, pc);
9aef40ed
RH		 743}
744# else
745static inline void tcg_gen_insn_start(target_ulong pc)
746{
b7e8b17a 747 tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32));
9aef40ed
RH		 748}
749# endif
750#elif TARGET_INSN_START_WORDS == 2
751# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
752static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
753{
b7e8b17a 754 tcg_gen_op2(INDEX_op_insn_start, pc, a1);
9aef40ed
RH		 755}
756# else
757static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
758{
b7e8b17a 759 tcg_gen_op4(INDEX_op_insn_start,
9aef40ed
RH		 760 (uint32_t)pc, (uint32_t)(pc >> 32),
761 (uint32_t)a1, (uint32_t)(a1 >> 32));
762}
763# endif
764#elif TARGET_INSN_START_WORDS == 3
765# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
766static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
767 target_ulong a2)
768{
b7e8b17a 769 tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2);
9aef40ed
RH		 770}
771# else
772static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
773 target_ulong a2)
774{
b7e8b17a 775 tcg_gen_op6(INDEX_op_insn_start,
9aef40ed
RH		 776 (uint32_t)pc, (uint32_t)(pc >> 32),
777 (uint32_t)a1, (uint32_t)(a1 >> 32),
778 (uint32_t)a2, (uint32_t)(a2 >> 32));
779}
780# endif
951c6300 781#else
9aef40ed 782# error "Unhandled number of operands to insn_start"
951c6300 783#endif
c896fe29 784
07ea28b4
RH		 785/**
786 * tcg_gen_exit_tb() - output exit_tb TCG operation
787 * @tb: The TranslationBlock from which we are exiting
788 * @idx: Direct jump slot index, or exit request
789 *
790 * See tcg/README for more info about this TCG operation.
791 * See also tcg.h and the block comment above TB_EXIT_MASK.
792 *
793 * For a normal exit from the TB, back to the main loop, @tb should
794 * be NULL and @idx should be 0. Otherwise, @tb should be valid and
795 * @idx should be one of the TB_EXIT_ values.
796 */
797void tcg_gen_exit_tb(TranslationBlock *tb, unsigned idx);
c896fe29 798
5b053a4a
SF		 799/**
800 * tcg_gen_goto_tb() - output goto_tb TCG operation
801 * @idx: Direct jump slot index (0 or 1)
802 *
803 * See tcg/README for more info about this TCG operation.
804 *
90aa39a1
SF		 805 * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within
806 * the pages this TB resides in because we don't take care of direct jumps when
807 * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a
808 * static address translation, so the destination address is always valid, TBs
809 * are always invalidated properly, and direct jumps are reset when mapping
810 * changes.
5b053a4a 811 */
951c6300 812void tcg_gen_goto_tb(unsigned idx);
c896fe29 813
cedbcb01 814/**
7f11636d 815 * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid
cedbcb01
EC		 816 * @addr: Guest address of the target TB
817 *
818 * If the TB is not valid, jump to the epilogue.
819 *
820 * This operation is optional. If the TCG backend does not implement goto_ptr,
821 * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument.
822 */
7f11636d 823void tcg_gen_lookup_and_goto_ptr(void);
cedbcb01 824
a7812ae4 825#if TARGET_LONG_BITS == 32
a7812ae4
PB		 826#define tcg_temp_new() tcg_temp_new_i32()
827#define tcg_global_reg_new tcg_global_reg_new_i32
828#define tcg_global_mem_new tcg_global_mem_new_i32
df9247b2 829#define tcg_temp_local_new() tcg_temp_local_new_i32()
a7812ae4 830#define tcg_temp_free tcg_temp_free_i32
f713d6ad
RH		 831#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
832#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
a7812ae4 833#else
a7812ae4
PB		 834#define tcg_temp_new() tcg_temp_new_i64()
835#define tcg_global_reg_new tcg_global_reg_new_i64
836#define tcg_global_mem_new tcg_global_mem_new_i64
df9247b2 837#define tcg_temp_local_new() tcg_temp_local_new_i64()
a7812ae4 838#define tcg_temp_free tcg_temp_free_i64
f713d6ad
RH		 839#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
840#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
a7812ae4
PB		 841#endif
842
f713d6ad
RH		 843void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
844void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
845void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
846void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
c896fe29 847
ac56dd48 848static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
c896fe29 849{
f713d6ad 850 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
c896fe29
FB		 851}
852
ac56dd48 853static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
c896fe29 854{
f713d6ad 855 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
c896fe29
FB		 856}
857
ac56dd48 858static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
c896fe29 859{
f713d6ad 860 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
c896fe29
FB		 861}
862
ac56dd48 863static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
c896fe29 864{
f713d6ad 865 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
c896fe29
FB		 866}
867
ac56dd48 868static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
c896fe29 869{
f713d6ad 870 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
c896fe29
FB		 871}
872
ac56dd48 873static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
c896fe29 874{
f713d6ad 875 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
c896fe29
FB		 876}
877
a7812ae4 878static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
c896fe29 879{
f713d6ad 880 tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ);
c896fe29
FB		 881}
882
ac56dd48 883static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
c896fe29 884{
f713d6ad 885 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
c896fe29
FB		 886}
887
ac56dd48 888static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
c896fe29 889{
f713d6ad 890 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
c896fe29
FB		 891}
892
ac56dd48 893static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
c896fe29 894{
f713d6ad 895 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
c896fe29
FB		 896}
897
a7812ae4 898static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
c896fe29 899{
f713d6ad 900 tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ);
c896fe29
FB		 901}
902
c482cb11
RH		 903void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
904 TCGArg, TCGMemOp);
905void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
906 TCGArg, TCGMemOp);
907
908void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
909void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
5507c2bf 910
c482cb11
RH		 911void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
912void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
913void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
914void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
915void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
916void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
917void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
918void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
5507c2bf
RH		 919void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
920void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
921void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
922void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
923void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
924void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
925void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
926void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
927
c482cb11
RH		 928void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
929void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
930void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
931void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
932void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
933void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
934void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
935void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
5507c2bf
RH		 936void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
937void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
938void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
939void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
940void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
941void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
942void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
943void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
c482cb11 944
d2fd745f
RH		 945void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);
946void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);
947void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64);
948void tcg_gen_dup8i_vec(TCGv_vec, uint32_t);
949void tcg_gen_dup16i_vec(TCGv_vec, uint32_t);
950void tcg_gen_dup32i_vec(TCGv_vec, uint32_t);
951void tcg_gen_dup64i_vec(TCGv_vec, uint64_t);
db432672 952void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t);
d2fd745f
RH		 953void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
954void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
3774030a 955void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
d2fd745f
RH		 956void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
957void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
958void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
959void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
960void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
961void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
962void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
963
d0ec9796
RH		 964void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
965void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
966void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
967
212be173
RH		 968void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
969 TCGv_vec a, TCGv_vec b);
970
d2fd745f
RH		 971void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
972void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
973void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
974
f8422f52 975#if TARGET_LONG_BITS == 64
f8422f52
BS		 976#define tcg_gen_movi_tl tcg_gen_movi_i64
977#define tcg_gen_mov_tl tcg_gen_mov_i64
978#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
979#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
980#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
981#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
982#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
983#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
984#define tcg_gen_ld_tl tcg_gen_ld_i64
985#define tcg_gen_st8_tl tcg_gen_st8_i64
986#define tcg_gen_st16_tl tcg_gen_st16_i64
987#define tcg_gen_st32_tl tcg_gen_st32_i64
988#define tcg_gen_st_tl tcg_gen_st_i64
989#define tcg_gen_add_tl tcg_gen_add_i64
990#define tcg_gen_addi_tl tcg_gen_addi_i64
991#define tcg_gen_sub_tl tcg_gen_sub_i64
390efc54 992#define tcg_gen_neg_tl tcg_gen_neg_i64
10460c8a 993#define tcg_gen_subfi_tl tcg_gen_subfi_i64
f8422f52
BS		 994#define tcg_gen_subi_tl tcg_gen_subi_i64
995#define tcg_gen_and_tl tcg_gen_and_i64
996#define tcg_gen_andi_tl tcg_gen_andi_i64
997#define tcg_gen_or_tl tcg_gen_or_i64
998#define tcg_gen_ori_tl tcg_gen_ori_i64
999#define tcg_gen_xor_tl tcg_gen_xor_i64
1000#define tcg_gen_xori_tl tcg_gen_xori_i64
0b6ce4cf 1001#define tcg_gen_not_tl tcg_gen_not_i64
f8422f52
BS		 1002#define tcg_gen_shl_tl tcg_gen_shl_i64
1003#define tcg_gen_shli_tl tcg_gen_shli_i64
1004#define tcg_gen_shr_tl tcg_gen_shr_i64
1005#define tcg_gen_shri_tl tcg_gen_shri_i64
1006#define tcg_gen_sar_tl tcg_gen_sar_i64
1007#define tcg_gen_sari_tl tcg_gen_sari_i64
0cf767d6 1008#define tcg_gen_brcond_tl tcg_gen_brcond_i64
cb63669a 1009#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
be210acb 1010#define tcg_gen_setcond_tl tcg_gen_setcond_i64
add1e7ea 1011#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
f730fd27
TS		 1012#define tcg_gen_mul_tl tcg_gen_mul_i64
1013#define tcg_gen_muli_tl tcg_gen_muli_i64
ab36421e
AJ		 1014#define tcg_gen_div_tl tcg_gen_div_i64
1015#define tcg_gen_rem_tl tcg_gen_rem_i64
864951af
AJ		 1016#define tcg_gen_divu_tl tcg_gen_divu_i64
1017#define tcg_gen_remu_tl tcg_gen_remu_i64
a768e4b2 1018#define tcg_gen_discard_tl tcg_gen_discard_i64
ecc7b3aa 1019#define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32
e429073d
BS		 1020#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
1021#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
1022#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
1023#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
1024#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
0b6ce4cf
FB		 1025#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
1026#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
1027#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
1028#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
1029#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
1030#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
911d79ba
AJ		 1031#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
1032#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
1033#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
945ca823 1034#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
3c51a985 1035#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
f24cb33e
AJ		 1036#define tcg_gen_andc_tl tcg_gen_andc_i64
1037#define tcg_gen_eqv_tl tcg_gen_eqv_i64
1038#define tcg_gen_nand_tl tcg_gen_nand_i64
1039#define tcg_gen_nor_tl tcg_gen_nor_i64
1040#define tcg_gen_orc_tl tcg_gen_orc_i64
0e28d006
RH		 1041#define tcg_gen_clz_tl tcg_gen_clz_i64
1042#define tcg_gen_ctz_tl tcg_gen_ctz_i64
1043#define tcg_gen_clzi_tl tcg_gen_clzi_i64
1044#define tcg_gen_ctzi_tl tcg_gen_ctzi_i64
086920c2 1045#define tcg_gen_clrsb_tl tcg_gen_clrsb_i64
a768e4e9 1046#define tcg_gen_ctpop_tl tcg_gen_ctpop_i64
15824571
AJ		 1047#define tcg_gen_rotl_tl tcg_gen_rotl_i64
1048#define tcg_gen_rotli_tl tcg_gen_rotli_i64
1049#define tcg_gen_rotr_tl tcg_gen_rotr_i64
1050#define tcg_gen_rotri_tl tcg_gen_rotri_i64
b7767f0f 1051#define tcg_gen_deposit_tl tcg_gen_deposit_i64
07cc68d5 1052#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
7ec8bab3
RH		 1053#define tcg_gen_extract_tl tcg_gen_extract_i64
1054#define tcg_gen_sextract_tl tcg_gen_sextract_i64
a98824ac 1055#define tcg_const_tl tcg_const_i64
bdffd4a9 1056#define tcg_const_local_tl tcg_const_local_i64
ffc5ea09 1057#define tcg_gen_movcond_tl tcg_gen_movcond_i64
f6953a73
RH		 1058#define tcg_gen_add2_tl tcg_gen_add2_i64
1059#define tcg_gen_sub2_tl tcg_gen_sub2_i64
696a8be6
RH		 1060#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
1061#define tcg_gen_muls2_tl tcg_gen_muls2_i64
5087abfb 1062#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
b87fb8cd
RH		 1063#define tcg_gen_smin_tl tcg_gen_smin_i64
1064#define tcg_gen_umin_tl tcg_gen_umin_i64
1065#define tcg_gen_smax_tl tcg_gen_smax_i64
1066#define tcg_gen_umax_tl tcg_gen_umax_i64
c482cb11
RH		 1067#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
1068#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
1069#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
1070#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64
1071#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64
1072#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64
5507c2bf
RH		 1073#define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i64
1074#define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i64
1075#define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i64
1076#define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i64
c482cb11
RH		 1077#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64
1078#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
1079#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
1080#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
5507c2bf
RH		 1081#define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i64
1082#define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i64
1083#define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64
1084#define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64
d2fd745f 1085#define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec
f8422f52 1086#else
f8422f52
BS		 1087#define tcg_gen_movi_tl tcg_gen_movi_i32
1088#define tcg_gen_mov_tl tcg_gen_mov_i32
1089#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
1090#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
1091#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
1092#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
1093#define tcg_gen_ld32u_tl tcg_gen_ld_i32
1094#define tcg_gen_ld32s_tl tcg_gen_ld_i32
1095#define tcg_gen_ld_tl tcg_gen_ld_i32
1096#define tcg_gen_st8_tl tcg_gen_st8_i32
1097#define tcg_gen_st16_tl tcg_gen_st16_i32
1098#define tcg_gen_st32_tl tcg_gen_st_i32
1099#define tcg_gen_st_tl tcg_gen_st_i32
1100#define tcg_gen_add_tl tcg_gen_add_i32
1101#define tcg_gen_addi_tl tcg_gen_addi_i32
1102#define tcg_gen_sub_tl tcg_gen_sub_i32
390efc54 1103#define tcg_gen_neg_tl tcg_gen_neg_i32
0045734a 1104#define tcg_gen_subfi_tl tcg_gen_subfi_i32
f8422f52
BS		 1105#define tcg_gen_subi_tl tcg_gen_subi_i32
1106#define tcg_gen_and_tl tcg_gen_and_i32
1107#define tcg_gen_andi_tl tcg_gen_andi_i32
1108#define tcg_gen_or_tl tcg_gen_or_i32
1109#define tcg_gen_ori_tl tcg_gen_ori_i32
1110#define tcg_gen_xor_tl tcg_gen_xor_i32
1111#define tcg_gen_xori_tl tcg_gen_xori_i32
0b6ce4cf 1112#define tcg_gen_not_tl tcg_gen_not_i32
f8422f52
BS		 1113#define tcg_gen_shl_tl tcg_gen_shl_i32
1114#define tcg_gen_shli_tl tcg_gen_shli_i32
1115#define tcg_gen_shr_tl tcg_gen_shr_i32
1116#define tcg_gen_shri_tl tcg_gen_shri_i32
1117#define tcg_gen_sar_tl tcg_gen_sar_i32
1118#define tcg_gen_sari_tl tcg_gen_sari_i32
0cf767d6 1119#define tcg_gen_brcond_tl tcg_gen_brcond_i32
cb63669a 1120#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
be210acb 1121#define tcg_gen_setcond_tl tcg_gen_setcond_i32
add1e7ea 1122#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
f730fd27
TS		 1123#define tcg_gen_mul_tl tcg_gen_mul_i32
1124#define tcg_gen_muli_tl tcg_gen_muli_i32
ab36421e
AJ		 1125#define tcg_gen_div_tl tcg_gen_div_i32
1126#define tcg_gen_rem_tl tcg_gen_rem_i32
864951af
AJ		 1127#define tcg_gen_divu_tl tcg_gen_divu_i32
1128#define tcg_gen_remu_tl tcg_gen_remu_i32
a768e4b2 1129#define tcg_gen_discard_tl tcg_gen_discard_i32
e429073d 1130#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
ecc7b3aa 1131#define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32
e429073d
BS		 1132#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
1133#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
1134#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
1135#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
0b6ce4cf
FB		 1136#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
1137#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
1138#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
1139#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
1140#define tcg_gen_ext32u_tl tcg_gen_mov_i32
1141#define tcg_gen_ext32s_tl tcg_gen_mov_i32
911d79ba
AJ		 1142#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
1143#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
945ca823 1144#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
e3eb9806 1145#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
f24cb33e
AJ		 1146#define tcg_gen_andc_tl tcg_gen_andc_i32
1147#define tcg_gen_eqv_tl tcg_gen_eqv_i32
1148#define tcg_gen_nand_tl tcg_gen_nand_i32
1149#define tcg_gen_nor_tl tcg_gen_nor_i32
1150#define tcg_gen_orc_tl tcg_gen_orc_i32
0e28d006
RH		 1151#define tcg_gen_clz_tl tcg_gen_clz_i32
1152#define tcg_gen_ctz_tl tcg_gen_ctz_i32
1153#define tcg_gen_clzi_tl tcg_gen_clzi_i32
1154#define tcg_gen_ctzi_tl tcg_gen_ctzi_i32
086920c2 1155#define tcg_gen_clrsb_tl tcg_gen_clrsb_i32
a768e4e9 1156#define tcg_gen_ctpop_tl tcg_gen_ctpop_i32
15824571
AJ		 1157#define tcg_gen_rotl_tl tcg_gen_rotl_i32
1158#define tcg_gen_rotli_tl tcg_gen_rotli_i32
1159#define tcg_gen_rotr_tl tcg_gen_rotr_i32
1160#define tcg_gen_rotri_tl tcg_gen_rotri_i32
b7767f0f 1161#define tcg_gen_deposit_tl tcg_gen_deposit_i32
07cc68d5 1162#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
7ec8bab3
RH		 1163#define tcg_gen_extract_tl tcg_gen_extract_i32
1164#define tcg_gen_sextract_tl tcg_gen_sextract_i32
a98824ac 1165#define tcg_const_tl tcg_const_i32
bdffd4a9 1166#define tcg_const_local_tl tcg_const_local_i32
ffc5ea09 1167#define tcg_gen_movcond_tl tcg_gen_movcond_i32
f6953a73
RH		 1168#define tcg_gen_add2_tl tcg_gen_add2_i32
1169#define tcg_gen_sub2_tl tcg_gen_sub2_i32
696a8be6
RH		 1170#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
1171#define tcg_gen_muls2_tl tcg_gen_muls2_i32
5087abfb 1172#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
b87fb8cd
RH		 1173#define tcg_gen_smin_tl tcg_gen_smin_i32
1174#define tcg_gen_umin_tl tcg_gen_umin_i32
1175#define tcg_gen_smax_tl tcg_gen_smax_i32
1176#define tcg_gen_umax_tl tcg_gen_umax_i32
c482cb11
RH		 1177#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
1178#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
1179#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32
1180#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32
1181#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32
1182#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32
5507c2bf
RH		 1183#define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i32
1184#define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i32
1185#define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i32
1186#define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i32
c482cb11
RH		 1187#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32
1188#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
1189#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
1190#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
5507c2bf
RH		 1191#define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i32
1192#define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i32
1193#define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32
1194#define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32
d2fd745f 1195#define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec
f8422f52 1196#endif
6ddbc6e4 1197
71b92699 1198#if UINTPTR_MAX == UINT32_MAX
5bfa8034
RH		 1199# define PTR i32
1200# define NAT TCGv_i32
f713d6ad 1201#else
5bfa8034
RH		 1202# define PTR i64
1203# define NAT TCGv_i64
1204#endif
1205
1206static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
1207{
1208 glue(tcg_gen_ld_,PTR)((NAT)r, a, o);
1209}
1210
1211static inline void tcg_gen_discard_ptr(TCGv_ptr a)
1212{
1213 glue(tcg_gen_discard_,PTR)((NAT)a);
1214}
1215
1216static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b)
1217{
1218 glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b);
1219}
1220
1221static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b)
1222{
1223 glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b);
1224}
1225
1226static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a,
1227 intptr_t b, TCGLabel *label)
1228{
1229 glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label);
1230}
1231
1232static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a)
1233{
1234#if UINTPTR_MAX == UINT32_MAX
1235 tcg_gen_mov_i32((NAT)r, a);
1236#else
1237 tcg_gen_ext_i32_i64((NAT)r, a);
1238#endif
1239}
1240
1241static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a)
1242{
1243#if UINTPTR_MAX == UINT32_MAX
1244 tcg_gen_extrl_i64_i32((NAT)r, a);
1245#else
1246 tcg_gen_mov_i64((NAT)r, a);
1247#endif
1248}
1249
1250static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a)
1251{
1252#if UINTPTR_MAX == UINT32_MAX
1253 tcg_gen_extu_i32_i64(r, (NAT)a);
1254#else
1255 tcg_gen_mov_i64(r, (NAT)a);
1256#endif
1257}
1258
1259static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a)
1260{
1261#if UINTPTR_MAX == UINT32_MAX
1262 tcg_gen_mov_i32(r, (NAT)a);
1263#else
1264 tcg_gen_extrl_i64_i32(r, (NAT)a);
1265#endif
1266}
1267
1268#undef PTR
1269#undef NAT
Empty description
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