[qemu.git] / hw / i386 / q35-acpi-dsdt.dsl

/*
 * Bochs/QEMU ACPI DSDT ASL definition
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License version 2 as published by the Free Software Foundation.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
/*
 * Copyright (c) 2010 Isaku Yamahata
 *                    yamahata at valinux co jp
 * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
 */

ACPI_EXTRACT_ALL_CODE Q35AcpiDsdtAmlCode

DefinitionBlock (
    "q35-acpi-dsdt.aml",// Output Filename
    "DSDT",             // Signature
    0x01,               // DSDT Compliance Revision
    "BXPC",             // OEMID
    "BXDSDT",           // TABLE ID
    0x2                 // OEM Revision
    )
{

#include "acpi-dsdt-dbug.dsl"

    Scope(\_SB) {
        OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
        OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
        Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
            PCIB, 8,
        }
    }


/****************************************************************
 * PCI Bus definition
 ****************************************************************/
#define BOARD_SPECIFIC_PCI_RESOURSES \
     WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
         0x0000, \
         0x0000, \
         0x0CD7, \
         0x0000, \
         0x0CD8, \
         ,, , TypeStatic) \
     /* 0xcd8-0xcf7 hole for CPU hotplug, hw/acpi/ich9.c:ICH9_PROC_BASE */ \
     WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
         0x0000, \
         0x0D00, \
         0xFFFF, \
         0x0000, \
         0xF300, \
         ,, , TypeStatic)

    Scope(\_SB) {
        Device(PCI0) {
            Name(_HID, EisaId("PNP0A08"))
            Name(_CID, EisaId("PNP0A03"))
            Name(_ADR, 0x00)
            Name(_UID, 1)

            External(ISA, DeviceObj)

            // _OSC: based on sample of ACPI3.0b spec
            Name(SUPP, 0) // PCI _OSC Support Field value
            Name(CTRL, 0) // PCI _OSC Control Field value
            Method(_OSC, 4) {
                // Create DWORD-addressable fields from the Capabilities Buffer
                CreateDWordField(Arg3, 0, CDW1)

                // Check for proper UUID
                If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
                    // Create DWORD-addressable fields from the Capabilities Buffer
                    CreateDWordField(Arg3, 4, CDW2)
                    CreateDWordField(Arg3, 8, CDW3)

                    // Save Capabilities DWORD2 & 3
                    Store(CDW2, SUPP)
                    Store(CDW3, CTRL)

                    // Always allow native PME, AER (no dependencies)
                    // Never allow SHPC (no SHPC controller in this system)
                    And(CTRL, 0x1D, CTRL)

#if 0 // For now, nothing to do
                    If (Not(And(CDW1, 1))) { // Query flag clear?
                        // Disable GPEs for features granted native control.
                        If (And(CTRL, 0x01)) { // Hot plug control granted?
                            Store(0, HPCE) // clear the hot plug SCI enable bit
                            Store(1, HPCS) // clear the hot plug SCI status bit
                        }
                        If (And(CTRL, 0x04)) { // PME control granted?
                            Store(0, PMCE) // clear the PME SCI enable bit
                            Store(1, PMCS) // clear the PME SCI status bit
                        }
                        If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
                            // Set status to not restore PCI Express cap structure
                            // upon resume from S3
                            Store(1, S3CR)
                        }
                    }
#endif
                    If (LNotEqual(Arg1, One)) {
                        // Unknown revision
                        Or(CDW1, 0x08, CDW1)
                    }
                    If (LNotEqual(CDW3, CTRL)) {
                        // Capabilities bits were masked
                        Or(CDW1, 0x10, CDW1)
                    }
                    // Update DWORD3 in the buffer
                    Store(CTRL, CDW3)
                } Else {
                    Or(CDW1, 4, CDW1) // Unrecognized UUID
                }
                Return (Arg3)
            }
        }
    }

#include "acpi-dsdt-pci-crs.dsl"
#include "acpi-dsdt-hpet.dsl"


/****************************************************************
 * LPC ISA bridge
 ****************************************************************/

    Scope(\_SB.PCI0) {
        /* PCI D31:f0 LPC ISA bridge */
        Device(ISA) {
            Name (_ADR, 0x001F0000)  // _ADR: Address

            /* ICH9 PCI to ISA irq remapping */
            OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)

            OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
            Field(LPCD, AnyAcc, NoLock, Preserve) {
                COMA,   3,
                    ,   1,
                COMB,   3,

                Offset(0x01),
                LPTD,   2,
                    ,   2,
                FDCD,   2
            }
            OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
            Field(LPCE, AnyAcc, NoLock, Preserve) {
                CAEN,   1,
                CBEN,   1,
                LPEN,   1,
                FDEN,   1
            }
        }
    }

#define DSDT_APPLESMC_STA q35_dsdt_applesmc_sta
#include "acpi-dsdt-isa.dsl"


/****************************************************************
 * PCI IRQs
 ****************************************************************/

    /* Zero => PIC mode, One => APIC Mode */
    Name(\PICF, Zero)
    Method(\_PIC, 1, NotSerialized) {
        Store(Arg0, \PICF)
    }

    Scope(\_SB) {
        Scope(PCI0) {
#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3)  \
    Package() { nr##ffff, 0, lnk0, 0 },           \
    Package() { nr##ffff, 1, lnk1, 0 },           \
    Package() { nr##ffff, 2, lnk2, 0 },           \
    Package() { nr##ffff, 3, lnk3, 0 }

#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)

#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)

            Name(PRTP, package() {
                prt_slot_lnkE(0x0000),
                prt_slot_lnkF(0x0001),
                prt_slot_lnkG(0x0002),
                prt_slot_lnkH(0x0003),
                prt_slot_lnkE(0x0004),
                prt_slot_lnkF(0x0005),
                prt_slot_lnkG(0x0006),
                prt_slot_lnkH(0x0007),
                prt_slot_lnkE(0x0008),
                prt_slot_lnkF(0x0009),
                prt_slot_lnkG(0x000a),
                prt_slot_lnkH(0x000b),
                prt_slot_lnkE(0x000c),
                prt_slot_lnkF(0x000d),
                prt_slot_lnkG(0x000e),
                prt_slot_lnkH(0x000f),
                prt_slot_lnkE(0x0010),
                prt_slot_lnkF(0x0011),
                prt_slot_lnkG(0x0012),
                prt_slot_lnkH(0x0013),
                prt_slot_lnkE(0x0014),
                prt_slot_lnkF(0x0015),
                prt_slot_lnkG(0x0016),
                prt_slot_lnkH(0x0017),
                prt_slot_lnkE(0x0018),

                /* INTA -> PIRQA for slot 25 - 31
                   see the default value of D<N>IR */
                prt_slot_lnkA(0x0019),
                prt_slot_lnkA(0x001a),
                prt_slot_lnkA(0x001b),
                prt_slot_lnkA(0x001c),
                prt_slot_lnkA(0x001d),

                /* PCIe->PCI bridge. use PIRQ[E-H] */
                prt_slot_lnkE(0x001e),

                prt_slot_lnkA(0x001f)
            })

#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3)  \
    Package() { nr##ffff, 0, gsi0, 0 },           \
    Package() { nr##ffff, 1, gsi1, 0 },           \
    Package() { nr##ffff, 2, gsi2, 0 },           \
    Package() { nr##ffff, 3, gsi3, 0 }

#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)

#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)

            Name(PRTA, package() {
                prt_slot_gsiE(0x0000),
                prt_slot_gsiF(0x0001),
                prt_slot_gsiG(0x0002),
                prt_slot_gsiH(0x0003),
                prt_slot_gsiE(0x0004),
                prt_slot_gsiF(0x0005),
                prt_slot_gsiG(0x0006),
                prt_slot_gsiH(0x0007),
                prt_slot_gsiE(0x0008),
                prt_slot_gsiF(0x0009),
                prt_slot_gsiG(0x000a),
                prt_slot_gsiH(0x000b),
                prt_slot_gsiE(0x000c),
                prt_slot_gsiF(0x000d),
                prt_slot_gsiG(0x000e),
                prt_slot_gsiH(0x000f),
                prt_slot_gsiE(0x0010),
                prt_slot_gsiF(0x0011),
                prt_slot_gsiG(0x0012),
                prt_slot_gsiH(0x0013),
                prt_slot_gsiE(0x0014),
                prt_slot_gsiF(0x0015),
                prt_slot_gsiG(0x0016),
                prt_slot_gsiH(0x0017),
                prt_slot_gsiE(0x0018),

                /* INTA -> PIRQA for slot 25 - 31, but 30
                   see the default value of D<N>IR */
                prt_slot_gsiA(0x0019),
                prt_slot_gsiA(0x001a),
                prt_slot_gsiA(0x001b),
                prt_slot_gsiA(0x001c),
                prt_slot_gsiA(0x001d),

                /* PCIe->PCI bridge. use PIRQ[E-H] */
                prt_slot_gsiE(0x001e),

                prt_slot_gsiA(0x001f)
            })

            Method(_PRT, 0, NotSerialized) {
                /* PCI IRQ routing table, example from ACPI 2.0a specification,
                   section 6.2.8.1 */
                /* Note: we provide the same info as the PCI routing
                   table of the Bochs BIOS */
                If (LEqual(\PICF, Zero)) {
                    Return (PRTP)
                } Else {
                    Return (PRTA)
                }
            }
        }

        Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
            PRQA,   8,
            PRQB,   8,
            PRQC,   8,
            PRQD,   8,

            Offset(0x08),
            PRQE,   8,
            PRQF,   8,
            PRQG,   8,
            PRQH,   8
        }

        Method(IQST, 1, NotSerialized) {
            // _STA method - get status
            If (And(0x80, Arg0)) {
                Return (0x09)
            }
            Return (0x0B)
        }
        Method(IQCR, 1, Serialized) {
            // _CRS method - get current settings
            Name(PRR0, ResourceTemplate() {
                Interrupt(, Level, ActiveHigh, Shared) { 0 }
            })
            CreateDWordField(PRR0, 0x05, PRRI)
            Store(And(Arg0, 0x0F), PRRI)
            Return (PRR0)
        }

#define define_link(link, uid, reg)                             \
        Device(link) {                                          \
            Name(_HID, EISAID("PNP0C0F"))                       \
            Name(_UID, uid)                                     \
            Name(_PRS, ResourceTemplate() {                     \
                Interrupt(, Level, ActiveHigh, Shared) {        \
                    5, 10, 11                                   \
                }                                               \
            })                                                  \
            Method(_STA, 0, NotSerialized) {                    \
                Return (IQST(reg))                              \
            }                                                   \
            Method(_DIS, 0, NotSerialized) {                    \
                Or(reg, 0x80, reg)                              \
            }                                                   \
            Method(_CRS, 0, NotSerialized) {                    \
                Return (IQCR(reg))                              \
            }                                                   \
            Method(_SRS, 1, NotSerialized) {                    \
                CreateDWordField(Arg0, 0x05, PRRI)              \
                Store(PRRI, reg)                                \
            }                                                   \
        }

        define_link(LNKA, 0, PRQA)
        define_link(LNKB, 1, PRQB)
        define_link(LNKC, 2, PRQC)
        define_link(LNKD, 3, PRQD)
        define_link(LNKE, 4, PRQE)
        define_link(LNKF, 5, PRQF)
        define_link(LNKG, 6, PRQG)
        define_link(LNKH, 7, PRQH)

#define define_gsi_link(link, uid, gsi)                         \
        Device(link) {                                          \
            Name(_HID, EISAID("PNP0C0F"))                       \
            Name(_UID, uid)                                     \
            Name(_PRS, ResourceTemplate() {                     \
                Interrupt(, Level, ActiveHigh, Shared) {        \
                    gsi                                         \
                }                                               \
            })                                                  \
            Name(_CRS, ResourceTemplate() {                     \
                Interrupt(, Level, ActiveHigh, Shared) {        \
                    gsi                                         \
                }                                               \
            })                                                  \
            Method(_SRS, 1, NotSerialized) {                    \
            }                                                   \
        }

        define_gsi_link(GSIA, 0, 0x10)
        define_gsi_link(GSIB, 0, 0x11)
        define_gsi_link(GSIC, 0, 0x12)
        define_gsi_link(GSID, 0, 0x13)
        define_gsi_link(GSIE, 0, 0x14)
        define_gsi_link(GSIF, 0, 0x15)
        define_gsi_link(GSIG, 0, 0x16)
        define_gsi_link(GSIH, 0, 0x17)
    }

#include "hw/acpi/cpu_hotplug_defs.h"
#define CPU_STATUS_BASE ICH9_CPU_HOTPLUG_IO_BASE
#include "acpi-dsdt-cpu-hotplug.dsl"


/****************************************************************
 * General purpose events
 ****************************************************************/

    Scope(\_GPE) {
        Name(_HID, "ACPI0006")

        Method(_L00) {
        }
        Method(_L01) {
        }
        Method(_E02) {
            // CPU hotplug event
            \_SB.PRSC()
        }
        Method(_L03) {
        }
        Method(_L04) {
        }
        Method(_L05) {
        }
        Method(_L06) {
        }
        Method(_L07) {
        }
        Method(_L08) {
        }
        Method(_L09) {
        }
        Method(_L0A) {
        }
        Method(_L0B) {
        }
        Method(_L0C) {
        }
        Method(_L0D) {
        }
        Method(_L0E) {
        }
        Method(_L0F) {
        }
    }
}
Commit	Line	Data
74523b85 MT	1	/*
	2	* Bochs/QEMU ACPI DSDT ASL definition
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License version 2 as published by the Free Software Foundation.
	9	*
	10	* This library is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* Lesser General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU Lesser General Public
	16	* License along with this library; if not, write to the Free Software
	17	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	18	*/
	19	/*
	20	* Copyright (c) 2010 Isaku Yamahata
	21	* yamahata at valinux co jp
	22	* Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
	23	*/
	24
	25	ACPI_EXTRACT_ALL_CODE Q35AcpiDsdtAmlCode
	26
	27	DefinitionBlock (
	28	"q35-acpi-dsdt.aml",// Output Filename
	29	"DSDT", // Signature
	30	0x01, // DSDT Compliance Revision
	31	"BXPC", // OEMID
	32	"BXDSDT", // TABLE ID
	33	0x2 // OEM Revision
	34	)
	35	{
	36
	37	#include "acpi-dsdt-dbug.dsl"
	38
	39	Scope(\_SB) {
	40	OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
	41	OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
	42	Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
	43	PCIB, 8,
	44	}
	45	}
	46
	47
	48	/****************************************************************
	49	* PCI Bus definition
	50	****************************************************************/
1aa149b4	51	#define BOARD_SPECIFIC_PCI_RESOURSES \
562e56a9 IM	52	WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
	53	0x0000, \
	54	0x0000, \
	55	0x0CD7, \
	56	0x0000, \
	57	0x0CD8, \
	58	,, , TypeStatic) \
	59	/* 0xcd8-0xcf7 hole for CPU hotplug, hw/acpi/ich9.c:ICH9_PROC_BASE */ \
1aa149b4 IM	60	WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
	61	0x0000, \
	62	0x0D00, \
	63	0xFFFF, \
	64	0x0000, \
	65	0xF300, \
	66	,, , TypeStatic)
74523b85 MT	67
	68	Scope(\_SB) {
	69	Device(PCI0) {
	70	Name(_HID, EisaId("PNP0A08"))
	71	Name(_CID, EisaId("PNP0A03"))
	72	Name(_ADR, 0x00)
	73	Name(_UID, 1)
	74
8dcf525a MT	75	External(ISA, DeviceObj)
8dcf525a MT	76
74523b85 MT	77	// _OSC: based on sample of ACPI3.0b spec
	78	Name(SUPP, 0) // PCI _OSC Support Field value
	79	Name(CTRL, 0) // PCI _OSC Control Field value
	80	Method(_OSC, 4) {
	81	// Create DWORD-addressable fields from the Capabilities Buffer
	82	CreateDWordField(Arg3, 0, CDW1)
	83
	84	// Check for proper UUID
	85	If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
	86	// Create DWORD-addressable fields from the Capabilities Buffer
	87	CreateDWordField(Arg3, 4, CDW2)
	88	CreateDWordField(Arg3, 8, CDW3)
	89
	90	// Save Capabilities DWORD2 & 3
	91	Store(CDW2, SUPP)
	92	Store(CDW3, CTRL)
	93
	94	// Always allow native PME, AER (no dependencies)
	95	// Never allow SHPC (no SHPC controller in this system)
	96	And(CTRL, 0x1D, CTRL)
	97
	98	#if 0 // For now, nothing to do
	99	If (Not(And(CDW1, 1))) { // Query flag clear?
	100	// Disable GPEs for features granted native control.
	101	If (And(CTRL, 0x01)) { // Hot plug control granted?
	102	Store(0, HPCE) // clear the hot plug SCI enable bit
	103	Store(1, HPCS) // clear the hot plug SCI status bit
	104	}
	105	If (And(CTRL, 0x04)) { // PME control granted?
	106	Store(0, PMCE) // clear the PME SCI enable bit
	107	Store(1, PMCS) // clear the PME SCI status bit
	108	}
	109	If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
	110	// Set status to not restore PCI Express cap structure
	111	// upon resume from S3
	112	Store(1, S3CR)
	113	}
	114	}
	115	#endif
	116	If (LNotEqual(Arg1, One)) {
	117	// Unknown revision
	118	Or(CDW1, 0x08, CDW1)
	119	}
	120	If (LNotEqual(CDW3, CTRL)) {
	121	// Capabilities bits were masked
	122	Or(CDW1, 0x10, CDW1)
	123	}
	124	// Update DWORD3 in the buffer
	125	Store(CTRL, CDW3)
	126	} Else {
	127	Or(CDW1, 4, CDW1) // Unrecognized UUID
	128	}
	129	Return (Arg3)
	130	}
	131	}
	132	}
	133
	134	#include "acpi-dsdt-pci-crs.dsl"
	135	#include "acpi-dsdt-hpet.dsl"
	136
	137
74523b85 MT	138	/****************************************************************
	139	* LPC ISA bridge
	140	****************************************************************/
	141
	142	Scope(\_SB.PCI0) {
	143	/* PCI D31:f0 LPC ISA bridge */
	144	Device(ISA) {
8dcf525a	145	Name (_ADR, 0x001F0000) // _ADR: Address
74523b85 MT	146
	147	/* ICH9 PCI to ISA irq remapping */
	148	OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)
	149
	150	OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
	151	Field(LPCD, AnyAcc, NoLock, Preserve) {
	152	COMA, 3,
	153	, 1,
	154	COMB, 3,
	155
	156	Offset(0x01),
	157	LPTD, 2,
	158	, 2,
	159	FDCD, 2
	160	}
	161	OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
	162	Field(LPCE, AnyAcc, NoLock, Preserve) {
	163	CAEN, 1,
	164	CBEN, 1,
	165	LPEN, 1,
	166	FDEN, 1
	167	}
	168	}
	169	}
	170
15bce1b7	171	#define DSDT_APPLESMC_STA q35_dsdt_applesmc_sta
74523b85 MT	172	#include "acpi-dsdt-isa.dsl"
	173
	174
	175	/****************************************************************
	176	* PCI IRQs
	177	****************************************************************/
	178
	179	/* Zero => PIC mode, One => APIC Mode */
	180	Name(\PICF, Zero)
	181	Method(\_PIC, 1, NotSerialized) {
	182	Store(Arg0, \PICF)
	183	}
	184
	185	Scope(\_SB) {
	186	Scope(PCI0) {
	187	#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \
	188	Package() { nr##ffff, 0, lnk0, 0 }, \
	189	Package() { nr##ffff, 1, lnk1, 0 }, \
	190	Package() { nr##ffff, 2, lnk2, 0 }, \
	191	Package() { nr##ffff, 3, lnk3, 0 }
	192
	193	#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
	194	#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
	195	#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
	196	#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
	197
	198	#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
	199	#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
	200	#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
	201	#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
	202
	203	Name(PRTP, package() {
	204	prt_slot_lnkE(0x0000),
	205	prt_slot_lnkF(0x0001),
	206	prt_slot_lnkG(0x0002),
	207	prt_slot_lnkH(0x0003),
	208	prt_slot_lnkE(0x0004),
	209	prt_slot_lnkF(0x0005),
	210	prt_slot_lnkG(0x0006),
	211	prt_slot_lnkH(0x0007),
	212	prt_slot_lnkE(0x0008),
	213	prt_slot_lnkF(0x0009),
	214	prt_slot_lnkG(0x000a),
	215	prt_slot_lnkH(0x000b),
	216	prt_slot_lnkE(0x000c),
	217	prt_slot_lnkF(0x000d),
	218	prt_slot_lnkG(0x000e),
	219	prt_slot_lnkH(0x000f),
	220	prt_slot_lnkE(0x0010),
	221	prt_slot_lnkF(0x0011),
	222	prt_slot_lnkG(0x0012),
	223	prt_slot_lnkH(0x0013),
	224	prt_slot_lnkE(0x0014),
	225	prt_slot_lnkF(0x0015),
	226	prt_slot_lnkG(0x0016),
	227	prt_slot_lnkH(0x0017),
	228	prt_slot_lnkE(0x0018),
	229
	230	/* INTA -> PIRQA for slot 25 - 31
	231	see the default value of D<N>IR */
	232	prt_slot_lnkA(0x0019),
	233	prt_slot_lnkA(0x001a),
	234	prt_slot_lnkA(0x001b),
	235	prt_slot_lnkA(0x001c),
236	prt_slot_lnkA(0x001d),
237
238	/* PCIe->PCI bridge. use PIRQ[E-H] */
239	prt_slot_lnkE(0x001e),
240
241	prt_slot_lnkA(0x001f)
242	})
243
244	#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
245	Package() { nr##ffff, 0, gsi0, 0 }, \
246	Package() { nr##ffff, 1, gsi1, 0 }, \
247	Package() { nr##ffff, 2, gsi2, 0 }, \
248	Package() { nr##ffff, 3, gsi3, 0 }
249
250	#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
251	#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
252	#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
253	#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
254
255	#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
256	#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
257	#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
258	#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
259
260	Name(PRTA, package() {
261	prt_slot_gsiE(0x0000),
262	prt_slot_gsiF(0x0001),
263	prt_slot_gsiG(0x0002),
264	prt_slot_gsiH(0x0003),
265	prt_slot_gsiE(0x0004),
266	prt_slot_gsiF(0x0005),
267	prt_slot_gsiG(0x0006),
268	prt_slot_gsiH(0x0007),
269	prt_slot_gsiE(0x0008),
270	prt_slot_gsiF(0x0009),
271	prt_slot_gsiG(0x000a),
272	prt_slot_gsiH(0x000b),
273	prt_slot_gsiE(0x000c),
274	prt_slot_gsiF(0x000d),
275	prt_slot_gsiG(0x000e),
276	prt_slot_gsiH(0x000f),
277	prt_slot_gsiE(0x0010),
278	prt_slot_gsiF(0x0011),
279	prt_slot_gsiG(0x0012),
280	prt_slot_gsiH(0x0013),
281	prt_slot_gsiE(0x0014),
282	prt_slot_gsiF(0x0015),
283	prt_slot_gsiG(0x0016),
284	prt_slot_gsiH(0x0017),
285	prt_slot_gsiE(0x0018),
286
287	/* INTA -> PIRQA for slot 25 - 31, but 30
288	see the default value of D<N>IR */
289	prt_slot_gsiA(0x0019),
290	prt_slot_gsiA(0x001a),
291	prt_slot_gsiA(0x001b),
292	prt_slot_gsiA(0x001c),
293	prt_slot_gsiA(0x001d),
294
295	/* PCIe->PCI bridge. use PIRQ[E-H] */
296	prt_slot_gsiE(0x001e),
297
298	prt_slot_gsiA(0x001f)
299	})
300
301	Method(_PRT, 0, NotSerialized) {
302	/* PCI IRQ routing table, example from ACPI 2.0a specification,
303	section 6.2.8.1 */
304	/* Note: we provide the same info as the PCI routing
305	table of the Bochs BIOS */
306	If (LEqual(\PICF, Zero)) {
307	Return (PRTP)
308	} Else {
309	Return (PRTA)
310	}
311	}
312	}
313
314	Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
315	PRQA, 8,
316	PRQB, 8,
317	PRQC, 8,
318	PRQD, 8,
319
320	Offset(0x08),
321	PRQE, 8,
322	PRQF, 8,
323	PRQG, 8,
324	PRQH, 8
325	}
326
327	Method(IQST, 1, NotSerialized) {
328	// _STA method - get status
329	If (And(0x80, Arg0)) {
330	Return (0x09)
331	}
332	Return (0x0B)
333	}
6b9b4405	334	Method(IQCR, 1, Serialized) {
74523b85 MT	335	// _CRS method - get current settings
	336	Name(PRR0, ResourceTemplate() {
	337	Interrupt(, Level, ActiveHigh, Shared) { 0 }
	338	})
	339	CreateDWordField(PRR0, 0x05, PRRI)
	340	Store(And(Arg0, 0x0F), PRRI)
	341	Return (PRR0)
	342	}
	343
	344	#define define_link(link, uid, reg) \
	345	Device(link) { \
	346	Name(_HID, EISAID("PNP0C0F")) \
	347	Name(_UID, uid) \
	348	Name(_PRS, ResourceTemplate() { \
	349	Interrupt(, Level, ActiveHigh, Shared) { \
	350	5, 10, 11 \
	351	} \
	352	}) \
	353	Method(_STA, 0, NotSerialized) { \
	354	Return (IQST(reg)) \
	355	} \
	356	Method(_DIS, 0, NotSerialized) { \
	357	Or(reg, 0x80, reg) \
	358	} \
	359	Method(_CRS, 0, NotSerialized) { \
	360	Return (IQCR(reg)) \
	361	} \
	362	Method(_SRS, 1, NotSerialized) { \
	363	CreateDWordField(Arg0, 0x05, PRRI) \
	364	Store(PRRI, reg) \
	365	} \
	366	}
	367
	368	define_link(LNKA, 0, PRQA)
	369	define_link(LNKB, 1, PRQB)
	370	define_link(LNKC, 2, PRQC)
	371	define_link(LNKD, 3, PRQD)
	372	define_link(LNKE, 4, PRQE)
	373	define_link(LNKF, 5, PRQF)
	374	define_link(LNKG, 6, PRQG)
	375	define_link(LNKH, 7, PRQH)
	376
	377	#define define_gsi_link(link, uid, gsi) \
	378	Device(link) { \
	379	Name(_HID, EISAID("PNP0C0F")) \
	380	Name(_UID, uid) \
	381	Name(_PRS, ResourceTemplate() { \
	382	Interrupt(, Level, ActiveHigh, Shared) { \
	383	gsi \
	384	} \
	385	}) \
	386	Name(_CRS, ResourceTemplate() { \
	387	Interrupt(, Level, ActiveHigh, Shared) { \
	388	gsi \
	389	} \
	390	}) \
	391	Method(_SRS, 1, NotSerialized) { \
	392	} \
	393	}
	394
	395	define_gsi_link(GSIA, 0, 0x10)
	396	define_gsi_link(GSIB, 0, 0x11)
	397	define_gsi_link(GSIC, 0, 0x12)
	398	define_gsi_link(GSID, 0, 0x13)
399	define_gsi_link(GSIE, 0, 0x14)
400	define_gsi_link(GSIF, 0, 0x15)
401	define_gsi_link(GSIG, 0, 0x16)
402	define_gsi_link(GSIH, 0, 0x17)
403	}
404
e4cf8ed0 IM	405	#include "hw/acpi/cpu_hotplug_defs.h"
e4cf8ed0 IM	406	#define CPU_STATUS_BASE ICH9_CPU_HOTPLUG_IO_BASE
74523b85 MT	407	#include "acpi-dsdt-cpu-hotplug.dsl"
	408
	409
	410	/****************************************************************
	411	* General purpose events
	412	****************************************************************/
	413
	414	Scope(\_GPE) {
	415	Name(_HID, "ACPI0006")
	416
	417	Method(_L00) {
	418	}
	419	Method(_L01) {
c1a1af87 IM	420	}
c1a1af87 IM	421	Method(_E02) {
74523b85 MT	422	// CPU hotplug event
	423	\_SB.PRSC()
	424	}
74523b85 MT	425	Method(_L03) {
	426	}
	427	Method(_L04) {
	428	}
	429	Method(_L05) {
	430	}
	431	Method(_L06) {
	432	}
	433	Method(_L07) {
	434	}
	435	Method(_L08) {
	436	}
	437	Method(_L09) {
	438	}
	439	Method(_L0A) {
	440	}
	441	Method(_L0B) {
	442	}
	443	Method(_L0C) {
	444	}
	445	Method(_L0D) {
	446	}
	447	Method(_L0E) {
	448	}
	449	Method(_L0F) {
	450	}
	451	}
	452	}