[qemu.git] / hw / i386 / pc_q35.c

/*
 * Q35 chipset based pc system emulator
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2009, 2010
 *               Isaku Yamahata <yamahata at valinux co jp>
 *               VA Linux Systems Japan K.K.
 * Copyright (C) 2012 Jason Baron <[email protected]>
 *
 * This is based on pc.c, but heavily modified.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw/hw.h"
#include "hw/loader.h"
#include "sysemu/arch_init.h"
#include "hw/i2c/smbus.h"
#include "hw/boards.h"
#include "hw/timer/mc146818rtc.h"
#include "hw/xen/xen.h"
#include "sysemu/kvm.h"
#include "hw/kvm/clock.h"
#include "hw/pci-host/q35.h"
#include "exec/address-spaces.h"
#include "hw/i386/ich9.h"
#include "hw/i386/smbios.h"
#include "hw/ide/pci.h"
#include "hw/ide/ahci.h"
#include "hw/usb.h"
#include "hw/cpu/icc_bus.h"

/* ICH9 AHCI has 6 ports */
#define MAX_SATA_PORTS     6

static bool has_pci_info;
static bool has_acpi_build = true;
static bool smbios_type1_defaults = true;
/* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
 * host addresses aligned at 1Gbyte boundaries.  This way we can use 1GByte
 * pages in the host.
 */
static bool gigabyte_align = true;

/* PC hardware initialisation */
static void pc_q35_init(QEMUMachineInitArgs *args)
{
    ram_addr_t below_4g_mem_size, above_4g_mem_size;
    Q35PCIHost *q35_host;
    PCIHostState *phb;
    PCIBus *host_bus;
    PCIDevice *lpc;
    BusState *idebus[MAX_SATA_PORTS];
    ISADevice *rtc_state;
    ISADevice *floppy;
    MemoryRegion *pci_memory;
    MemoryRegion *rom_memory;
    MemoryRegion *ram_memory;
    GSIState *gsi_state;
    ISABus *isa_bus;
    int pci_enabled = 1;
    qemu_irq *cpu_irq;
    qemu_irq *gsi;
    qemu_irq *i8259;
    int i;
    ICH9LPCState *ich9_lpc;
    PCIDevice *ahci;
    DeviceState *icc_bridge;
    PcGuestInfo *guest_info;

    if (xen_enabled() && xen_hvm_init(&ram_memory) != 0) {
        fprintf(stderr, "xen hardware virtual machine initialisation failed\n");
        exit(1);
    }

    icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
    object_property_add_child(qdev_get_machine(), "icc-bridge",
                              OBJECT(icc_bridge), NULL);

    pc_cpus_init(args->cpu_model, icc_bridge);
    pc_acpi_init("q35-acpi-dsdt.aml");

    kvmclock_create();

    /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
     * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
     * also known as MMCFG).
     * If it doesn't, we need to split it in chunks below and above 4G.
     * In any case, try to make sure that guest addresses aligned at
     * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
     * For old machine types, use whatever split we used historically to avoid
     * breaking migration.
     */
    if (args->ram_size >= 0xb0000000) {
        ram_addr_t lowmem = gigabyte_align ? 0x80000000 : 0xb0000000;
        above_4g_mem_size = args->ram_size - lowmem;
        below_4g_mem_size = lowmem;
    } else {
        above_4g_mem_size = 0;
        below_4g_mem_size = args->ram_size;
    }

    /* pci enabled */
    if (pci_enabled) {
        pci_memory = g_new(MemoryRegion, 1);
        memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
        rom_memory = pci_memory;
    } else {
        pci_memory = NULL;
        rom_memory = get_system_memory();
    }

    guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
    guest_info->has_pci_info = has_pci_info;
    guest_info->isapc_ram_fw = false;
    guest_info->has_acpi_build = has_acpi_build;

    if (smbios_type1_defaults) {
        /* These values are guest ABI, do not change */
        smbios_set_type1_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
                                  args->machine->name);
    }

    /* allocate ram and load rom/bios */
    if (!xen_enabled()) {
        pc_memory_init(get_system_memory(),
                       args->kernel_filename, args->kernel_cmdline,
                       args->initrd_filename,
                       below_4g_mem_size, above_4g_mem_size,
                       rom_memory, &ram_memory, guest_info);
    }

    /* irq lines */
    gsi_state = g_malloc0(sizeof(*gsi_state));
    if (kvm_irqchip_in_kernel()) {
        kvm_pc_setup_irq_routing(pci_enabled);
        gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
                                 GSI_NUM_PINS);
    } else {
        gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
    }

    /* create pci host bus */
    q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));

    object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
    q35_host->mch.ram_memory = ram_memory;
    q35_host->mch.pci_address_space = pci_memory;
    q35_host->mch.system_memory = get_system_memory();
    q35_host->mch.address_space_io = get_system_io();
    q35_host->mch.below_4g_mem_size = below_4g_mem_size;
    q35_host->mch.above_4g_mem_size = above_4g_mem_size;
    q35_host->mch.guest_info = guest_info;
    /* pci */
    qdev_init_nofail(DEVICE(q35_host));
    phb = PCI_HOST_BRIDGE(q35_host);
    host_bus = phb->bus;
    /* create ISA bus */
    lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
                                          ICH9_LPC_FUNC), true,
                                          TYPE_ICH9_LPC_DEVICE);
    ich9_lpc = ICH9_LPC_DEVICE(lpc);
    ich9_lpc->pic = gsi;
    ich9_lpc->ioapic = gsi_state->ioapic_irq;
    pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
                 ICH9_LPC_NB_PIRQS);
    pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
    isa_bus = ich9_lpc->isa_bus;

    /*end early*/
    isa_bus_irqs(isa_bus, gsi);

    if (kvm_irqchip_in_kernel()) {
        i8259 = kvm_i8259_init(isa_bus);
    } else if (xen_enabled()) {
        i8259 = xen_interrupt_controller_init();
    } else {
        cpu_irq = pc_allocate_cpu_irq();
        i8259 = i8259_init(isa_bus, cpu_irq[0]);
    }

    for (i = 0; i < ISA_NUM_IRQS; i++) {
        gsi_state->i8259_irq[i] = i8259[i];
    }
    if (pci_enabled) {
        ioapic_init_gsi(gsi_state, NULL);
    }
    qdev_init_nofail(icc_bridge);

    pc_register_ferr_irq(gsi[13]);

    /* init basic PC hardware */
    pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false, 0xff0104);

    /* connect pm stuff to lpc */
    ich9_lpc_pm_init(lpc);

    /* ahci and SATA device, for q35 1 ahci controller is built-in */
    ahci = pci_create_simple_multifunction(host_bus,
                                           PCI_DEVFN(ICH9_SATA1_DEV,
                                                     ICH9_SATA1_FUNC),
                                           true, "ich9-ahci");
    idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
    idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");

    if (usb_enabled(false)) {
        /* Should we create 6 UHCI according to ich9 spec? */
        ehci_create_ich9_with_companions(host_bus, 0x1d);
    }

    /* TODO: Populate SPD eeprom data.  */
    smbus_eeprom_init(ich9_smb_init(host_bus,
                                    PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
                                    0xb100),
                      8, NULL, 0);

    pc_cmos_init(below_4g_mem_size, above_4g_mem_size, args->boot_order,
                 floppy, idebus[0], idebus[1], rtc_state);

    /* the rest devices to which pci devfn is automatically assigned */
    pc_vga_init(isa_bus, host_bus);
    pc_nic_init(isa_bus, host_bus);
    if (pci_enabled) {
        pc_pci_device_init(host_bus);
    }
}

static void pc_compat_1_7(QEMUMachineInitArgs *args)
{
    smbios_type1_defaults = false;
    gigabyte_align = false;
    option_rom_has_mr = true;
}

static void pc_compat_1_6(QEMUMachineInitArgs *args)
{
    pc_compat_1_7(args);
    has_pci_info = false;
    rom_file_has_mr = false;
    has_acpi_build = false;
}

static void pc_compat_1_5(QEMUMachineInitArgs *args)
{
    pc_compat_1_6(args);
}

static void pc_compat_1_4(QEMUMachineInitArgs *args)
{
    pc_compat_1_5(args);
    x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE);
    x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
}

static void pc_q35_init_1_7(QEMUMachineInitArgs *args)
{
    pc_compat_1_7(args);
    pc_q35_init(args);
}

static void pc_q35_init_1_6(QEMUMachineInitArgs *args)
{
    pc_compat_1_6(args);
    pc_q35_init(args);
}

static void pc_q35_init_1_5(QEMUMachineInitArgs *args)
{
    pc_compat_1_5(args);
    pc_q35_init(args);
}

static void pc_q35_init_1_4(QEMUMachineInitArgs *args)
{
    pc_compat_1_4(args);
    pc_q35_init(args);
}

#define PC_Q35_MACHINE_OPTIONS \
    PC_DEFAULT_MACHINE_OPTIONS, \
    .desc = "Standard PC (Q35 + ICH9, 2009)", \
    .hot_add_cpu = pc_hot_add_cpu

#define PC_Q35_2_0_MACHINE_OPTIONS                      \
    PC_Q35_MACHINE_OPTIONS,                             \
    .default_machine_opts = "firmware=bios-256k.bin"

static QEMUMachine pc_q35_machine_v2_0 = {
    PC_Q35_2_0_MACHINE_OPTIONS,
    .name = "pc-q35-2.0",
    .alias = "q35",
    .init = pc_q35_init,
};

#define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS

static QEMUMachine pc_q35_machine_v1_7 = {
    PC_Q35_1_7_MACHINE_OPTIONS,
    .name = "pc-q35-1.7",
    .init = pc_q35_init_1_7,
    .compat_props = (GlobalProperty[]) {
        PC_Q35_COMPAT_1_7,
        { /* end of list */ }
    },
};

#define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS

static QEMUMachine pc_q35_machine_v1_6 = {
    PC_Q35_1_6_MACHINE_OPTIONS,
    .name = "pc-q35-1.6",
    .init = pc_q35_init_1_6,
    .compat_props = (GlobalProperty[]) {
        PC_Q35_COMPAT_1_6,
        { /* end of list */ }
    },
};

static QEMUMachine pc_q35_machine_v1_5 = {
    PC_Q35_1_6_MACHINE_OPTIONS,
    .name = "pc-q35-1.5",
    .init = pc_q35_init_1_5,
    .compat_props = (GlobalProperty[]) {
        PC_Q35_COMPAT_1_5,
        { /* end of list */ }
    },
};

#define PC_Q35_1_4_MACHINE_OPTIONS \
    PC_Q35_1_6_MACHINE_OPTIONS, \
    .hot_add_cpu = NULL

static QEMUMachine pc_q35_machine_v1_4 = {
    PC_Q35_1_4_MACHINE_OPTIONS,
    .name = "pc-q35-1.4",
    .init = pc_q35_init_1_4,
    .compat_props = (GlobalProperty[]) {
        PC_COMPAT_1_4,
        { /* end of list */ }
    },
};

static void pc_q35_machine_init(void)
{
    qemu_register_machine(&pc_q35_machine_v2_0);
    qemu_register_machine(&pc_q35_machine_v1_7);
    qemu_register_machine(&pc_q35_machine_v1_6);
    qemu_register_machine(&pc_q35_machine_v1_5);
    qemu_register_machine(&pc_q35_machine_v1_4);
}

machine_init(pc_q35_machine_init);
Commit	Line	Data
df2d8b3e IY	1	/*
	2	* Q35 chipset based pc system emulator
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2009, 2010
	6	* Isaku Yamahata <yamahata at valinux co jp>
	7	* VA Linux Systems Japan K.K.
	8	* Copyright (C) 2012 Jason Baron <[email protected]>
	9	*
	10	* This is based on pc.c, but heavily modified.
	11	*
	12	* Permission is hereby granted, free of charge, to any person obtaining a copy
	13	* of this software and associated documentation files (the "Software"), to deal
	14	* in the Software without restriction, including without limitation the rights
	15	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	16	* copies of the Software, and to permit persons to whom the Software is
	17	* furnished to do so, subject to the following conditions:
	18	*
	19	* The above copyright notice and this permission notice shall be included in
	20	* all copies or substantial portions of the Software.
	21	*
	22	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	23	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	24	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	25	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	26	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	27	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	28	* THE SOFTWARE.
	29	*/
83c9f4ca	30	#include "hw/hw.h"
04920fc0	31	#include "hw/loader.h"
9c17d615	32	#include "sysemu/arch_init.h"
0d09e41a	33	#include "hw/i2c/smbus.h"
83c9f4ca	34	#include "hw/boards.h"
0d09e41a PB	35	#include "hw/timer/mc146818rtc.h"
0d09e41a PB	36	#include "hw/xen/xen.h"
9c17d615	37	#include "sysemu/kvm.h"
83c9f4ca	38	#include "hw/kvm/clock.h"
0d09e41a	39	#include "hw/pci-host/q35.h"
022c62cb	40	#include "exec/address-spaces.h"
0d09e41a	41	#include "hw/i386/ich9.h"
b29ad07e	42	#include "hw/i386/smbios.h"
df2d8b3e IY	43	#include "hw/ide/pci.h"
	44	#include "hw/ide/ahci.h"
	45	#include "hw/usb.h"
f0513d2c	46	#include "hw/cpu/icc_bus.h"
df2d8b3e IY	47
	48	/* ICH9 AHCI has 6 ports */
	49	#define MAX_SATA_PORTS 6
	50
7f1bb742	51	static bool has_pci_info;
72c194f7	52	static bool has_acpi_build = true;
b29ad07e	53	static bool smbios_type1_defaults = true;
4e17997d MT	54	/* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
	55	* host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte
	56	* pages in the host.
	57	*/
9a305c8f	58	static bool gigabyte_align = true;
3ab135f3	59
df2d8b3e IY	60	/* PC hardware initialisation */
	61	static void pc_q35_init(QEMUMachineInitArgs *args)
	62	{
df2d8b3e IY	63	ram_addr_t below_4g_mem_size, above_4g_mem_size;
df2d8b3e IY	64	Q35PCIHost *q35_host;
ce88812f	65	PCIHostState *phb;
df2d8b3e IY	66	PCIBus *host_bus;
	67	PCIDevice *lpc;
	68	BusState *idebus[MAX_SATA_PORTS];
	69	ISADevice *rtc_state;
	70	ISADevice *floppy;
	71	MemoryRegion *pci_memory;
	72	MemoryRegion *rom_memory;
	73	MemoryRegion *ram_memory;
	74	GSIState *gsi_state;
	75	ISABus *isa_bus;
	76	int pci_enabled = 1;
	77	qemu_irq *cpu_irq;
	78	qemu_irq *gsi;
	79	qemu_irq *i8259;
	80	int i;
	81	ICH9LPCState *ich9_lpc;
	82	PCIDevice *ahci;
f0513d2c	83	DeviceState *icc_bridge;
3459a625	84	PcGuestInfo *guest_info;
f0513d2c	85
254c1282 AP	86	if (xen_enabled() && xen_hvm_init(&ram_memory) != 0) {
	87	fprintf(stderr, "xen hardware virtual machine initialisation failed\n");
	88	exit(1);
	89	}
	90
f0513d2c IM	91	icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
	92	object_property_add_child(qdev_get_machine(), "icc-bridge",
	93	OBJECT(icc_bridge), NULL);
df2d8b3e	94
3b6fb9ca	95	pc_cpus_init(args->cpu_model, icc_bridge);
f7e4dd6c	96	pc_acpi_init("q35-acpi-dsdt.aml");
df2d8b3e	97
21022c92 JK	98	kvmclock_create();
21022c92 JK	99
4e17997d MT	100	/* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
	101	* and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
	102	* also known as MMCFG).
	103	* If it doesn't, we need to split it in chunks below and above 4G.
	104	* In any case, try to make sure that guest addresses aligned at
	105	* 1G boundaries get mapped to host addresses aligned at 1G boundaries.
	106	* For old machine types, use whatever split we used historically to avoid
	107	* breaking migration.
	108	*/
3b6fb9ca	109	if (args->ram_size >= 0xb0000000) {
9a305c8f GH	110	ram_addr_t lowmem = gigabyte_align ? 0x80000000 : 0xb0000000;
	111	above_4g_mem_size = args->ram_size - lowmem;
	112	below_4g_mem_size = lowmem;
df2d8b3e IY	113	} else {
df2d8b3e IY	114	above_4g_mem_size = 0;
3b6fb9ca	115	below_4g_mem_size = args->ram_size;
df2d8b3e IY	116	}
	117
	118	/* pci enabled */
	119	if (pci_enabled) {
	120	pci_memory = g_new(MemoryRegion, 1);
286690e3	121	memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
df2d8b3e IY	122	rom_memory = pci_memory;
	123	} else {
	124	pci_memory = NULL;
	125	rom_memory = get_system_memory();
	126	}
	127
3459a625	128	guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
f8c457b8	129	guest_info->has_pci_info = has_pci_info;
6dd2a5c9	130	guest_info->isapc_ram_fw = false;
72c194f7	131	guest_info->has_acpi_build = has_acpi_build;
3459a625	132
b29ad07e MA	133	if (smbios_type1_defaults) {
	134	/* These values are guest ABI, do not change */
	135	smbios_set_type1_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
	136	args->machine->name);
	137	}
	138
df2d8b3e IY	139	/* allocate ram and load rom/bios */
df2d8b3e IY	140	if (!xen_enabled()) {
3b6fb9ca MA	141	pc_memory_init(get_system_memory(),
	142	args->kernel_filename, args->kernel_cmdline,
	143	args->initrd_filename,
	144	below_4g_mem_size, above_4g_mem_size,
3459a625	145	rom_memory, &ram_memory, guest_info);
df2d8b3e IY	146	}
	147
	148	/* irq lines */
	149	gsi_state = g_malloc0(sizeof(*gsi_state));
	150	if (kvm_irqchip_in_kernel()) {
	151	kvm_pc_setup_irq_routing(pci_enabled);
	152	gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
	153	GSI_NUM_PINS);
	154	} else {
	155	gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
	156	}
	157
	158	/* create pci host bus */
	159	q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
	160
c52dc697	161	object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
df2d8b3e IY	162	q35_host->mch.ram_memory = ram_memory;
	163	q35_host->mch.pci_address_space = pci_memory;
	164	q35_host->mch.system_memory = get_system_memory();
c7e775e4	165	q35_host->mch.address_space_io = get_system_io();
df2d8b3e IY	166	q35_host->mch.below_4g_mem_size = below_4g_mem_size;
df2d8b3e IY	167	q35_host->mch.above_4g_mem_size = above_4g_mem_size;
3459a625	168	q35_host->mch.guest_info = guest_info;
df2d8b3e IY	169	/* pci */
df2d8b3e IY	170	qdev_init_nofail(DEVICE(q35_host));
ce88812f HT	171	phb = PCI_HOST_BRIDGE(q35_host);
ce88812f HT	172	host_bus = phb->bus;
df2d8b3e IY	173	/* create ISA bus */
	174	lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
	175	ICH9_LPC_FUNC), true,
	176	TYPE_ICH9_LPC_DEVICE);
	177	ich9_lpc = ICH9_LPC_DEVICE(lpc);
	178	ich9_lpc->pic = gsi;
	179	ich9_lpc->ioapic = gsi_state->ioapic_irq;
	180	pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
	181	ICH9_LPC_NB_PIRQS);
91c3f2f0	182	pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
df2d8b3e IY	183	isa_bus = ich9_lpc->isa_bus;
	184
	185	/end early/
	186	isa_bus_irqs(isa_bus, gsi);
	187
	188	if (kvm_irqchip_in_kernel()) {
	189	i8259 = kvm_i8259_init(isa_bus);
	190	} else if (xen_enabled()) {
	191	i8259 = xen_interrupt_controller_init();
	192	} else {
	193	cpu_irq = pc_allocate_cpu_irq();
	194	i8259 = i8259_init(isa_bus, cpu_irq[0]);
	195	}
	196
	197	for (i = 0; i < ISA_NUM_IRQS; i++) {
	198	gsi_state->i8259_irq[i] = i8259[i];
	199	}
	200	if (pci_enabled) {
	201	ioapic_init_gsi(gsi_state, NULL);
	202	}
f0513d2c	203	qdev_init_nofail(icc_bridge);
df2d8b3e IY	204
	205	pc_register_ferr_irq(gsi[13]);
	206
	207	/* init basic PC hardware */
7a10ef51	208	pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false, 0xff0104);
df2d8b3e IY	209
df2d8b3e IY	210	/* connect pm stuff to lpc */
a3ac6b53	211	ich9_lpc_pm_init(lpc);
df2d8b3e IY	212
	213	/* ahci and SATA device, for q35 1 ahci controller is built-in */
	214	ahci = pci_create_simple_multifunction(host_bus,
	215	PCI_DEVFN(ICH9_SATA1_DEV,
	216	ICH9_SATA1_FUNC),
	217	true, "ich9-ahci");
	218	idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
	219	idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
	220
	221	if (usb_enabled(false)) {
	222	/* Should we create 6 UHCI according to ich9 spec? */
	223	ehci_create_ich9_with_companions(host_bus, 0x1d);
	224	}
	225
	226	/* TODO: Populate SPD eeprom data. */
	227	smbus_eeprom_init(ich9_smb_init(host_bus,
	228	PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
	229	0xb100),
	230	8, NULL, 0);
	231
c1654732	232	pc_cmos_init(below_4g_mem_size, above_4g_mem_size, args->boot_order,
df2d8b3e IY	233	floppy, idebus[0], idebus[1], rtc_state);
	234
	235	/* the rest devices to which pci devfn is automatically assigned */
	236	pc_vga_init(isa_bus, host_bus);
df2d8b3e IY	237	pc_nic_init(isa_bus, host_bus);
	238	if (pci_enabled) {
	239	pc_pci_device_init(host_bus);
	240	}
	241	}
	242
b29ad07e MA	243	static void pc_compat_1_7(QEMUMachineInitArgs *args)
	244	{
	245	smbios_type1_defaults = false;
9a305c8f	246	gigabyte_align = false;
ac41881b	247	option_rom_has_mr = true;
b29ad07e MA	248	}
b29ad07e MA	249
89b439f3	250	static void pc_compat_1_6(QEMUMachineInitArgs *args)
f8c457b8	251	{
b29ad07e	252	pc_compat_1_7(args);
f8c457b8	253	has_pci_info = false;
98bc3ab0	254	rom_file_has_mr = false;
72c194f7	255	has_acpi_build = false;
f8c457b8 MT	256	}
f8c457b8 MT	257
89b439f3	258	static void pc_compat_1_5(QEMUMachineInitArgs *args)
9604f70f	259	{
89b439f3	260	pc_compat_1_6(args);
9604f70f MT	261	}
9604f70f MT	262
89b439f3	263	static void pc_compat_1_4(QEMUMachineInitArgs *args)
9953f882	264	{
396f79f4	265	pc_compat_1_5(args);
4458c236	266	x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE);
56383703	267	x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
89b439f3 EH	268	}
89b439f3 EH	269
b29ad07e MA	270	static void pc_q35_init_1_7(QEMUMachineInitArgs *args)
	271	{
	272	pc_compat_1_7(args);
	273	pc_q35_init(args);
	274	}
	275
89b439f3 EH	276	static void pc_q35_init_1_6(QEMUMachineInitArgs *args)
	277	{
	278	pc_compat_1_6(args);
	279	pc_q35_init(args);
	280	}
	281
	282	static void pc_q35_init_1_5(QEMUMachineInitArgs *args)
	283	{
	284	pc_compat_1_5(args);
	285	pc_q35_init(args);
	286	}
	287
	288	static void pc_q35_init_1_4(QEMUMachineInitArgs *args)
	289	{
	290	pc_compat_1_4(args);
	291	pc_q35_init(args);
9953f882 MA	292	}
9953f882 MA	293
a0dba644 MT	294	#define PC_Q35_MACHINE_OPTIONS \
	295	PC_DEFAULT_MACHINE_OPTIONS, \
	296	.desc = "Standard PC (Q35 + ICH9, 2009)", \
	297	.hot_add_cpu = pc_hot_add_cpu
	298
bcf2b7d2 GH	299	#define PC_Q35_2_0_MACHINE_OPTIONS \
	300	PC_Q35_MACHINE_OPTIONS, \
	301	.default_machine_opts = "firmware=bios-256k.bin"
aeca6e8d GH	302
	303	static QEMUMachine pc_q35_machine_v2_0 = {
	304	PC_Q35_2_0_MACHINE_OPTIONS,
	305	.name = "pc-q35-2.0",
	306	.alias = "q35",
	307	.init = pc_q35_init,
	308	};
	309
e9845f09 VM	310	#define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
	311
	312	static QEMUMachine pc_q35_machine_v1_7 = {
	313	PC_Q35_1_7_MACHINE_OPTIONS,
	314	.name = "pc-q35-1.7",
7a10ef51 LPF	315	.init = pc_q35_init_1_7,
	316	.compat_props = (GlobalProperty[]) {
	317	PC_Q35_COMPAT_1_7,
	318	{ /* end of list */ }
	319	},
e9845f09 VM	320	};
e9845f09 VM	321
a0dba644 MT	322	#define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
a0dba644 MT	323
45053fde	324	static QEMUMachine pc_q35_machine_v1_6 = {
a0dba644	325	PC_Q35_1_6_MACHINE_OPTIONS,
45053fde	326	.name = "pc-q35-1.6",
9604f70f	327	.init = pc_q35_init_1_6,
e9845f09	328	.compat_props = (GlobalProperty[]) {
7a10ef51	329	PC_Q35_COMPAT_1_6,
e9845f09 VM	330	{ /* end of list */ }
e9845f09 VM	331	},
45053fde EH	332	};
45053fde EH	333
bf3caa3d	334	static QEMUMachine pc_q35_machine_v1_5 = {
a0dba644	335	PC_Q35_1_6_MACHINE_OPTIONS,
bf3caa3d	336	.name = "pc-q35-1.5",
f8c457b8	337	.init = pc_q35_init_1_5,
ffce9ebb	338	.compat_props = (GlobalProperty[]) {
7a10ef51	339	PC_Q35_COMPAT_1_5,
ffce9ebb EH	340	{ /* end of list */ }
ffce9ebb EH	341	},
df2d8b3e IY	342	};
df2d8b3e IY	343
a0dba644 MT	344	#define PC_Q35_1_4_MACHINE_OPTIONS \
	345	PC_Q35_1_6_MACHINE_OPTIONS, \
	346	.hot_add_cpu = NULL
	347
bf3caa3d	348	static QEMUMachine pc_q35_machine_v1_4 = {
a0dba644	349	PC_Q35_1_4_MACHINE_OPTIONS,
bf3caa3d	350	.name = "pc-q35-1.4",
9953f882	351	.init = pc_q35_init_1_4,
bf3caa3d PB	352	.compat_props = (GlobalProperty[]) {
	353	PC_COMPAT_1_4,
	354	{ /* end of list */ }
	355	},
bf3caa3d PB	356	};
bf3caa3d PB	357
df2d8b3e IY	358	static void pc_q35_machine_init(void)
df2d8b3e IY	359	{
aeca6e8d	360	qemu_register_machine(&pc_q35_machine_v2_0);
e9845f09	361	qemu_register_machine(&pc_q35_machine_v1_7);
45053fde	362	qemu_register_machine(&pc_q35_machine_v1_6);
bf3caa3d PB	363	qemu_register_machine(&pc_q35_machine_v1_5);
bf3caa3d PB	364	qemu_register_machine(&pc_q35_machine_v1_4);
df2d8b3e IY	365	}
	366
	367	machine_init(pc_q35_machine_init);