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target/arm: Convert Neon 2-reg-scalar VQRDMLAH, VQRDMLSH to decodetree
[qemu.git] / target / arm / neon-dp.decode
CommitLineData
625e3dd4
PM		 1# AArch32 Neon data-processing instruction descriptions
2#
3# Copyright (c) 2020 Linaro, Ltd
4#
5# This library is free software; you can redistribute it and/or
6# modify it under the terms of the GNU Lesser General Public
7# License as published by the Free Software Foundation; either
8# version 2 of the License, or (at your option) any later version.
9#
10# This library is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13# Lesser General Public License for more details.
14#
15# You should have received a copy of the GNU Lesser General Public
16# License along with this library; if not, see <http://www.gnu.org/licenses/>.
17
18#
19# This file is processed by scripts/decodetree.py
20#
a4e143ac
PM		 21# VFP/Neon register fields; same as vfp.decode
22%vm_dp 5:1 0:4
23%vn_dp 7:1 16:4
24%vd_dp 22:1 12:4
625e3dd4
PM		 25
26# Encodings for Neon data processing instructions where the T32 encoding
27# is a simple transformation of the A32 encoding.
28# More specifically, this file covers instructions where the A32 encoding is
29# 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
30# and the T32 encoding is
31# 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
32# This file works on the A32 encoding only; calling code for T32 has to
33# transform the insn into the A32 version first.
a4e143ac
PM		 34
35######################################################################
36# 3-reg-same grouping:
37# 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
38######################################################################
39
40&3same vm vn vd q size
41
42@3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
43 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
44
059c2398
PM		 45@3same_q0 .... ... . . . size:2 .... .... .... . 0 . . .... \
46 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
47
a26a352b
PM		 48# For FP insns the high bit of 'size' is used as part of opcode decode
49@3same_fp .... ... . . . . size:1 .... .... .... . q:1 . . .... \
50 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
ab978335
PM		 51@3same_fp_q0 .... ... . . . . size:1 .... .... .... . 0 . . .... \
52 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
a26a352b 53
cb294bca
PM		 54VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
55VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
7a9497f1
PM		 56VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
57VQADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same
58
8e44d03f
PM		 59VRHADD_S_3s 1111 001 0 0 . .. .... .... 0001 . . . 0 .... @3same
60VRHADD_U_3s 1111 001 1 0 . .. .... .... 0001 . . . 0 .... @3same
61
35a548ed
PM		 62@3same_logic .... ... . . . .. .... .... .... . q:1 .. .... \
63 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
64
65VAND_3s 1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic
66VBIC_3s 1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic
67VORR_3s 1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic
68VORN_3s 1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic
69VEOR_3s 1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic
70VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
71VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
72VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
73
8e44d03f
PM		 74VHSUB_S_3s 1111 001 0 0 . .. .... .... 0010 . . . 0 .... @3same
75VHSUB_U_3s 1111 001 1 0 . .. .... .... 0010 . . . 0 .... @3same
76
7a9497f1
PM		 77VQSUB_S_3s 1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same
78VQSUB_U_3s 1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same
79
02bd0cdb
PM		 80VCGT_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
81VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
82VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
83VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
84
e9eee531
RH		 85# The _rev suffix indicates that Vn and Vm are reversed. This is
86# the case for shifts. In the Arm ARM these insns are documented
87# with the Vm and Vn fields in their usual places, but in the
88# assembly the operands are listed "backwards", ie in the order
89# Dd, Dm, Dn where other insns use Dd, Dn, Dm. For QEMU we choose
90# to consider Vm and Vn as being in different fields in the insn,
91# which allows us to avoid special-casing shifts in the trans_
92# function code. We would otherwise need to manually swap the operands
93# over to call Neon helper functions that are shared with AArch64,
94# which does not have this odd reversed-operand situation.
95@3same_rev .... ... . . . size:2 .... .... .... . q:1 . . .... \
96 &3same vn=%vm_dp vm=%vn_dp vd=%vd_dp
97
98VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same_rev
99VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev
0de34fd4 100
35d4352f
PM		 101# Insns operating on 64-bit elements (size!=0b11 handled elsewhere)
102# The _rev suffix indicates that Vn and Vm are reversed (as explained
103# by the comment for the @3same_rev format).
104@3same_64_rev .... ... . . . 11 .... .... .... . q:1 . . .... \
105 &3same vm=%vn_dp vn=%vm_dp vd=%vd_dp size=3
106
6812dfdc
PM		 107{
108 VQSHL_S64_3s 1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
109 VQSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_rev
110}
111{
112 VQSHL_U64_3s 1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
113 VQSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_rev
114}
115{
116 VRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
117 VRSHL_S_3s 1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_rev
118}
119{
120 VRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
121 VRSHL_U_3s 1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_rev
122}
123{
124 VQRSHL_S64_3s 1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
125 VQRSHL_S_3s 1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_rev
126}
127{
128 VQRSHL_U64_3s 1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
129 VQRSHL_U_3s 1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_rev
130}
35d4352f 131
36b59310
PM		 132VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
133VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
134VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
135VMIN_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
136
7715098f
PM		 137VABD_S_3s 1111 001 0 0 . .. .... .... 0111 . . . 0 .... @3same
138VABD_U_3s 1111 001 1 0 . .. .... .... 0111 . . . 0 .... @3same
139
140VABA_S_3s 1111 001 0 0 . .. .... .... 0111 . . . 1 .... @3same
141VABA_U_3s 1111 001 1 0 . .. .... .... 0111 . . . 1 .... @3same
142
a4e143ac
PM		 143VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
144VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
02bd0cdb
PM		 145
146VTST_3s 1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
147VCEQ_3s 1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
0de34fd4
PM		 148
149VMLA_3s 1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same
150VMLS_3s 1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same
151
152VMUL_3s 1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
153VMUL_p_3s 1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
a0635695 154
059c2398
PM		 155VPMAX_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 0 .... @3same_q0
156VPMAX_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 0 .... @3same_q0
157
158VPMIN_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0
159VPMIN_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0
160
7ecc28bc
PM		 161VQDMULH_3s 1111 001 0 0 . .. .... .... 1011 . . . 0 .... @3same
162VQRDMULH_3s 1111 001 1 0 . .. .... .... 1011 . . . 0 .... @3same
163
fa22827d
PM		 164VPADD_3s 1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0
165
a0635695 166VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
21290edf 167
effa992f
RH		 168@3same_crypto .... .... .... .... .... .... .... .... \
169 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
170
afc8b7d3
RH		 171SHA1C_3s 1111 001 0 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
172SHA1P_3s 1111 001 0 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
173SHA1M_3s 1111 001 0 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
174SHA1SU0_3s 1111 001 0 0 . 11 .... .... 1100 . 1 . 0 .... @3same_crypto
effa992f
RH		 175SHA256H_3s 1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
176SHA256H2_3s 1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
177SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
21290edf 178
e95485f8
PM		 179VFMA_fp_3s 1111 001 0 0 . 0 . .... .... 1100 ... 1 .... @3same_fp
180VFMS_fp_3s 1111 001 0 0 . 1 . .... .... 1100 ... 1 .... @3same_fp
181
a0635695 182VQRDMLSH_3s 1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same
a26a352b
PM		 183
184VADD_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp
185VSUB_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
ab978335 186VPADD_fp_3s 1111 001 1 0 . 0 . .... .... 1101 ... 0 .... @3same_fp_q0
a26a352b 187VABD_fp_3s 1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
8aa71ead
PM		 188VMLA_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
189VMLS_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 1 .... @3same_fp
190VMUL_fp_3s 1111 001 1 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
727ff1d6
PM		 191VCEQ_fp_3s 1111 001 0 0 . 0 . .... .... 1110 ... 0 .... @3same_fp
192VCGE_fp_3s 1111 001 1 0 . 0 . .... .... 1110 ... 0 .... @3same_fp
193VACGE_fp_3s 1111 001 1 0 . 0 . .... .... 1110 ... 1 .... @3same_fp
194VCGT_fp_3s 1111 001 1 0 . 1 . .... .... 1110 ... 0 .... @3same_fp
195VACGT_fp_3s 1111 001 1 0 . 1 . .... .... 1110 ... 1 .... @3same_fp
d5fdf9e9
PM		 196VMAX_fp_3s 1111 001 0 0 . 0 . .... .... 1111 ... 0 .... @3same_fp
197VMIN_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 0 .... @3same_fp
ab978335
PM		 198VPMAX_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 0 .... @3same_fp_q0
199VPMIN_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 0 .... @3same_fp_q0
d5fdf9e9
PM		 200VRECPS_fp_3s 1111 001 0 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
201VRSQRTS_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
202VMAXNM_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
203VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
d3c8c736
PM		 204
205######################################################################
206# 2-reg-and-shift grouping:
207# 1111 001 U 1 D immH:3 immL:3 Vd:4 opc:4 L Q M 1 Vm:4
208######################################################################
209&2reg_shift vm vd q shift size
210
66432d6b
PM		 211# Right shifts are encoded as N - shift, where N is the element size in bits.
212%neon_rshift_i6 16:6 !function=rsub_64
213%neon_rshift_i5 16:5 !function=rsub_32
214%neon_rshift_i4 16:4 !function=rsub_16
215%neon_rshift_i3 16:3 !function=rsub_8
216
217@2reg_shr_d .... ... . . . ...... .... .... 1 q:1 . . .... \
218 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 shift=%neon_rshift_i6
219@2reg_shr_s .... ... . . . 1 ..... .... .... 0 q:1 . . .... \
220 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
221@2reg_shr_h .... ... . . . 01 .... .... .... 0 q:1 . . .... \
222 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
223@2reg_shr_b .... ... . . . 001 ... .... .... 0 q:1 . . .... \
224 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i3
225
d3c8c736
PM		 226@2reg_shl_d .... ... . . . shift:6 .... .... 1 q:1 . . .... \
227 &2reg_shift vm=%vm_dp vd=%vd_dp size=3
228@2reg_shl_s .... ... . . . 1 shift:5 .... .... 0 q:1 . . .... \
229 &2reg_shift vm=%vm_dp vd=%vd_dp size=2
230@2reg_shl_h .... ... . . . 01 shift:4 .... .... 0 q:1 . . .... \
231 &2reg_shift vm=%vm_dp vd=%vd_dp size=1
232@2reg_shl_b .... ... . . . 001 shift:3 .... .... 0 q:1 . . .... \
233 &2reg_shift vm=%vm_dp vd=%vd_dp size=0
234
712182d3
PM		 235# Narrowing right shifts: here the Q bit is part of the opcode decode
236@2reg_shrn_d .... ... . . . 1 ..... .... .... 0 . . . .... \
237 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 q=0 \
238 shift=%neon_rshift_i5
239@2reg_shrn_s .... ... . . . 01 .... .... .... 0 . . . .... \
240 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0 \
241 shift=%neon_rshift_i4
242@2reg_shrn_h .... ... . . . 001 ... .... .... 0 . . . .... \
243 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
244 shift=%neon_rshift_i3
245
968bf842
PM		 246# Long left shifts: again Q is part of opcode decode
247@2reg_shll_s .... ... . . . 1 shift:5 .... .... 0 . . . .... \
248 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0
249@2reg_shll_h .... ... . . . 01 shift:4 .... .... 0 . . . .... \
250 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0
251@2reg_shll_b .... ... . . . 001 shift:3 .... .... 0 . . . .... \
252 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
253
3da26f11
PM		 254# We use size=0 for fp32 and size=1 for fp16 to match the 3-same encodings.
255@2reg_vcvt .... ... . . . 1 ..... .... .... . q:1 . . .... \
256 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i5
257
66432d6b
PM		 258VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
259VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
260VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
261VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
262
263VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
264VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
265VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
266VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
267
434f71ef
PM		 268VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
269VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
270VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
271VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
272
273VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
274VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
275VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
276VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
277
278VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
279VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
280VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
281VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
282
283VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
284VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
285VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
286VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
287
288VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
289VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
290VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
291VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
292
293VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
294VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
295VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
296VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
297
298VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_d
299VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_s
300VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_h
301VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_b
302
d3c8c736
PM		 303VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
304VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
305VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
306VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
307
308VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
309VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
310VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
311VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
37bfce81
PM		 312
313VQSHLU_64_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_d
314VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_s
315VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_h
316VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_b
317
318VQSHL_S_64_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
319VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
320VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
321VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
322
323VQSHL_U_64_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
324VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
325VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
326VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
712182d3
PM		 327
328VSHRN_64_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
329VSHRN_32_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
330VSHRN_16_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
331
332VRSHRN_64_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
333VRSHRN_32_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
334VRSHRN_16_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
335
336VQSHRUN_64_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
337VQSHRUN_32_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
338VQSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
339
340VQRSHRUN_64_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
341VQRSHRUN_32_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
342VQRSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
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PM		 343
344# VQSHRN with signed input
345VQSHRN_S64_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
346VQSHRN_S32_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
347VQSHRN_S16_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
348
349# VQRSHRN with signed input
350VQRSHRN_S64_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
351VQRSHRN_S32_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
352VQRSHRN_S16_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
353
354# VQSHRN with unsigned input
355VQSHRN_U64_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
356VQSHRN_U32_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
357VQSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
358
359# VQRSHRN with unsigned input
360VQRSHRN_U64_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
361VQRSHRN_U32_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
362VQRSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
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PM		 363
364VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
365VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
366VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
367
368VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
369VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
370VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
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PM		 371
372# VCVT fixed<->float conversions
373# TODO: FP16 fixed<->float conversions are opc==0b1100 and 0b1101
374VCVT_SF_2sh 1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
375VCVT_UF_2sh 1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
376VCVT_FS_2sh 1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
377VCVT_FU_2sh 1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
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PM		 378
379######################################################################
380# 1-reg-and-modified-immediate grouping:
381# 1111 001 i 1 D 000 imm:3 Vd:4 cmode:4 0 Q op 1 Vm:4
382######################################################################
383
384&1reg_imm vd q imm cmode op
385
386%asimd_imm_value 24:1 16:3 0:4
387
388@1reg_imm .... ... . . . ... ... .... .... . q:1 . . .... \
389 &1reg_imm imm=%asimd_imm_value vd=%vd_dp
390
391# The cmode/op bits here decode VORR/VBIC/VMOV/VMNV, but
392# not in a way we can conveniently represent in decodetree without
393# a lot of repetition:
394# VORR: op=0, (cmode & 1) && cmode < 12
395# VBIC: op=1, (cmode & 1) && cmode < 12
396# VMOV: everything else
397# So we have a single decode line and check the cmode/op in the
398# trans function.
399Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
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PM		 400
401######################################################################
402# Within the "two registers, or three registers of different lengths"
403# grouping ([23,4]=0b10), bits [21:20] are either part of the opcode
404# decode: 0b11 for VEXT, two-reg-misc, VTBL, and duplicate-scalar;
405# or they are a size field for the three-reg-different-lengths and
406# two-reg-and-scalar insn groups (where size cannot be 0b11). This
407# is slightly awkward for decodetree: we handle it with this
408# non-exclusive group which contains within it two exclusive groups:
409# one for the size=0b11 patterns, and one for the size-not-0b11
410# patterns. This allows us to check that none of the insns within
411# each subgroup accidentally overlap each other. Note that all the
412# trans functions for the size-not-0b11 patterns must check and
413# return false for size==3.
414######################################################################
415{
416 # 0b11 subgroup will go here
417
418 # Subgroup for size != 0b11
419 [
420 ##################################################################
421 # 3-reg-different-length grouping:
422 # 1111 001 U 1 D sz!=11 Vn:4 Vd:4 opc:4 N 0 M 0 Vm:4
423 ##################################################################
424
425 &3diff vm vn vd size
426
427 @3diff .... ... . . . size:2 .... .... .... . . . . .... \
428 &3diff vm=%vm_dp vn=%vn_dp vd=%vd_dp
429
430 VADDL_S_3d 1111 001 0 1 . .. .... .... 0000 . 0 . 0 .... @3diff
431 VADDL_U_3d 1111 001 1 1 . .. .... .... 0000 . 0 . 0 .... @3diff
432
433 VADDW_S_3d 1111 001 0 1 . .. .... .... 0001 . 0 . 0 .... @3diff
434 VADDW_U_3d 1111 001 1 1 . .. .... .... 0001 . 0 . 0 .... @3diff
435
436 VSUBL_S_3d 1111 001 0 1 . .. .... .... 0010 . 0 . 0 .... @3diff
437 VSUBL_U_3d 1111 001 1 1 . .. .... .... 0010 . 0 . 0 .... @3diff
438
439 VSUBW_S_3d 1111 001 0 1 . .. .... .... 0011 . 0 . 0 .... @3diff
440 VSUBW_U_3d 1111 001 1 1 . .. .... .... 0011 . 0 . 0 .... @3diff
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PM		 441
442 VADDHN_3d 1111 001 0 1 . .. .... .... 0100 . 0 . 0 .... @3diff
443 VRADDHN_3d 1111 001 1 1 . .. .... .... 0100 . 0 . 0 .... @3diff
444
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PM		 445 VABAL_S_3d 1111 001 0 1 . .. .... .... 0101 . 0 . 0 .... @3diff
446 VABAL_U_3d 1111 001 1 1 . .. .... .... 0101 . 0 . 0 .... @3diff
447
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PM		 448 VSUBHN_3d 1111 001 0 1 . .. .... .... 0110 . 0 . 0 .... @3diff
449 VRSUBHN_3d 1111 001 1 1 . .. .... .... 0110 . 0 . 0 .... @3diff
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PM		 450
451 VABDL_S_3d 1111 001 0 1 . .. .... .... 0111 . 0 . 0 .... @3diff
452 VABDL_U_3d 1111 001 1 1 . .. .... .... 0111 . 0 . 0 .... @3diff
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PM		 453
454 VMLAL_S_3d 1111 001 0 1 . .. .... .... 1000 . 0 . 0 .... @3diff
455 VMLAL_U_3d 1111 001 1 1 . .. .... .... 1000 . 0 . 0 .... @3diff
456
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PM		 457 VQDMLAL_3d 1111 001 0 1 . .. .... .... 1001 . 0 . 0 .... @3diff
458
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PM		 459 VMLSL_S_3d 1111 001 0 1 . .. .... .... 1010 . 0 . 0 .... @3diff
460 VMLSL_U_3d 1111 001 1 1 . .. .... .... 1010 . 0 . 0 .... @3diff
461
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PM		 462 VQDMLSL_3d 1111 001 0 1 . .. .... .... 1011 . 0 . 0 .... @3diff
463
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PM		 464 VMULL_S_3d 1111 001 0 1 . .. .... .... 1100 . 0 . 0 .... @3diff
465 VMULL_U_3d 1111 001 1 1 . .. .... .... 1100 . 0 . 0 .... @3diff
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PM		 466
467 VQDMULL_3d 1111 001 0 1 . .. .... .... 1101 . 0 . 0 .... @3diff
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PM		 468
469 VMULL_P_3d 1111 001 0 1 . .. .... .... 1110 . 0 . 0 .... @3diff
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PM		 470
471 ##################################################################
472 # 2-regs-plus-scalar grouping:
473 # 1111 001 Q 1 D sz!=11 Vn:4 Vd:4 opc:4 N 1 M 0 Vm:4
474 ##################################################################
475 &2scalar vm vn vd size q
476
477 @2scalar .... ... q:1 . . size:2 .... .... .... . . . . .... \
478 &2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp
479
480 VMLA_2sc 1111 001 . 1 . .. .... .... 0000 . 1 . 0 .... @2scalar
85ac9aef 481 VMLA_F_2sc 1111 001 . 1 . .. .... .... 0001 . 1 . 0 .... @2scalar
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PM		 482
483 VMLS_2sc 1111 001 . 1 . .. .... .... 0100 . 1 . 0 .... @2scalar
85ac9aef 484 VMLS_F_2sc 1111 001 . 1 . .. .... .... 0101 . 1 . 0 .... @2scalar
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PM		 485
486 VMUL_2sc 1111 001 . 1 . .. .... .... 1000 . 1 . 0 .... @2scalar
85ac9aef 487 VMUL_F_2sc 1111 001 . 1 . .. .... .... 1001 . 1 . 0 .... @2scalar
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PM		 488
489 VQDMULH_2sc 1111 001 . 1 . .. .... .... 1100 . 1 . 0 .... @2scalar
490 VQRDMULH_2sc 1111 001 . 1 . .. .... .... 1101 . 1 . 0 .... @2scalar
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PM		 491
492 VQRDMLAH_2sc 1111 001 . 1 . .. .... .... 1110 . 1 . 0 .... @2scalar
493 VQRDMLSH_2sc 1111 001 . 1 . .. .... .... 1111 . 1 . 0 .... @2scalar
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PM		 494 ]
495}
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