target/arm: Convert Neon VPMAX/VPMIN 3-reg-same insns to decodetree

[qemu.git] / target / arm / neon-dp.decode

# AArch32 Neon data-processing instruction descriptions
#
#  Copyright (c) 2020 Linaro, Ltd
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.

#
# This file is processed by scripts/decodetree.py
#
# VFP/Neon register fields; same as vfp.decode
%vm_dp  5:1 0:4
%vn_dp  7:1 16:4
%vd_dp  22:1 12:4

# Encodings for Neon data processing instructions where the T32 encoding
# is a simple transformation of the A32 encoding.
# More specifically, this file covers instructions where the A32 encoding is
#   0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
# and the T32 encoding is
#   0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
# This file works on the A32 encoding only; calling code for T32 has to
# transform the insn into the A32 version first.

######################################################################
# 3-reg-same grouping:
# 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
######################################################################

&3same vm vn vd q size

@3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp

@3same_q0        .... ... . . . size:2 .... .... .... . 0 . . .... \
                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0

VHADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
VHADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
VQADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
VQADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same

VRHADD_S_3s      1111 001 0 0 . .. .... .... 0001 . . . 0 .... @3same
VRHADD_U_3s      1111 001 1 0 . .. .... .... 0001 . . . 0 .... @3same

@3same_logic     .... ... . . . .. .... .... .... . q:1 .. .... \
                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0

VAND_3s          1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic
VBIC_3s          1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic
VORR_3s          1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic
VORN_3s          1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic
VEOR_3s          1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic
VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic

VHSUB_S_3s       1111 001 0 0 . .. .... .... 0010 . . . 0 .... @3same
VHSUB_U_3s       1111 001 1 0 . .. .... .... 0010 . . . 0 .... @3same

VQSUB_S_3s       1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same
VQSUB_U_3s       1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same

VCGT_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
VCGE_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same

# The _rev suffix indicates that Vn and Vm are reversed. This is
# the case for shifts. In the Arm ARM these insns are documented
# with the Vm and Vn fields in their usual places, but in the
# assembly the operands are listed "backwards", ie in the order
# Dd, Dm, Dn where other insns use Dd, Dn, Dm. For QEMU we choose
# to consider Vm and Vn as being in different fields in the insn,
# which allows us to avoid special-casing shifts in the trans_
# function code. We would otherwise need to manually swap the operands
# over to call Neon helper functions that are shared with AArch64,
# which does not have this odd reversed-operand situation.
@3same_rev       .... ... . . . size:2 .... .... .... . q:1 . . .... \
                 &3same vn=%vm_dp vm=%vn_dp vd=%vd_dp

VSHL_S_3s        1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same_rev
VSHL_U_3s        1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev

# Insns operating on 64-bit elements (size!=0b11 handled elsewhere)
# The _rev suffix indicates that Vn and Vm are reversed (as explained
# by the comment for the @3same_rev format).
@3same_64_rev    .... ... . . . 11 .... .... .... . q:1 . . .... \
                 &3same vm=%vn_dp vn=%vm_dp vd=%vd_dp size=3

{
  VQSHL_S64_3s   1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
  VQSHL_S_3s     1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_rev
}
{
  VQSHL_U64_3s   1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_64_rev
  VQSHL_U_3s     1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_rev
}
{
  VRSHL_S64_3s   1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
  VRSHL_S_3s     1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_rev
}
{
  VRSHL_U64_3s   1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_64_rev
  VRSHL_U_3s     1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_rev
}
{
  VQRSHL_S64_3s  1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
  VQRSHL_S_3s    1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_rev
}
{
  VQRSHL_U64_3s  1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_64_rev
  VQRSHL_U_3s    1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_rev
}

VMAX_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
VMAX_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
VMIN_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
VMIN_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same

VABD_S_3s        1111 001 0 0 . .. .... .... 0111 . . . 0 .... @3same
VABD_U_3s        1111 001 1 0 . .. .... .... 0111 . . . 0 .... @3same

VABA_S_3s        1111 001 0 0 . .. .... .... 0111 . . . 1 .... @3same
VABA_U_3s        1111 001 1 0 . .. .... .... 0111 . . . 1 .... @3same

VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same

VTST_3s          1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
VCEQ_3s          1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same

VMLA_3s          1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same
VMLS_3s          1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same

VMUL_3s          1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
VMUL_p_3s        1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same

VPMAX_S_3s       1111 001 0 0 . .. .... .... 1010 . . . 0 .... @3same_q0
VPMAX_U_3s       1111 001 1 0 . .. .... .... 1010 . . . 0 .... @3same_q0

VPMIN_S_3s       1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0
VPMIN_U_3s       1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0

VQRDMLAH_3s      1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same

SHA1_3s          1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \
                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
SHA256H_3s       1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... \
                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
SHA256H2_3s      1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... \
                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... \
                 vm=%vm_dp vn=%vn_dp vd=%vd_dp

VQRDMLSH_3s      1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same