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CommitLineData
c896fe29
FB
1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
c896fe29
FB
25/* define it to use liveness analysis (better code) */
26#define USE_LIVENESS_ANALYSIS
8f2e8c07 27#define USE_TCG_OPTIMIZATIONS
c896fe29 28
cca82982
AJ
29#include "config.h"
30
813da627
RH
31/* Define to jump the ELF file used to communicate with GDB. */
32#undef DEBUG_JIT
33
a6c6f76c 34#if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
cca82982
AJ
35/* define it to suppress various consistency checks (faster) */
36#define NDEBUG
37#endif
38
ca10f867 39#include "qemu-common.h"
1de7afc9
PB
40#include "qemu/cache-utils.h"
41#include "qemu/host-utils.h"
42#include "qemu/timer.h"
c896fe29 43
c5d3c498 44/* Note: the long term plan is to reduce the dependencies on the QEMU
c896fe29
FB
45 CPU definitions. Currently they are used for qemu_ld/st
46 instructions */
47#define NO_CPU_IO_DEFS
48#include "cpu.h"
c896fe29
FB
49
50#include "tcg-op.h"
813da627 51
edee2579 52#if UINTPTR_MAX == UINT32_MAX
813da627 53# define ELF_CLASS ELFCLASS32
edee2579
RH
54#else
55# define ELF_CLASS ELFCLASS64
813da627
RH
56#endif
57#ifdef HOST_WORDS_BIGENDIAN
58# define ELF_DATA ELFDATA2MSB
59#else
60# define ELF_DATA ELFDATA2LSB
61#endif
62
c896fe29
FB
63#include "elf.h"
64
c0ad3001 65/* Forward declarations for functions declared in tcg-target.c and used here. */
e4d58b41
RH
66static void tcg_target_init(TCGContext *s);
67static void tcg_target_qemu_prologue(TCGContext *s);
1813e175 68static void patch_reloc(tcg_insn_unit *code_ptr, int type,
2ba7fae2 69 intptr_t value, intptr_t addend);
c896fe29 70
497a22eb
RH
71/* The CIE and FDE header definitions will be common to all hosts. */
72typedef struct {
73 uint32_t len __attribute__((aligned((sizeof(void *)))));
74 uint32_t id;
75 uint8_t version;
76 char augmentation[1];
77 uint8_t code_align;
78 uint8_t data_align;
79 uint8_t return_column;
80} DebugFrameCIE;
81
82typedef struct QEMU_PACKED {
83 uint32_t len __attribute__((aligned((sizeof(void *)))));
84 uint32_t cie_offset;
edee2579
RH
85 uintptr_t func_start;
86 uintptr_t func_len;
497a22eb
RH
87} DebugFrameFDEHeader;
88
2c90784a
RH
89typedef struct QEMU_PACKED {
90 DebugFrameCIE cie;
91 DebugFrameFDEHeader fde;
92} DebugFrameHeader;
93
813da627 94static void tcg_register_jit_int(void *buf, size_t size,
2c90784a
RH
95 const void *debug_frame,
96 size_t debug_frame_size)
813da627
RH
97 __attribute__((unused));
98
c0ad3001
SW
99/* Forward declarations for functions declared and used in tcg-target.c. */
100static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str);
2a534aff 101static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
a05b5b9b 102 intptr_t arg2);
2a534aff 103static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
c0ad3001 104static void tcg_out_movi(TCGContext *s, TCGType type,
2a534aff 105 TCGReg ret, tcg_target_long arg);
c0ad3001
SW
106static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
107 const int *const_args);
2a534aff 108static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
a05b5b9b 109 intptr_t arg2);
cf066674 110static void tcg_out_call(TCGContext *s, tcg_insn_unit *target);
f6c6afc1 111static int tcg_target_const_match(tcg_target_long val, TCGType type,
c0ad3001 112 const TCGArgConstraint *arg_ct);
9ecefc84
RH
113static void tcg_out_tb_init(TCGContext *s);
114static void tcg_out_tb_finalize(TCGContext *s);
115
c0ad3001 116
8399ad59 117TCGOpDef tcg_op_defs[] = {
0e2029a0 118#define DEF(s, oargs, iargs, cargs, flags) { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags },
c896fe29
FB
119#include "tcg-opc.h"
120#undef DEF
c896fe29 121};
2a24374a 122const size_t tcg_op_defs_max = ARRAY_SIZE(tcg_op_defs);
c896fe29 123
b1d8e52e
BS
124static TCGRegSet tcg_target_available_regs[2];
125static TCGRegSet tcg_target_call_clobber_regs;
c896fe29 126
1813e175 127#if TCG_TARGET_INSN_UNIT_SIZE == 1
c896fe29
FB
128static inline void tcg_out8(TCGContext *s, uint8_t v)
129{
130 *s->code_ptr++ = v;
131}
132
1813e175 133static inline void tcg_patch8(tcg_insn_unit *p, uint8_t v)
5c53bb81 134{
1813e175 135 *p = v;
5c53bb81 136}
1813e175 137#endif
5c53bb81 138
1813e175 139#if TCG_TARGET_INSN_UNIT_SIZE <= 2
c896fe29
FB
140static inline void tcg_out16(TCGContext *s, uint16_t v)
141{
1813e175
RH
142 if (TCG_TARGET_INSN_UNIT_SIZE == 2) {
143 *s->code_ptr++ = v;
144 } else {
145 tcg_insn_unit *p = s->code_ptr;
146 memcpy(p, &v, sizeof(v));
147 s->code_ptr = p + (2 / TCG_TARGET_INSN_UNIT_SIZE);
148 }
c896fe29
FB
149}
150
1813e175 151static inline void tcg_patch16(tcg_insn_unit *p, uint16_t v)
5c53bb81 152{
1813e175
RH
153 if (TCG_TARGET_INSN_UNIT_SIZE == 2) {
154 *p = v;
155 } else {
156 memcpy(p, &v, sizeof(v));
157 }
5c53bb81 158}
1813e175 159#endif
5c53bb81 160
1813e175 161#if TCG_TARGET_INSN_UNIT_SIZE <= 4
c896fe29
FB
162static inline void tcg_out32(TCGContext *s, uint32_t v)
163{
1813e175
RH
164 if (TCG_TARGET_INSN_UNIT_SIZE == 4) {
165 *s->code_ptr++ = v;
166 } else {
167 tcg_insn_unit *p = s->code_ptr;
168 memcpy(p, &v, sizeof(v));
169 s->code_ptr = p + (4 / TCG_TARGET_INSN_UNIT_SIZE);
170 }
c896fe29
FB
171}
172
1813e175 173static inline void tcg_patch32(tcg_insn_unit *p, uint32_t v)
5c53bb81 174{
1813e175
RH
175 if (TCG_TARGET_INSN_UNIT_SIZE == 4) {
176 *p = v;
177 } else {
178 memcpy(p, &v, sizeof(v));
179 }
5c53bb81 180}
1813e175 181#endif
5c53bb81 182
1813e175 183#if TCG_TARGET_INSN_UNIT_SIZE <= 8
ac26eb69
RH
184static inline void tcg_out64(TCGContext *s, uint64_t v)
185{
1813e175
RH
186 if (TCG_TARGET_INSN_UNIT_SIZE == 8) {
187 *s->code_ptr++ = v;
188 } else {
189 tcg_insn_unit *p = s->code_ptr;
190 memcpy(p, &v, sizeof(v));
191 s->code_ptr = p + (8 / TCG_TARGET_INSN_UNIT_SIZE);
192 }
ac26eb69
RH
193}
194
1813e175 195static inline void tcg_patch64(tcg_insn_unit *p, uint64_t v)
5c53bb81 196{
1813e175
RH
197 if (TCG_TARGET_INSN_UNIT_SIZE == 8) {
198 *p = v;
199 } else {
200 memcpy(p, &v, sizeof(v));
201 }
5c53bb81 202}
1813e175 203#endif
5c53bb81 204
c896fe29
FB
205/* label relocation processing */
206
1813e175 207static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type,
2ba7fae2 208 int label_index, intptr_t addend)
c896fe29
FB
209{
210 TCGLabel *l;
211 TCGRelocation *r;
212
213 l = &s->labels[label_index];
214 if (l->has_value) {
623e265c
PB
215 /* FIXME: This may break relocations on RISC targets that
216 modify instruction fields in place. The caller may not have
217 written the initial value. */
f54b3f92 218 patch_reloc(code_ptr, type, l->u.value, addend);
c896fe29
FB
219 } else {
220 /* add a new relocation entry */
221 r = tcg_malloc(sizeof(TCGRelocation));
222 r->type = type;
223 r->ptr = code_ptr;
224 r->addend = addend;
225 r->next = l->u.first_reloc;
226 l->u.first_reloc = r;
227 }
228}
229
1813e175 230static void tcg_out_label(TCGContext *s, int label_index, tcg_insn_unit *ptr)
c896fe29 231{
1813e175 232 TCGLabel *l = &s->labels[label_index];
2ba7fae2 233 intptr_t value = (intptr_t)ptr;
1813e175 234 TCGRelocation *r;
c896fe29 235
1813e175
RH
236 assert(!l->has_value);
237
238 for (r = l->u.first_reloc; r != NULL; r = r->next) {
f54b3f92 239 patch_reloc(r->ptr, r->type, value, r->addend);
c896fe29 240 }
1813e175 241
c896fe29 242 l->has_value = 1;
1813e175 243 l->u.value_ptr = ptr;
c896fe29
FB
244}
245
246int gen_new_label(void)
247{
248 TCGContext *s = &tcg_ctx;
249 int idx;
250 TCGLabel *l;
251
252 if (s->nb_labels >= TCG_MAX_LABELS)
253 tcg_abort();
254 idx = s->nb_labels++;
255 l = &s->labels[idx];
256 l->has_value = 0;
257 l->u.first_reloc = NULL;
258 return idx;
259}
260
261#include "tcg-target.c"
262
c896fe29
FB
263/* pool based memory allocation */
264void *tcg_malloc_internal(TCGContext *s, int size)
265{
266 TCGPool *p;
267 int pool_size;
268
269 if (size > TCG_POOL_CHUNK_SIZE) {
270 /* big malloc: insert a new pool (XXX: could optimize) */
7267c094 271 p = g_malloc(sizeof(TCGPool) + size);
c896fe29 272 p->size = size;
4055299e
KB
273 p->next = s->pool_first_large;
274 s->pool_first_large = p;
275 return p->data;
c896fe29
FB
276 } else {
277 p = s->pool_current;
278 if (!p) {
279 p = s->pool_first;
280 if (!p)
281 goto new_pool;
282 } else {
283 if (!p->next) {
284 new_pool:
285 pool_size = TCG_POOL_CHUNK_SIZE;
7267c094 286 p = g_malloc(sizeof(TCGPool) + pool_size);
c896fe29
FB
287 p->size = pool_size;
288 p->next = NULL;
289 if (s->pool_current)
290 s->pool_current->next = p;
291 else
292 s->pool_first = p;
293 } else {
294 p = p->next;
295 }
296 }
297 }
298 s->pool_current = p;
299 s->pool_cur = p->data + size;
300 s->pool_end = p->data + p->size;
301 return p->data;
302}
303
304void tcg_pool_reset(TCGContext *s)
305{
4055299e
KB
306 TCGPool *p, *t;
307 for (p = s->pool_first_large; p; p = t) {
308 t = p->next;
309 g_free(p);
310 }
311 s->pool_first_large = NULL;
c896fe29
FB
312 s->pool_cur = s->pool_end = NULL;
313 s->pool_current = NULL;
314}
315
100b5e01
RH
316typedef struct TCGHelperInfo {
317 void *func;
318 const char *name;
afb49896
RH
319 unsigned flags;
320 unsigned sizemask;
100b5e01
RH
321} TCGHelperInfo;
322
2ef6175a
RH
323#include "exec/helper-proto.h"
324
100b5e01 325static const TCGHelperInfo all_helpers[] = {
2ef6175a 326#include "exec/helper-tcg.h"
100b5e01
RH
327};
328
c896fe29
FB
329void tcg_context_init(TCGContext *s)
330{
100b5e01 331 int op, total_args, n, i;
c896fe29
FB
332 TCGOpDef *def;
333 TCGArgConstraint *args_ct;
334 int *sorted_args;
84fd9dd3 335 GHashTable *helper_table;
c896fe29
FB
336
337 memset(s, 0, sizeof(*s));
c896fe29
FB
338 s->nb_globals = 0;
339
340 /* Count total number of arguments and allocate the corresponding
341 space */
342 total_args = 0;
343 for(op = 0; op < NB_OPS; op++) {
344 def = &tcg_op_defs[op];
345 n = def->nb_iargs + def->nb_oargs;
346 total_args += n;
347 }
348
7267c094
AL
349 args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
350 sorted_args = g_malloc(sizeof(int) * total_args);
c896fe29
FB
351
352 for(op = 0; op < NB_OPS; op++) {
353 def = &tcg_op_defs[op];
354 def->args_ct = args_ct;
355 def->sorted_args = sorted_args;
356 n = def->nb_iargs + def->nb_oargs;
357 sorted_args += n;
358 args_ct += n;
359 }
5cd8f621
RH
360
361 /* Register helpers. */
84fd9dd3
RH
362 /* Use g_direct_hash/equal for direct pointer comparisons on func. */
363 s->helpers = helper_table = g_hash_table_new(NULL, NULL);
364
100b5e01 365 for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) {
84fd9dd3 366 g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func,
72866e82 367 (gpointer)&all_helpers[i]);
100b5e01 368 }
5cd8f621 369
c896fe29 370 tcg_target_init(s);
9002ec79 371}
b03cce8e 372
9002ec79
RH
373void tcg_prologue_init(TCGContext *s)
374{
b03cce8e 375 /* init global prologue and epilogue */
0b0d3320 376 s->code_buf = s->code_gen_prologue;
b03cce8e
FB
377 s->code_ptr = s->code_buf;
378 tcg_target_qemu_prologue(s);
b93949ef 379 flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
d6b64b2b
RH
380
381#ifdef DEBUG_DISAS
382 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
1813e175 383 size_t size = tcg_current_code_size(s);
d6b64b2b
RH
384 qemu_log("PROLOGUE: [size=%zu]\n", size);
385 log_disas(s->code_buf, size);
386 qemu_log("\n");
387 qemu_log_flush();
388 }
389#endif
c896fe29
FB
390}
391
e2c6d1b4 392void tcg_set_frame(TCGContext *s, int reg, intptr_t start, intptr_t size)
c896fe29
FB
393{
394 s->frame_start = start;
395 s->frame_end = start + size;
396 s->frame_reg = reg;
397}
398
c896fe29
FB
399void tcg_func_start(TCGContext *s)
400{
401 tcg_pool_reset(s);
402 s->nb_temps = s->nb_globals;
0ec9eabc
RH
403
404 /* No temps have been previously allocated for size or locality. */
405 memset(s->free_temps, 0, sizeof(s->free_temps));
406
c896fe29
FB
407 s->labels = tcg_malloc(sizeof(TCGLabel) * TCG_MAX_LABELS);
408 s->nb_labels = 0;
409 s->current_frame_offset = s->frame_start;
410
0a209d4b
RH
411#ifdef CONFIG_DEBUG_TCG
412 s->goto_tb_issue_mask = 0;
413#endif
414
92414b31 415 s->gen_opc_ptr = s->gen_opc_buf;
1ff0a2c5 416 s->gen_opparam_ptr = s->gen_opparam_buf;
b76f0d8c 417
9ecefc84 418 s->be = tcg_malloc(sizeof(TCGBackendData));
c896fe29
FB
419}
420
421static inline void tcg_temp_alloc(TCGContext *s, int n)
422{
423 if (n > TCG_MAX_TEMPS)
424 tcg_abort();
425}
426
a7812ae4
PB
427static inline int tcg_global_reg_new_internal(TCGType type, int reg,
428 const char *name)
c896fe29
FB
429{
430 TCGContext *s = &tcg_ctx;
431 TCGTemp *ts;
432 int idx;
433
434#if TCG_TARGET_REG_BITS == 32
435 if (type != TCG_TYPE_I32)
436 tcg_abort();
437#endif
438 if (tcg_regset_test_reg(s->reserved_regs, reg))
439 tcg_abort();
440 idx = s->nb_globals;
441 tcg_temp_alloc(s, s->nb_globals + 1);
442 ts = &s->temps[s->nb_globals];
443 ts->base_type = type;
444 ts->type = type;
445 ts->fixed_reg = 1;
446 ts->reg = reg;
c896fe29
FB
447 ts->name = name;
448 s->nb_globals++;
449 tcg_regset_set_reg(s->reserved_regs, reg);
a7812ae4
PB
450 return idx;
451}
452
453TCGv_i32 tcg_global_reg_new_i32(int reg, const char *name)
454{
455 int idx;
456
457 idx = tcg_global_reg_new_internal(TCG_TYPE_I32, reg, name);
458 return MAKE_TCGV_I32(idx);
459}
460
461TCGv_i64 tcg_global_reg_new_i64(int reg, const char *name)
462{
463 int idx;
464
465 idx = tcg_global_reg_new_internal(TCG_TYPE_I64, reg, name);
466 return MAKE_TCGV_I64(idx);
c896fe29
FB
467}
468
a7812ae4 469static inline int tcg_global_mem_new_internal(TCGType type, int reg,
2f2f244d 470 intptr_t offset,
a7812ae4 471 const char *name)
c896fe29
FB
472{
473 TCGContext *s = &tcg_ctx;
474 TCGTemp *ts;
475 int idx;
476
477 idx = s->nb_globals;
478#if TCG_TARGET_REG_BITS == 32
479 if (type == TCG_TYPE_I64) {
480 char buf[64];
c588979b 481 tcg_temp_alloc(s, s->nb_globals + 2);
c896fe29
FB
482 ts = &s->temps[s->nb_globals];
483 ts->base_type = type;
484 ts->type = TCG_TYPE_I32;
485 ts->fixed_reg = 0;
486 ts->mem_allocated = 1;
487 ts->mem_reg = reg;
02eb19d0 488#ifdef HOST_WORDS_BIGENDIAN
c896fe29
FB
489 ts->mem_offset = offset + 4;
490#else
491 ts->mem_offset = offset;
492#endif
c896fe29
FB
493 pstrcpy(buf, sizeof(buf), name);
494 pstrcat(buf, sizeof(buf), "_0");
495 ts->name = strdup(buf);
496 ts++;
497
498 ts->base_type = type;
499 ts->type = TCG_TYPE_I32;
500 ts->fixed_reg = 0;
501 ts->mem_allocated = 1;
502 ts->mem_reg = reg;
02eb19d0 503#ifdef HOST_WORDS_BIGENDIAN
c896fe29
FB
504 ts->mem_offset = offset;
505#else
506 ts->mem_offset = offset + 4;
507#endif
c896fe29
FB
508 pstrcpy(buf, sizeof(buf), name);
509 pstrcat(buf, sizeof(buf), "_1");
510 ts->name = strdup(buf);
511
512 s->nb_globals += 2;
513 } else
514#endif
515 {
516 tcg_temp_alloc(s, s->nb_globals + 1);
517 ts = &s->temps[s->nb_globals];
518 ts->base_type = type;
519 ts->type = type;
520 ts->fixed_reg = 0;
521 ts->mem_allocated = 1;
522 ts->mem_reg = reg;
523 ts->mem_offset = offset;
c896fe29
FB
524 ts->name = name;
525 s->nb_globals++;
526 }
a7812ae4
PB
527 return idx;
528}
529
2f2f244d 530TCGv_i32 tcg_global_mem_new_i32(int reg, intptr_t offset, const char *name)
a7812ae4 531{
2f2f244d 532 int idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
a7812ae4
PB
533 return MAKE_TCGV_I32(idx);
534}
535
2f2f244d 536TCGv_i64 tcg_global_mem_new_i64(int reg, intptr_t offset, const char *name)
a7812ae4 537{
2f2f244d 538 int idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
a7812ae4 539 return MAKE_TCGV_I64(idx);
c896fe29
FB
540}
541
a7812ae4 542static inline int tcg_temp_new_internal(TCGType type, int temp_local)
c896fe29
FB
543{
544 TCGContext *s = &tcg_ctx;
545 TCGTemp *ts;
641d5fbe 546 int idx, k;
c896fe29 547
0ec9eabc
RH
548 k = type + (temp_local ? TCG_TYPE_COUNT : 0);
549 idx = find_first_bit(s->free_temps[k].l, TCG_MAX_TEMPS);
550 if (idx < TCG_MAX_TEMPS) {
551 /* There is already an available temp with the right type. */
552 clear_bit(idx, s->free_temps[k].l);
553
e8996ee0 554 ts = &s->temps[idx];
e8996ee0 555 ts->temp_allocated = 1;
0ec9eabc 556 assert(ts->base_type == type);
641d5fbe 557 assert(ts->temp_local == temp_local);
e8996ee0
FB
558 } else {
559 idx = s->nb_temps;
c896fe29 560#if TCG_TARGET_REG_BITS == 32
e8996ee0 561 if (type == TCG_TYPE_I64) {
8df1ca4b 562 tcg_temp_alloc(s, s->nb_temps + 2);
e8996ee0
FB
563 ts = &s->temps[s->nb_temps];
564 ts->base_type = type;
565 ts->type = TCG_TYPE_I32;
566 ts->temp_allocated = 1;
641d5fbe 567 ts->temp_local = temp_local;
e8996ee0
FB
568 ts->name = NULL;
569 ts++;
f6aa2f7d 570 ts->base_type = type;
e8996ee0
FB
571 ts->type = TCG_TYPE_I32;
572 ts->temp_allocated = 1;
641d5fbe 573 ts->temp_local = temp_local;
e8996ee0
FB
574 ts->name = NULL;
575 s->nb_temps += 2;
576 } else
c896fe29 577#endif
e8996ee0
FB
578 {
579 tcg_temp_alloc(s, s->nb_temps + 1);
580 ts = &s->temps[s->nb_temps];
581 ts->base_type = type;
582 ts->type = type;
583 ts->temp_allocated = 1;
641d5fbe 584 ts->temp_local = temp_local;
e8996ee0
FB
585 ts->name = NULL;
586 s->nb_temps++;
587 }
c896fe29 588 }
27bfd83c
PM
589
590#if defined(CONFIG_DEBUG_TCG)
591 s->temps_in_use++;
592#endif
a7812ae4 593 return idx;
c896fe29
FB
594}
595
a7812ae4
PB
596TCGv_i32 tcg_temp_new_internal_i32(int temp_local)
597{
598 int idx;
599
600 idx = tcg_temp_new_internal(TCG_TYPE_I32, temp_local);
601 return MAKE_TCGV_I32(idx);
602}
603
604TCGv_i64 tcg_temp_new_internal_i64(int temp_local)
605{
606 int idx;
607
608 idx = tcg_temp_new_internal(TCG_TYPE_I64, temp_local);
609 return MAKE_TCGV_I64(idx);
610}
611
0ec9eabc 612static void tcg_temp_free_internal(int idx)
c896fe29
FB
613{
614 TCGContext *s = &tcg_ctx;
615 TCGTemp *ts;
641d5fbe 616 int k;
c896fe29 617
27bfd83c
PM
618#if defined(CONFIG_DEBUG_TCG)
619 s->temps_in_use--;
620 if (s->temps_in_use < 0) {
621 fprintf(stderr, "More temporaries freed than allocated!\n");
622 }
623#endif
624
e8996ee0 625 assert(idx >= s->nb_globals && idx < s->nb_temps);
c896fe29 626 ts = &s->temps[idx];
e8996ee0
FB
627 assert(ts->temp_allocated != 0);
628 ts->temp_allocated = 0;
0ec9eabc 629
18d13fa2 630 k = ts->base_type + (ts->temp_local ? TCG_TYPE_COUNT : 0);
0ec9eabc 631 set_bit(idx, s->free_temps[k].l);
c896fe29
FB
632}
633
a7812ae4
PB
634void tcg_temp_free_i32(TCGv_i32 arg)
635{
636 tcg_temp_free_internal(GET_TCGV_I32(arg));
637}
638
639void tcg_temp_free_i64(TCGv_i64 arg)
640{
641 tcg_temp_free_internal(GET_TCGV_I64(arg));
642}
e8996ee0 643
a7812ae4 644TCGv_i32 tcg_const_i32(int32_t val)
c896fe29 645{
a7812ae4
PB
646 TCGv_i32 t0;
647 t0 = tcg_temp_new_i32();
e8996ee0
FB
648 tcg_gen_movi_i32(t0, val);
649 return t0;
650}
c896fe29 651
a7812ae4 652TCGv_i64 tcg_const_i64(int64_t val)
e8996ee0 653{
a7812ae4
PB
654 TCGv_i64 t0;
655 t0 = tcg_temp_new_i64();
e8996ee0
FB
656 tcg_gen_movi_i64(t0, val);
657 return t0;
c896fe29
FB
658}
659
a7812ae4 660TCGv_i32 tcg_const_local_i32(int32_t val)
bdffd4a9 661{
a7812ae4
PB
662 TCGv_i32 t0;
663 t0 = tcg_temp_local_new_i32();
bdffd4a9
AJ
664 tcg_gen_movi_i32(t0, val);
665 return t0;
666}
667
a7812ae4 668TCGv_i64 tcg_const_local_i64(int64_t val)
bdffd4a9 669{
a7812ae4
PB
670 TCGv_i64 t0;
671 t0 = tcg_temp_local_new_i64();
bdffd4a9
AJ
672 tcg_gen_movi_i64(t0, val);
673 return t0;
674}
675
27bfd83c
PM
676#if defined(CONFIG_DEBUG_TCG)
677void tcg_clear_temp_count(void)
678{
679 TCGContext *s = &tcg_ctx;
680 s->temps_in_use = 0;
681}
682
683int tcg_check_temp_count(void)
684{
685 TCGContext *s = &tcg_ctx;
686 if (s->temps_in_use) {
687 /* Clear the count so that we don't give another
688 * warning immediately next time around.
689 */
690 s->temps_in_use = 0;
691 return 1;
692 }
693 return 0;
694}
695#endif
696
39cf05d3
FB
697/* Note: we convert the 64 bit args to 32 bit and do some alignment
698 and endian swap. Maybe it would be better to do the alignment
699 and endian swap in tcg_reg_alloc_call(). */
bbb8a1b4
RH
700void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
701 int nargs, TCGArg *args)
c896fe29 702{
bbb8a1b4
RH
703 int i, real_args, nb_rets;
704 unsigned sizemask, flags;
a7812ae4 705 TCGArg *nparam;
afb49896
RH
706 TCGHelperInfo *info;
707
708 info = g_hash_table_lookup(s->helpers, (gpointer)func);
bbb8a1b4
RH
709 flags = info->flags;
710 sizemask = info->sizemask;
2bece2c8 711
34b1a49c
RH
712#if defined(__sparc__) && !defined(__arch64__) \
713 && !defined(CONFIG_TCG_INTERPRETER)
714 /* We have 64-bit values in one register, but need to pass as two
715 separate parameters. Split them. */
716 int orig_sizemask = sizemask;
717 int orig_nargs = nargs;
718 TCGv_i64 retl, reth;
719
720 TCGV_UNUSED_I64(retl);
721 TCGV_UNUSED_I64(reth);
722 if (sizemask != 0) {
723 TCGArg *split_args = __builtin_alloca(sizeof(TCGArg) * nargs * 2);
724 for (i = real_args = 0; i < nargs; ++i) {
725 int is_64bit = sizemask & (1 << (i+1)*2);
726 if (is_64bit) {
727 TCGv_i64 orig = MAKE_TCGV_I64(args[i]);
728 TCGv_i32 h = tcg_temp_new_i32();
729 TCGv_i32 l = tcg_temp_new_i32();
730 tcg_gen_extr_i64_i32(l, h, orig);
731 split_args[real_args++] = GET_TCGV_I32(h);
732 split_args[real_args++] = GET_TCGV_I32(l);
733 } else {
734 split_args[real_args++] = args[i];
735 }
736 }
737 nargs = real_args;
738 args = split_args;
739 sizemask = 0;
740 }
741#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
2bece2c8
RH
742 for (i = 0; i < nargs; ++i) {
743 int is_64bit = sizemask & (1 << (i+1)*2);
744 int is_signed = sizemask & (2 << (i+1)*2);
745 if (!is_64bit) {
746 TCGv_i64 temp = tcg_temp_new_i64();
747 TCGv_i64 orig = MAKE_TCGV_I64(args[i]);
748 if (is_signed) {
749 tcg_gen_ext32s_i64(temp, orig);
750 } else {
751 tcg_gen_ext32u_i64(temp, orig);
752 }
753 args[i] = GET_TCGV_I64(temp);
754 }
755 }
756#endif /* TCG_TARGET_EXTEND_ARGS */
757
efd7f486 758 *s->gen_opc_ptr++ = INDEX_op_call;
c4afe5c4 759 nparam = s->gen_opparam_ptr++;
a7812ae4 760 if (ret != TCG_CALL_DUMMY_ARG) {
34b1a49c
RH
761#if defined(__sparc__) && !defined(__arch64__) \
762 && !defined(CONFIG_TCG_INTERPRETER)
763 if (orig_sizemask & 1) {
764 /* The 32-bit ABI is going to return the 64-bit value in
765 the %o0/%o1 register pair. Prepare for this by using
766 two return temporaries, and reassemble below. */
767 retl = tcg_temp_new_i64();
768 reth = tcg_temp_new_i64();
769 *s->gen_opparam_ptr++ = GET_TCGV_I64(reth);
770 *s->gen_opparam_ptr++ = GET_TCGV_I64(retl);
771 nb_rets = 2;
772 } else {
773 *s->gen_opparam_ptr++ = ret;
774 nb_rets = 1;
775 }
776#else
777 if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) {
02eb19d0 778#ifdef HOST_WORDS_BIGENDIAN
c4afe5c4
EV
779 *s->gen_opparam_ptr++ = ret + 1;
780 *s->gen_opparam_ptr++ = ret;
39cf05d3 781#else
c4afe5c4
EV
782 *s->gen_opparam_ptr++ = ret;
783 *s->gen_opparam_ptr++ = ret + 1;
39cf05d3 784#endif
a7812ae4 785 nb_rets = 2;
34b1a49c 786 } else {
c4afe5c4 787 *s->gen_opparam_ptr++ = ret;
a7812ae4 788 nb_rets = 1;
c896fe29 789 }
34b1a49c 790#endif
a7812ae4
PB
791 } else {
792 nb_rets = 0;
c896fe29 793 }
a7812ae4
PB
794 real_args = 0;
795 for (i = 0; i < nargs; i++) {
2bece2c8 796 int is_64bit = sizemask & (1 << (i+1)*2);
bbb8a1b4 797 if (TCG_TARGET_REG_BITS < 64 && is_64bit) {
39cf05d3
FB
798#ifdef TCG_TARGET_CALL_ALIGN_ARGS
799 /* some targets want aligned 64 bit args */
ebd486d5 800 if (real_args & 1) {
c4afe5c4 801 *s->gen_opparam_ptr++ = TCG_CALL_DUMMY_ARG;
ebd486d5 802 real_args++;
39cf05d3
FB
803 }
804#endif
3f90f252
RH
805 /* If stack grows up, then we will be placing successive
806 arguments at lower addresses, which means we need to
807 reverse the order compared to how we would normally
808 treat either big or little-endian. For those arguments
809 that will wind up in registers, this still works for
810 HPPA (the only current STACK_GROWSUP target) since the
811 argument registers are *also* allocated in decreasing
812 order. If another such target is added, this logic may
813 have to get more complicated to differentiate between
814 stack arguments and register arguments. */
02eb19d0 815#if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
c4afe5c4
EV
816 *s->gen_opparam_ptr++ = args[i] + 1;
817 *s->gen_opparam_ptr++ = args[i];
c896fe29 818#else
c4afe5c4
EV
819 *s->gen_opparam_ptr++ = args[i];
820 *s->gen_opparam_ptr++ = args[i] + 1;
c896fe29 821#endif
a7812ae4 822 real_args += 2;
2bece2c8 823 continue;
c896fe29 824 }
2bece2c8 825
c4afe5c4 826 *s->gen_opparam_ptr++ = args[i];
2bece2c8 827 real_args++;
c896fe29 828 }
cf066674 829 *s->gen_opparam_ptr++ = (uintptr_t)func;
c4afe5c4 830 *s->gen_opparam_ptr++ = flags;
a7812ae4 831
cf066674 832 *nparam = (nb_rets << 16) | real_args;
a7812ae4
PB
833
834 /* total parameters, needed to go backward in the instruction stream */
c4afe5c4 835 *s->gen_opparam_ptr++ = 1 + nb_rets + real_args + 3;
2bece2c8 836
34b1a49c
RH
837#if defined(__sparc__) && !defined(__arch64__) \
838 && !defined(CONFIG_TCG_INTERPRETER)
839 /* Free all of the parts we allocated above. */
840 for (i = real_args = 0; i < orig_nargs; ++i) {
841 int is_64bit = orig_sizemask & (1 << (i+1)*2);
842 if (is_64bit) {
843 TCGv_i32 h = MAKE_TCGV_I32(args[real_args++]);
844 TCGv_i32 l = MAKE_TCGV_I32(args[real_args++]);
845 tcg_temp_free_i32(h);
846 tcg_temp_free_i32(l);
847 } else {
848 real_args++;
849 }
850 }
851 if (orig_sizemask & 1) {
852 /* The 32-bit ABI returned two 32-bit pieces. Re-assemble them.
853 Note that describing these as TCGv_i64 eliminates an unnecessary
854 zero-extension that tcg_gen_concat_i32_i64 would create. */
855 tcg_gen_concat32_i64(MAKE_TCGV_I64(ret), retl, reth);
856 tcg_temp_free_i64(retl);
857 tcg_temp_free_i64(reth);
858 }
859#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
2bece2c8
RH
860 for (i = 0; i < nargs; ++i) {
861 int is_64bit = sizemask & (1 << (i+1)*2);
862 if (!is_64bit) {
863 TCGv_i64 temp = MAKE_TCGV_I64(args[i]);
864 tcg_temp_free_i64(temp);
865 }
866 }
867#endif /* TCG_TARGET_EXTEND_ARGS */
c896fe29 868}
c896fe29 869
ac56dd48 870#if TCG_TARGET_REG_BITS == 32
a7812ae4 871void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
c896fe29
FB
872 int c, int right, int arith)
873{
cf60bce4 874 if (c == 0) {
a7812ae4 875 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
cf60bce4
FB
876 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
877 } else if (c >= 32) {
c896fe29
FB
878 c -= 32;
879 if (right) {
880 if (arith) {
a7812ae4 881 tcg_gen_sari_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), c);
ac56dd48 882 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), 31);
c896fe29 883 } else {
a7812ae4 884 tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), c);
ac56dd48 885 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
c896fe29
FB
886 }
887 } else {
a7812ae4
PB
888 tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c);
889 tcg_gen_movi_i32(TCGV_LOW(ret), 0);
c896fe29
FB
890 }
891 } else {
a7812ae4 892 TCGv_i32 t0, t1;
c896fe29 893
a7812ae4
PB
894 t0 = tcg_temp_new_i32();
895 t1 = tcg_temp_new_i32();
c896fe29 896 if (right) {
ac56dd48 897 tcg_gen_shli_i32(t0, TCGV_HIGH(arg1), 32 - c);
c896fe29 898 if (arith)
ac56dd48 899 tcg_gen_sari_i32(t1, TCGV_HIGH(arg1), c);
a7812ae4 900 else
ac56dd48 901 tcg_gen_shri_i32(t1, TCGV_HIGH(arg1), c);
a7812ae4
PB
902 tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
903 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t0);
ac56dd48 904 tcg_gen_mov_i32(TCGV_HIGH(ret), t1);
c896fe29 905 } else {
a7812ae4 906 tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
c896fe29 907 /* Note: ret can be the same as arg1, so we use t1 */
a7812ae4 908 tcg_gen_shli_i32(t1, TCGV_LOW(arg1), c);
ac56dd48
PB
909 tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
910 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t0);
a7812ae4 911 tcg_gen_mov_i32(TCGV_LOW(ret), t1);
c896fe29 912 }
a7812ae4
PB
913 tcg_temp_free_i32(t0);
914 tcg_temp_free_i32(t1);
c896fe29
FB
915 }
916}
ac56dd48 917#endif
c896fe29 918
f713d6ad
RH
919static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)
920{
921 switch (op & MO_SIZE) {
922 case MO_8:
923 op &= ~MO_BSWAP;
924 break;
925 case MO_16:
926 break;
927 case MO_32:
928 if (!is64) {
929 op &= ~MO_SIGN;
930 }
931 break;
932 case MO_64:
933 if (!is64) {
934 tcg_abort();
935 }
936 break;
937 }
938 if (st) {
939 op &= ~MO_SIGN;
940 }
941 return op;
942}
943
f713d6ad
RH
944void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
945{
946 memop = tcg_canonicalize_memop(memop, 0, 0);
947
3d1b2ff6
RH
948 *tcg_ctx.gen_opc_ptr++ = INDEX_op_qemu_ld_i32;
949 tcg_add_param_i32(val);
950 tcg_add_param_tl(addr);
951 *tcg_ctx.gen_opparam_ptr++ = memop;
952 *tcg_ctx.gen_opparam_ptr++ = idx;
f713d6ad
RH
953}
954
955void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
956{
957 memop = tcg_canonicalize_memop(memop, 0, 1);
958
3d1b2ff6
RH
959 *tcg_ctx.gen_opc_ptr++ = INDEX_op_qemu_st_i32;
960 tcg_add_param_i32(val);
961 tcg_add_param_tl(addr);
962 *tcg_ctx.gen_opparam_ptr++ = memop;
963 *tcg_ctx.gen_opparam_ptr++ = idx;
f713d6ad
RH
964}
965
966void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
967{
968 memop = tcg_canonicalize_memop(memop, 1, 0);
969
970#if TCG_TARGET_REG_BITS == 32
971 if ((memop & MO_SIZE) < MO_64) {
972 tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);
973 if (memop & MO_SIGN) {
974 tcg_gen_sari_i32(TCGV_HIGH(val), TCGV_LOW(val), 31);
975 } else {
976 tcg_gen_movi_i32(TCGV_HIGH(val), 0);
977 }
978 return;
979 }
980#endif
981
3d1b2ff6 982 *tcg_ctx.gen_opc_ptr++ = INDEX_op_qemu_ld_i64;
f713d6ad
RH
983 tcg_add_param_i64(val);
984 tcg_add_param_tl(addr);
3d1b2ff6 985 *tcg_ctx.gen_opparam_ptr++ = memop;
f713d6ad
RH
986 *tcg_ctx.gen_opparam_ptr++ = idx;
987}
988
989void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
990{
991 memop = tcg_canonicalize_memop(memop, 1, 1);
992
993#if TCG_TARGET_REG_BITS == 32
994 if ((memop & MO_SIZE) < MO_64) {
995 tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);
996 return;
997 }
998#endif
999
3d1b2ff6 1000 *tcg_ctx.gen_opc_ptr++ = INDEX_op_qemu_st_i64;
f713d6ad
RH
1001 tcg_add_param_i64(val);
1002 tcg_add_param_tl(addr);
3d1b2ff6 1003 *tcg_ctx.gen_opparam_ptr++ = memop;
f713d6ad
RH
1004 *tcg_ctx.gen_opparam_ptr++ = idx;
1005}
be210acb 1006
8fcd3692 1007static void tcg_reg_alloc_start(TCGContext *s)
c896fe29
FB
1008{
1009 int i;
1010 TCGTemp *ts;
1011 for(i = 0; i < s->nb_globals; i++) {
1012 ts = &s->temps[i];
1013 if (ts->fixed_reg) {
1014 ts->val_type = TEMP_VAL_REG;
1015 } else {
1016 ts->val_type = TEMP_VAL_MEM;
1017 }
1018 }
e8996ee0
FB
1019 for(i = s->nb_globals; i < s->nb_temps; i++) {
1020 ts = &s->temps[i];
7dfd8c6a
AJ
1021 if (ts->temp_local) {
1022 ts->val_type = TEMP_VAL_MEM;
1023 } else {
1024 ts->val_type = TEMP_VAL_DEAD;
1025 }
e8996ee0
FB
1026 ts->mem_allocated = 0;
1027 ts->fixed_reg = 0;
1028 }
c896fe29
FB
1029 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
1030 s->reg_to_temp[i] = -1;
1031 }
1032}
1033
ac56dd48
PB
1034static char *tcg_get_arg_str_idx(TCGContext *s, char *buf, int buf_size,
1035 int idx)
c896fe29
FB
1036{
1037 TCGTemp *ts;
ac56dd48 1038
7f6f0ae5 1039 assert(idx >= 0 && idx < s->nb_temps);
ac56dd48
PB
1040 ts = &s->temps[idx];
1041 if (idx < s->nb_globals) {
1042 pstrcpy(buf, buf_size, ts->name);
c896fe29 1043 } else {
641d5fbe
FB
1044 if (ts->temp_local)
1045 snprintf(buf, buf_size, "loc%d", idx - s->nb_globals);
1046 else
1047 snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals);
c896fe29
FB
1048 }
1049 return buf;
1050}
1051
a7812ae4
PB
1052char *tcg_get_arg_str_i32(TCGContext *s, char *buf, int buf_size, TCGv_i32 arg)
1053{
1054 return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I32(arg));
1055}
1056
1057char *tcg_get_arg_str_i64(TCGContext *s, char *buf, int buf_size, TCGv_i64 arg)
ac56dd48 1058{
a810a2de 1059 return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I64(arg));
ac56dd48
PB
1060}
1061
6e085f72
RH
1062/* Find helper name. */
1063static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val)
4dc81f28 1064{
6e085f72
RH
1065 const char *ret = NULL;
1066 if (s->helpers) {
72866e82
RH
1067 TCGHelperInfo *info = g_hash_table_lookup(s->helpers, (gpointer)val);
1068 if (info) {
1069 ret = info->name;
1070 }
4dc81f28 1071 }
6e085f72 1072 return ret;
4dc81f28
FB
1073}
1074
f48f3ede
BS
1075static const char * const cond_name[] =
1076{
0aed257f
RH
1077 [TCG_COND_NEVER] = "never",
1078 [TCG_COND_ALWAYS] = "always",
f48f3ede
BS
1079 [TCG_COND_EQ] = "eq",
1080 [TCG_COND_NE] = "ne",
1081 [TCG_COND_LT] = "lt",
1082 [TCG_COND_GE] = "ge",
1083 [TCG_COND_LE] = "le",
1084 [TCG_COND_GT] = "gt",
1085 [TCG_COND_LTU] = "ltu",
1086 [TCG_COND_GEU] = "geu",
1087 [TCG_COND_LEU] = "leu",
1088 [TCG_COND_GTU] = "gtu"
1089};
1090
f713d6ad
RH
1091static const char * const ldst_name[] =
1092{
1093 [MO_UB] = "ub",
1094 [MO_SB] = "sb",
1095 [MO_LEUW] = "leuw",
1096 [MO_LESW] = "lesw",
1097 [MO_LEUL] = "leul",
1098 [MO_LESL] = "lesl",
1099 [MO_LEQ] = "leq",
1100 [MO_BEUW] = "beuw",
1101 [MO_BESW] = "besw",
1102 [MO_BEUL] = "beul",
1103 [MO_BESL] = "besl",
1104 [MO_BEQ] = "beq",
1105};
1106
eeacee4d 1107void tcg_dump_ops(TCGContext *s)
c896fe29
FB
1108{
1109 const uint16_t *opc_ptr;
1110 const TCGArg *args;
1111 TCGArg arg;
a9751609
RH
1112 TCGOpcode c;
1113 int i, k, nb_oargs, nb_iargs, nb_cargs, first_insn;
c896fe29
FB
1114 const TCGOpDef *def;
1115 char buf[128];
1116
7e4597d7 1117 first_insn = 1;
92414b31 1118 opc_ptr = s->gen_opc_buf;
1ff0a2c5 1119 args = s->gen_opparam_buf;
efd7f486 1120 while (opc_ptr < s->gen_opc_ptr) {
c896fe29
FB
1121 c = *opc_ptr++;
1122 def = &tcg_op_defs[c];
7e4597d7
FB
1123 if (c == INDEX_op_debug_insn_start) {
1124 uint64_t pc;
1125#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1126 pc = ((uint64_t)args[1] << 32) | args[0];
1127#else
1128 pc = args[0];
1129#endif
eeacee4d
BS
1130 if (!first_insn) {
1131 qemu_log("\n");
1132 }
1133 qemu_log(" ---- 0x%" PRIx64, pc);
7e4597d7
FB
1134 first_insn = 0;
1135 nb_oargs = def->nb_oargs;
1136 nb_iargs = def->nb_iargs;
1137 nb_cargs = def->nb_cargs;
1138 } else if (c == INDEX_op_call) {
c896fe29 1139 TCGArg arg;
4dc81f28 1140
c896fe29
FB
1141 /* variable number of arguments */
1142 arg = *args++;
1143 nb_oargs = arg >> 16;
1144 nb_iargs = arg & 0xffff;
1145 nb_cargs = def->nb_cargs;
c896fe29 1146
cf066674
RH
1147 /* function name, flags, out args */
1148 qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name,
1149 tcg_find_helper(s, args[nb_oargs + nb_iargs]),
1150 args[nb_oargs + nb_iargs + 1], nb_oargs);
1151 for (i = 0; i < nb_oargs; i++) {
1152 qemu_log(",%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
eeacee4d 1153 args[i]));
b03cce8e 1154 }
cf066674
RH
1155 for (i = 0; i < nb_iargs; i++) {
1156 TCGArg arg = args[nb_oargs + i];
1157 const char *t = "<dummy>";
1158 if (arg != TCG_CALL_DUMMY_ARG) {
1159 t = tcg_get_arg_str_idx(s, buf, sizeof(buf), arg);
eeacee4d 1160 }
cf066674 1161 qemu_log(",%s", t);
e8996ee0 1162 }
b03cce8e 1163 } else {
eeacee4d 1164 qemu_log(" %s ", def->name);
b03cce8e
FB
1165 if (c == INDEX_op_nopn) {
1166 /* variable number of arguments */
1167 nb_cargs = *args;
1168 nb_oargs = 0;
1169 nb_iargs = 0;
1170 } else {
1171 nb_oargs = def->nb_oargs;
1172 nb_iargs = def->nb_iargs;
1173 nb_cargs = def->nb_cargs;
1174 }
1175
1176 k = 0;
1177 for(i = 0; i < nb_oargs; i++) {
eeacee4d
BS
1178 if (k != 0) {
1179 qemu_log(",");
1180 }
1181 qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
1182 args[k++]));
b03cce8e
FB
1183 }
1184 for(i = 0; i < nb_iargs; i++) {
eeacee4d
BS
1185 if (k != 0) {
1186 qemu_log(",");
1187 }
1188 qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
1189 args[k++]));
b03cce8e 1190 }
be210acb
RH
1191 switch (c) {
1192 case INDEX_op_brcond_i32:
be210acb 1193 case INDEX_op_setcond_i32:
ffc5ea09 1194 case INDEX_op_movcond_i32:
ffc5ea09 1195 case INDEX_op_brcond2_i32:
be210acb 1196 case INDEX_op_setcond2_i32:
ffc5ea09 1197 case INDEX_op_brcond_i64:
be210acb 1198 case INDEX_op_setcond_i64:
ffc5ea09 1199 case INDEX_op_movcond_i64:
eeacee4d
BS
1200 if (args[k] < ARRAY_SIZE(cond_name) && cond_name[args[k]]) {
1201 qemu_log(",%s", cond_name[args[k++]]);
1202 } else {
1203 qemu_log(",$0x%" TCG_PRIlx, args[k++]);
1204 }
f48f3ede 1205 i = 1;
be210acb 1206 break;
f713d6ad
RH
1207 case INDEX_op_qemu_ld_i32:
1208 case INDEX_op_qemu_st_i32:
1209 case INDEX_op_qemu_ld_i64:
1210 case INDEX_op_qemu_st_i64:
1211 if (args[k] < ARRAY_SIZE(ldst_name) && ldst_name[args[k]]) {
1212 qemu_log(",%s", ldst_name[args[k++]]);
1213 } else {
1214 qemu_log(",$0x%" TCG_PRIlx, args[k++]);
1215 }
1216 i = 1;
1217 break;
be210acb 1218 default:
f48f3ede 1219 i = 0;
be210acb
RH
1220 break;
1221 }
f48f3ede 1222 for(; i < nb_cargs; i++) {
eeacee4d
BS
1223 if (k != 0) {
1224 qemu_log(",");
1225 }
b03cce8e 1226 arg = args[k++];
eeacee4d 1227 qemu_log("$0x%" TCG_PRIlx, arg);
b03cce8e 1228 }
c896fe29 1229 }
eeacee4d 1230 qemu_log("\n");
c896fe29
FB
1231 args += nb_iargs + nb_oargs + nb_cargs;
1232 }
1233}
1234
1235/* we give more priority to constraints with less registers */
1236static int get_constraint_priority(const TCGOpDef *def, int k)
1237{
1238 const TCGArgConstraint *arg_ct;
1239
1240 int i, n;
1241 arg_ct = &def->args_ct[k];
1242 if (arg_ct->ct & TCG_CT_ALIAS) {
1243 /* an alias is equivalent to a single register */
1244 n = 1;
1245 } else {
1246 if (!(arg_ct->ct & TCG_CT_REG))
1247 return 0;
1248 n = 0;
1249 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
1250 if (tcg_regset_test_reg(arg_ct->u.regs, i))
1251 n++;
1252 }
1253 }
1254 return TCG_TARGET_NB_REGS - n + 1;
1255}
1256
1257/* sort from highest priority to lowest */
1258static void sort_constraints(TCGOpDef *def, int start, int n)
1259{
1260 int i, j, p1, p2, tmp;
1261
1262 for(i = 0; i < n; i++)
1263 def->sorted_args[start + i] = start + i;
1264 if (n <= 1)
1265 return;
1266 for(i = 0; i < n - 1; i++) {
1267 for(j = i + 1; j < n; j++) {
1268 p1 = get_constraint_priority(def, def->sorted_args[start + i]);
1269 p2 = get_constraint_priority(def, def->sorted_args[start + j]);
1270 if (p1 < p2) {
1271 tmp = def->sorted_args[start + i];
1272 def->sorted_args[start + i] = def->sorted_args[start + j];
1273 def->sorted_args[start + j] = tmp;
1274 }
1275 }
1276 }
1277}
1278
1279void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs)
1280{
a9751609 1281 TCGOpcode op;
c896fe29
FB
1282 TCGOpDef *def;
1283 const char *ct_str;
1284 int i, nb_args;
1285
1286 for(;;) {
a9751609 1287 if (tdefs->op == (TCGOpcode)-1)
c896fe29
FB
1288 break;
1289 op = tdefs->op;
c3b08d0e 1290 assert((unsigned)op < NB_OPS);
c896fe29 1291 def = &tcg_op_defs[op];
c68aaa18
SW
1292#if defined(CONFIG_DEBUG_TCG)
1293 /* Duplicate entry in op definitions? */
1294 assert(!def->used);
1295 def->used = 1;
1296#endif
c896fe29
FB
1297 nb_args = def->nb_iargs + def->nb_oargs;
1298 for(i = 0; i < nb_args; i++) {
1299 ct_str = tdefs->args_ct_str[i];
c68aaa18
SW
1300 /* Incomplete TCGTargetOpDef entry? */
1301 assert(ct_str != NULL);
c896fe29
FB
1302 tcg_regset_clear(def->args_ct[i].u.regs);
1303 def->args_ct[i].ct = 0;
1304 if (ct_str[0] >= '0' && ct_str[0] <= '9') {
1305 int oarg;
1306 oarg = ct_str[0] - '0';
1307 assert(oarg < def->nb_oargs);
1308 assert(def->args_ct[oarg].ct & TCG_CT_REG);
1309 /* TCG_CT_ALIAS is for the output arguments. The input
5ff9d6a4 1310 argument is tagged with TCG_CT_IALIAS. */
c896fe29 1311 def->args_ct[i] = def->args_ct[oarg];
5ff9d6a4
FB
1312 def->args_ct[oarg].ct = TCG_CT_ALIAS;
1313 def->args_ct[oarg].alias_index = i;
c896fe29 1314 def->args_ct[i].ct |= TCG_CT_IALIAS;
5ff9d6a4 1315 def->args_ct[i].alias_index = oarg;
c896fe29
FB
1316 } else {
1317 for(;;) {
1318 if (*ct_str == '\0')
1319 break;
1320 switch(*ct_str) {
1321 case 'i':
1322 def->args_ct[i].ct |= TCG_CT_CONST;
1323 ct_str++;
1324 break;
1325 default:
1326 if (target_parse_constraint(&def->args_ct[i], &ct_str) < 0) {
1327 fprintf(stderr, "Invalid constraint '%s' for arg %d of operation '%s'\n",
1328 ct_str, i, def->name);
1329 exit(1);
1330 }
1331 }
1332 }
1333 }
1334 }
1335
c68aaa18
SW
1336 /* TCGTargetOpDef entry with too much information? */
1337 assert(i == TCG_MAX_OP_ARGS || tdefs->args_ct_str[i] == NULL);
1338
c896fe29
FB
1339 /* sort the constraints (XXX: this is just an heuristic) */
1340 sort_constraints(def, 0, def->nb_oargs);
1341 sort_constraints(def, def->nb_oargs, def->nb_iargs);
1342
1343#if 0
1344 {
1345 int i;
1346
1347 printf("%s: sorted=", def->name);
1348 for(i = 0; i < def->nb_oargs + def->nb_iargs; i++)
1349 printf(" %d", def->sorted_args[i]);
1350 printf("\n");
1351 }
1352#endif
1353 tdefs++;
1354 }
1355
c68aaa18 1356#if defined(CONFIG_DEBUG_TCG)
a9751609 1357 i = 0;
c68aaa18 1358 for (op = 0; op < ARRAY_SIZE(tcg_op_defs); op++) {
f412c762 1359 const TCGOpDef *def = &tcg_op_defs[op];
c1a61f6c 1360 if (def->flags & TCG_OPF_NOT_PRESENT) {
c68aaa18 1361 /* Wrong entry in op definitions? */
f412c762
RH
1362 if (def->used) {
1363 fprintf(stderr, "Invalid op definition for %s\n", def->name);
a9751609
RH
1364 i = 1;
1365 }
c68aaa18
SW
1366 } else {
1367 /* Missing entry in op definitions? */
f412c762
RH
1368 if (!def->used) {
1369 fprintf(stderr, "Missing op definition for %s\n", def->name);
a9751609
RH
1370 i = 1;
1371 }
c68aaa18
SW
1372 }
1373 }
a9751609
RH
1374 if (i == 1) {
1375 tcg_abort();
1376 }
c68aaa18 1377#endif
c896fe29
FB
1378}
1379
1380#ifdef USE_LIVENESS_ANALYSIS
1381
1382/* set a nop for an operation using 'nb_args' */
1383static inline void tcg_set_nop(TCGContext *s, uint16_t *opc_ptr,
1384 TCGArg *args, int nb_args)
1385{
1386 if (nb_args == 0) {
1387 *opc_ptr = INDEX_op_nop;
1388 } else {
1389 *opc_ptr = INDEX_op_nopn;
1390 args[0] = nb_args;
1391 args[nb_args - 1] = nb_args;
1392 }
1393}
1394
9c43b68d
AJ
1395/* liveness analysis: end of function: all temps are dead, and globals
1396 should be in memory. */
1397static inline void tcg_la_func_end(TCGContext *s, uint8_t *dead_temps,
1398 uint8_t *mem_temps)
c896fe29 1399{
9c43b68d
AJ
1400 memset(dead_temps, 1, s->nb_temps);
1401 memset(mem_temps, 1, s->nb_globals);
1402 memset(mem_temps + s->nb_globals, 0, s->nb_temps - s->nb_globals);
c896fe29
FB
1403}
1404
9c43b68d
AJ
1405/* liveness analysis: end of basic block: all temps are dead, globals
1406 and local temps should be in memory. */
1407static inline void tcg_la_bb_end(TCGContext *s, uint8_t *dead_temps,
1408 uint8_t *mem_temps)
641d5fbe
FB
1409{
1410 int i;
641d5fbe 1411
9c43b68d
AJ
1412 memset(dead_temps, 1, s->nb_temps);
1413 memset(mem_temps, 1, s->nb_globals);
641d5fbe 1414 for(i = s->nb_globals; i < s->nb_temps; i++) {
9c43b68d 1415 mem_temps[i] = s->temps[i].temp_local;
641d5fbe
FB
1416 }
1417}
1418
866cb6cb 1419/* Liveness analysis : update the opc_dead_args array to tell if a
c896fe29
FB
1420 given input arguments is dead. Instructions updating dead
1421 temporaries are removed. */
8fcd3692 1422static void tcg_liveness_analysis(TCGContext *s)
c896fe29 1423{
cf066674 1424 int i, op_index, nb_args, nb_iargs, nb_oargs, nb_ops;
03271524 1425 TCGOpcode op, op_new, op_new2;
cf066674 1426 TCGArg *args, arg;
c896fe29 1427 const TCGOpDef *def;
9c43b68d 1428 uint8_t *dead_temps, *mem_temps;
ec7a869d
AJ
1429 uint16_t dead_args;
1430 uint8_t sync_args;
03271524 1431 bool have_op_new2;
c896fe29 1432
efd7f486 1433 s->gen_opc_ptr++; /* skip end */
c896fe29 1434
92414b31 1435 nb_ops = s->gen_opc_ptr - s->gen_opc_buf;
c896fe29 1436
866cb6cb 1437 s->op_dead_args = tcg_malloc(nb_ops * sizeof(uint16_t));
ec7a869d 1438 s->op_sync_args = tcg_malloc(nb_ops * sizeof(uint8_t));
c896fe29
FB
1439
1440 dead_temps = tcg_malloc(s->nb_temps);
9c43b68d
AJ
1441 mem_temps = tcg_malloc(s->nb_temps);
1442 tcg_la_func_end(s, dead_temps, mem_temps);
c896fe29 1443
c4afe5c4 1444 args = s->gen_opparam_ptr;
c896fe29
FB
1445 op_index = nb_ops - 1;
1446 while (op_index >= 0) {
92414b31 1447 op = s->gen_opc_buf[op_index];
c896fe29
FB
1448 def = &tcg_op_defs[op];
1449 switch(op) {
1450 case INDEX_op_call:
c6e113f5
FB
1451 {
1452 int call_flags;
c896fe29 1453
c6e113f5
FB
1454 nb_args = args[-1];
1455 args -= nb_args;
cf066674
RH
1456 arg = *args++;
1457 nb_iargs = arg & 0xffff;
1458 nb_oargs = arg >> 16;
1459 call_flags = args[nb_oargs + nb_iargs + 1];
c6e113f5
FB
1460
1461 /* pure functions can be removed if their result is not
1462 used */
78505279 1463 if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) {
cf066674 1464 for (i = 0; i < nb_oargs; i++) {
c6e113f5 1465 arg = args[i];
9c43b68d 1466 if (!dead_temps[arg] || mem_temps[arg]) {
c6e113f5 1467 goto do_not_remove_call;
9c43b68d 1468 }
c6e113f5 1469 }
92414b31 1470 tcg_set_nop(s, s->gen_opc_buf + op_index,
c6e113f5
FB
1471 args - 1, nb_args);
1472 } else {
1473 do_not_remove_call:
c896fe29 1474
c6e113f5 1475 /* output args are dead */
6b64b624 1476 dead_args = 0;
ec7a869d 1477 sync_args = 0;
cf066674 1478 for (i = 0; i < nb_oargs; i++) {
c6e113f5 1479 arg = args[i];
6b64b624
AJ
1480 if (dead_temps[arg]) {
1481 dead_args |= (1 << i);
1482 }
9c43b68d
AJ
1483 if (mem_temps[arg]) {
1484 sync_args |= (1 << i);
1485 }
c6e113f5 1486 dead_temps[arg] = 1;
9c43b68d 1487 mem_temps[arg] = 0;
c6e113f5 1488 }
78505279
AJ
1489
1490 if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) {
1491 /* globals should be synced to memory */
1492 memset(mem_temps, 1, s->nb_globals);
1493 }
1494 if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS |
1495 TCG_CALL_NO_READ_GLOBALS))) {
9c43b68d
AJ
1496 /* globals should go back to memory */
1497 memset(dead_temps, 1, s->nb_globals);
b9c18f56
AJ
1498 }
1499
c6e113f5 1500 /* input args are live */
cf066674 1501 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
866cb6cb 1502 arg = args[i];
39cf05d3
FB
1503 if (arg != TCG_CALL_DUMMY_ARG) {
1504 if (dead_temps[arg]) {
866cb6cb 1505 dead_args |= (1 << i);
39cf05d3
FB
1506 }
1507 dead_temps[arg] = 0;
c6e113f5 1508 }
c6e113f5 1509 }
866cb6cb 1510 s->op_dead_args[op_index] = dead_args;
ec7a869d 1511 s->op_sync_args[op_index] = sync_args;
c896fe29 1512 }
c6e113f5 1513 args--;
c896fe29 1514 }
c896fe29 1515 break;
7e4597d7
FB
1516 case INDEX_op_debug_insn_start:
1517 args -= def->nb_args;
1518 break;
c896fe29
FB
1519 case INDEX_op_nopn:
1520 nb_args = args[-1];
1521 args -= nb_args;
1522 break;
5ff9d6a4
FB
1523 case INDEX_op_discard:
1524 args--;
1525 /* mark the temporary as dead */
1526 dead_temps[args[0]] = 1;
9c43b68d 1527 mem_temps[args[0]] = 0;
5ff9d6a4 1528 break;
c896fe29
FB
1529 case INDEX_op_end:
1530 break;
1305c451
RH
1531
1532 case INDEX_op_add2_i32:
f1fae40c
RH
1533 op_new = INDEX_op_add_i32;
1534 goto do_addsub2;
1305c451 1535 case INDEX_op_sub2_i32:
f1fae40c
RH
1536 op_new = INDEX_op_sub_i32;
1537 goto do_addsub2;
1538 case INDEX_op_add2_i64:
1539 op_new = INDEX_op_add_i64;
1540 goto do_addsub2;
1541 case INDEX_op_sub2_i64:
1542 op_new = INDEX_op_sub_i64;
1543 do_addsub2:
1305c451
RH
1544 args -= 6;
1545 nb_iargs = 4;
1546 nb_oargs = 2;
1547 /* Test if the high part of the operation is dead, but not
1548 the low part. The result can be optimized to a simple
1549 add or sub. This happens often for x86_64 guest when the
1550 cpu mode is set to 32 bit. */
3c5645fa
KB
1551 if (dead_temps[args[1]] && !mem_temps[args[1]]) {
1552 if (dead_temps[args[0]] && !mem_temps[args[0]]) {
1305c451
RH
1553 goto do_remove;
1554 }
1555 /* Create the single operation plus nop. */
f1fae40c 1556 s->gen_opc_buf[op_index] = op = op_new;
1305c451
RH
1557 args[1] = args[2];
1558 args[2] = args[4];
92414b31
EV
1559 assert(s->gen_opc_buf[op_index + 1] == INDEX_op_nop);
1560 tcg_set_nop(s, s->gen_opc_buf + op_index + 1, args + 3, 3);
1305c451
RH
1561 /* Fall through and mark the single-word operation live. */
1562 nb_iargs = 2;
1563 nb_oargs = 1;
1564 }
1565 goto do_not_remove;
1566
1414968a 1567 case INDEX_op_mulu2_i32:
03271524
RH
1568 op_new = INDEX_op_mul_i32;
1569 op_new2 = INDEX_op_muluh_i32;
1570 have_op_new2 = TCG_TARGET_HAS_muluh_i32;
1571 goto do_mul2;
f1fae40c
RH
1572 case INDEX_op_muls2_i32:
1573 op_new = INDEX_op_mul_i32;
03271524
RH
1574 op_new2 = INDEX_op_mulsh_i32;
1575 have_op_new2 = TCG_TARGET_HAS_mulsh_i32;
f1fae40c
RH
1576 goto do_mul2;
1577 case INDEX_op_mulu2_i64:
03271524
RH
1578 op_new = INDEX_op_mul_i64;
1579 op_new2 = INDEX_op_muluh_i64;
1580 have_op_new2 = TCG_TARGET_HAS_muluh_i64;
1581 goto do_mul2;
f1fae40c
RH
1582 case INDEX_op_muls2_i64:
1583 op_new = INDEX_op_mul_i64;
03271524
RH
1584 op_new2 = INDEX_op_mulsh_i64;
1585 have_op_new2 = TCG_TARGET_HAS_mulsh_i64;
1586 goto do_mul2;
f1fae40c 1587 do_mul2:
1414968a
RH
1588 args -= 4;
1589 nb_iargs = 2;
1590 nb_oargs = 2;
3c5645fa
KB
1591 if (dead_temps[args[1]] && !mem_temps[args[1]]) {
1592 if (dead_temps[args[0]] && !mem_temps[args[0]]) {
03271524 1593 /* Both parts of the operation are dead. */
1414968a
RH
1594 goto do_remove;
1595 }
03271524 1596 /* The high part of the operation is dead; generate the low. */
f1fae40c 1597 s->gen_opc_buf[op_index] = op = op_new;
1414968a
RH
1598 args[1] = args[2];
1599 args[2] = args[3];
03271524
RH
1600 } else if (have_op_new2 && dead_temps[args[0]]
1601 && !mem_temps[args[0]]) {
1602 /* The low part of the operation is dead; generate the high. */
1603 s->gen_opc_buf[op_index] = op = op_new2;
1604 args[0] = args[1];
1605 args[1] = args[2];
1606 args[2] = args[3];
1607 } else {
1608 goto do_not_remove;
1414968a 1609 }
03271524
RH
1610 assert(s->gen_opc_buf[op_index + 1] == INDEX_op_nop);
1611 tcg_set_nop(s, s->gen_opc_buf + op_index + 1, args + 3, 1);
1612 /* Mark the single-word operation live. */
1613 nb_oargs = 1;
1414968a
RH
1614 goto do_not_remove;
1615
c896fe29 1616 default:
1305c451 1617 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
49516bc0
AJ
1618 args -= def->nb_args;
1619 nb_iargs = def->nb_iargs;
1620 nb_oargs = def->nb_oargs;
c896fe29 1621
49516bc0
AJ
1622 /* Test if the operation can be removed because all
1623 its outputs are dead. We assume that nb_oargs == 0
1624 implies side effects */
1625 if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) {
1626 for(i = 0; i < nb_oargs; i++) {
1627 arg = args[i];
9c43b68d 1628 if (!dead_temps[arg] || mem_temps[arg]) {
49516bc0 1629 goto do_not_remove;
9c43b68d 1630 }
49516bc0 1631 }
1305c451 1632 do_remove:
92414b31 1633 tcg_set_nop(s, s->gen_opc_buf + op_index, args, def->nb_args);
c896fe29 1634#ifdef CONFIG_PROFILER
49516bc0 1635 s->del_op_count++;
c896fe29 1636#endif
49516bc0
AJ
1637 } else {
1638 do_not_remove:
c896fe29 1639
49516bc0 1640 /* output args are dead */
6b64b624 1641 dead_args = 0;
ec7a869d 1642 sync_args = 0;
49516bc0
AJ
1643 for(i = 0; i < nb_oargs; i++) {
1644 arg = args[i];
6b64b624
AJ
1645 if (dead_temps[arg]) {
1646 dead_args |= (1 << i);
1647 }
9c43b68d
AJ
1648 if (mem_temps[arg]) {
1649 sync_args |= (1 << i);
1650 }
49516bc0 1651 dead_temps[arg] = 1;
9c43b68d 1652 mem_temps[arg] = 0;
49516bc0
AJ
1653 }
1654
1655 /* if end of basic block, update */
1656 if (def->flags & TCG_OPF_BB_END) {
9c43b68d 1657 tcg_la_bb_end(s, dead_temps, mem_temps);
3d5c5f87
AJ
1658 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) {
1659 /* globals should be synced to memory */
9c43b68d 1660 memset(mem_temps, 1, s->nb_globals);
49516bc0
AJ
1661 }
1662
1663 /* input args are live */
866cb6cb
AJ
1664 for(i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
1665 arg = args[i];
49516bc0 1666 if (dead_temps[arg]) {
866cb6cb 1667 dead_args |= (1 << i);
c896fe29 1668 }
49516bc0 1669 dead_temps[arg] = 0;
c896fe29 1670 }
866cb6cb 1671 s->op_dead_args[op_index] = dead_args;
ec7a869d 1672 s->op_sync_args[op_index] = sync_args;
c896fe29
FB
1673 }
1674 break;
1675 }
1676 op_index--;
1677 }
1678
1ff0a2c5 1679 if (args != s->gen_opparam_buf) {
c896fe29 1680 tcg_abort();
1ff0a2c5 1681 }
c896fe29
FB
1682}
1683#else
1684/* dummy liveness analysis */
655feed5 1685static void tcg_liveness_analysis(TCGContext *s)
c896fe29
FB
1686{
1687 int nb_ops;
92414b31 1688 nb_ops = s->gen_opc_ptr - s->gen_opc_buf;
c896fe29 1689
866cb6cb
AJ
1690 s->op_dead_args = tcg_malloc(nb_ops * sizeof(uint16_t));
1691 memset(s->op_dead_args, 0, nb_ops * sizeof(uint16_t));
ec7a869d
AJ
1692 s->op_sync_args = tcg_malloc(nb_ops * sizeof(uint8_t));
1693 memset(s->op_sync_args, 0, nb_ops * sizeof(uint8_t));
c896fe29
FB
1694}
1695#endif
1696
1697#ifndef NDEBUG
1698static void dump_regs(TCGContext *s)
1699{
1700 TCGTemp *ts;
1701 int i;
1702 char buf[64];
1703
1704 for(i = 0; i < s->nb_temps; i++) {
1705 ts = &s->temps[i];
ac56dd48 1706 printf(" %10s: ", tcg_get_arg_str_idx(s, buf, sizeof(buf), i));
c896fe29
FB
1707 switch(ts->val_type) {
1708 case TEMP_VAL_REG:
1709 printf("%s", tcg_target_reg_names[ts->reg]);
1710 break;
1711 case TEMP_VAL_MEM:
1712 printf("%d(%s)", (int)ts->mem_offset, tcg_target_reg_names[ts->mem_reg]);
1713 break;
1714 case TEMP_VAL_CONST:
1715 printf("$0x%" TCG_PRIlx, ts->val);
1716 break;
1717 case TEMP_VAL_DEAD:
1718 printf("D");
1719 break;
1720 default:
1721 printf("???");
1722 break;
1723 }
1724 printf("\n");
1725 }
1726
1727 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
1728 if (s->reg_to_temp[i] >= 0) {
1729 printf("%s: %s\n",
1730 tcg_target_reg_names[i],
ac56dd48 1731 tcg_get_arg_str_idx(s, buf, sizeof(buf), s->reg_to_temp[i]));
c896fe29
FB
1732 }
1733 }
1734}
1735
1736static void check_regs(TCGContext *s)
1737{
1738 int reg, k;
1739 TCGTemp *ts;
1740 char buf[64];
1741
1742 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
1743 k = s->reg_to_temp[reg];
1744 if (k >= 0) {
1745 ts = &s->temps[k];
1746 if (ts->val_type != TEMP_VAL_REG ||
1747 ts->reg != reg) {
1748 printf("Inconsistency for register %s:\n",
1749 tcg_target_reg_names[reg]);
b03cce8e 1750 goto fail;
c896fe29
FB
1751 }
1752 }
1753 }
1754 for(k = 0; k < s->nb_temps; k++) {
1755 ts = &s->temps[k];
1756 if (ts->val_type == TEMP_VAL_REG &&
1757 !ts->fixed_reg &&
1758 s->reg_to_temp[ts->reg] != k) {
1759 printf("Inconsistency for temp %s:\n",
ac56dd48 1760 tcg_get_arg_str_idx(s, buf, sizeof(buf), k));
b03cce8e 1761 fail:
c896fe29
FB
1762 printf("reg state:\n");
1763 dump_regs(s);
1764 tcg_abort();
1765 }
1766 }
1767}
1768#endif
1769
1770static void temp_allocate_frame(TCGContext *s, int temp)
1771{
1772 TCGTemp *ts;
1773 ts = &s->temps[temp];
9b9c37c3
RH
1774#if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64)
1775 /* Sparc64 stack is accessed with offset of 2047 */
b591dc59
BS
1776 s->current_frame_offset = (s->current_frame_offset +
1777 (tcg_target_long)sizeof(tcg_target_long) - 1) &
1778 ~(sizeof(tcg_target_long) - 1);
f44c9960 1779#endif
b591dc59
BS
1780 if (s->current_frame_offset + (tcg_target_long)sizeof(tcg_target_long) >
1781 s->frame_end) {
5ff9d6a4 1782 tcg_abort();
b591dc59 1783 }
c896fe29
FB
1784 ts->mem_offset = s->current_frame_offset;
1785 ts->mem_reg = s->frame_reg;
1786 ts->mem_allocated = 1;
e2c6d1b4 1787 s->current_frame_offset += sizeof(tcg_target_long);
c896fe29
FB
1788}
1789
7f6ceedf
AJ
1790/* sync register 'reg' by saving it to the corresponding temporary */
1791static inline void tcg_reg_sync(TCGContext *s, int reg)
1792{
1793 TCGTemp *ts;
1794 int temp;
1795
1796 temp = s->reg_to_temp[reg];
1797 ts = &s->temps[temp];
1798 assert(ts->val_type == TEMP_VAL_REG);
1799 if (!ts->mem_coherent && !ts->fixed_reg) {
1800 if (!ts->mem_allocated) {
1801 temp_allocate_frame(s, temp);
1802 }
1803 tcg_out_st(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
1804 }
1805 ts->mem_coherent = 1;
1806}
1807
c896fe29
FB
1808/* free register 'reg' by spilling the corresponding temporary if necessary */
1809static void tcg_reg_free(TCGContext *s, int reg)
1810{
c896fe29
FB
1811 int temp;
1812
1813 temp = s->reg_to_temp[reg];
1814 if (temp != -1) {
7f6ceedf
AJ
1815 tcg_reg_sync(s, reg);
1816 s->temps[temp].val_type = TEMP_VAL_MEM;
c896fe29
FB
1817 s->reg_to_temp[reg] = -1;
1818 }
1819}
1820
1821/* Allocate a register belonging to reg1 & ~reg2 */
1822static int tcg_reg_alloc(TCGContext *s, TCGRegSet reg1, TCGRegSet reg2)
1823{
1824 int i, reg;
1825 TCGRegSet reg_ct;
1826
1827 tcg_regset_andnot(reg_ct, reg1, reg2);
1828
1829 /* first try free registers */
0954d0d9 1830 for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
c896fe29
FB
1831 reg = tcg_target_reg_alloc_order[i];
1832 if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] == -1)
1833 return reg;
1834 }
1835
1836 /* XXX: do better spill choice */
0954d0d9 1837 for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
c896fe29
FB
1838 reg = tcg_target_reg_alloc_order[i];
1839 if (tcg_regset_test_reg(reg_ct, reg)) {
1840 tcg_reg_free(s, reg);
1841 return reg;
1842 }
1843 }
1844
1845 tcg_abort();
1846}
1847
639368dd
AJ
1848/* mark a temporary as dead. */
1849static inline void temp_dead(TCGContext *s, int temp)
1850{
1851 TCGTemp *ts;
1852
1853 ts = &s->temps[temp];
1854 if (!ts->fixed_reg) {
1855 if (ts->val_type == TEMP_VAL_REG) {
1856 s->reg_to_temp[ts->reg] = -1;
1857 }
e5138db5 1858 if (temp < s->nb_globals || ts->temp_local) {
639368dd
AJ
1859 ts->val_type = TEMP_VAL_MEM;
1860 } else {
1861 ts->val_type = TEMP_VAL_DEAD;
1862 }
1863 }
1864}
1865
1ad80729 1866/* sync a temporary to memory. 'allocated_regs' is used in case a
641d5fbe 1867 temporary registers needs to be allocated to store a constant. */
1ad80729 1868static inline void temp_sync(TCGContext *s, int temp, TCGRegSet allocated_regs)
641d5fbe
FB
1869{
1870 TCGTemp *ts;
641d5fbe
FB
1871
1872 ts = &s->temps[temp];
1873 if (!ts->fixed_reg) {
1874 switch(ts->val_type) {
1ad80729
AJ
1875 case TEMP_VAL_CONST:
1876 ts->reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
1877 allocated_regs);
1878 ts->val_type = TEMP_VAL_REG;
1879 s->reg_to_temp[ts->reg] = temp;
1880 ts->mem_coherent = 0;
1881 tcg_out_movi(s, ts->type, ts->reg, ts->val);
1882 /* fallthrough*/
641d5fbe 1883 case TEMP_VAL_REG:
1ad80729 1884 tcg_reg_sync(s, ts->reg);
641d5fbe
FB
1885 break;
1886 case TEMP_VAL_DEAD:
641d5fbe
FB
1887 case TEMP_VAL_MEM:
1888 break;
1889 default:
1890 tcg_abort();
1891 }
1892 }
1893}
1894
1ad80729
AJ
1895/* save a temporary to memory. 'allocated_regs' is used in case a
1896 temporary registers needs to be allocated to store a constant. */
1897static inline void temp_save(TCGContext *s, int temp, TCGRegSet allocated_regs)
1898{
2c0366f0
AJ
1899#ifdef USE_LIVENESS_ANALYSIS
1900 /* The liveness analysis already ensures that globals are back
1901 in memory. Keep an assert for safety. */
1902 assert(s->temps[temp].val_type == TEMP_VAL_MEM || s->temps[temp].fixed_reg);
1903#else
1ad80729
AJ
1904 temp_sync(s, temp, allocated_regs);
1905 temp_dead(s, temp);
2c0366f0 1906#endif
1ad80729
AJ
1907}
1908
9814dd27 1909/* save globals to their canonical location and assume they can be
e8996ee0
FB
1910 modified be the following code. 'allocated_regs' is used in case a
1911 temporary registers needs to be allocated to store a constant. */
1912static void save_globals(TCGContext *s, TCGRegSet allocated_regs)
c896fe29 1913{
641d5fbe 1914 int i;
c896fe29
FB
1915
1916 for(i = 0; i < s->nb_globals; i++) {
641d5fbe 1917 temp_save(s, i, allocated_regs);
c896fe29 1918 }
e5097dc8
FB
1919}
1920
3d5c5f87
AJ
1921/* sync globals to their canonical location and assume they can be
1922 read by the following code. 'allocated_regs' is used in case a
1923 temporary registers needs to be allocated to store a constant. */
1924static void sync_globals(TCGContext *s, TCGRegSet allocated_regs)
1925{
1926 int i;
1927
1928 for (i = 0; i < s->nb_globals; i++) {
1929#ifdef USE_LIVENESS_ANALYSIS
1930 assert(s->temps[i].val_type != TEMP_VAL_REG || s->temps[i].fixed_reg ||
1931 s->temps[i].mem_coherent);
1932#else
1933 temp_sync(s, i, allocated_regs);
1934#endif
1935 }
1936}
1937
e5097dc8 1938/* at the end of a basic block, we assume all temporaries are dead and
e8996ee0
FB
1939 all globals are stored at their canonical location. */
1940static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs)
e5097dc8
FB
1941{
1942 TCGTemp *ts;
1943 int i;
1944
c896fe29
FB
1945 for(i = s->nb_globals; i < s->nb_temps; i++) {
1946 ts = &s->temps[i];
641d5fbe
FB
1947 if (ts->temp_local) {
1948 temp_save(s, i, allocated_regs);
1949 } else {
2c0366f0
AJ
1950#ifdef USE_LIVENESS_ANALYSIS
1951 /* The liveness analysis already ensures that temps are dead.
1952 Keep an assert for safety. */
1953 assert(ts->val_type == TEMP_VAL_DEAD);
1954#else
639368dd 1955 temp_dead(s, i);
2c0366f0 1956#endif
c896fe29
FB
1957 }
1958 }
e8996ee0
FB
1959
1960 save_globals(s, allocated_regs);
c896fe29
FB
1961}
1962
866cb6cb 1963#define IS_DEAD_ARG(n) ((dead_args >> (n)) & 1)
ec7a869d 1964#define NEED_SYNC_ARG(n) ((sync_args >> (n)) & 1)
c896fe29 1965
ec7a869d
AJ
1966static void tcg_reg_alloc_movi(TCGContext *s, const TCGArg *args,
1967 uint16_t dead_args, uint8_t sync_args)
e8996ee0
FB
1968{
1969 TCGTemp *ots;
1970 tcg_target_ulong val;
1971
1972 ots = &s->temps[args[0]];
1973 val = args[1];
1974
1975 if (ots->fixed_reg) {
1976 /* for fixed registers, we do not do any constant
1977 propagation */
1978 tcg_out_movi(s, ots->type, ots->reg, val);
1979 } else {
1235fc06 1980 /* The movi is not explicitly generated here */
e8996ee0
FB
1981 if (ots->val_type == TEMP_VAL_REG)
1982 s->reg_to_temp[ots->reg] = -1;
1983 ots->val_type = TEMP_VAL_CONST;
1984 ots->val = val;
1985 }
ec7a869d
AJ
1986 if (NEED_SYNC_ARG(0)) {
1987 temp_sync(s, args[0], s->reserved_regs);
1988 }
4c4e1ab2
AJ
1989 if (IS_DEAD_ARG(0)) {
1990 temp_dead(s, args[0]);
1991 }
e8996ee0
FB
1992}
1993
c896fe29 1994static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
ec7a869d
AJ
1995 const TCGArg *args, uint16_t dead_args,
1996 uint8_t sync_args)
c896fe29 1997{
c29c1d7e 1998 TCGRegSet allocated_regs;
c896fe29 1999 TCGTemp *ts, *ots;
450445d5 2000 TCGType otype, itype;
c896fe29 2001
c29c1d7e 2002 tcg_regset_set(allocated_regs, s->reserved_regs);
c896fe29
FB
2003 ots = &s->temps[args[0]];
2004 ts = &s->temps[args[1]];
450445d5
RH
2005
2006 /* Note that otype != itype for no-op truncation. */
2007 otype = ots->type;
2008 itype = ts->type;
c29c1d7e
AJ
2009
2010 /* If the source value is not in a register, and we're going to be
2011 forced to have it in a register in order to perform the copy,
2012 then copy the SOURCE value into its own register first. That way
2013 we don't have to reload SOURCE the next time it is used. */
2014 if (((NEED_SYNC_ARG(0) || ots->fixed_reg) && ts->val_type != TEMP_VAL_REG)
2015 || ts->val_type == TEMP_VAL_MEM) {
450445d5 2016 ts->reg = tcg_reg_alloc(s, tcg_target_available_regs[itype],
af3cbfbe 2017 allocated_regs);
c29c1d7e 2018 if (ts->val_type == TEMP_VAL_MEM) {
450445d5 2019 tcg_out_ld(s, itype, ts->reg, ts->mem_reg, ts->mem_offset);
c29c1d7e
AJ
2020 ts->mem_coherent = 1;
2021 } else if (ts->val_type == TEMP_VAL_CONST) {
450445d5 2022 tcg_out_movi(s, itype, ts->reg, ts->val);
c29c1d7e
AJ
2023 }
2024 s->reg_to_temp[ts->reg] = args[1];
2025 ts->val_type = TEMP_VAL_REG;
2026 }
c896fe29 2027
c29c1d7e
AJ
2028 if (IS_DEAD_ARG(0) && !ots->fixed_reg) {
2029 /* mov to a non-saved dead register makes no sense (even with
2030 liveness analysis disabled). */
2031 assert(NEED_SYNC_ARG(0));
2032 /* The code above should have moved the temp to a register. */
2033 assert(ts->val_type == TEMP_VAL_REG);
2034 if (!ots->mem_allocated) {
2035 temp_allocate_frame(s, args[0]);
2036 }
450445d5 2037 tcg_out_st(s, otype, ts->reg, ots->mem_reg, ots->mem_offset);
c29c1d7e
AJ
2038 if (IS_DEAD_ARG(1)) {
2039 temp_dead(s, args[1]);
2040 }
2041 temp_dead(s, args[0]);
2042 } else if (ts->val_type == TEMP_VAL_CONST) {
2043 /* propagate constant */
2044 if (ots->val_type == TEMP_VAL_REG) {
2045 s->reg_to_temp[ots->reg] = -1;
2046 }
2047 ots->val_type = TEMP_VAL_CONST;
2048 ots->val = ts->val;
2049 } else {
2050 /* The code in the first if block should have moved the
2051 temp to a register. */
2052 assert(ts->val_type == TEMP_VAL_REG);
866cb6cb 2053 if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) {
c896fe29 2054 /* the mov can be suppressed */
c29c1d7e 2055 if (ots->val_type == TEMP_VAL_REG) {
c896fe29 2056 s->reg_to_temp[ots->reg] = -1;
c29c1d7e
AJ
2057 }
2058 ots->reg = ts->reg;
639368dd 2059 temp_dead(s, args[1]);
c896fe29 2060 } else {
c29c1d7e
AJ
2061 if (ots->val_type != TEMP_VAL_REG) {
2062 /* When allocating a new register, make sure to not spill the
2063 input one. */
2064 tcg_regset_set_reg(allocated_regs, ts->reg);
450445d5 2065 ots->reg = tcg_reg_alloc(s, tcg_target_available_regs[otype],
af3cbfbe 2066 allocated_regs);
c896fe29 2067 }
450445d5 2068 tcg_out_mov(s, otype, ots->reg, ts->reg);
c896fe29 2069 }
c29c1d7e
AJ
2070 ots->val_type = TEMP_VAL_REG;
2071 ots->mem_coherent = 0;
2072 s->reg_to_temp[ots->reg] = args[0];
2073 if (NEED_SYNC_ARG(0)) {
2074 tcg_reg_sync(s, ots->reg);
c896fe29 2075 }
ec7a869d 2076 }
c896fe29
FB
2077}
2078
2079static void tcg_reg_alloc_op(TCGContext *s,
a9751609 2080 const TCGOpDef *def, TCGOpcode opc,
ec7a869d
AJ
2081 const TCGArg *args, uint16_t dead_args,
2082 uint8_t sync_args)
c896fe29
FB
2083{
2084 TCGRegSet allocated_regs;
2085 int i, k, nb_iargs, nb_oargs, reg;
2086 TCGArg arg;
2087 const TCGArgConstraint *arg_ct;
2088 TCGTemp *ts;
2089 TCGArg new_args[TCG_MAX_OP_ARGS];
2090 int const_args[TCG_MAX_OP_ARGS];
2091
2092 nb_oargs = def->nb_oargs;
2093 nb_iargs = def->nb_iargs;
2094
2095 /* copy constants */
2096 memcpy(new_args + nb_oargs + nb_iargs,
2097 args + nb_oargs + nb_iargs,
2098 sizeof(TCGArg) * def->nb_cargs);
2099
2100 /* satisfy input constraints */
2101 tcg_regset_set(allocated_regs, s->reserved_regs);
2102 for(k = 0; k < nb_iargs; k++) {
2103 i = def->sorted_args[nb_oargs + k];
2104 arg = args[i];
2105 arg_ct = &def->args_ct[i];
2106 ts = &s->temps[arg];
2107 if (ts->val_type == TEMP_VAL_MEM) {
2108 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
e4d5434c 2109 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
c896fe29
FB
2110 ts->val_type = TEMP_VAL_REG;
2111 ts->reg = reg;
2112 ts->mem_coherent = 1;
2113 s->reg_to_temp[reg] = arg;
2114 } else if (ts->val_type == TEMP_VAL_CONST) {
f6c6afc1 2115 if (tcg_target_const_match(ts->val, ts->type, arg_ct)) {
c896fe29
FB
2116 /* constant is OK for instruction */
2117 const_args[i] = 1;
2118 new_args[i] = ts->val;
2119 goto iarg_end;
2120 } else {
e8996ee0 2121 /* need to move to a register */
c896fe29
FB
2122 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
2123 tcg_out_movi(s, ts->type, reg, ts->val);
e8996ee0
FB
2124 ts->val_type = TEMP_VAL_REG;
2125 ts->reg = reg;
2126 ts->mem_coherent = 0;
2127 s->reg_to_temp[reg] = arg;
c896fe29
FB
2128 }
2129 }
2130 assert(ts->val_type == TEMP_VAL_REG);
5ff9d6a4
FB
2131 if (arg_ct->ct & TCG_CT_IALIAS) {
2132 if (ts->fixed_reg) {
2133 /* if fixed register, we must allocate a new register
2134 if the alias is not the same register */
2135 if (arg != args[arg_ct->alias_index])
2136 goto allocate_in_reg;
2137 } else {
2138 /* if the input is aliased to an output and if it is
2139 not dead after the instruction, we must allocate
2140 a new register and move it */
866cb6cb 2141 if (!IS_DEAD_ARG(i)) {
5ff9d6a4 2142 goto allocate_in_reg;
866cb6cb 2143 }
5ff9d6a4 2144 }
c896fe29
FB
2145 }
2146 reg = ts->reg;
2147 if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
2148 /* nothing to do : the constraint is satisfied */
2149 } else {
2150 allocate_in_reg:
2151 /* allocate a new register matching the constraint
2152 and move the temporary register into it */
2153 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
3b6dac34 2154 tcg_out_mov(s, ts->type, reg, ts->reg);
c896fe29 2155 }
c896fe29
FB
2156 new_args[i] = reg;
2157 const_args[i] = 0;
2158 tcg_regset_set_reg(allocated_regs, reg);
2159 iarg_end: ;
2160 }
2161
a52ad07e
AJ
2162 /* mark dead temporaries and free the associated registers */
2163 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
2164 if (IS_DEAD_ARG(i)) {
2165 temp_dead(s, args[i]);
2166 }
2167 }
2168
e8996ee0
FB
2169 if (def->flags & TCG_OPF_BB_END) {
2170 tcg_reg_alloc_bb_end(s, allocated_regs);
2171 } else {
e8996ee0
FB
2172 if (def->flags & TCG_OPF_CALL_CLOBBER) {
2173 /* XXX: permit generic clobber register list ? */
2174 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
2175 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) {
2176 tcg_reg_free(s, reg);
2177 }
c896fe29 2178 }
3d5c5f87
AJ
2179 }
2180 if (def->flags & TCG_OPF_SIDE_EFFECTS) {
2181 /* sync globals if the op has side effects and might trigger
2182 an exception. */
2183 sync_globals(s, allocated_regs);
c896fe29 2184 }
e8996ee0
FB
2185
2186 /* satisfy the output constraints */
2187 tcg_regset_set(allocated_regs, s->reserved_regs);
2188 for(k = 0; k < nb_oargs; k++) {
2189 i = def->sorted_args[k];
2190 arg = args[i];
2191 arg_ct = &def->args_ct[i];
2192 ts = &s->temps[arg];
2193 if (arg_ct->ct & TCG_CT_ALIAS) {
2194 reg = new_args[arg_ct->alias_index];
2195 } else {
2196 /* if fixed register, we try to use it */
2197 reg = ts->reg;
2198 if (ts->fixed_reg &&
2199 tcg_regset_test_reg(arg_ct->u.regs, reg)) {
2200 goto oarg_end;
2201 }
2202 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
c896fe29 2203 }
e8996ee0
FB
2204 tcg_regset_set_reg(allocated_regs, reg);
2205 /* if a fixed register is used, then a move will be done afterwards */
2206 if (!ts->fixed_reg) {
ec7a869d
AJ
2207 if (ts->val_type == TEMP_VAL_REG) {
2208 s->reg_to_temp[ts->reg] = -1;
2209 }
2210 ts->val_type = TEMP_VAL_REG;
2211 ts->reg = reg;
2212 /* temp value is modified, so the value kept in memory is
2213 potentially not the same */
2214 ts->mem_coherent = 0;
2215 s->reg_to_temp[reg] = arg;
e8996ee0
FB
2216 }
2217 oarg_end:
2218 new_args[i] = reg;
c896fe29 2219 }
c896fe29
FB
2220 }
2221
c896fe29
FB
2222 /* emit instruction */
2223 tcg_out_op(s, opc, new_args, const_args);
2224
2225 /* move the outputs in the correct register if needed */
2226 for(i = 0; i < nb_oargs; i++) {
2227 ts = &s->temps[args[i]];
2228 reg = new_args[i];
2229 if (ts->fixed_reg && ts->reg != reg) {
3b6dac34 2230 tcg_out_mov(s, ts->type, ts->reg, reg);
c896fe29 2231 }
ec7a869d
AJ
2232 if (NEED_SYNC_ARG(i)) {
2233 tcg_reg_sync(s, reg);
2234 }
2235 if (IS_DEAD_ARG(i)) {
2236 temp_dead(s, args[i]);
2237 }
c896fe29
FB
2238 }
2239}
2240
b03cce8e
FB
2241#ifdef TCG_TARGET_STACK_GROWSUP
2242#define STACK_DIR(x) (-(x))
2243#else
2244#define STACK_DIR(x) (x)
2245#endif
2246
c896fe29 2247static int tcg_reg_alloc_call(TCGContext *s, const TCGOpDef *def,
a9751609 2248 TCGOpcode opc, const TCGArg *args,
ec7a869d 2249 uint16_t dead_args, uint8_t sync_args)
c896fe29
FB
2250{
2251 int nb_iargs, nb_oargs, flags, nb_regs, i, reg, nb_params;
cf066674 2252 TCGArg arg;
c896fe29 2253 TCGTemp *ts;
d3452f1f
RH
2254 intptr_t stack_offset;
2255 size_t call_stack_size;
cf066674
RH
2256 tcg_insn_unit *func_addr;
2257 int allocate_args;
c896fe29 2258 TCGRegSet allocated_regs;
c896fe29
FB
2259
2260 arg = *args++;
2261
2262 nb_oargs = arg >> 16;
2263 nb_iargs = arg & 0xffff;
cf066674 2264 nb_params = nb_iargs;
c896fe29 2265
cf066674
RH
2266 func_addr = (tcg_insn_unit *)(intptr_t)args[nb_oargs + nb_iargs];
2267 flags = args[nb_oargs + nb_iargs + 1];
c896fe29 2268
6e17d0c5 2269 nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs);
cf066674 2270 if (nb_regs > nb_params) {
c896fe29 2271 nb_regs = nb_params;
cf066674 2272 }
c896fe29
FB
2273
2274 /* assign stack slots first */
c896fe29
FB
2275 call_stack_size = (nb_params - nb_regs) * sizeof(tcg_target_long);
2276 call_stack_size = (call_stack_size + TCG_TARGET_STACK_ALIGN - 1) &
2277 ~(TCG_TARGET_STACK_ALIGN - 1);
b03cce8e
FB
2278 allocate_args = (call_stack_size > TCG_STATIC_CALL_ARGS_SIZE);
2279 if (allocate_args) {
345649c0
BS
2280 /* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed,
2281 preallocate call stack */
2282 tcg_abort();
b03cce8e 2283 }
39cf05d3
FB
2284
2285 stack_offset = TCG_TARGET_CALL_STACK_OFFSET;
c896fe29
FB
2286 for(i = nb_regs; i < nb_params; i++) {
2287 arg = args[nb_oargs + i];
39cf05d3
FB
2288#ifdef TCG_TARGET_STACK_GROWSUP
2289 stack_offset -= sizeof(tcg_target_long);
2290#endif
2291 if (arg != TCG_CALL_DUMMY_ARG) {
2292 ts = &s->temps[arg];
2293 if (ts->val_type == TEMP_VAL_REG) {
2294 tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset);
2295 } else if (ts->val_type == TEMP_VAL_MEM) {
2296 reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
2297 s->reserved_regs);
2298 /* XXX: not correct if reading values from the stack */
2299 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
2300 tcg_out_st(s, ts->type, reg, TCG_REG_CALL_STACK, stack_offset);
2301 } else if (ts->val_type == TEMP_VAL_CONST) {
2302 reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
2303 s->reserved_regs);
2304 /* XXX: sign extend may be needed on some targets */
2305 tcg_out_movi(s, ts->type, reg, ts->val);
2306 tcg_out_st(s, ts->type, reg, TCG_REG_CALL_STACK, stack_offset);
2307 } else {
2308 tcg_abort();
2309 }
c896fe29 2310 }
39cf05d3
FB
2311#ifndef TCG_TARGET_STACK_GROWSUP
2312 stack_offset += sizeof(tcg_target_long);
2313#endif
c896fe29
FB
2314 }
2315
2316 /* assign input registers */
2317 tcg_regset_set(allocated_regs, s->reserved_regs);
2318 for(i = 0; i < nb_regs; i++) {
2319 arg = args[nb_oargs + i];
39cf05d3
FB
2320 if (arg != TCG_CALL_DUMMY_ARG) {
2321 ts = &s->temps[arg];
2322 reg = tcg_target_call_iarg_regs[i];
2323 tcg_reg_free(s, reg);
2324 if (ts->val_type == TEMP_VAL_REG) {
2325 if (ts->reg != reg) {
3b6dac34 2326 tcg_out_mov(s, ts->type, reg, ts->reg);
39cf05d3
FB
2327 }
2328 } else if (ts->val_type == TEMP_VAL_MEM) {
2329 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
2330 } else if (ts->val_type == TEMP_VAL_CONST) {
2331 /* XXX: sign extend ? */
2332 tcg_out_movi(s, ts->type, reg, ts->val);
2333 } else {
2334 tcg_abort();
c896fe29 2335 }
39cf05d3 2336 tcg_regset_set_reg(allocated_regs, reg);
c896fe29 2337 }
c896fe29
FB
2338 }
2339
c896fe29 2340 /* mark dead temporaries and free the associated registers */
866cb6cb 2341 for(i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
866cb6cb 2342 if (IS_DEAD_ARG(i)) {
639368dd 2343 temp_dead(s, args[i]);
c896fe29
FB
2344 }
2345 }
2346
2347 /* clobber call registers */
2348 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
2349 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) {
2350 tcg_reg_free(s, reg);
2351 }
2352 }
78505279
AJ
2353
2354 /* Save globals if they might be written by the helper, sync them if
2355 they might be read. */
2356 if (flags & TCG_CALL_NO_READ_GLOBALS) {
2357 /* Nothing to do */
2358 } else if (flags & TCG_CALL_NO_WRITE_GLOBALS) {
2359 sync_globals(s, allocated_regs);
2360 } else {
b9c18f56
AJ
2361 save_globals(s, allocated_regs);
2362 }
c896fe29 2363
cf066674 2364 tcg_out_call(s, func_addr);
c896fe29
FB
2365
2366 /* assign output registers and emit moves if needed */
2367 for(i = 0; i < nb_oargs; i++) {
2368 arg = args[i];
2369 ts = &s->temps[arg];
2370 reg = tcg_target_call_oarg_regs[i];
e8996ee0 2371 assert(s->reg_to_temp[reg] == -1);
34b1a49c 2372
c896fe29
FB
2373 if (ts->fixed_reg) {
2374 if (ts->reg != reg) {
3b6dac34 2375 tcg_out_mov(s, ts->type, ts->reg, reg);
c896fe29
FB
2376 }
2377 } else {
ec7a869d
AJ
2378 if (ts->val_type == TEMP_VAL_REG) {
2379 s->reg_to_temp[ts->reg] = -1;
2380 }
2381 ts->val_type = TEMP_VAL_REG;
2382 ts->reg = reg;
2383 ts->mem_coherent = 0;
2384 s->reg_to_temp[reg] = arg;
2385 if (NEED_SYNC_ARG(i)) {
2386 tcg_reg_sync(s, reg);
2387 }
8c11ad25 2388 if (IS_DEAD_ARG(i)) {
639368dd 2389 temp_dead(s, args[i]);
8c11ad25 2390 }
c896fe29
FB
2391 }
2392 }
2393
2394 return nb_iargs + nb_oargs + def->nb_cargs + 1;
2395}
2396
2397#ifdef CONFIG_PROFILER
2398
54604f74 2399static int64_t tcg_table_op_count[NB_OPS];
c896fe29 2400
871e6c35 2401static void dump_op_count(void)
c896fe29
FB
2402{
2403 int i;
2404 FILE *f;
54604f74 2405 f = fopen("/tmp/op.log", "w");
c896fe29 2406 for(i = INDEX_op_end; i < NB_OPS; i++) {
54604f74 2407 fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name, tcg_table_op_count[i]);
c896fe29
FB
2408 }
2409 fclose(f);
2410}
2411#endif
2412
2413
1813e175
RH
2414static inline int tcg_gen_code_common(TCGContext *s,
2415 tcg_insn_unit *gen_code_buf,
2ba1eeb6 2416 long search_pc)
c896fe29 2417{
a9751609
RH
2418 TCGOpcode opc;
2419 int op_index;
c896fe29 2420 const TCGOpDef *def;
c896fe29
FB
2421 const TCGArg *args;
2422
2423#ifdef DEBUG_DISAS
8fec2b8c 2424 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
93fcfe39 2425 qemu_log("OP:\n");
eeacee4d 2426 tcg_dump_ops(s);
93fcfe39 2427 qemu_log("\n");
c896fe29
FB
2428 }
2429#endif
2430
c5cc28ff
AJ
2431#ifdef CONFIG_PROFILER
2432 s->opt_time -= profile_getclock();
2433#endif
2434
8f2e8c07 2435#ifdef USE_TCG_OPTIMIZATIONS
c4afe5c4 2436 s->gen_opparam_ptr =
1ff0a2c5 2437 tcg_optimize(s, s->gen_opc_ptr, s->gen_opparam_buf, tcg_op_defs);
8f2e8c07
KB
2438#endif
2439
a23a9ec6 2440#ifdef CONFIG_PROFILER
c5cc28ff 2441 s->opt_time += profile_getclock();
a23a9ec6
FB
2442 s->la_time -= profile_getclock();
2443#endif
c5cc28ff 2444
c896fe29 2445 tcg_liveness_analysis(s);
c5cc28ff 2446
a23a9ec6
FB
2447#ifdef CONFIG_PROFILER
2448 s->la_time += profile_getclock();
2449#endif
c896fe29
FB
2450
2451#ifdef DEBUG_DISAS
8fec2b8c 2452 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) {
c5cc28ff 2453 qemu_log("OP after optimization and liveness analysis:\n");
eeacee4d 2454 tcg_dump_ops(s);
93fcfe39 2455 qemu_log("\n");
c896fe29
FB
2456 }
2457#endif
2458
2459 tcg_reg_alloc_start(s);
2460
2461 s->code_buf = gen_code_buf;
2462 s->code_ptr = gen_code_buf;
2463
9ecefc84
RH
2464 tcg_out_tb_init(s);
2465
1ff0a2c5 2466 args = s->gen_opparam_buf;
c896fe29 2467 op_index = 0;
b3db8758 2468
c896fe29 2469 for(;;) {
92414b31 2470 opc = s->gen_opc_buf[op_index];
c896fe29 2471#ifdef CONFIG_PROFILER
54604f74 2472 tcg_table_op_count[opc]++;
c896fe29
FB
2473#endif
2474 def = &tcg_op_defs[opc];
2475#if 0
2476 printf("%s: %d %d %d\n", def->name,
2477 def->nb_oargs, def->nb_iargs, def->nb_cargs);
2478 // dump_regs(s);
2479#endif
2480 switch(opc) {
2481 case INDEX_op_mov_i32:
c896fe29 2482 case INDEX_op_mov_i64:
ec7a869d
AJ
2483 tcg_reg_alloc_mov(s, def, args, s->op_dead_args[op_index],
2484 s->op_sync_args[op_index]);
c896fe29 2485 break;
e8996ee0 2486 case INDEX_op_movi_i32:
e8996ee0 2487 case INDEX_op_movi_i64:
ec7a869d
AJ
2488 tcg_reg_alloc_movi(s, args, s->op_dead_args[op_index],
2489 s->op_sync_args[op_index]);
e8996ee0 2490 break;
7e4597d7
FB
2491 case INDEX_op_debug_insn_start:
2492 /* debug instruction */
2493 break;
c896fe29
FB
2494 case INDEX_op_nop:
2495 case INDEX_op_nop1:
2496 case INDEX_op_nop2:
2497 case INDEX_op_nop3:
2498 break;
2499 case INDEX_op_nopn:
2500 args += args[0];
2501 goto next;
5ff9d6a4 2502 case INDEX_op_discard:
639368dd 2503 temp_dead(s, args[0]);
5ff9d6a4 2504 break;
c896fe29 2505 case INDEX_op_set_label:
e8996ee0 2506 tcg_reg_alloc_bb_end(s, s->reserved_regs);
9d6fca70 2507 tcg_out_label(s, args[0], s->code_ptr);
c896fe29
FB
2508 break;
2509 case INDEX_op_call:
ec7a869d
AJ
2510 args += tcg_reg_alloc_call(s, def, opc, args,
2511 s->op_dead_args[op_index],
2512 s->op_sync_args[op_index]);
c896fe29
FB
2513 goto next;
2514 case INDEX_op_end:
2515 goto the_end;
c896fe29 2516 default:
25c4d9cc
RH
2517 /* Sanity check that we've not introduced any unhandled opcodes. */
2518 if (def->flags & TCG_OPF_NOT_PRESENT) {
2519 tcg_abort();
2520 }
c896fe29
FB
2521 /* Note: in order to speed up the code, it would be much
2522 faster to have specialized register allocator functions for
2523 some common argument patterns */
ec7a869d
AJ
2524 tcg_reg_alloc_op(s, def, opc, args, s->op_dead_args[op_index],
2525 s->op_sync_args[op_index]);
c896fe29
FB
2526 break;
2527 }
2528 args += def->nb_args;
8df1ca4b 2529 next:
1813e175 2530 if (search_pc >= 0 && search_pc < tcg_current_code_size(s)) {
b314f270 2531 return op_index;
c896fe29
FB
2532 }
2533 op_index++;
2534#ifndef NDEBUG
2535 check_regs(s);
2536#endif
2537 }
2538 the_end:
b76f0d8c
YL
2539 /* Generate TB finalization at the end of block */
2540 tcg_out_tb_finalize(s);
c896fe29
FB
2541 return -1;
2542}
2543
1813e175 2544int tcg_gen_code(TCGContext *s, tcg_insn_unit *gen_code_buf)
c896fe29
FB
2545{
2546#ifdef CONFIG_PROFILER
2547 {
c896fe29 2548 int n;
92414b31 2549 n = (s->gen_opc_ptr - s->gen_opc_buf);
a23a9ec6
FB
2550 s->op_count += n;
2551 if (n > s->op_count_max)
2552 s->op_count_max = n;
2553
2554 s->temp_count += s->nb_temps;
2555 if (s->nb_temps > s->temp_count_max)
2556 s->temp_count_max = s->nb_temps;
c896fe29
FB
2557 }
2558#endif
2559
2ba1eeb6 2560 tcg_gen_code_common(s, gen_code_buf, -1);
c896fe29
FB
2561
2562 /* flush instruction cache */
1813e175 2563 flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
2aeabc08 2564
1813e175 2565 return tcg_current_code_size(s);
c896fe29
FB
2566}
2567
2ba1eeb6 2568/* Return the index of the micro operation such as the pc after is <
623e265c
PB
2569 offset bytes from the start of the TB. The contents of gen_code_buf must
2570 not be changed, though writing the same values is ok.
2571 Return -1 if not found. */
1813e175
RH
2572int tcg_gen_code_search_pc(TCGContext *s, tcg_insn_unit *gen_code_buf,
2573 long offset)
c896fe29 2574{
623e265c 2575 return tcg_gen_code_common(s, gen_code_buf, offset);
c896fe29 2576}
a23a9ec6
FB
2577
2578#ifdef CONFIG_PROFILER
405cf9ff 2579void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
a23a9ec6
FB
2580{
2581 TCGContext *s = &tcg_ctx;
2582 int64_t tot;
2583
2584 tot = s->interm_time + s->code_time;
2585 cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n",
2586 tot, tot / 2.4e9);
2587 cpu_fprintf(f, "translated TBs %" PRId64 " (aborted=%" PRId64 " %0.1f%%)\n",
2588 s->tb_count,
2589 s->tb_count1 - s->tb_count,
2590 s->tb_count1 ? (double)(s->tb_count1 - s->tb_count) / s->tb_count1 * 100.0 : 0);
2591 cpu_fprintf(f, "avg ops/TB %0.1f max=%d\n",
2592 s->tb_count ? (double)s->op_count / s->tb_count : 0, s->op_count_max);
a23a9ec6
FB
2593 cpu_fprintf(f, "deleted ops/TB %0.2f\n",
2594 s->tb_count ?
2595 (double)s->del_op_count / s->tb_count : 0);
2596 cpu_fprintf(f, "avg temps/TB %0.2f max=%d\n",
2597 s->tb_count ?
2598 (double)s->temp_count / s->tb_count : 0,
2599 s->temp_count_max);
2600
2601 cpu_fprintf(f, "cycles/op %0.1f\n",
2602 s->op_count ? (double)tot / s->op_count : 0);
2603 cpu_fprintf(f, "cycles/in byte %0.1f\n",
2604 s->code_in_len ? (double)tot / s->code_in_len : 0);
2605 cpu_fprintf(f, "cycles/out byte %0.1f\n",
2606 s->code_out_len ? (double)tot / s->code_out_len : 0);
2607 if (tot == 0)
2608 tot = 1;
2609 cpu_fprintf(f, " gen_interm time %0.1f%%\n",
2610 (double)s->interm_time / tot * 100.0);
2611 cpu_fprintf(f, " gen_code time %0.1f%%\n",
2612 (double)s->code_time / tot * 100.0);
c5cc28ff
AJ
2613 cpu_fprintf(f, "optim./code time %0.1f%%\n",
2614 (double)s->opt_time / (s->code_time ? s->code_time : 1)
2615 * 100.0);
a23a9ec6
FB
2616 cpu_fprintf(f, "liveness/code time %0.1f%%\n",
2617 (double)s->la_time / (s->code_time ? s->code_time : 1) * 100.0);
2618 cpu_fprintf(f, "cpu_restore count %" PRId64 "\n",
2619 s->restore_count);
2620 cpu_fprintf(f, " avg cycles %0.1f\n",
2621 s->restore_count ? (double)s->restore_time / s->restore_count : 0);
871e6c35
BS
2622
2623 dump_op_count();
a23a9ec6
FB
2624}
2625#else
405cf9ff 2626void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
a23a9ec6 2627{
24bf7b3a 2628 cpu_fprintf(f, "[TCG profiler not compiled]\n");
a23a9ec6
FB
2629}
2630#endif
813da627
RH
2631
2632#ifdef ELF_HOST_MACHINE
5872bbf2
RH
2633/* In order to use this feature, the backend needs to do three things:
2634
2635 (1) Define ELF_HOST_MACHINE to indicate both what value to
2636 put into the ELF image and to indicate support for the feature.
2637
2638 (2) Define tcg_register_jit. This should create a buffer containing
2639 the contents of a .debug_frame section that describes the post-
2640 prologue unwind info for the tcg machine.
2641
2642 (3) Call tcg_register_jit_int, with the constructed .debug_frame.
2643*/
813da627
RH
2644
2645/* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */
2646typedef enum {
2647 JIT_NOACTION = 0,
2648 JIT_REGISTER_FN,
2649 JIT_UNREGISTER_FN
2650} jit_actions_t;
2651
2652struct jit_code_entry {
2653 struct jit_code_entry *next_entry;
2654 struct jit_code_entry *prev_entry;
2655 const void *symfile_addr;
2656 uint64_t symfile_size;
2657};
2658
2659struct jit_descriptor {
2660 uint32_t version;
2661 uint32_t action_flag;
2662 struct jit_code_entry *relevant_entry;
2663 struct jit_code_entry *first_entry;
2664};
2665
2666void __jit_debug_register_code(void) __attribute__((noinline));
2667void __jit_debug_register_code(void)
2668{
2669 asm("");
2670}
2671
2672/* Must statically initialize the version, because GDB may check
2673 the version before we can set it. */
2674struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 };
2675
2676/* End GDB interface. */
2677
2678static int find_string(const char *strtab, const char *str)
2679{
2680 const char *p = strtab + 1;
2681
2682 while (1) {
2683 if (strcmp(p, str) == 0) {
2684 return p - strtab;
2685 }
2686 p += strlen(p) + 1;
2687 }
2688}
2689
5872bbf2 2690static void tcg_register_jit_int(void *buf_ptr, size_t buf_size,
2c90784a
RH
2691 const void *debug_frame,
2692 size_t debug_frame_size)
813da627 2693{
5872bbf2
RH
2694 struct __attribute__((packed)) DebugInfo {
2695 uint32_t len;
2696 uint16_t version;
2697 uint32_t abbrev;
2698 uint8_t ptr_size;
2699 uint8_t cu_die;
2700 uint16_t cu_lang;
2701 uintptr_t cu_low_pc;
2702 uintptr_t cu_high_pc;
2703 uint8_t fn_die;
2704 char fn_name[16];
2705 uintptr_t fn_low_pc;
2706 uintptr_t fn_high_pc;
2707 uint8_t cu_eoc;
2708 };
813da627
RH
2709
2710 struct ElfImage {
2711 ElfW(Ehdr) ehdr;
2712 ElfW(Phdr) phdr;
5872bbf2
RH
2713 ElfW(Shdr) shdr[7];
2714 ElfW(Sym) sym[2];
2715 struct DebugInfo di;
2716 uint8_t da[24];
2717 char str[80];
2718 };
2719
2720 struct ElfImage *img;
2721
2722 static const struct ElfImage img_template = {
2723 .ehdr = {
2724 .e_ident[EI_MAG0] = ELFMAG0,
2725 .e_ident[EI_MAG1] = ELFMAG1,
2726 .e_ident[EI_MAG2] = ELFMAG2,
2727 .e_ident[EI_MAG3] = ELFMAG3,
2728 .e_ident[EI_CLASS] = ELF_CLASS,
2729 .e_ident[EI_DATA] = ELF_DATA,
2730 .e_ident[EI_VERSION] = EV_CURRENT,
2731 .e_type = ET_EXEC,
2732 .e_machine = ELF_HOST_MACHINE,
2733 .e_version = EV_CURRENT,
2734 .e_phoff = offsetof(struct ElfImage, phdr),
2735 .e_shoff = offsetof(struct ElfImage, shdr),
2736 .e_ehsize = sizeof(ElfW(Shdr)),
2737 .e_phentsize = sizeof(ElfW(Phdr)),
2738 .e_phnum = 1,
2739 .e_shentsize = sizeof(ElfW(Shdr)),
2740 .e_shnum = ARRAY_SIZE(img->shdr),
2741 .e_shstrndx = ARRAY_SIZE(img->shdr) - 1,
abbb3eae
RH
2742#ifdef ELF_HOST_FLAGS
2743 .e_flags = ELF_HOST_FLAGS,
2744#endif
2745#ifdef ELF_OSABI
2746 .e_ident[EI_OSABI] = ELF_OSABI,
2747#endif
5872bbf2
RH
2748 },
2749 .phdr = {
2750 .p_type = PT_LOAD,
2751 .p_flags = PF_X,
2752 },
2753 .shdr = {
2754 [0] = { .sh_type = SHT_NULL },
2755 /* Trick: The contents of code_gen_buffer are not present in
2756 this fake ELF file; that got allocated elsewhere. Therefore
2757 we mark .text as SHT_NOBITS (similar to .bss) so that readers
2758 will not look for contents. We can record any address. */
2759 [1] = { /* .text */
2760 .sh_type = SHT_NOBITS,
2761 .sh_flags = SHF_EXECINSTR | SHF_ALLOC,
2762 },
2763 [2] = { /* .debug_info */
2764 .sh_type = SHT_PROGBITS,
2765 .sh_offset = offsetof(struct ElfImage, di),
2766 .sh_size = sizeof(struct DebugInfo),
2767 },
2768 [3] = { /* .debug_abbrev */
2769 .sh_type = SHT_PROGBITS,
2770 .sh_offset = offsetof(struct ElfImage, da),
2771 .sh_size = sizeof(img->da),
2772 },
2773 [4] = { /* .debug_frame */
2774 .sh_type = SHT_PROGBITS,
2775 .sh_offset = sizeof(struct ElfImage),
2776 },
2777 [5] = { /* .symtab */
2778 .sh_type = SHT_SYMTAB,
2779 .sh_offset = offsetof(struct ElfImage, sym),
2780 .sh_size = sizeof(img->sym),
2781 .sh_info = 1,
2782 .sh_link = ARRAY_SIZE(img->shdr) - 1,
2783 .sh_entsize = sizeof(ElfW(Sym)),
2784 },
2785 [6] = { /* .strtab */
2786 .sh_type = SHT_STRTAB,
2787 .sh_offset = offsetof(struct ElfImage, str),
2788 .sh_size = sizeof(img->str),
2789 }
2790 },
2791 .sym = {
2792 [1] = { /* code_gen_buffer */
2793 .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC),
2794 .st_shndx = 1,
2795 }
2796 },
2797 .di = {
2798 .len = sizeof(struct DebugInfo) - 4,
2799 .version = 2,
2800 .ptr_size = sizeof(void *),
2801 .cu_die = 1,
2802 .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */
2803 .fn_die = 2,
2804 .fn_name = "code_gen_buffer"
2805 },
2806 .da = {
2807 1, /* abbrev number (the cu) */
2808 0x11, 1, /* DW_TAG_compile_unit, has children */
2809 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */
2810 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2811 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2812 0, 0, /* end of abbrev */
2813 2, /* abbrev number (the fn) */
2814 0x2e, 0, /* DW_TAG_subprogram, no children */
2815 0x3, 0x8, /* DW_AT_name, DW_FORM_string */
2816 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2817 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2818 0, 0, /* end of abbrev */
2819 0 /* no more abbrev */
2820 },
2821 .str = "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0"
2822 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer",
813da627
RH
2823 };
2824
2825 /* We only need a single jit entry; statically allocate it. */
2826 static struct jit_code_entry one_entry;
2827
5872bbf2 2828 uintptr_t buf = (uintptr_t)buf_ptr;
813da627 2829 size_t img_size = sizeof(struct ElfImage) + debug_frame_size;
2c90784a 2830 DebugFrameHeader *dfh;
813da627 2831
5872bbf2
RH
2832 img = g_malloc(img_size);
2833 *img = img_template;
813da627 2834
5872bbf2
RH
2835 img->phdr.p_vaddr = buf;
2836 img->phdr.p_paddr = buf;
2837 img->phdr.p_memsz = buf_size;
813da627 2838
813da627 2839 img->shdr[1].sh_name = find_string(img->str, ".text");
5872bbf2 2840 img->shdr[1].sh_addr = buf;
813da627
RH
2841 img->shdr[1].sh_size = buf_size;
2842
5872bbf2
RH
2843 img->shdr[2].sh_name = find_string(img->str, ".debug_info");
2844 img->shdr[3].sh_name = find_string(img->str, ".debug_abbrev");
2845
2846 img->shdr[4].sh_name = find_string(img->str, ".debug_frame");
2847 img->shdr[4].sh_size = debug_frame_size;
2848
2849 img->shdr[5].sh_name = find_string(img->str, ".symtab");
2850 img->shdr[6].sh_name = find_string(img->str, ".strtab");
2851
2852 img->sym[1].st_name = find_string(img->str, "code_gen_buffer");
2853 img->sym[1].st_value = buf;
2854 img->sym[1].st_size = buf_size;
813da627 2855
5872bbf2 2856 img->di.cu_low_pc = buf;
45aba097 2857 img->di.cu_high_pc = buf + buf_size;
5872bbf2 2858 img->di.fn_low_pc = buf;
45aba097 2859 img->di.fn_high_pc = buf + buf_size;
813da627 2860
2c90784a
RH
2861 dfh = (DebugFrameHeader *)(img + 1);
2862 memcpy(dfh, debug_frame, debug_frame_size);
2863 dfh->fde.func_start = buf;
2864 dfh->fde.func_len = buf_size;
2865
813da627
RH
2866#ifdef DEBUG_JIT
2867 /* Enable this block to be able to debug the ELF image file creation.
2868 One can use readelf, objdump, or other inspection utilities. */
2869 {
2870 FILE *f = fopen("/tmp/qemu.jit", "w+b");
2871 if (f) {
5872bbf2 2872 if (fwrite(img, img_size, 1, f) != img_size) {
813da627
RH
2873 /* Avoid stupid unused return value warning for fwrite. */
2874 }
2875 fclose(f);
2876 }
2877 }
2878#endif
2879
2880 one_entry.symfile_addr = img;
2881 one_entry.symfile_size = img_size;
2882
2883 __jit_debug_descriptor.action_flag = JIT_REGISTER_FN;
2884 __jit_debug_descriptor.relevant_entry = &one_entry;
2885 __jit_debug_descriptor.first_entry = &one_entry;
2886 __jit_debug_register_code();
2887}
2888#else
5872bbf2
RH
2889/* No support for the feature. Provide the entry point expected by exec.c,
2890 and implement the internal function we declared earlier. */
813da627
RH
2891
2892static void tcg_register_jit_int(void *buf, size_t size,
2c90784a
RH
2893 const void *debug_frame,
2894 size_t debug_frame_size)
813da627
RH
2895{
2896}
2897
2898void tcg_register_jit(void *buf, size_t buf_size)
2899{
2900}
2901#endif /* ELF_HOST_MACHINE */
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