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Commit | Line | Data |
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5fafdf24 | 1 | /* |
bdd5003a PB |
2 | * Arm PrimeCell PL110 Color LCD Controller |
3 | * | |
2e9bdce5 | 4 | * Copyright (c) 2005-2009 CodeSourcery. |
bdd5003a PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GNU LGPL |
bdd5003a PB |
8 | */ |
9 | ||
83c9f4ca | 10 | #include "hw/sysbus.h" |
28ecbaee | 11 | #include "ui/console.h" |
47b43a1f | 12 | #include "framebuffer.h" |
28ecbaee | 13 | #include "ui/pixel_ops.h" |
bdd5003a PB |
14 | |
15 | #define PL110_CR_EN 0x001 | |
e9c05b42 | 16 | #define PL110_CR_BGR 0x100 |
bdd5003a PB |
17 | #define PL110_CR_BEBO 0x200 |
18 | #define PL110_CR_BEPO 0x400 | |
19 | #define PL110_CR_PWR 0x800 | |
20 | ||
21 | enum pl110_bppmode | |
22 | { | |
23 | BPP_1, | |
24 | BPP_2, | |
25 | BPP_4, | |
26 | BPP_8, | |
27 | BPP_16, | |
4fbf5556 PM |
28 | BPP_32, |
29 | BPP_16_565, /* PL111 only */ | |
30 | BPP_12 /* PL111 only */ | |
31 | }; | |
32 | ||
33 | ||
34 | /* The Versatile/PB uses a slightly modified PL110 controller. */ | |
35 | enum pl110_version | |
36 | { | |
37 | PL110, | |
38 | PL110_VERSATILE, | |
39 | PL111 | |
bdd5003a PB |
40 | }; |
41 | ||
5d7a11e4 AF |
42 | #define TYPE_PL110 "pl110" |
43 | #define PL110(obj) OBJECT_CHECK(PL110State, (obj), TYPE_PL110) | |
44 | ||
513960ea | 45 | typedef struct PL110State { |
5d7a11e4 AF |
46 | SysBusDevice parent_obj; |
47 | ||
1a6b31ce | 48 | MemoryRegion iomem; |
c78f7137 | 49 | QemuConsole *con; |
c60e08d9 | 50 | |
4fbf5556 | 51 | int version; |
bdd5003a PB |
52 | uint32_t timing[4]; |
53 | uint32_t cr; | |
54 | uint32_t upbase; | |
55 | uint32_t lpbase; | |
56 | uint32_t int_status; | |
57 | uint32_t int_mask; | |
58 | int cols; | |
59 | int rows; | |
60 | enum pl110_bppmode bpp; | |
61 | int invalidate; | |
242ea2c6 | 62 | uint32_t mux_ctrl; |
6e4c0d1f PM |
63 | uint32_t palette[256]; |
64 | uint32_t raw_palette[128]; | |
d537cf6c | 65 | qemu_irq irq; |
513960ea | 66 | } PL110State; |
bdd5003a | 67 | |
128939a9 PM |
68 | static int vmstate_pl110_post_load(void *opaque, int version_id); |
69 | ||
8c60d065 PM |
70 | static const VMStateDescription vmstate_pl110 = { |
71 | .name = "pl110", | |
242ea2c6 | 72 | .version_id = 2, |
8c60d065 | 73 | .minimum_version_id = 1, |
128939a9 | 74 | .post_load = vmstate_pl110_post_load, |
8c60d065 | 75 | .fields = (VMStateField[]) { |
513960ea AF |
76 | VMSTATE_INT32(version, PL110State), |
77 | VMSTATE_UINT32_ARRAY(timing, PL110State, 4), | |
78 | VMSTATE_UINT32(cr, PL110State), | |
79 | VMSTATE_UINT32(upbase, PL110State), | |
80 | VMSTATE_UINT32(lpbase, PL110State), | |
81 | VMSTATE_UINT32(int_status, PL110State), | |
82 | VMSTATE_UINT32(int_mask, PL110State), | |
83 | VMSTATE_INT32(cols, PL110State), | |
84 | VMSTATE_INT32(rows, PL110State), | |
85 | VMSTATE_UINT32(bpp, PL110State), | |
86 | VMSTATE_INT32(invalidate, PL110State), | |
87 | VMSTATE_UINT32_ARRAY(palette, PL110State, 256), | |
88 | VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128), | |
89 | VMSTATE_UINT32_V(mux_ctrl, PL110State, 2), | |
8c60d065 PM |
90 | VMSTATE_END_OF_LIST() |
91 | } | |
92 | }; | |
93 | ||
bdd5003a PB |
94 | static const unsigned char pl110_id[] = |
95 | { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; | |
96 | ||
4fbf5556 PM |
97 | static const unsigned char pl111_id[] = { |
98 | 0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1 | |
99 | }; | |
100 | ||
031c44e4 | 101 | |
4fbf5556 PM |
102 | /* Indexed by pl110_version */ |
103 | static const unsigned char *idregs[] = { | |
104 | pl110_id, | |
031c44e4 PM |
105 | /* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board |
106 | * has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware | |
107 | * itself has the same ID values as a stock PL110, and guests (in | |
108 | * particular Linux) rely on this. We emulate what the hardware does, | |
109 | * rather than what the docs claim it ought to do. | |
110 | */ | |
111 | pl110_id, | |
4fbf5556 PM |
112 | pl111_id |
113 | }; | |
114 | ||
bdd5003a | 115 | #define BITS 8 |
47b43a1f | 116 | #include "pl110_template.h" |
bdd5003a | 117 | #define BITS 15 |
47b43a1f | 118 | #include "pl110_template.h" |
bdd5003a | 119 | #define BITS 16 |
47b43a1f | 120 | #include "pl110_template.h" |
bdd5003a | 121 | #define BITS 24 |
47b43a1f | 122 | #include "pl110_template.h" |
bdd5003a | 123 | #define BITS 32 |
47b43a1f | 124 | #include "pl110_template.h" |
bdd5003a | 125 | |
513960ea | 126 | static int pl110_enabled(PL110State *s) |
bdd5003a PB |
127 | { |
128 | return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR); | |
129 | } | |
130 | ||
95219897 | 131 | static void pl110_update_display(void *opaque) |
bdd5003a | 132 | { |
513960ea | 133 | PL110State *s = (PL110State *)opaque; |
5d7a11e4 | 134 | SysBusDevice *sbd; |
c78f7137 | 135 | DisplaySurface *surface = qemu_console_surface(s->con); |
bdd5003a PB |
136 | drawfn* fntable; |
137 | drawfn fn; | |
bdd5003a PB |
138 | int dest_width; |
139 | int src_width; | |
e9c05b42 | 140 | int bpp_offset; |
714fa308 PB |
141 | int first; |
142 | int last; | |
bdd5003a | 143 | |
5d7a11e4 | 144 | if (!pl110_enabled(s)) { |
bdd5003a | 145 | return; |
5d7a11e4 AF |
146 | } |
147 | ||
148 | sbd = SYS_BUS_DEVICE(s); | |
3b46e624 | 149 | |
c78f7137 | 150 | switch (surface_bits_per_pixel(surface)) { |
af2f6733 PB |
151 | case 0: |
152 | return; | |
bdd5003a PB |
153 | case 8: |
154 | fntable = pl110_draw_fn_8; | |
155 | dest_width = 1; | |
156 | break; | |
157 | case 15: | |
158 | fntable = pl110_draw_fn_15; | |
159 | dest_width = 2; | |
160 | break; | |
161 | case 16: | |
162 | fntable = pl110_draw_fn_16; | |
163 | dest_width = 2; | |
164 | break; | |
165 | case 24: | |
166 | fntable = pl110_draw_fn_24; | |
167 | dest_width = 3; | |
168 | break; | |
169 | case 32: | |
170 | fntable = pl110_draw_fn_32; | |
171 | dest_width = 4; | |
172 | break; | |
173 | default: | |
af2f6733 | 174 | fprintf(stderr, "pl110: Bad color depth\n"); |
bdd5003a PB |
175 | exit(1); |
176 | } | |
e9c05b42 AZ |
177 | if (s->cr & PL110_CR_BGR) |
178 | bpp_offset = 0; | |
179 | else | |
4fbf5556 PM |
180 | bpp_offset = 24; |
181 | ||
182 | if ((s->version != PL111) && (s->bpp == BPP_16)) { | |
183 | /* The PL110's native 16 bit mode is 5551; however | |
184 | * most boards with a PL110 implement an external | |
185 | * mux which allows bits to be reshuffled to give | |
186 | * 565 format. The mux is typically controlled by | |
187 | * an external system register. | |
242ea2c6 | 188 | * This is controlled by a GPIO input pin |
4fbf5556 | 189 | * so boards can wire it up to their register. |
4fbf5556 PM |
190 | * |
191 | * The PL111 straightforwardly implements both | |
192 | * 5551 and 565 under control of the bpp field | |
193 | * in the LCDControl register. | |
194 | */ | |
242ea2c6 PM |
195 | switch (s->mux_ctrl) { |
196 | case 3: /* 565 BGR */ | |
197 | bpp_offset = (BPP_16_565 - BPP_16); | |
198 | break; | |
199 | case 1: /* 5551 */ | |
200 | break; | |
201 | case 0: /* 888; also if we have loaded vmstate from an old version */ | |
202 | case 2: /* 565 RGB */ | |
203 | default: | |
204 | /* treat as 565 but honour BGR bit */ | |
205 | bpp_offset += (BPP_16_565 - BPP_16); | |
206 | break; | |
207 | } | |
4fbf5556 | 208 | } |
e9c05b42 | 209 | |
bdd5003a | 210 | if (s->cr & PL110_CR_BEBO) |
4fbf5556 | 211 | fn = fntable[s->bpp + 8 + bpp_offset]; |
bdd5003a | 212 | else if (s->cr & PL110_CR_BEPO) |
4fbf5556 | 213 | fn = fntable[s->bpp + 16 + bpp_offset]; |
bdd5003a | 214 | else |
e9c05b42 | 215 | fn = fntable[s->bpp + bpp_offset]; |
3b46e624 | 216 | |
bdd5003a PB |
217 | src_width = s->cols; |
218 | switch (s->bpp) { | |
219 | case BPP_1: | |
220 | src_width >>= 3; | |
221 | break; | |
222 | case BPP_2: | |
223 | src_width >>= 2; | |
224 | break; | |
225 | case BPP_4: | |
226 | src_width >>= 1; | |
227 | break; | |
228 | case BPP_8: | |
229 | break; | |
230 | case BPP_16: | |
4fbf5556 PM |
231 | case BPP_16_565: |
232 | case BPP_12: | |
bdd5003a PB |
233 | src_width <<= 1; |
234 | break; | |
235 | case BPP_32: | |
236 | src_width <<= 2; | |
237 | break; | |
238 | } | |
239 | dest_width *= s->cols; | |
714fa308 | 240 | first = 0; |
5d7a11e4 | 241 | framebuffer_update_display(surface, sysbus_address_space(sbd), |
714fa308 PB |
242 | s->upbase, s->cols, s->rows, |
243 | src_width, dest_width, 0, | |
244 | s->invalidate, | |
6e4c0d1f | 245 | fn, s->palette, |
714fa308 PB |
246 | &first, &last); |
247 | if (first >= 0) { | |
c78f7137 | 248 | dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1); |
bdd5003a | 249 | } |
bdd5003a | 250 | s->invalidate = 0; |
bdd5003a PB |
251 | } |
252 | ||
95219897 | 253 | static void pl110_invalidate_display(void * opaque) |
bdd5003a | 254 | { |
513960ea | 255 | PL110State *s = (PL110State *)opaque; |
bdd5003a | 256 | s->invalidate = 1; |
bfdb3629 | 257 | if (pl110_enabled(s)) { |
c78f7137 | 258 | qemu_console_resize(s->con, s->cols, s->rows); |
bfdb3629 | 259 | } |
bdd5003a PB |
260 | } |
261 | ||
513960ea | 262 | static void pl110_update_palette(PL110State *s, int n) |
bdd5003a | 263 | { |
c78f7137 | 264 | DisplaySurface *surface = qemu_console_surface(s->con); |
bdd5003a PB |
265 | int i; |
266 | uint32_t raw; | |
267 | unsigned int r, g, b; | |
268 | ||
6e4c0d1f | 269 | raw = s->raw_palette[n]; |
bdd5003a PB |
270 | n <<= 1; |
271 | for (i = 0; i < 2; i++) { | |
272 | r = (raw & 0x1f) << 3; | |
273 | raw >>= 5; | |
274 | g = (raw & 0x1f) << 3; | |
275 | raw >>= 5; | |
276 | b = (raw & 0x1f) << 3; | |
277 | /* The I bit is ignored. */ | |
278 | raw >>= 6; | |
c78f7137 | 279 | switch (surface_bits_per_pixel(surface)) { |
bdd5003a | 280 | case 8: |
6e4c0d1f | 281 | s->palette[n] = rgb_to_pixel8(r, g, b); |
bdd5003a PB |
282 | break; |
283 | case 15: | |
6e4c0d1f | 284 | s->palette[n] = rgb_to_pixel15(r, g, b); |
bdd5003a PB |
285 | break; |
286 | case 16: | |
6e4c0d1f | 287 | s->palette[n] = rgb_to_pixel16(r, g, b); |
bdd5003a PB |
288 | break; |
289 | case 24: | |
290 | case 32: | |
6e4c0d1f | 291 | s->palette[n] = rgb_to_pixel32(r, g, b); |
bdd5003a PB |
292 | break; |
293 | } | |
294 | n++; | |
295 | } | |
296 | } | |
297 | ||
513960ea | 298 | static void pl110_resize(PL110State *s, int width, int height) |
bdd5003a PB |
299 | { |
300 | if (width != s->cols || height != s->rows) { | |
301 | if (pl110_enabled(s)) { | |
c78f7137 | 302 | qemu_console_resize(s->con, width, height); |
bdd5003a PB |
303 | } |
304 | } | |
305 | s->cols = width; | |
306 | s->rows = height; | |
307 | } | |
308 | ||
309 | /* Update interrupts. */ | |
513960ea | 310 | static void pl110_update(PL110State *s) |
bdd5003a PB |
311 | { |
312 | /* TODO: Implement interrupts. */ | |
313 | } | |
314 | ||
a8170e5e | 315 | static uint64_t pl110_read(void *opaque, hwaddr offset, |
1a6b31ce | 316 | unsigned size) |
bdd5003a | 317 | { |
513960ea | 318 | PL110State *s = (PL110State *)opaque; |
bdd5003a | 319 | |
bdd5003a | 320 | if (offset >= 0xfe0 && offset < 0x1000) { |
4fbf5556 | 321 | return idregs[s->version][(offset - 0xfe0) >> 2]; |
bdd5003a PB |
322 | } |
323 | if (offset >= 0x200 && offset < 0x400) { | |
6e4c0d1f | 324 | return s->raw_palette[(offset - 0x200) >> 2]; |
bdd5003a PB |
325 | } |
326 | switch (offset >> 2) { | |
327 | case 0: /* LCDTiming0 */ | |
328 | return s->timing[0]; | |
329 | case 1: /* LCDTiming1 */ | |
330 | return s->timing[1]; | |
331 | case 2: /* LCDTiming2 */ | |
332 | return s->timing[2]; | |
333 | case 3: /* LCDTiming3 */ | |
334 | return s->timing[3]; | |
335 | case 4: /* LCDUPBASE */ | |
336 | return s->upbase; | |
337 | case 5: /* LCDLPBASE */ | |
338 | return s->lpbase; | |
339 | case 6: /* LCDIMSC */ | |
4fbf5556 PM |
340 | if (s->version != PL110) { |
341 | return s->cr; | |
342 | } | |
bdd5003a PB |
343 | return s->int_mask; |
344 | case 7: /* LCDControl */ | |
4fbf5556 PM |
345 | if (s->version != PL110) { |
346 | return s->int_mask; | |
347 | } | |
bdd5003a PB |
348 | return s->cr; |
349 | case 8: /* LCDRIS */ | |
350 | return s->int_status; | |
351 | case 9: /* LCDMIS */ | |
352 | return s->int_status & s->int_mask; | |
353 | case 11: /* LCDUPCURR */ | |
354 | /* TODO: Implement vertical refresh. */ | |
355 | return s->upbase; | |
356 | case 12: /* LCDLPCURR */ | |
357 | return s->lpbase; | |
358 | default: | |
375cb560 PM |
359 | qemu_log_mask(LOG_GUEST_ERROR, |
360 | "pl110_read: Bad offset %x\n", (int)offset); | |
bdd5003a PB |
361 | return 0; |
362 | } | |
363 | } | |
364 | ||
a8170e5e | 365 | static void pl110_write(void *opaque, hwaddr offset, |
1a6b31ce | 366 | uint64_t val, unsigned size) |
bdd5003a | 367 | { |
513960ea | 368 | PL110State *s = (PL110State *)opaque; |
bdd5003a PB |
369 | int n; |
370 | ||
371 | /* For simplicity invalidate the display whenever a control register | |
66a0a2cb | 372 | is written to. */ |
bdd5003a | 373 | s->invalidate = 1; |
bdd5003a | 374 | if (offset >= 0x200 && offset < 0x400) { |
6e4c0d1f | 375 | /* Palette. */ |
bdd5003a | 376 | n = (offset - 0x200) >> 2; |
6e4c0d1f PM |
377 | s->raw_palette[(offset - 0x200) >> 2] = val; |
378 | pl110_update_palette(s, n); | |
e10c2bfb | 379 | return; |
bdd5003a PB |
380 | } |
381 | switch (offset >> 2) { | |
382 | case 0: /* LCDTiming0 */ | |
383 | s->timing[0] = val; | |
384 | n = ((val & 0xfc) + 4) * 4; | |
385 | pl110_resize(s, n, s->rows); | |
386 | break; | |
387 | case 1: /* LCDTiming1 */ | |
388 | s->timing[1] = val; | |
389 | n = (val & 0x3ff) + 1; | |
390 | pl110_resize(s, s->cols, n); | |
391 | break; | |
392 | case 2: /* LCDTiming2 */ | |
393 | s->timing[2] = val; | |
394 | break; | |
395 | case 3: /* LCDTiming3 */ | |
396 | s->timing[3] = val; | |
397 | break; | |
398 | case 4: /* LCDUPBASE */ | |
399 | s->upbase = val; | |
400 | break; | |
401 | case 5: /* LCDLPBASE */ | |
402 | s->lpbase = val; | |
403 | break; | |
404 | case 6: /* LCDIMSC */ | |
4fbf5556 | 405 | if (s->version != PL110) { |
cdbdb648 | 406 | goto control; |
4fbf5556 | 407 | } |
cdbdb648 | 408 | imsc: |
bdd5003a PB |
409 | s->int_mask = val; |
410 | pl110_update(s); | |
411 | break; | |
412 | case 7: /* LCDControl */ | |
4fbf5556 | 413 | if (s->version != PL110) { |
cdbdb648 | 414 | goto imsc; |
4fbf5556 | 415 | } |
cdbdb648 | 416 | control: |
bdd5003a PB |
417 | s->cr = val; |
418 | s->bpp = (val >> 1) & 7; | |
419 | if (pl110_enabled(s)) { | |
c78f7137 | 420 | qemu_console_resize(s->con, s->cols, s->rows); |
bdd5003a PB |
421 | } |
422 | break; | |
423 | case 10: /* LCDICR */ | |
424 | s->int_status &= ~val; | |
425 | pl110_update(s); | |
426 | break; | |
427 | default: | |
375cb560 PM |
428 | qemu_log_mask(LOG_GUEST_ERROR, |
429 | "pl110_write: Bad offset %x\n", (int)offset); | |
bdd5003a PB |
430 | } |
431 | } | |
432 | ||
1a6b31ce AK |
433 | static const MemoryRegionOps pl110_ops = { |
434 | .read = pl110_read, | |
435 | .write = pl110_write, | |
436 | .endianness = DEVICE_NATIVE_ENDIAN, | |
bdd5003a PB |
437 | }; |
438 | ||
242ea2c6 PM |
439 | static void pl110_mux_ctrl_set(void *opaque, int line, int level) |
440 | { | |
513960ea | 441 | PL110State *s = (PL110State *)opaque; |
242ea2c6 PM |
442 | s->mux_ctrl = level; |
443 | } | |
444 | ||
128939a9 PM |
445 | static int vmstate_pl110_post_load(void *opaque, int version_id) |
446 | { | |
513960ea | 447 | PL110State *s = opaque; |
128939a9 PM |
448 | /* Make sure we redraw, and at the right size */ |
449 | pl110_invalidate_display(s); | |
450 | return 0; | |
451 | } | |
452 | ||
380cd056 GH |
453 | static const GraphicHwOps pl110_gfx_ops = { |
454 | .invalidate = pl110_invalidate_display, | |
455 | .gfx_update = pl110_update_display, | |
456 | }; | |
457 | ||
5d7a11e4 | 458 | static int pl110_initfn(SysBusDevice *sbd) |
bdd5003a | 459 | { |
5d7a11e4 AF |
460 | DeviceState *dev = DEVICE(sbd); |
461 | PL110State *s = PL110(dev); | |
bdd5003a | 462 | |
3eadad55 | 463 | memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000); |
5d7a11e4 AF |
464 | sysbus_init_mmio(sbd, &s->iomem); |
465 | sysbus_init_irq(sbd, &s->irq); | |
466 | qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1); | |
5643706a | 467 | s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s); |
81a322d4 | 468 | return 0; |
bdd5003a | 469 | } |
2e9bdce5 | 470 | |
5d7a11e4 AF |
471 | static void pl110_init(Object *obj) |
472 | { | |
473 | PL110State *s = PL110(obj); | |
474 | ||
475 | s->version = PL110; | |
476 | } | |
477 | ||
478 | static void pl110_versatile_init(Object *obj) | |
2e9bdce5 | 479 | { |
5d7a11e4 AF |
480 | PL110State *s = PL110(obj); |
481 | ||
4fbf5556 | 482 | s->version = PL110_VERSATILE; |
4fbf5556 PM |
483 | } |
484 | ||
5d7a11e4 | 485 | static void pl111_init(Object *obj) |
4fbf5556 | 486 | { |
5d7a11e4 AF |
487 | PL110State *s = PL110(obj); |
488 | ||
4fbf5556 | 489 | s->version = PL111; |
2e9bdce5 PB |
490 | } |
491 | ||
999e12bb AL |
492 | static void pl110_class_init(ObjectClass *klass, void *data) |
493 | { | |
39bffca2 | 494 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
495 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
496 | ||
5d7a11e4 | 497 | k->init = pl110_initfn; |
125ee0ed | 498 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); |
39bffca2 | 499 | dc->vmsd = &vmstate_pl110; |
999e12bb AL |
500 | } |
501 | ||
8c43a6f0 | 502 | static const TypeInfo pl110_info = { |
5d7a11e4 | 503 | .name = TYPE_PL110, |
39bffca2 | 504 | .parent = TYPE_SYS_BUS_DEVICE, |
513960ea | 505 | .instance_size = sizeof(PL110State), |
5d7a11e4 | 506 | .instance_init = pl110_init, |
39bffca2 | 507 | .class_init = pl110_class_init, |
8c60d065 PM |
508 | }; |
509 | ||
8c43a6f0 | 510 | static const TypeInfo pl110_versatile_info = { |
39bffca2 | 511 | .name = "pl110_versatile", |
5d7a11e4 AF |
512 | .parent = TYPE_PL110, |
513 | .instance_init = pl110_versatile_init, | |
8c60d065 PM |
514 | }; |
515 | ||
8c43a6f0 | 516 | static const TypeInfo pl111_info = { |
39bffca2 | 517 | .name = "pl111", |
5d7a11e4 AF |
518 | .parent = TYPE_PL110, |
519 | .instance_init = pl111_init, | |
4fbf5556 PM |
520 | }; |
521 | ||
83f7d43a | 522 | static void pl110_register_types(void) |
2e9bdce5 | 523 | { |
39bffca2 AL |
524 | type_register_static(&pl110_info); |
525 | type_register_static(&pl110_versatile_info); | |
526 | type_register_static(&pl111_info); | |
2e9bdce5 PB |
527 | } |
528 | ||
83f7d43a | 529 | type_init(pl110_register_types) |