[qemu.git] / target / i386 / gdbstub.c

/*
 * x86 gdb server stub
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 * Copyright (c) 2013 SUSE LINUX Products GmbH
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "cpu.h"
#include "exec/gdbstub.h"

#ifdef TARGET_X86_64
static const int gpr_map[16] = {
    R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
    8, 9, 10, 11, 12, 13, 14, 15
};
#else
#define gpr_map gpr_map32
#endif
static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };

/*
 * Keep these in sync with assignment to
 * gdb_num_core_regs in target/i386/cpu.c
 * and with the machine description
 */

/*
 * SEG: 6 segments, plus fs_base, gs_base, kernel_gs_base
 */

/*
 * general regs ----->  8 or 16
 */
#define IDX_NB_IP       1
#define IDX_NB_FLAGS    1
#define IDX_NB_SEG      (6 + 3)
#define IDX_NB_CTL      6
#define IDX_NB_FP       16
/*
 * fpu regs ----------> 8 or 16
 */
#define IDX_NB_MXCSR    1
/*
 *          total ----> 8+1+1+9+6+16+8+1=50 or 16+1+1+9+6+16+16+1=66
 */

#define IDX_IP_REG      CPU_NB_REGS
#define IDX_FLAGS_REG   (IDX_IP_REG + IDX_NB_IP)
#define IDX_SEG_REGS    (IDX_FLAGS_REG + IDX_NB_FLAGS)
#define IDX_CTL_REGS    (IDX_SEG_REGS + IDX_NB_SEG)
#define IDX_FP_REGS     (IDX_CTL_REGS + IDX_NB_CTL)
#define IDX_XMM_REGS    (IDX_FP_REGS + IDX_NB_FP)
#define IDX_MXCSR_REG   (IDX_XMM_REGS + CPU_NB_REGS)

#define IDX_CTL_CR0_REG     (IDX_CTL_REGS + 0)
#define IDX_CTL_CR2_REG     (IDX_CTL_REGS + 1)
#define IDX_CTL_CR3_REG     (IDX_CTL_REGS + 2)
#define IDX_CTL_CR4_REG     (IDX_CTL_REGS + 3)
#define IDX_CTL_CR8_REG     (IDX_CTL_REGS + 4)
#define IDX_CTL_EFER_REG    (IDX_CTL_REGS + 5)

#ifdef TARGET_X86_64
#define GDB_FORCE_64 1
#else
#define GDB_FORCE_64 0
#endif


int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
    X86CPU *cpu = X86_CPU(cs);
    CPUX86State *env = &cpu->env;

    uint64_t tpr;

    /* N.B. GDB can't deal with changes in registers or sizes in the middle
       of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
       as if we're on a 64-bit cpu. */

    if (n < CPU_NB_REGS) {
        if (TARGET_LONG_BITS == 64) {
            if (env->hflags & HF_CS64_MASK) {
                return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
            } else if (n < CPU_NB_REGS32) {
                return gdb_get_reg64(mem_buf,
                                     env->regs[gpr_map[n]] & 0xffffffffUL);
            } else {
                memset(mem_buf, 0, sizeof(target_ulong));
                return sizeof(target_ulong);
            }
        } else {
            return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
        }
    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
#ifdef USE_X86LDOUBLE
        /* FIXME: byteswap float values - after fixing fpregs layout. */
        memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
#else
        memset(mem_buf, 0, 10);
#endif
        return 10;
    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
        n -= IDX_XMM_REGS;
        if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {
            stq_p(mem_buf, env->xmm_regs[n].ZMM_Q(0));
            stq_p(mem_buf + 8, env->xmm_regs[n].ZMM_Q(1));
            return 16;
        }
    } else {
        switch (n) {
        case IDX_IP_REG:
            if (TARGET_LONG_BITS == 64) {
                if (env->hflags & HF_CS64_MASK) {
                    return gdb_get_reg64(mem_buf, env->eip);
                } else {
                    return gdb_get_reg64(mem_buf, env->eip & 0xffffffffUL);
                }
            } else {
                return gdb_get_reg32(mem_buf, env->eip);
            }
        case IDX_FLAGS_REG:
            return gdb_get_reg32(mem_buf, env->eflags);

        case IDX_SEG_REGS:
            return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
        case IDX_SEG_REGS + 1:
            return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
        case IDX_SEG_REGS + 2:
            return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
        case IDX_SEG_REGS + 3:
            return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
        case IDX_SEG_REGS + 4:
            return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
        case IDX_SEG_REGS + 5:
            return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);

        case IDX_SEG_REGS + 6:
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->segs[R_FS].base);
            }
            return gdb_get_reg32(mem_buf, env->segs[R_FS].base);

        case IDX_SEG_REGS + 7:
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->segs[R_GS].base);
            }
            return gdb_get_reg32(mem_buf, env->segs[R_GS].base);

        case IDX_SEG_REGS + 8:
#ifdef TARGET_X86_64
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->kernelgsbase);
            }
            return gdb_get_reg32(mem_buf, env->kernelgsbase);
#else
            return gdb_get_reg32(mem_buf, 0);
#endif

        case IDX_FP_REGS + 8:
            return gdb_get_reg32(mem_buf, env->fpuc);
        case IDX_FP_REGS + 9:
            return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) |
                                          (env->fpstt & 0x7) << 11);
        case IDX_FP_REGS + 10:
            return gdb_get_reg32(mem_buf, 0); /* ftag */
        case IDX_FP_REGS + 11:
            return gdb_get_reg32(mem_buf, 0); /* fiseg */
        case IDX_FP_REGS + 12:
            return gdb_get_reg32(mem_buf, 0); /* fioff */
        case IDX_FP_REGS + 13:
            return gdb_get_reg32(mem_buf, 0); /* foseg */
        case IDX_FP_REGS + 14:
            return gdb_get_reg32(mem_buf, 0); /* fooff */
        case IDX_FP_REGS + 15:
            return gdb_get_reg32(mem_buf, 0); /* fop */

        case IDX_MXCSR_REG:
            return gdb_get_reg32(mem_buf, env->mxcsr);

        case IDX_CTL_CR0_REG:
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->cr[0]);
            }
            return gdb_get_reg32(mem_buf, env->cr[0]);

        case IDX_CTL_CR2_REG:
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->cr[2]);
            }
            return gdb_get_reg32(mem_buf, env->cr[2]);

        case IDX_CTL_CR3_REG:
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->cr[3]);
            }
            return gdb_get_reg32(mem_buf, env->cr[3]);

        case IDX_CTL_CR4_REG:
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->cr[4]);
            }
            return gdb_get_reg32(mem_buf, env->cr[4]);

        case IDX_CTL_CR8_REG:
#ifdef CONFIG_SOFTMMU
            tpr = cpu_get_apic_tpr(cpu->apic_state);
#else
            tpr = 0;
#endif
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, tpr);
            }
            return gdb_get_reg32(mem_buf, tpr);

        case IDX_CTL_EFER_REG:
            if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
                return gdb_get_reg64(mem_buf, env->efer);
            }
            return gdb_get_reg32(mem_buf, env->efer);
        }
    }
    return 0;
}

static int x86_cpu_gdb_load_seg(X86CPU *cpu, int sreg, uint8_t *mem_buf)
{
    CPUX86State *env = &cpu->env;
    uint16_t selector = ldl_p(mem_buf);

    if (selector != env->segs[sreg].selector) {
#if defined(CONFIG_USER_ONLY)
        cpu_x86_load_seg(env, sreg, selector);
#else
        unsigned int limit, flags;
        target_ulong base;

        if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
            int dpl = (env->eflags & VM_MASK) ? 3 : 0;
            base = selector << 4;
            limit = 0xffff;
            flags = DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
                    DESC_A_MASK | (dpl << DESC_DPL_SHIFT);
        } else {
            if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
                                         &flags)) {
                return 4;
            }
        }
        cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
#endif
    }
    return 4;
}

int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
    X86CPU *cpu = X86_CPU(cs);
    CPUX86State *env = &cpu->env;
    uint32_t tmp;

    /* N.B. GDB can't deal with changes in registers or sizes in the middle
       of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
       as if we're on a 64-bit cpu. */

    if (n < CPU_NB_REGS) {
        if (TARGET_LONG_BITS == 64) {
            if (env->hflags & HF_CS64_MASK) {
                env->regs[gpr_map[n]] = ldtul_p(mem_buf);
            } else if (n < CPU_NB_REGS32) {
                env->regs[gpr_map[n]] = ldtul_p(mem_buf) & 0xffffffffUL;
            }
            return sizeof(target_ulong);
        } else if (n < CPU_NB_REGS32) {
            n = gpr_map32[n];
            env->regs[n] &= ~0xffffffffUL;
            env->regs[n] |= (uint32_t)ldl_p(mem_buf);
            return 4;
        }
    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
#ifdef USE_X86LDOUBLE
        /* FIXME: byteswap float values - after fixing fpregs layout. */
        memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
#endif
        return 10;
    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
        n -= IDX_XMM_REGS;
        if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {
            env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf);
            env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8);
            return 16;
        }
    } else {
        switch (n) {
        case IDX_IP_REG:
            if (TARGET_LONG_BITS == 64) {
                if (env->hflags & HF_CS64_MASK) {
                    env->eip = ldq_p(mem_buf);
                } else {
                    env->eip = ldq_p(mem_buf) & 0xffffffffUL;
                }
                return 8;
            } else {
                env->eip &= ~0xffffffffUL;
                env->eip |= (uint32_t)ldl_p(mem_buf);
                return 4;
            }
        case IDX_FLAGS_REG:
            env->eflags = ldl_p(mem_buf);
            return 4;

        case IDX_SEG_REGS:
            return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf);
        case IDX_SEG_REGS + 1:
            return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf);
        case IDX_SEG_REGS + 2:
            return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf);
        case IDX_SEG_REGS + 3:
            return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf);
        case IDX_SEG_REGS + 4:
            return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf);
        case IDX_SEG_REGS + 5:
            return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);

        case IDX_SEG_REGS + 6:
            if (env->hflags & HF_CS64_MASK) {
                env->segs[R_FS].base = ldq_p(mem_buf);
                return 8;
            }
            env->segs[R_FS].base = ldl_p(mem_buf);
            return 4;

        case IDX_SEG_REGS + 7:
            if (env->hflags & HF_CS64_MASK) {
                env->segs[R_GS].base = ldq_p(mem_buf);
                return 8;
            }
            env->segs[R_GS].base = ldl_p(mem_buf);
            return 4;

#ifdef TARGET_X86_64
        case IDX_SEG_REGS + 8:
            if (env->hflags & HF_CS64_MASK) {
                env->kernelgsbase = ldq_p(mem_buf);
                return 8;
            }
            env->kernelgsbase = ldl_p(mem_buf);
            return 4;
#endif

        case IDX_FP_REGS + 8:
            cpu_set_fpuc(env, ldl_p(mem_buf));
            return 4;
        case IDX_FP_REGS + 9:
            tmp = ldl_p(mem_buf);
            env->fpstt = (tmp >> 11) & 7;
            env->fpus = tmp & ~0x3800;
            return 4;
        case IDX_FP_REGS + 10: /* ftag */
            return 4;
        case IDX_FP_REGS + 11: /* fiseg */
            return 4;
        case IDX_FP_REGS + 12: /* fioff */
            return 4;
        case IDX_FP_REGS + 13: /* foseg */
            return 4;
        case IDX_FP_REGS + 14: /* fooff */
            return 4;
        case IDX_FP_REGS + 15: /* fop */
            return 4;

        case IDX_MXCSR_REG:
            cpu_set_mxcsr(env, ldl_p(mem_buf));
            return 4;

        case IDX_CTL_CR0_REG:
            if (env->hflags & HF_CS64_MASK) {
                cpu_x86_update_cr0(env, ldq_p(mem_buf));
                return 8;
            }
            cpu_x86_update_cr0(env, ldl_p(mem_buf));
            return 4;

        case IDX_CTL_CR2_REG:
            if (env->hflags & HF_CS64_MASK) {
                env->cr[2] = ldq_p(mem_buf);
                return 8;
            }
            env->cr[2] = ldl_p(mem_buf);
            return 4;

        case IDX_CTL_CR3_REG:
            if (env->hflags & HF_CS64_MASK) {
                cpu_x86_update_cr3(env, ldq_p(mem_buf));
                return 8;
            }
            cpu_x86_update_cr3(env, ldl_p(mem_buf));
            return 4;

        case IDX_CTL_CR4_REG:
            if (env->hflags & HF_CS64_MASK) {
                cpu_x86_update_cr4(env, ldq_p(mem_buf));
                return 8;
            }
            cpu_x86_update_cr4(env, ldl_p(mem_buf));
            return 4;

        case IDX_CTL_CR8_REG:
            if (env->hflags & HF_CS64_MASK) {
#ifdef CONFIG_SOFTMMU
                cpu_set_apic_tpr(cpu->apic_state, ldq_p(mem_buf));
#endif
                return 8;
            }
#ifdef CONFIG_SOFTMMU
            cpu_set_apic_tpr(cpu->apic_state, ldl_p(mem_buf));
#endif
            return 4;

        case IDX_CTL_EFER_REG:
            if (env->hflags & HF_CS64_MASK) {
                cpu_load_efer(env, ldq_p(mem_buf));
                return 8;
            }
            cpu_load_efer(env, ldl_p(mem_buf));
            return 4;

        }
    }
    /* Unrecognised register.  */
    return 0;
}
Commit	Line	Data
f20f9df0 AF	1	/*
	2	* x86 gdb server stub
	3	*
	4	* Copyright (c) 2003-2005 Fabrice Bellard
	5	* Copyright (c) 2013 SUSE LINUX Products GmbH
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
b6a0aa05	20	#include "qemu/osdep.h"
5b50e790	21	#include "qemu-common.h"
33c11879	22	#include "cpu.h"
5b50e790	23	#include "exec/gdbstub.h"
f20f9df0 AF	24
	25	#ifdef TARGET_X86_64
	26	static const int gpr_map[16] = {
	27	R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
	28	8, 9, 10, 11, 12, 13, 14, 15
	29	};
	30	#else
	31	#define gpr_map gpr_map32
	32	#endif
	33	static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
	34
7b0f97ba DG	35	/*
	36	* Keep these in sync with assignment to
	37	* gdb_num_core_regs in target/i386/cpu.c
	38	* and with the machine description
	39	*/
	40
	41	/*
	42	* SEG: 6 segments, plus fs_base, gs_base, kernel_gs_base
	43	*/
	44
	45	/*
	46	* general regs -----> 8 or 16
	47	*/
	48	#define IDX_NB_IP 1
	49	#define IDX_NB_FLAGS 1
	50	#define IDX_NB_SEG (6 + 3)
	51	#define IDX_NB_CTL 6
	52	#define IDX_NB_FP 16
	53	/*
	54	* fpu regs ----------> 8 or 16
	55	*/
	56	#define IDX_NB_MXCSR 1
	57	/*
	58	* total ----> 8+1+1+9+6+16+8+1=50 or 16+1+1+9+6+16+16+1=66
	59	*/
	60
f20f9df0	61	#define IDX_IP_REG CPU_NB_REGS
7b0f97ba DG	62	#define IDX_FLAGS_REG (IDX_IP_REG + IDX_NB_IP)
	63	#define IDX_SEG_REGS (IDX_FLAGS_REG + IDX_NB_FLAGS)
	64	#define IDX_CTL_REGS (IDX_SEG_REGS + IDX_NB_SEG)
	65	#define IDX_FP_REGS (IDX_CTL_REGS + IDX_NB_CTL)
	66	#define IDX_XMM_REGS (IDX_FP_REGS + IDX_NB_FP)
f20f9df0 AF	67	#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
f20f9df0 AF	68
7b0f97ba DG	69	#define IDX_CTL_CR0_REG (IDX_CTL_REGS + 0)
	70	#define IDX_CTL_CR2_REG (IDX_CTL_REGS + 1)
	71	#define IDX_CTL_CR3_REG (IDX_CTL_REGS + 2)
	72	#define IDX_CTL_CR4_REG (IDX_CTL_REGS + 3)
	73	#define IDX_CTL_CR8_REG (IDX_CTL_REGS + 4)
	74	#define IDX_CTL_EFER_REG (IDX_CTL_REGS + 5)
	75
	76	#ifdef TARGET_X86_64
	77	#define GDB_FORCE_64 1
	78	#else
	79	#define GDB_FORCE_64 0
	80	#endif
	81
	82
5b50e790	83	int x86_cpu_gdb_read_register(CPUState cs, uint8_t mem_buf, int n)
f20f9df0	84	{
5b50e790 AF	85	X86CPU *cpu = X86_CPU(cs);
	86	CPUX86State *env = &cpu->env;
	87
7b0f97ba DG	88	uint64_t tpr;
7b0f97ba DG	89
e3592bc9 DE	90	/* N.B. GDB can't deal with changes in registers or sizes in the middle
	91	of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
	92	as if we're on a 64-bit cpu. */
	93
f20f9df0	94	if (n < CPU_NB_REGS) {
e3592bc9 DE	95	if (TARGET_LONG_BITS == 64) {
	96	if (env->hflags & HF_CS64_MASK) {
	97	return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
	98	} else if (n < CPU_NB_REGS32) {
	99	return gdb_get_reg64(mem_buf,
	100	env->regs[gpr_map[n]] & 0xffffffffUL);
	101	} else {
	102	memset(mem_buf, 0, sizeof(target_ulong));
	103	return sizeof(target_ulong);
	104	}
	105	} else {
986a2998	106	return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
f20f9df0 AF	107	}
	108	} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
	109	#ifdef USE_X86LDOUBLE
	110	/* FIXME: byteswap float values - after fixing fpregs layout. */
	111	memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
	112	#else
	113	memset(mem_buf, 0, 10);
	114	#endif
	115	return 10;
	116	} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
	117	n -= IDX_XMM_REGS;
e3592bc9	118	if (n < CPU_NB_REGS32 \|\| TARGET_LONG_BITS == 64) {
19cbd87c EH	119	stq_p(mem_buf, env->xmm_regs[n].ZMM_Q(0));
19cbd87c EH	120	stq_p(mem_buf + 8, env->xmm_regs[n].ZMM_Q(1));
f20f9df0 AF	121	return 16;
	122	}
	123	} else {
	124	switch (n) {
	125	case IDX_IP_REG:
e3592bc9 DE	126	if (TARGET_LONG_BITS == 64) {
	127	if (env->hflags & HF_CS64_MASK) {
	128	return gdb_get_reg64(mem_buf, env->eip);
	129	} else {
	130	return gdb_get_reg64(mem_buf, env->eip & 0xffffffffUL);
	131	}
f20f9df0	132	} else {
986a2998	133	return gdb_get_reg32(mem_buf, env->eip);
f20f9df0 AF	134	}
f20f9df0 AF	135	case IDX_FLAGS_REG:
986a2998	136	return gdb_get_reg32(mem_buf, env->eflags);
f20f9df0 AF	137
f20f9df0 AF	138	case IDX_SEG_REGS:
986a2998	139	return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
f20f9df0	140	case IDX_SEG_REGS + 1:
986a2998	141	return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
f20f9df0	142	case IDX_SEG_REGS + 2:
986a2998	143	return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
f20f9df0	144	case IDX_SEG_REGS + 3:
986a2998	145	return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
f20f9df0	146	case IDX_SEG_REGS + 4:
986a2998	147	return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
f20f9df0	148	case IDX_SEG_REGS + 5:
986a2998	149	return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
f20f9df0	150
7b0f97ba DG	151	case IDX_SEG_REGS + 6:
	152	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	153	return gdb_get_reg64(mem_buf, env->segs[R_FS].base);
	154	}
	155	return gdb_get_reg32(mem_buf, env->segs[R_FS].base);
	156
	157	case IDX_SEG_REGS + 7:
	158	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	159	return gdb_get_reg64(mem_buf, env->segs[R_GS].base);
	160	}
	161	return gdb_get_reg32(mem_buf, env->segs[R_GS].base);
	162
	163	case IDX_SEG_REGS + 8:
	164	#ifdef TARGET_X86_64
	165	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	166	return gdb_get_reg64(mem_buf, env->kernelgsbase);
	167	}
	168	return gdb_get_reg32(mem_buf, env->kernelgsbase);
	169	#else
	170	return gdb_get_reg32(mem_buf, 0);
	171	#endif
	172
f20f9df0	173	case IDX_FP_REGS + 8:
986a2998	174	return gdb_get_reg32(mem_buf, env->fpuc);
f20f9df0	175	case IDX_FP_REGS + 9:
986a2998 AF	176	return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) \|
986a2998 AF	177	(env->fpstt & 0x7) << 11);
f20f9df0	178	case IDX_FP_REGS + 10:
986a2998	179	return gdb_get_reg32(mem_buf, 0); /* ftag */
f20f9df0	180	case IDX_FP_REGS + 11:
986a2998	181	return gdb_get_reg32(mem_buf, 0); /* fiseg */
f20f9df0	182	case IDX_FP_REGS + 12:
986a2998	183	return gdb_get_reg32(mem_buf, 0); /* fioff */
f20f9df0	184	case IDX_FP_REGS + 13:
986a2998	185	return gdb_get_reg32(mem_buf, 0); /* foseg */
f20f9df0	186	case IDX_FP_REGS + 14:
986a2998	187	return gdb_get_reg32(mem_buf, 0); /* fooff */
f20f9df0	188	case IDX_FP_REGS + 15:
986a2998	189	return gdb_get_reg32(mem_buf, 0); /* fop */
f20f9df0 AF	190
f20f9df0 AF	191	case IDX_MXCSR_REG:
986a2998	192	return gdb_get_reg32(mem_buf, env->mxcsr);
7b0f97ba DG	193
	194	case IDX_CTL_CR0_REG:
	195	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	196	return gdb_get_reg64(mem_buf, env->cr[0]);
	197	}
	198	return gdb_get_reg32(mem_buf, env->cr[0]);
	199
	200	case IDX_CTL_CR2_REG:
	201	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	202	return gdb_get_reg64(mem_buf, env->cr[2]);
	203	}
	204	return gdb_get_reg32(mem_buf, env->cr[2]);
	205
	206	case IDX_CTL_CR3_REG:
	207	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	208	return gdb_get_reg64(mem_buf, env->cr[3]);
	209	}
	210	return gdb_get_reg32(mem_buf, env->cr[3]);
	211
	212	case IDX_CTL_CR4_REG:
	213	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	214	return gdb_get_reg64(mem_buf, env->cr[4]);
	215	}
	216	return gdb_get_reg32(mem_buf, env->cr[4]);
	217
	218	case IDX_CTL_CR8_REG:
	219	#ifdef CONFIG_SOFTMMU
	220	tpr = cpu_get_apic_tpr(cpu->apic_state);
	221	#else
	222	tpr = 0;
	223	#endif
	224	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	225	return gdb_get_reg64(mem_buf, tpr);
	226	}
	227	return gdb_get_reg32(mem_buf, tpr);
	228
	229	case IDX_CTL_EFER_REG:
	230	if ((env->hflags & HF_CS64_MASK) \|\| GDB_FORCE_64) {
	231	return gdb_get_reg64(mem_buf, env->efer);
	232	}
	233	return gdb_get_reg32(mem_buf, env->efer);
f20f9df0 AF	234	}
	235	}
	236	return 0;
	237	}
	238
5b50e790	239	static int x86_cpu_gdb_load_seg(X86CPU cpu, int sreg, uint8_t mem_buf)
f20f9df0	240	{
5b50e790	241	CPUX86State *env = &cpu->env;
f20f9df0 AF	242	uint16_t selector = ldl_p(mem_buf);
	243
	244	if (selector != env->segs[sreg].selector) {
	245	#if defined(CONFIG_USER_ONLY)
	246	cpu_x86_load_seg(env, sreg, selector);
	247	#else
	248	unsigned int limit, flags;
	249	target_ulong base;
	250
	251	if (!(env->cr[0] & CR0_PE_MASK) \|\| (env->eflags & VM_MASK)) {
b98dbc90	252	int dpl = (env->eflags & VM_MASK) ? 3 : 0;
f20f9df0 AF	253	base = selector << 4;
f20f9df0 AF	254	limit = 0xffff;
b98dbc90 PB	255	flags = DESC_P_MASK \| DESC_S_MASK \| DESC_W_MASK \|
b98dbc90 PB	256	DESC_A_MASK \| (dpl << DESC_DPL_SHIFT);
f20f9df0 AF	257	} else {
	258	if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
	259	&flags)) {
	260	return 4;
	261	}
	262	}
	263	cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
	264	#endif
	265	}
	266	return 4;
	267	}
	268
5b50e790	269	int x86_cpu_gdb_write_register(CPUState cs, uint8_t mem_buf, int n)
f20f9df0	270	{
5b50e790 AF	271	X86CPU *cpu = X86_CPU(cs);
5b50e790 AF	272	CPUX86State *env = &cpu->env;
f20f9df0 AF	273	uint32_t tmp;
f20f9df0 AF	274
e3592bc9 DE	275	/* N.B. GDB can't deal with changes in registers or sizes in the middle
	276	of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
	277	as if we're on a 64-bit cpu. */
	278
f20f9df0	279	if (n < CPU_NB_REGS) {
e3592bc9 DE	280	if (TARGET_LONG_BITS == 64) {
	281	if (env->hflags & HF_CS64_MASK) {
	282	env->regs[gpr_map[n]] = ldtul_p(mem_buf);
	283	} else if (n < CPU_NB_REGS32) {
	284	env->regs[gpr_map[n]] = ldtul_p(mem_buf) & 0xffffffffUL;
	285	}
f20f9df0 AF	286	return sizeof(target_ulong);
	287	} else if (n < CPU_NB_REGS32) {
	288	n = gpr_map32[n];
	289	env->regs[n] &= ~0xffffffffUL;
	290	env->regs[n] \|= (uint32_t)ldl_p(mem_buf);
	291	return 4;
	292	}
	293	} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
	294	#ifdef USE_X86LDOUBLE
	295	/* FIXME: byteswap float values - after fixing fpregs layout. */
	296	memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
	297	#endif
	298	return 10;
	299	} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
	300	n -= IDX_XMM_REGS;
e3592bc9	301	if (n < CPU_NB_REGS32 \|\| TARGET_LONG_BITS == 64) {
19cbd87c EH	302	env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf);
19cbd87c EH	303	env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8);
f20f9df0 AF	304	return 16;
	305	}
	306	} else {
	307	switch (n) {
	308	case IDX_IP_REG:
e3592bc9 DE	309	if (TARGET_LONG_BITS == 64) {
	310	if (env->hflags & HF_CS64_MASK) {
	311	env->eip = ldq_p(mem_buf);
	312	} else {
	313	env->eip = ldq_p(mem_buf) & 0xffffffffUL;
	314	}
f20f9df0 AF	315	return 8;
	316	} else {
	317	env->eip &= ~0xffffffffUL;
	318	env->eip \|= (uint32_t)ldl_p(mem_buf);
	319	return 4;
	320	}
	321	case IDX_FLAGS_REG:
	322	env->eflags = ldl_p(mem_buf);
	323	return 4;
	324
	325	case IDX_SEG_REGS:
5b50e790	326	return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf);
f20f9df0	327	case IDX_SEG_REGS + 1:
5b50e790	328	return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf);
f20f9df0	329	case IDX_SEG_REGS + 2:
5b50e790	330	return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf);
f20f9df0	331	case IDX_SEG_REGS + 3:
5b50e790	332	return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf);
f20f9df0	333	case IDX_SEG_REGS + 4:
5b50e790	334	return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf);
f20f9df0	335	case IDX_SEG_REGS + 5:
5b50e790	336	return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);
f20f9df0	337
7b0f97ba DG	338	case IDX_SEG_REGS + 6:
	339	if (env->hflags & HF_CS64_MASK) {
	340	env->segs[R_FS].base = ldq_p(mem_buf);
	341	return 8;
	342	}
	343	env->segs[R_FS].base = ldl_p(mem_buf);
	344	return 4;
	345
	346	case IDX_SEG_REGS + 7:
	347	if (env->hflags & HF_CS64_MASK) {
	348	env->segs[R_GS].base = ldq_p(mem_buf);
	349	return 8;
	350	}
	351	env->segs[R_GS].base = ldl_p(mem_buf);
	352	return 4;
	353
	354	#ifdef TARGET_X86_64
	355	case IDX_SEG_REGS + 8:
	356	if (env->hflags & HF_CS64_MASK) {
	357	env->kernelgsbase = ldq_p(mem_buf);
	358	return 8;
	359	}
	360	env->kernelgsbase = ldl_p(mem_buf);
	361	return 4;
	362	#endif
	363
f20f9df0	364	case IDX_FP_REGS + 8:
5bde1407	365	cpu_set_fpuc(env, ldl_p(mem_buf));
f20f9df0 AF	366	return 4;
	367	case IDX_FP_REGS + 9:
	368	tmp = ldl_p(mem_buf);
	369	env->fpstt = (tmp >> 11) & 7;
	370	env->fpus = tmp & ~0x3800;
	371	return 4;
	372	case IDX_FP_REGS + 10: /* ftag */
	373	return 4;
	374	case IDX_FP_REGS + 11: /* fiseg */
	375	return 4;
	376	case IDX_FP_REGS + 12: /* fioff */
	377	return 4;
	378	case IDX_FP_REGS + 13: /* foseg */
	379	return 4;
	380	case IDX_FP_REGS + 14: /* fooff */
	381	return 4;
	382	case IDX_FP_REGS + 15: /* fop */
	383	return 4;
	384
	385	case IDX_MXCSR_REG:
4e47e39a	386	cpu_set_mxcsr(env, ldl_p(mem_buf));
f20f9df0	387	return 4;
7b0f97ba DG	388
	389	case IDX_CTL_CR0_REG:
	390	if (env->hflags & HF_CS64_MASK) {
	391	cpu_x86_update_cr0(env, ldq_p(mem_buf));
	392	return 8;
	393	}
	394	cpu_x86_update_cr0(env, ldl_p(mem_buf));
	395	return 4;
	396
	397	case IDX_CTL_CR2_REG:
	398	if (env->hflags & HF_CS64_MASK) {
	399	env->cr[2] = ldq_p(mem_buf);
	400	return 8;
	401	}
	402	env->cr[2] = ldl_p(mem_buf);
	403	return 4;
	404
	405	case IDX_CTL_CR3_REG:
	406	if (env->hflags & HF_CS64_MASK) {
	407	cpu_x86_update_cr3(env, ldq_p(mem_buf));
	408	return 8;
	409	}
	410	cpu_x86_update_cr3(env, ldl_p(mem_buf));
	411	return 4;
	412
	413	case IDX_CTL_CR4_REG:
	414	if (env->hflags & HF_CS64_MASK) {
	415	cpu_x86_update_cr4(env, ldq_p(mem_buf));
	416	return 8;
	417	}
	418	cpu_x86_update_cr4(env, ldl_p(mem_buf));
	419	return 4;
	420
	421	case IDX_CTL_CR8_REG:
	422	if (env->hflags & HF_CS64_MASK) {
	423	#ifdef CONFIG_SOFTMMU
	424	cpu_set_apic_tpr(cpu->apic_state, ldq_p(mem_buf));
	425	#endif
	426	return 8;
	427	}
	428	#ifdef CONFIG_SOFTMMU
	429	cpu_set_apic_tpr(cpu->apic_state, ldl_p(mem_buf));
	430	#endif
	431	return 4;
	432
	433	case IDX_CTL_EFER_REG:
	434	if (env->hflags & HF_CS64_MASK) {
	435	cpu_load_efer(env, ldq_p(mem_buf));
	436	return 8;
	437	}
	438	cpu_load_efer(env, ldl_p(mem_buf));
	439	return 4;
	440
f20f9df0 AF	441	}
	442	}
	443	/* Unrecognised register. */
	444	return 0;
	445	}