[qemu.git] / target-i386 / gdbstub.c

/*
 * x86 gdb server stub
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 * Copyright (c) 2013 SUSE LINUX Products GmbH
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifdef TARGET_X86_64
static const int gpr_map[16] = {
    R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
    8, 9, 10, 11, 12, 13, 14, 15
};
#else
#define gpr_map gpr_map32
#endif
static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };

#define IDX_IP_REG      CPU_NB_REGS
#define IDX_FLAGS_REG   (IDX_IP_REG + 1)
#define IDX_SEG_REGS    (IDX_FLAGS_REG + 1)
#define IDX_FP_REGS     (IDX_SEG_REGS + 6)
#define IDX_XMM_REGS    (IDX_FP_REGS + 16)
#define IDX_MXCSR_REG   (IDX_XMM_REGS + CPU_NB_REGS)

static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
{
    if (n < CPU_NB_REGS) {
        if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
            return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
        } else if (n < CPU_NB_REGS32) {
            return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
        }
    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
#ifdef USE_X86LDOUBLE
        /* FIXME: byteswap float values - after fixing fpregs layout. */
        memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
#else
        memset(mem_buf, 0, 10);
#endif
        return 10;
    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
        n -= IDX_XMM_REGS;
        if (n < CPU_NB_REGS32 ||
            (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
            stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
            stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
            return 16;
        }
    } else {
        switch (n) {
        case IDX_IP_REG:
            if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
                return gdb_get_reg64(mem_buf, env->eip);
            } else {
                return gdb_get_reg32(mem_buf, env->eip);
            }
        case IDX_FLAGS_REG:
            return gdb_get_reg32(mem_buf, env->eflags);

        case IDX_SEG_REGS:
            return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
        case IDX_SEG_REGS + 1:
            return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
        case IDX_SEG_REGS + 2:
            return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
        case IDX_SEG_REGS + 3:
            return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
        case IDX_SEG_REGS + 4:
            return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
        case IDX_SEG_REGS + 5:
            return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);

        case IDX_FP_REGS + 8:
            return gdb_get_reg32(mem_buf, env->fpuc);
        case IDX_FP_REGS + 9:
            return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) |
                                          (env->fpstt & 0x7) << 11);
        case IDX_FP_REGS + 10:
            return gdb_get_reg32(mem_buf, 0); /* ftag */
        case IDX_FP_REGS + 11:
            return gdb_get_reg32(mem_buf, 0); /* fiseg */
        case IDX_FP_REGS + 12:
            return gdb_get_reg32(mem_buf, 0); /* fioff */
        case IDX_FP_REGS + 13:
            return gdb_get_reg32(mem_buf, 0); /* foseg */
        case IDX_FP_REGS + 14:
            return gdb_get_reg32(mem_buf, 0); /* fooff */
        case IDX_FP_REGS + 15:
            return gdb_get_reg32(mem_buf, 0); /* fop */

        case IDX_MXCSR_REG:
            return gdb_get_reg32(mem_buf, env->mxcsr);
        }
    }
    return 0;
}

static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf)
{
    uint16_t selector = ldl_p(mem_buf);

    if (selector != env->segs[sreg].selector) {
#if defined(CONFIG_USER_ONLY)
        cpu_x86_load_seg(env, sreg, selector);
#else
        unsigned int limit, flags;
        target_ulong base;

        if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
            base = selector << 4;
            limit = 0xffff;
            flags = 0;
        } else {
            if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
                                         &flags)) {
                return 4;
            }
        }
        cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
#endif
    }
    return 4;
}

static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
{
    uint32_t tmp;

    if (n < CPU_NB_REGS) {
        if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
            env->regs[gpr_map[n]] = ldtul_p(mem_buf);
            return sizeof(target_ulong);
        } else if (n < CPU_NB_REGS32) {
            n = gpr_map32[n];
            env->regs[n] &= ~0xffffffffUL;
            env->regs[n] |= (uint32_t)ldl_p(mem_buf);
            return 4;
        }
    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
#ifdef USE_X86LDOUBLE
        /* FIXME: byteswap float values - after fixing fpregs layout. */
        memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
#endif
        return 10;
    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
        n -= IDX_XMM_REGS;
        if (n < CPU_NB_REGS32 ||
            (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
            env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
            env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
            return 16;
        }
    } else {
        switch (n) {
        case IDX_IP_REG:
            if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
                env->eip = ldq_p(mem_buf);
                return 8;
            } else {
                env->eip &= ~0xffffffffUL;
                env->eip |= (uint32_t)ldl_p(mem_buf);
                return 4;
            }
        case IDX_FLAGS_REG:
            env->eflags = ldl_p(mem_buf);
            return 4;

        case IDX_SEG_REGS:
            return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
        case IDX_SEG_REGS + 1:
            return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
        case IDX_SEG_REGS + 2:
            return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
        case IDX_SEG_REGS + 3:
            return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
        case IDX_SEG_REGS + 4:
            return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
        case IDX_SEG_REGS + 5:
            return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);

        case IDX_FP_REGS + 8:
            env->fpuc = ldl_p(mem_buf);
            return 4;
        case IDX_FP_REGS + 9:
            tmp = ldl_p(mem_buf);
            env->fpstt = (tmp >> 11) & 7;
            env->fpus = tmp & ~0x3800;
            return 4;
        case IDX_FP_REGS + 10: /* ftag */
            return 4;
        case IDX_FP_REGS + 11: /* fiseg */
            return 4;
        case IDX_FP_REGS + 12: /* fioff */
            return 4;
        case IDX_FP_REGS + 13: /* foseg */
            return 4;
        case IDX_FP_REGS + 14: /* fooff */
            return 4;
        case IDX_FP_REGS + 15: /* fop */
            return 4;

        case IDX_MXCSR_REG:
            env->mxcsr = ldl_p(mem_buf);
            return 4;
        }
    }
    /* Unrecognised register.  */
    return 0;
}
Commit	Line	Data
f20f9df0 AF	1	/*
	2	* x86 gdb server stub
	3	*
	4	* Copyright (c) 2003-2005 Fabrice Bellard
	5	* Copyright (c) 2013 SUSE LINUX Products GmbH
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#ifdef TARGET_X86_64
	22	static const int gpr_map[16] = {
	23	R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
	24	8, 9, 10, 11, 12, 13, 14, 15
	25	};
	26	#else
	27	#define gpr_map gpr_map32
	28	#endif
	29	static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
	30
	31	#define IDX_IP_REG CPU_NB_REGS
	32	#define IDX_FLAGS_REG (IDX_IP_REG + 1)
	33	#define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
	34	#define IDX_FP_REGS (IDX_SEG_REGS + 6)
	35	#define IDX_XMM_REGS (IDX_FP_REGS + 16)
	36	#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
	37
	38	static int cpu_gdb_read_register(CPUX86State env, uint8_t mem_buf, int n)
	39	{
	40	if (n < CPU_NB_REGS) {
	41	if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
986a2998	42	return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
f20f9df0	43	} else if (n < CPU_NB_REGS32) {
986a2998	44	return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
f20f9df0 AF	45	}
	46	} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
	47	#ifdef USE_X86LDOUBLE
	48	/* FIXME: byteswap float values - after fixing fpregs layout. */
	49	memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
	50	#else
	51	memset(mem_buf, 0, 10);
	52	#endif
	53	return 10;
	54	} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
	55	n -= IDX_XMM_REGS;
	56	if (n < CPU_NB_REGS32 \|\|
	57	(TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
	58	stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
	59	stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
	60	return 16;
	61	}
	62	} else {
	63	switch (n) {
	64	case IDX_IP_REG:
	65	if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
986a2998	66	return gdb_get_reg64(mem_buf, env->eip);
f20f9df0	67	} else {
986a2998	68	return gdb_get_reg32(mem_buf, env->eip);
f20f9df0 AF	69	}
f20f9df0 AF	70	case IDX_FLAGS_REG:
986a2998	71	return gdb_get_reg32(mem_buf, env->eflags);
f20f9df0 AF	72
f20f9df0 AF	73	case IDX_SEG_REGS:
986a2998	74	return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
f20f9df0	75	case IDX_SEG_REGS + 1:
986a2998	76	return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
f20f9df0	77	case IDX_SEG_REGS + 2:
986a2998	78	return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
f20f9df0	79	case IDX_SEG_REGS + 3:
986a2998	80	return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
f20f9df0	81	case IDX_SEG_REGS + 4:
986a2998	82	return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
f20f9df0	83	case IDX_SEG_REGS + 5:
986a2998	84	return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
f20f9df0 AF	85
f20f9df0 AF	86	case IDX_FP_REGS + 8:
986a2998	87	return gdb_get_reg32(mem_buf, env->fpuc);
f20f9df0	88	case IDX_FP_REGS + 9:
986a2998 AF	89	return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) \|
986a2998 AF	90	(env->fpstt & 0x7) << 11);
f20f9df0	91	case IDX_FP_REGS + 10:
986a2998	92	return gdb_get_reg32(mem_buf, 0); /* ftag */
f20f9df0	93	case IDX_FP_REGS + 11:
986a2998	94	return gdb_get_reg32(mem_buf, 0); /* fiseg */
f20f9df0	95	case IDX_FP_REGS + 12:
986a2998	96	return gdb_get_reg32(mem_buf, 0); /* fioff */
f20f9df0	97	case IDX_FP_REGS + 13:
986a2998	98	return gdb_get_reg32(mem_buf, 0); /* foseg */
f20f9df0	99	case IDX_FP_REGS + 14:
986a2998	100	return gdb_get_reg32(mem_buf, 0); /* fooff */
f20f9df0	101	case IDX_FP_REGS + 15:
986a2998	102	return gdb_get_reg32(mem_buf, 0); /* fop */
f20f9df0 AF	103
f20f9df0 AF	104	case IDX_MXCSR_REG:
986a2998	105	return gdb_get_reg32(mem_buf, env->mxcsr);
f20f9df0 AF	106	}
	107	}
	108	return 0;
	109	}
	110
	111	static int cpu_x86_gdb_load_seg(CPUX86State env, int sreg, uint8_t mem_buf)
	112	{
	113	uint16_t selector = ldl_p(mem_buf);
	114
	115	if (selector != env->segs[sreg].selector) {
	116	#if defined(CONFIG_USER_ONLY)
	117	cpu_x86_load_seg(env, sreg, selector);
	118	#else
	119	unsigned int limit, flags;
	120	target_ulong base;
	121
	122	if (!(env->cr[0] & CR0_PE_MASK) \|\| (env->eflags & VM_MASK)) {
	123	base = selector << 4;
	124	limit = 0xffff;
	125	flags = 0;
	126	} else {
	127	if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
	128	&flags)) {
	129	return 4;
	130	}
	131	}
	132	cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
	133	#endif
	134	}
	135	return 4;
	136	}
	137
	138	static int cpu_gdb_write_register(CPUX86State env, uint8_t mem_buf, int n)
	139	{
	140	uint32_t tmp;
	141
	142	if (n < CPU_NB_REGS) {
	143	if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
	144	env->regs[gpr_map[n]] = ldtul_p(mem_buf);
	145	return sizeof(target_ulong);
	146	} else if (n < CPU_NB_REGS32) {
	147	n = gpr_map32[n];
	148	env->regs[n] &= ~0xffffffffUL;
	149	env->regs[n] \|= (uint32_t)ldl_p(mem_buf);
	150	return 4;
	151	}
	152	} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
	153	#ifdef USE_X86LDOUBLE
	154	/* FIXME: byteswap float values - after fixing fpregs layout. */
	155	memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
	156	#endif
	157	return 10;
	158	} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
	159	n -= IDX_XMM_REGS;
	160	if (n < CPU_NB_REGS32 \|\|
	161	(TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
	162	env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
	163	env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
	164	return 16;
	165	}
	166	} else {
	167	switch (n) {
	168	case IDX_IP_REG:
	169	if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
170	env->eip = ldq_p(mem_buf);
171	return 8;
172	} else {
173	env->eip &= ~0xffffffffUL;
174	env->eip \|= (uint32_t)ldl_p(mem_buf);
175	return 4;
176	}
177	case IDX_FLAGS_REG:
178	env->eflags = ldl_p(mem_buf);
179	return 4;
180
181	case IDX_SEG_REGS:
182	return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
183	case IDX_SEG_REGS + 1:
184	return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
185	case IDX_SEG_REGS + 2:
186	return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
187	case IDX_SEG_REGS + 3:
188	return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
189	case IDX_SEG_REGS + 4:
190	return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
191	case IDX_SEG_REGS + 5:
192	return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
193
194	case IDX_FP_REGS + 8:
195	env->fpuc = ldl_p(mem_buf);
196	return 4;
197	case IDX_FP_REGS + 9:
198	tmp = ldl_p(mem_buf);
199	env->fpstt = (tmp >> 11) & 7;
200	env->fpus = tmp & ~0x3800;
201	return 4;
202	case IDX_FP_REGS + 10: /* ftag */
203	return 4;
204	case IDX_FP_REGS + 11: /* fiseg */
205	return 4;
206	case IDX_FP_REGS + 12: /* fioff */
207	return 4;
208	case IDX_FP_REGS + 13: /* foseg */
209	return 4;
210	case IDX_FP_REGS + 14: /* fooff */
211	return 4;
212	case IDX_FP_REGS + 15: /* fop */
213	return 4;
214
215	case IDX_MXCSR_REG:
216	env->mxcsr = ldl_p(mem_buf);
217	return 4;
218	}
219	}
220	/* Unrecognised register. */
221	return 0;
222	}