[qemu.git] / hw / serial.c

/*
 * QEMU 16450 UART emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "qemu-char.h"
#include "isa.h"
#include "pc.h"
#include "qemu-timer.h"

//#define DEBUG_SERIAL

#define UART_LCR_DLAB	0x80	/* Divisor latch access bit */

#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */

#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */

#define UART_IIR_MSI	0x00	/* Modem status interrupt */
#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */

/*
 * These are the definitions for the Modem Control Register
 */
#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
#define UART_MCR_OUT2	0x08	/* Out2 complement */
#define UART_MCR_OUT1	0x04	/* Out1 complement */
#define UART_MCR_RTS	0x02	/* RTS complement */
#define UART_MCR_DTR	0x01	/* DTR complement */

/*
 * These are the definitions for the Modem Status Register
 */
#define UART_MSR_DCD	0x80	/* Data Carrier Detect */
#define UART_MSR_RI	0x40	/* Ring Indicator */
#define UART_MSR_DSR	0x20	/* Data Set Ready */
#define UART_MSR_CTS	0x10	/* Clear to Send */
#define UART_MSR_DDCD	0x08	/* Delta DCD */
#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */
#define UART_MSR_DDSR	0x02	/* Delta DSR */
#define UART_MSR_DCTS	0x01	/* Delta CTS */
#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */

#define UART_LSR_TEMT	0x40	/* Transmitter empty */
#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
#define UART_LSR_BI	0x10	/* Break interrupt indicator */
#define UART_LSR_FE	0x08	/* Frame error indicator */
#define UART_LSR_PE	0x04	/* Parity error indicator */
#define UART_LSR_OE	0x02	/* Overrun error indicator */
#define UART_LSR_DR	0x01	/* Receiver data ready */

/*
 * Delay TX IRQ after sending as much characters as the given interval would
 * contain on real hardware. This avoids overloading the guest if it processes
 * its output buffer in a loop inside the TX IRQ handler.
 */
#define THROTTLE_TX_INTERVAL	10 /* ms */

struct SerialState {
    uint16_t divider;
    uint8_t rbr; /* receive register */
    uint8_t ier;
    uint8_t iir; /* read only */
    uint8_t lcr;
    uint8_t mcr;
    uint8_t lsr; /* read only */
    uint8_t msr; /* read only */
    uint8_t scr;
    /* NOTE: this hidden state is necessary for tx irq generation as
       it can be reset while reading iir */
    int thr_ipending;
    qemu_irq irq;
    CharDriverState *chr;
    int last_break_enable;
    target_phys_addr_t base;
    int it_shift;
    int baudbase;
    QEMUTimer *tx_timer;
    int tx_burst;
};

static void serial_receive_byte(SerialState *s, int ch);

static void serial_update_irq(SerialState *s)
{
    if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
        s->iir = UART_IIR_RDI;
    } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
        s->iir = UART_IIR_THRI;
    } else {
        s->iir = UART_IIR_NO_INT;
    }
    if (s->iir != UART_IIR_NO_INT) {
        qemu_irq_raise(s->irq);
    } else {
        qemu_irq_lower(s->irq);
    }
}

static void serial_tx_done(void *opaque)
{
    SerialState *s = opaque;

    if (s->tx_burst < 0) {
        uint16_t divider;

        if (s->divider)
          divider = s->divider;
        else
          divider = 1;

        /* We assume 10 bits/char, OK for this purpose. */
        s->tx_burst = THROTTLE_TX_INTERVAL * 1000 /
            (1000000 * 10 / (s->baudbase / divider));
    }
    s->thr_ipending = 1;
    s->lsr |= UART_LSR_THRE;
    s->lsr |= UART_LSR_TEMT;
    serial_update_irq(s);
}

static void serial_update_parameters(SerialState *s)
{
    int speed, parity, data_bits, stop_bits;
    QEMUSerialSetParams ssp;

    if (s->lcr & 0x08) {
        if (s->lcr & 0x10)
            parity = 'E';
        else
            parity = 'O';
    } else {
            parity = 'N';
    }
    if (s->lcr & 0x04)
        stop_bits = 2;
    else
        stop_bits = 1;
    data_bits = (s->lcr & 0x03) + 5;
    if (s->divider == 0)
        return;
    speed = s->baudbase / s->divider;
    ssp.speed = speed;
    ssp.parity = parity;
    ssp.data_bits = data_bits;
    ssp.stop_bits = stop_bits;
    qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
#if 0
    printf("speed=%d parity=%c data=%d stop=%d\n",
           speed, parity, data_bits, stop_bits);
#endif
}

static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    SerialState *s = opaque;
    unsigned char ch;

    addr &= 7;
#ifdef DEBUG_SERIAL
    printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
#endif
    switch(addr) {
    default:
    case 0:
        if (s->lcr & UART_LCR_DLAB) {
            s->divider = (s->divider & 0xff00) | val;
            serial_update_parameters(s);
        } else {
            s->thr_ipending = 0;
            s->lsr &= ~UART_LSR_THRE;
            serial_update_irq(s);
            ch = val;
            if (!(s->mcr & UART_MCR_LOOP)) {
                /* when not in loopback mode, send the char */
                qemu_chr_write(s->chr, &ch, 1);
            } else {
                /* in loopback mode, say that we just received a char */
                serial_receive_byte(s, ch);
            }
            if (s->tx_burst > 0) {
                s->tx_burst--;
                serial_tx_done(s);
            } else if (s->tx_burst == 0) {
                s->tx_burst--;
                qemu_mod_timer(s->tx_timer, qemu_get_clock(vm_clock) +
                               ticks_per_sec * THROTTLE_TX_INTERVAL / 1000);
            }
        }
        break;
    case 1:
        if (s->lcr & UART_LCR_DLAB) {
            s->divider = (s->divider & 0x00ff) | (val << 8);
            serial_update_parameters(s);
        } else {
            s->ier = val & 0x0f;
            if (s->lsr & UART_LSR_THRE) {
                s->thr_ipending = 1;
            }
            serial_update_irq(s);
        }
        break;
    case 2:
        break;
    case 3:
        {
            int break_enable;
            s->lcr = val;
            serial_update_parameters(s);
            break_enable = (val >> 6) & 1;
            if (break_enable != s->last_break_enable) {
                s->last_break_enable = break_enable;
                qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
                               &break_enable);
            }
        }
        break;
    case 4:
        s->mcr = val & 0x1f;
        break;
    case 5:
        break;
    case 6:
        break;
    case 7:
        s->scr = val;
        break;
    }
}

static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
{
    SerialState *s = opaque;
    uint32_t ret;

    addr &= 7;
    switch(addr) {
    default:
    case 0:
        if (s->lcr & UART_LCR_DLAB) {
            ret = s->divider & 0xff;
        } else {
            ret = s->rbr;
            s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
            serial_update_irq(s);
            if (!(s->mcr & UART_MCR_LOOP)) {
                /* in loopback mode, don't receive any data */
                qemu_chr_accept_input(s->chr);
            }
        }
        break;
    case 1:
        if (s->lcr & UART_LCR_DLAB) {
            ret = (s->divider >> 8) & 0xff;
        } else {
            ret = s->ier;
        }
        break;
    case 2:
        ret = s->iir;
        /* reset THR pending bit */
        if ((ret & 0x7) == UART_IIR_THRI)
            s->thr_ipending = 0;
        serial_update_irq(s);
        break;
    case 3:
        ret = s->lcr;
        break;
    case 4:
        ret = s->mcr;
        break;
    case 5:
        ret = s->lsr;
        break;
    case 6:
        if (s->mcr & UART_MCR_LOOP) {
            /* in loopback, the modem output pins are connected to the
               inputs */
            ret = (s->mcr & 0x0c) << 4;
            ret |= (s->mcr & 0x02) << 3;
            ret |= (s->mcr & 0x01) << 5;
        } else {
            ret = s->msr;
        }
        break;
    case 7:
        ret = s->scr;
        break;
    }
#ifdef DEBUG_SERIAL
    printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
#endif
    return ret;
}

static int serial_can_receive(SerialState *s)
{
    return !(s->lsr & UART_LSR_DR);
}

static void serial_receive_byte(SerialState *s, int ch)
{
    s->rbr = ch;
    s->lsr |= UART_LSR_DR;
    serial_update_irq(s);
}

static void serial_receive_break(SerialState *s)
{
    s->rbr = 0;
    s->lsr |= UART_LSR_BI | UART_LSR_DR;
    serial_update_irq(s);
}

static int serial_can_receive1(void *opaque)
{
    SerialState *s = opaque;
    return serial_can_receive(s);
}

static void serial_receive1(void *opaque, const uint8_t *buf, int size)
{
    SerialState *s = opaque;
    serial_receive_byte(s, buf[0]);
}

static void serial_event(void *opaque, int event)
{
    SerialState *s = opaque;
    if (event == CHR_EVENT_BREAK)
        serial_receive_break(s);
}

static void serial_save(QEMUFile *f, void *opaque)
{
    SerialState *s = opaque;

    qemu_put_be16s(f,&s->divider);
    qemu_put_8s(f,&s->rbr);
    qemu_put_8s(f,&s->ier);
    qemu_put_8s(f,&s->iir);
    qemu_put_8s(f,&s->lcr);
    qemu_put_8s(f,&s->mcr);
    qemu_put_8s(f,&s->lsr);
    qemu_put_8s(f,&s->msr);
    qemu_put_8s(f,&s->scr);
}

static int serial_load(QEMUFile *f, void *opaque, int version_id)
{
    SerialState *s = opaque;

    if(version_id > 2)
        return -EINVAL;

    if (version_id >= 2)
        qemu_get_be16s(f, &s->divider);
    else
        s->divider = qemu_get_byte(f);
    qemu_get_8s(f,&s->rbr);
    qemu_get_8s(f,&s->ier);
    qemu_get_8s(f,&s->iir);
    qemu_get_8s(f,&s->lcr);
    qemu_get_8s(f,&s->mcr);
    qemu_get_8s(f,&s->lsr);
    qemu_get_8s(f,&s->msr);
    qemu_get_8s(f,&s->scr);

    return 0;
}

static void serial_reset(void *opaque)
{
    SerialState *s = opaque;

    s->divider = 0;
    s->rbr = 0;
    s->ier = 0;
    s->iir = UART_IIR_NO_INT;
    s->lcr = 0;
    s->mcr = 0;
    s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
    s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
    s->scr = 0;

    s->thr_ipending = 0;
    s->last_break_enable = 0;
    qemu_irq_lower(s->irq);
}

/* If fd is zero, it means that the serial device uses the console */
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
                         CharDriverState *chr)
{
    SerialState *s;

    s = qemu_mallocz(sizeof(SerialState));
    if (!s)
        return NULL;
    s->irq = irq;
    s->baudbase = baudbase;

    s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
    if (!s->tx_timer)
        return NULL;

    qemu_register_reset(serial_reset, s);
    serial_reset(s);

    register_savevm("serial", base, 2, serial_save, serial_load, s);

    register_ioport_write(base, 8, 1, serial_ioport_write, s);
    register_ioport_read(base, 8, 1, serial_ioport_read, s);
    s->chr = chr;
    qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
                          serial_event, s);
    return s;
}

/* Memory mapped interface */
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
{
    SerialState *s = opaque;

    return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
}

void serial_mm_writeb (void *opaque,
                       target_phys_addr_t addr, uint32_t value)
{
    SerialState *s = opaque;

    serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
}

uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
{
    SerialState *s = opaque;
    uint32_t val;

    val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap16(val);
#endif
    return val;
}

void serial_mm_writew (void *opaque,
                       target_phys_addr_t addr, uint32_t value)
{
    SerialState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap16(value);
#endif
    serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
}

uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
{
    SerialState *s = opaque;
    uint32_t val;

    val = serial_ioport_read(s, (addr - s->base) >> s->it_shift);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    return val;
}

void serial_mm_writel (void *opaque,
                       target_phys_addr_t addr, uint32_t value)
{
    SerialState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap32(value);
#endif
    serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
}

static CPUReadMemoryFunc *serial_mm_read[] = {
    &serial_mm_readb,
    &serial_mm_readw,
    &serial_mm_readl,
};

static CPUWriteMemoryFunc *serial_mm_write[] = {
    &serial_mm_writeb,
    &serial_mm_writew,
    &serial_mm_writel,
};

SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
                             qemu_irq irq, int baudbase,
                             CharDriverState *chr, int ioregister)
{
    SerialState *s;
    int s_io_memory;

    s = qemu_mallocz(sizeof(SerialState));
    if (!s)
        return NULL;
    s->irq = irq;
    s->base = base;
    s->it_shift = it_shift;
    s->baudbase= baudbase;

    s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
    if (!s->tx_timer)
        return NULL;

    qemu_register_reset(serial_reset, s);
    serial_reset(s);

    register_savevm("serial", base, 2, serial_save, serial_load, s);

    if (ioregister) {
        s_io_memory = cpu_register_io_memory(0, serial_mm_read,
                                             serial_mm_write, s);
        cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
    }
    s->chr = chr;
    qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
                          serial_event, s);
    return s;
}
Commit	Line	Data
80cabfad FB	1	/*
80cabfad FB	2	* QEMU 16450 UART emulation
5fafdf24	3	*
80cabfad	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
80cabfad FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "qemu-char.h"
	26	#include "isa.h"
	27	#include "pc.h"
6936bfe5	28	#include "qemu-timer.h"
80cabfad FB	29
	30	//#define DEBUG_SERIAL
	31
	32	#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
	33
	34	#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
	35	#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
	36	#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
	37	#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
	38
	39	#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
	40	#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
	41
	42	#define UART_IIR_MSI 0x00 /* Modem status interrupt */
	43	#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
	44	#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
	45	#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
	46
	47	/*
	48	* These are the definitions for the Modem Control Register
	49	*/
	50	#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
	51	#define UART_MCR_OUT2 0x08 /* Out2 complement */
	52	#define UART_MCR_OUT1 0x04 /* Out1 complement */
	53	#define UART_MCR_RTS 0x02 /* RTS complement */
	54	#define UART_MCR_DTR 0x01 /* DTR complement */
	55
	56	/*
	57	* These are the definitions for the Modem Status Register
	58	*/
	59	#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
	60	#define UART_MSR_RI 0x40 /* Ring Indicator */
	61	#define UART_MSR_DSR 0x20 /* Data Set Ready */
	62	#define UART_MSR_CTS 0x10 /* Clear to Send */
	63	#define UART_MSR_DDCD 0x08 /* Delta DCD */
	64	#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
	65	#define UART_MSR_DDSR 0x02 /* Delta DSR */
	66	#define UART_MSR_DCTS 0x01 /* Delta CTS */
	67	#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
	68
	69	#define UART_LSR_TEMT 0x40 /* Transmitter empty */
	70	#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
	71	#define UART_LSR_BI 0x10 /* Break interrupt indicator */
	72	#define UART_LSR_FE 0x08 /* Frame error indicator */
	73	#define UART_LSR_PE 0x04 /* Parity error indicator */
	74	#define UART_LSR_OE 0x02 /* Overrun error indicator */
	75	#define UART_LSR_DR 0x01 /* Receiver data ready */
	76
6936bfe5 AJ	77	/*
	78	* Delay TX IRQ after sending as much characters as the given interval would
	79	* contain on real hardware. This avoids overloading the guest if it processes
	80	* its output buffer in a loop inside the TX IRQ handler.
	81	*/
	82	#define THROTTLE_TX_INTERVAL 10 /* ms */
	83
b41a2cd1	84	struct SerialState {
508d92d0	85	uint16_t divider;
80cabfad FB	86	uint8_t rbr; /* receive register */
	87	uint8_t ier;
	88	uint8_t iir; /* read only */
	89	uint8_t lcr;
	90	uint8_t mcr;
	91	uint8_t lsr; /* read only */
3e749fe1	92	uint8_t msr; /* read only */
80cabfad FB	93	uint8_t scr;
	94	/* NOTE: this hidden state is necessary for tx irq generation as
	95	it can be reset while reading iir */
	96	int thr_ipending;
d537cf6c	97	qemu_irq irq;
82c643ff	98	CharDriverState *chr;
f8d179e3	99	int last_break_enable;
71db710f	100	target_phys_addr_t base;
e5d13e2f	101	int it_shift;
b6cd0ea1	102	int baudbase;
6936bfe5 AJ	103	QEMUTimer *tx_timer;
6936bfe5 AJ	104	int tx_burst;
b41a2cd1	105	};
80cabfad	106
b2a5160c AZ	107	static void serial_receive_byte(SerialState *s, int ch);
b2a5160c AZ	108
b41a2cd1	109	static void serial_update_irq(SerialState *s)
80cabfad	110	{
80cabfad FB	111	if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
	112	s->iir = UART_IIR_RDI;
	113	} else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
	114	s->iir = UART_IIR_THRI;
	115	} else {
	116	s->iir = UART_IIR_NO_INT;
	117	}
	118	if (s->iir != UART_IIR_NO_INT) {
d537cf6c	119	qemu_irq_raise(s->irq);
80cabfad	120	} else {
d537cf6c	121	qemu_irq_lower(s->irq);
80cabfad FB	122	}
	123	}
	124
6936bfe5 AJ	125	static void serial_tx_done(void *opaque)
	126	{
	127	SerialState *s = opaque;
	128
	129	if (s->tx_burst < 0) {
	130	uint16_t divider;
	131
	132	if (s->divider)
	133	divider = s->divider;
	134	else
	135	divider = 1;
	136
	137	/* We assume 10 bits/char, OK for this purpose. */
	138	s->tx_burst = THROTTLE_TX_INTERVAL * 1000 /
b6cd0ea1	139	(1000000 * 10 / (s->baudbase / divider));
6936bfe5 AJ	140	}
	141	s->thr_ipending = 1;
	142	s->lsr \|= UART_LSR_THRE;
	143	s->lsr \|= UART_LSR_TEMT;
	144	serial_update_irq(s);
	145	}
	146
f8d179e3 FB	147	static void serial_update_parameters(SerialState *s)
	148	{
	149	int speed, parity, data_bits, stop_bits;
2122c51a	150	QEMUSerialSetParams ssp;
f8d179e3 FB	151
	152	if (s->lcr & 0x08) {
	153	if (s->lcr & 0x10)
	154	parity = 'E';
	155	else
	156	parity = 'O';
	157	} else {
	158	parity = 'N';
	159	}
5fafdf24	160	if (s->lcr & 0x04)
f8d179e3 FB	161	stop_bits = 2;
	162	else
	163	stop_bits = 1;
	164	data_bits = (s->lcr & 0x03) + 5;
	165	if (s->divider == 0)
	166	return;
b6cd0ea1	167	speed = s->baudbase / s->divider;
2122c51a FB	168	ssp.speed = speed;
	169	ssp.parity = parity;
	170	ssp.data_bits = data_bits;
	171	ssp.stop_bits = stop_bits;
	172	qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
	173	#if 0
5fafdf24	174	printf("speed=%d parity=%c data=%d stop=%d\n",
f8d179e3 FB	175	speed, parity, data_bits, stop_bits);
	176	#endif
	177	}
	178
b41a2cd1	179	static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad	180	{
b41a2cd1	181	SerialState *s = opaque;
80cabfad	182	unsigned char ch;
3b46e624	183
80cabfad FB	184	addr &= 7;
	185	#ifdef DEBUG_SERIAL
	186	printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
	187	#endif
	188	switch(addr) {
	189	default:
	190	case 0:
	191	if (s->lcr & UART_LCR_DLAB) {
	192	s->divider = (s->divider & 0xff00) \| val;
f8d179e3	193	serial_update_parameters(s);
80cabfad FB	194	} else {
	195	s->thr_ipending = 0;
	196	s->lsr &= ~UART_LSR_THRE;
b41a2cd1	197	serial_update_irq(s);
82c643ff	198	ch = val;
b2a5160c AZ	199	if (!(s->mcr & UART_MCR_LOOP)) {
	200	/* when not in loopback mode, send the char */
	201	qemu_chr_write(s->chr, &ch, 1);
6936bfe5	202	} else {
b2a5160c AZ	203	/* in loopback mode, say that we just received a char */
	204	serial_receive_byte(s, ch);
	205	}
6936bfe5 AJ	206	if (s->tx_burst > 0) {
	207	s->tx_burst--;
	208	serial_tx_done(s);
	209	} else if (s->tx_burst == 0) {
	210	s->tx_burst--;
	211	qemu_mod_timer(s->tx_timer, qemu_get_clock(vm_clock) +
	212	ticks_per_sec * THROTTLE_TX_INTERVAL / 1000);
	213	}
80cabfad FB	214	}
	215	break;
	216	case 1:
	217	if (s->lcr & UART_LCR_DLAB) {
	218	s->divider = (s->divider & 0x00ff) \| (val << 8);
f8d179e3	219	serial_update_parameters(s);
80cabfad	220	} else {
60e336db FB	221	s->ier = val & 0x0f;
	222	if (s->lsr & UART_LSR_THRE) {
	223	s->thr_ipending = 1;
	224	}
b41a2cd1	225	serial_update_irq(s);
80cabfad FB	226	}
	227	break;
	228	case 2:
	229	break;
	230	case 3:
f8d179e3 FB	231	{
	232	int break_enable;
	233	s->lcr = val;
	234	serial_update_parameters(s);
	235	break_enable = (val >> 6) & 1;
	236	if (break_enable != s->last_break_enable) {
	237	s->last_break_enable = break_enable;
5fafdf24	238	qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
2122c51a	239	&break_enable);
f8d179e3 FB	240	}
f8d179e3 FB	241	}
80cabfad FB	242	break;
80cabfad FB	243	case 4:
60e336db	244	s->mcr = val & 0x1f;
80cabfad FB	245	break;
	246	case 5:
	247	break;
	248	case 6:
80cabfad FB	249	break;
	250	case 7:
	251	s->scr = val;
	252	break;
	253	}
	254	}
	255
b41a2cd1	256	static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
80cabfad	257	{
b41a2cd1	258	SerialState *s = opaque;
80cabfad FB	259	uint32_t ret;
	260
	261	addr &= 7;
	262	switch(addr) {
	263	default:
	264	case 0:
	265	if (s->lcr & UART_LCR_DLAB) {
5fafdf24	266	ret = s->divider & 0xff;
80cabfad FB	267	} else {
	268	ret = s->rbr;
	269	s->lsr &= ~(UART_LSR_DR \| UART_LSR_BI);
b41a2cd1	270	serial_update_irq(s);
b2a5160c AZ	271	if (!(s->mcr & UART_MCR_LOOP)) {
	272	/* in loopback mode, don't receive any data */
	273	qemu_chr_accept_input(s->chr);
	274	}
80cabfad FB	275	}
	276	break;
	277	case 1:
	278	if (s->lcr & UART_LCR_DLAB) {
	279	ret = (s->divider >> 8) & 0xff;
	280	} else {
	281	ret = s->ier;
	282	}
	283	break;
	284	case 2:
	285	ret = s->iir;
	286	/* reset THR pending bit */
	287	if ((ret & 0x7) == UART_IIR_THRI)
	288	s->thr_ipending = 0;
b41a2cd1	289	serial_update_irq(s);
80cabfad FB	290	break;
	291	case 3:
	292	ret = s->lcr;
	293	break;
	294	case 4:
	295	ret = s->mcr;
	296	break;
	297	case 5:
	298	ret = s->lsr;
	299	break;
	300	case 6:
	301	if (s->mcr & UART_MCR_LOOP) {
	302	/* in loopback, the modem output pins are connected to the
	303	inputs */
	304	ret = (s->mcr & 0x0c) << 4;
	305	ret \|= (s->mcr & 0x02) << 3;
	306	ret \|= (s->mcr & 0x01) << 5;
	307	} else {
	308	ret = s->msr;
	309	}
	310	break;
	311	case 7:
	312	ret = s->scr;
	313	break;
	314	}
	315	#ifdef DEBUG_SERIAL
	316	printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
	317	#endif
	318	return ret;
	319	}
	320
82c643ff	321	static int serial_can_receive(SerialState *s)
80cabfad	322	{
80cabfad FB	323	return !(s->lsr & UART_LSR_DR);
	324	}
	325
82c643ff	326	static void serial_receive_byte(SerialState *s, int ch)
80cabfad	327	{
80cabfad FB	328	s->rbr = ch;
80cabfad FB	329	s->lsr \|= UART_LSR_DR;
b41a2cd1	330	serial_update_irq(s);
80cabfad FB	331	}
80cabfad FB	332
82c643ff	333	static void serial_receive_break(SerialState *s)
80cabfad	334	{
80cabfad FB	335	s->rbr = 0;
80cabfad FB	336	s->lsr \|= UART_LSR_BI \| UART_LSR_DR;
b41a2cd1	337	serial_update_irq(s);
80cabfad FB	338	}
80cabfad FB	339
b41a2cd1	340	static int serial_can_receive1(void *opaque)
80cabfad	341	{
b41a2cd1 FB	342	SerialState *s = opaque;
	343	return serial_can_receive(s);
	344	}
	345
	346	static void serial_receive1(void opaque, const uint8_t buf, int size)
	347	{
	348	SerialState *s = opaque;
	349	serial_receive_byte(s, buf[0]);
	350	}
80cabfad	351
82c643ff FB	352	static void serial_event(void *opaque, int event)
	353	{
	354	SerialState *s = opaque;
	355	if (event == CHR_EVENT_BREAK)
	356	serial_receive_break(s);
	357	}
	358
8738a8d0 FB	359	static void serial_save(QEMUFile f, void opaque)
	360	{
	361	SerialState *s = opaque;
	362
508d92d0	363	qemu_put_be16s(f,&s->divider);
8738a8d0 FB	364	qemu_put_8s(f,&s->rbr);
	365	qemu_put_8s(f,&s->ier);
	366	qemu_put_8s(f,&s->iir);
	367	qemu_put_8s(f,&s->lcr);
	368	qemu_put_8s(f,&s->mcr);
	369	qemu_put_8s(f,&s->lsr);
	370	qemu_put_8s(f,&s->msr);
	371	qemu_put_8s(f,&s->scr);
	372	}
	373
	374	static int serial_load(QEMUFile f, void opaque, int version_id)
	375	{
	376	SerialState *s = opaque;
	377
508d92d0	378	if(version_id > 2)
8738a8d0 FB	379	return -EINVAL;
8738a8d0 FB	380
508d92d0 FB	381	if (version_id >= 2)
	382	qemu_get_be16s(f, &s->divider);
	383	else
	384	s->divider = qemu_get_byte(f);
8738a8d0 FB	385	qemu_get_8s(f,&s->rbr);
	386	qemu_get_8s(f,&s->ier);
	387	qemu_get_8s(f,&s->iir);
	388	qemu_get_8s(f,&s->lcr);
	389	qemu_get_8s(f,&s->mcr);
	390	qemu_get_8s(f,&s->lsr);
	391	qemu_get_8s(f,&s->msr);
	392	qemu_get_8s(f,&s->scr);
	393
	394	return 0;
	395	}
	396
b2a5160c AZ	397	static void serial_reset(void *opaque)
	398	{
	399	SerialState *s = opaque;
	400
	401	s->divider = 0;
	402	s->rbr = 0;
	403	s->ier = 0;
	404	s->iir = UART_IIR_NO_INT;
	405	s->lcr = 0;
	406	s->mcr = 0;
	407	s->lsr = UART_LSR_TEMT \| UART_LSR_THRE;
	408	s->msr = UART_MSR_DCD \| UART_MSR_DSR \| UART_MSR_CTS;
	409	s->scr = 0;
	410
	411	s->thr_ipending = 0;
	412	s->last_break_enable = 0;
	413	qemu_irq_lower(s->irq);
	414	}
	415
b41a2cd1	416	/* If fd is zero, it means that the serial device uses the console */
b6cd0ea1 AJ	417	SerialState *serial_init(int base, qemu_irq irq, int baudbase,
b6cd0ea1 AJ	418	CharDriverState *chr)
b41a2cd1 FB	419	{
	420	SerialState *s;
	421
	422	s = qemu_mallocz(sizeof(SerialState));
	423	if (!s)
	424	return NULL;
80cabfad	425	s->irq = irq;
b6cd0ea1	426	s->baudbase = baudbase;
b2a5160c	427
6936bfe5 AJ	428	s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
	429	if (!s->tx_timer)
	430	return NULL;
	431
b2a5160c AZ	432	qemu_register_reset(serial_reset, s);
b2a5160c AZ	433	serial_reset(s);
b41a2cd1	434
508d92d0	435	register_savevm("serial", base, 2, serial_save, serial_load, s);
8738a8d0	436
b41a2cd1 FB	437	register_ioport_write(base, 8, 1, serial_ioport_write, s);
b41a2cd1 FB	438	register_ioport_read(base, 8, 1, serial_ioport_read, s);
82c643ff	439	s->chr = chr;
e5b0bc44 PB	440	qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
e5b0bc44 PB	441	serial_event, s);
b41a2cd1	442	return s;
80cabfad	443	}
e5d13e2f FB	444
e5d13e2f FB	445	/* Memory mapped interface */
a4bc3afc	446	uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
e5d13e2f FB	447	{
	448	SerialState *s = opaque;
	449
	450	return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
	451	}
	452
a4bc3afc TS	453	void serial_mm_writeb (void *opaque,
a4bc3afc TS	454	target_phys_addr_t addr, uint32_t value)
e5d13e2f FB	455	{
	456	SerialState *s = opaque;
	457
	458	serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
	459	}
	460
a4bc3afc	461	uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
e5d13e2f FB	462	{
e5d13e2f FB	463	SerialState *s = opaque;
e918ee04	464	uint32_t val;
e5d13e2f	465
e918ee04 TS	466	val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
	467	#ifdef TARGET_WORDS_BIGENDIAN
	468	val = bswap16(val);
	469	#endif
	470	return val;
e5d13e2f FB	471	}
e5d13e2f FB	472
a4bc3afc TS	473	void serial_mm_writew (void *opaque,
a4bc3afc TS	474	target_phys_addr_t addr, uint32_t value)
e5d13e2f FB	475	{
e5d13e2f FB	476	SerialState *s = opaque;
e918ee04 TS	477	#ifdef TARGET_WORDS_BIGENDIAN
	478	value = bswap16(value);
	479	#endif
e5d13e2f FB	480	serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
	481	}
	482
a4bc3afc	483	uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
e5d13e2f FB	484	{
e5d13e2f FB	485	SerialState *s = opaque;
e918ee04	486	uint32_t val;
e5d13e2f	487
e918ee04 TS	488	val = serial_ioport_read(s, (addr - s->base) >> s->it_shift);
	489	#ifdef TARGET_WORDS_BIGENDIAN
	490	val = bswap32(val);
	491	#endif
	492	return val;
e5d13e2f FB	493	}
e5d13e2f FB	494
a4bc3afc TS	495	void serial_mm_writel (void *opaque,
a4bc3afc TS	496	target_phys_addr_t addr, uint32_t value)
e5d13e2f FB	497	{
e5d13e2f FB	498	SerialState *s = opaque;
e918ee04 TS	499	#ifdef TARGET_WORDS_BIGENDIAN
	500	value = bswap32(value);
	501	#endif
e5d13e2f FB	502	serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
	503	}
	504
	505	static CPUReadMemoryFunc *serial_mm_read[] = {
	506	&serial_mm_readb,
	507	&serial_mm_readw,
	508	&serial_mm_readl,
	509	};
	510
	511	static CPUWriteMemoryFunc *serial_mm_write[] = {
	512	&serial_mm_writeb,
	513	&serial_mm_writew,
	514	&serial_mm_writel,
	515	};
	516
71db710f	517	SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
b6cd0ea1 AJ	518	qemu_irq irq, int baudbase,
b6cd0ea1 AJ	519	CharDriverState *chr, int ioregister)
e5d13e2f FB	520	{
	521	SerialState *s;
	522	int s_io_memory;
	523
	524	s = qemu_mallocz(sizeof(SerialState));
	525	if (!s)
	526	return NULL;
e5d13e2f	527	s->irq = irq;
e5d13e2f FB	528	s->base = base;
e5d13e2f FB	529	s->it_shift = it_shift;
b6cd0ea1	530	s->baudbase= baudbase;
e5d13e2f	531
6936bfe5 AJ	532	s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
	533	if (!s->tx_timer)
	534	return NULL;
	535
b2a5160c AZ	536	qemu_register_reset(serial_reset, s);
	537	serial_reset(s);
	538
508d92d0	539	register_savevm("serial", base, 2, serial_save, serial_load, s);
e5d13e2f	540
a4bc3afc TS	541	if (ioregister) {
	542	s_io_memory = cpu_register_io_memory(0, serial_mm_read,
	543	serial_mm_write, s);
	544	cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
	545	}
e5d13e2f	546	s->chr = chr;
e5b0bc44 PB	547	qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
e5b0bc44 PB	548	serial_event, s);
e5d13e2f FB	549	return s;
e5d13e2f FB	550	}