[qemu.git] / hw / serial.c

/*
 * QEMU 16450 UART emulation
 * 
 * Copyright (c) 2003-2004 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define DEBUG_SERIAL

#define UART_LCR_DLAB	0x80	/* Divisor latch access bit */

#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */

#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */

#define UART_IIR_MSI	0x00	/* Modem status interrupt */
#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */

/*
 * These are the definitions for the Modem Control Register
 */
#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
#define UART_MCR_OUT2	0x08	/* Out2 complement */
#define UART_MCR_OUT1	0x04	/* Out1 complement */
#define UART_MCR_RTS	0x02	/* RTS complement */
#define UART_MCR_DTR	0x01	/* DTR complement */

/*
 * These are the definitions for the Modem Status Register
 */
#define UART_MSR_DCD	0x80	/* Data Carrier Detect */
#define UART_MSR_RI	0x40	/* Ring Indicator */
#define UART_MSR_DSR	0x20	/* Data Set Ready */
#define UART_MSR_CTS	0x10	/* Clear to Send */
#define UART_MSR_DDCD	0x08	/* Delta DCD */
#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */
#define UART_MSR_DDSR	0x02	/* Delta DSR */
#define UART_MSR_DCTS	0x01	/* Delta CTS */
#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */

#define UART_LSR_TEMT	0x40	/* Transmitter empty */
#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
#define UART_LSR_BI	0x10	/* Break interrupt indicator */
#define UART_LSR_FE	0x08	/* Frame error indicator */
#define UART_LSR_PE	0x04	/* Parity error indicator */
#define UART_LSR_OE	0x02	/* Overrun error indicator */
#define UART_LSR_DR	0x01	/* Receiver data ready */

struct SerialState {
    uint8_t divider;
    uint8_t rbr; /* receive register */
    uint8_t ier;
    uint8_t iir; /* read only */
    uint8_t lcr;
    uint8_t mcr;
    uint8_t lsr; /* read only */
    uint8_t msr;
    uint8_t scr;
    /* NOTE: this hidden state is necessary for tx irq generation as
       it can be reset while reading iir */
    int thr_ipending;
    int irq;
    CharDriverState *chr;
    int last_break_enable;
};

static void serial_update_irq(SerialState *s)
{
    if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
        s->iir = UART_IIR_RDI;
    } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
        s->iir = UART_IIR_THRI;
    } else {
        s->iir = UART_IIR_NO_INT;
    }
    if (s->iir != UART_IIR_NO_INT) {
        pic_set_irq(s->irq, 1);
    } else {
        pic_set_irq(s->irq, 0);
    }
}

static void serial_update_parameters(SerialState *s)
{
    int speed, parity, data_bits, stop_bits;

    if (s->lcr & 0x08) {
        if (s->lcr & 0x10)
            parity = 'E';
        else
            parity = 'O';
    } else {
            parity = 'N';
    }
    if (s->lcr & 0x04) 
        stop_bits = 2;
    else
        stop_bits = 1;
    data_bits = (s->lcr & 0x03) + 5;
    if (s->divider == 0)
        return;
    speed = 115200 / s->divider;
#if 0    
    printf("speed=%d parity=%c data=%d stop=%d\n", 
           speed, parity, data_bits, stop_bits);
#endif
}

static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    SerialState *s = opaque;
    unsigned char ch;
    
    addr &= 7;
#ifdef DEBUG_SERIAL
    printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
#endif
    switch(addr) {
    default:
    case 0:
        if (s->lcr & UART_LCR_DLAB) {
            s->divider = (s->divider & 0xff00) | val;
            serial_update_parameters(s);
        } else {
            s->thr_ipending = 0;
            s->lsr &= ~UART_LSR_THRE;
            serial_update_irq(s);
            ch = val;
            qemu_chr_write(s->chr, &ch, 1);
            s->thr_ipending = 1;
            s->lsr |= UART_LSR_THRE;
            s->lsr |= UART_LSR_TEMT;
            serial_update_irq(s);
        }
        break;
    case 1:
        if (s->lcr & UART_LCR_DLAB) {
            s->divider = (s->divider & 0x00ff) | (val << 8);
            serial_update_parameters(s);
        } else {
            s->ier = val & 0x0f;
            if (s->lsr & UART_LSR_THRE) {
                s->thr_ipending = 1;
            }
            serial_update_irq(s);
        }
        break;
    case 2:
        break;
    case 3:
        {
            int break_enable;
            s->lcr = val;
            serial_update_parameters(s);
            break_enable = (val >> 6) & 1;
            if (break_enable != s->last_break_enable) {
                s->last_break_enable = break_enable;
                qemu_chr_set_serial_break(s, break_enable);
            }
        }
        break;
    case 4:
        s->mcr = val & 0x1f;
        break;
    case 5:
        break;
    case 6:
        s->msr = val;
        break;
    case 7:
        s->scr = val;
        break;
    }
}

static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
{
    SerialState *s = opaque;
    uint32_t ret;

    addr &= 7;
    switch(addr) {
    default:
    case 0:
        if (s->lcr & UART_LCR_DLAB) {
            ret = s->divider & 0xff; 
        } else {
            ret = s->rbr;
            s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
            serial_update_irq(s);
        }
        break;
    case 1:
        if (s->lcr & UART_LCR_DLAB) {
            ret = (s->divider >> 8) & 0xff;
        } else {
            ret = s->ier;
        }
        break;
    case 2:
        ret = s->iir;
        /* reset THR pending bit */
        if ((ret & 0x7) == UART_IIR_THRI)
            s->thr_ipending = 0;
        serial_update_irq(s);
        break;
    case 3:
        ret = s->lcr;
        break;
    case 4:
        ret = s->mcr;
        break;
    case 5:
        ret = s->lsr;
        break;
    case 6:
        if (s->mcr & UART_MCR_LOOP) {
            /* in loopback, the modem output pins are connected to the
               inputs */
            ret = (s->mcr & 0x0c) << 4;
            ret |= (s->mcr & 0x02) << 3;
            ret |= (s->mcr & 0x01) << 5;
        } else {
            ret = s->msr;
        }
        break;
    case 7:
        ret = s->scr;
        break;
    }
#ifdef DEBUG_SERIAL
    printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
#endif
    return ret;
}

static int serial_can_receive(SerialState *s)
{
    return !(s->lsr & UART_LSR_DR);
}

static void serial_receive_byte(SerialState *s, int ch)
{
    s->rbr = ch;
    s->lsr |= UART_LSR_DR;
    serial_update_irq(s);
}

static void serial_receive_break(SerialState *s)
{
    s->rbr = 0;
    s->lsr |= UART_LSR_BI | UART_LSR_DR;
    serial_update_irq(s);
}

static int serial_can_receive1(void *opaque)
{
    SerialState *s = opaque;
    return serial_can_receive(s);
}

static void serial_receive1(void *opaque, const uint8_t *buf, int size)
{
    SerialState *s = opaque;
    serial_receive_byte(s, buf[0]);
}

static void serial_event(void *opaque, int event)
{
    SerialState *s = opaque;
    if (event == CHR_EVENT_BREAK)
        serial_receive_break(s);
}

static void serial_save(QEMUFile *f, void *opaque)
{
    SerialState *s = opaque;

    qemu_put_8s(f,&s->divider);
    qemu_put_8s(f,&s->rbr);
    qemu_put_8s(f,&s->ier);
    qemu_put_8s(f,&s->iir);
    qemu_put_8s(f,&s->lcr);
    qemu_put_8s(f,&s->mcr);
    qemu_put_8s(f,&s->lsr);
    qemu_put_8s(f,&s->msr);
    qemu_put_8s(f,&s->scr);
}

static int serial_load(QEMUFile *f, void *opaque, int version_id)
{
    SerialState *s = opaque;

    if(version_id != 1)
        return -EINVAL;

    qemu_get_8s(f,&s->divider);
    qemu_get_8s(f,&s->rbr);
    qemu_get_8s(f,&s->ier);
    qemu_get_8s(f,&s->iir);
    qemu_get_8s(f,&s->lcr);
    qemu_get_8s(f,&s->mcr);
    qemu_get_8s(f,&s->lsr);
    qemu_get_8s(f,&s->msr);
    qemu_get_8s(f,&s->scr);

    return 0;
}

/* If fd is zero, it means that the serial device uses the console */
SerialState *serial_init(int base, int irq, CharDriverState *chr)
{
    SerialState *s;

    s = qemu_mallocz(sizeof(SerialState));
    if (!s)
        return NULL;
    s->irq = irq;
    s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
    s->iir = UART_IIR_NO_INT;

    register_savevm("serial", base, 1, serial_save, serial_load, s);

    register_ioport_write(base, 8, 1, serial_ioport_write, s);
    register_ioport_read(base, 8, 1, serial_ioport_read, s);
    s->chr = chr;
    qemu_chr_add_read_handler(chr, serial_can_receive1, serial_receive1, s);
    qemu_chr_add_event_handler(chr, serial_event);
    return s;
}
Commit	Line	Data
80cabfad FB	1	/*
	2	* QEMU 16450 UART emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80cabfad FB	24	#include "vl.h"
	25
	26	//#define DEBUG_SERIAL
	27
	28	#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
	29
	30	#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
	31	#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
	32	#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
	33	#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
	34
	35	#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
	36	#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
	37
	38	#define UART_IIR_MSI 0x00 /* Modem status interrupt */
	39	#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
	40	#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
	41	#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
	42
	43	/*
	44	* These are the definitions for the Modem Control Register
	45	*/
	46	#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
	47	#define UART_MCR_OUT2 0x08 /* Out2 complement */
	48	#define UART_MCR_OUT1 0x04 /* Out1 complement */
	49	#define UART_MCR_RTS 0x02 /* RTS complement */
	50	#define UART_MCR_DTR 0x01 /* DTR complement */
	51
	52	/*
	53	* These are the definitions for the Modem Status Register
	54	*/
	55	#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
	56	#define UART_MSR_RI 0x40 /* Ring Indicator */
	57	#define UART_MSR_DSR 0x20 /* Data Set Ready */
	58	#define UART_MSR_CTS 0x10 /* Clear to Send */
	59	#define UART_MSR_DDCD 0x08 /* Delta DCD */
	60	#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
	61	#define UART_MSR_DDSR 0x02 /* Delta DSR */
	62	#define UART_MSR_DCTS 0x01 /* Delta CTS */
	63	#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
	64
	65	#define UART_LSR_TEMT 0x40 /* Transmitter empty */
	66	#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
	67	#define UART_LSR_BI 0x10 /* Break interrupt indicator */
	68	#define UART_LSR_FE 0x08 /* Frame error indicator */
	69	#define UART_LSR_PE 0x04 /* Parity error indicator */
	70	#define UART_LSR_OE 0x02 /* Overrun error indicator */
	71	#define UART_LSR_DR 0x01 /* Receiver data ready */
	72
b41a2cd1	73	struct SerialState {
80cabfad FB	74	uint8_t divider;
	75	uint8_t rbr; /* receive register */
	76	uint8_t ier;
	77	uint8_t iir; /* read only */
	78	uint8_t lcr;
	79	uint8_t mcr;
	80	uint8_t lsr; /* read only */
	81	uint8_t msr;
	82	uint8_t scr;
	83	/* NOTE: this hidden state is necessary for tx irq generation as
	84	it can be reset while reading iir */
	85	int thr_ipending;
	86	int irq;
82c643ff	87	CharDriverState *chr;
f8d179e3	88	int last_break_enable;
b41a2cd1	89	};
80cabfad	90
b41a2cd1	91	static void serial_update_irq(SerialState *s)
80cabfad	92	{
80cabfad FB	93	if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
	94	s->iir = UART_IIR_RDI;
	95	} else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
	96	s->iir = UART_IIR_THRI;
	97	} else {
	98	s->iir = UART_IIR_NO_INT;
	99	}
	100	if (s->iir != UART_IIR_NO_INT) {
	101	pic_set_irq(s->irq, 1);
	102	} else {
	103	pic_set_irq(s->irq, 0);
	104	}
	105	}
	106
f8d179e3 FB	107	static void serial_update_parameters(SerialState *s)
	108	{
	109	int speed, parity, data_bits, stop_bits;
	110
	111	if (s->lcr & 0x08) {
	112	if (s->lcr & 0x10)
	113	parity = 'E';
	114	else
	115	parity = 'O';
	116	} else {
	117	parity = 'N';
	118	}
	119	if (s->lcr & 0x04)
	120	stop_bits = 2;
	121	else
	122	stop_bits = 1;
	123	data_bits = (s->lcr & 0x03) + 5;
	124	if (s->divider == 0)
	125	return;
	126	speed = 115200 / s->divider;
	127	#if 0
	128	printf("speed=%d parity=%c data=%d stop=%d\n",
	129	speed, parity, data_bits, stop_bits);
	130	#endif
	131	}
	132
b41a2cd1	133	static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad	134	{
b41a2cd1	135	SerialState *s = opaque;
80cabfad	136	unsigned char ch;
80cabfad FB	137
	138	addr &= 7;
	139	#ifdef DEBUG_SERIAL
	140	printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
	141	#endif
	142	switch(addr) {
	143	default:
	144	case 0:
	145	if (s->lcr & UART_LCR_DLAB) {
	146	s->divider = (s->divider & 0xff00) \| val;
f8d179e3	147	serial_update_parameters(s);
80cabfad FB	148	} else {
	149	s->thr_ipending = 0;
	150	s->lsr &= ~UART_LSR_THRE;
b41a2cd1	151	serial_update_irq(s);
82c643ff FB	152	ch = val;
82c643ff FB	153	qemu_chr_write(s->chr, &ch, 1);
80cabfad FB	154	s->thr_ipending = 1;
	155	s->lsr \|= UART_LSR_THRE;
	156	s->lsr \|= UART_LSR_TEMT;
b41a2cd1	157	serial_update_irq(s);
80cabfad FB	158	}
	159	break;
	160	case 1:
	161	if (s->lcr & UART_LCR_DLAB) {
	162	s->divider = (s->divider & 0x00ff) \| (val << 8);
f8d179e3	163	serial_update_parameters(s);
80cabfad	164	} else {
60e336db FB	165	s->ier = val & 0x0f;
	166	if (s->lsr & UART_LSR_THRE) {
	167	s->thr_ipending = 1;
	168	}
b41a2cd1	169	serial_update_irq(s);
80cabfad FB	170	}
	171	break;
	172	case 2:
	173	break;
	174	case 3:
f8d179e3 FB	175	{
	176	int break_enable;
	177	s->lcr = val;
	178	serial_update_parameters(s);
	179	break_enable = (val >> 6) & 1;
	180	if (break_enable != s->last_break_enable) {
	181	s->last_break_enable = break_enable;
	182	qemu_chr_set_serial_break(s, break_enable);
	183	}
	184	}
80cabfad FB	185	break;
80cabfad FB	186	case 4:
60e336db	187	s->mcr = val & 0x1f;
80cabfad FB	188	break;
	189	case 5:
	190	break;
	191	case 6:
	192	s->msr = val;
	193	break;
	194	case 7:
	195	s->scr = val;
	196	break;
	197	}
	198	}
	199
b41a2cd1	200	static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
80cabfad	201	{
b41a2cd1	202	SerialState *s = opaque;
80cabfad FB	203	uint32_t ret;
	204
	205	addr &= 7;
	206	switch(addr) {
	207	default:
	208	case 0:
	209	if (s->lcr & UART_LCR_DLAB) {
	210	ret = s->divider & 0xff;
	211	} else {
	212	ret = s->rbr;
	213	s->lsr &= ~(UART_LSR_DR \| UART_LSR_BI);
b41a2cd1	214	serial_update_irq(s);
80cabfad FB	215	}
	216	break;
	217	case 1:
	218	if (s->lcr & UART_LCR_DLAB) {
	219	ret = (s->divider >> 8) & 0xff;
	220	} else {
	221	ret = s->ier;
	222	}
	223	break;
	224	case 2:
	225	ret = s->iir;
	226	/* reset THR pending bit */
	227	if ((ret & 0x7) == UART_IIR_THRI)
	228	s->thr_ipending = 0;
b41a2cd1	229	serial_update_irq(s);
80cabfad FB	230	break;
	231	case 3:
	232	ret = s->lcr;
	233	break;
	234	case 4:
	235	ret = s->mcr;
	236	break;
	237	case 5:
	238	ret = s->lsr;
	239	break;
	240	case 6:
	241	if (s->mcr & UART_MCR_LOOP) {
	242	/* in loopback, the modem output pins are connected to the
	243	inputs */
	244	ret = (s->mcr & 0x0c) << 4;
	245	ret \|= (s->mcr & 0x02) << 3;
	246	ret \|= (s->mcr & 0x01) << 5;
	247	} else {
	248	ret = s->msr;
	249	}
	250	break;
	251	case 7:
	252	ret = s->scr;
	253	break;
	254	}
	255	#ifdef DEBUG_SERIAL
	256	printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
	257	#endif
	258	return ret;
	259	}
	260
82c643ff	261	static int serial_can_receive(SerialState *s)
80cabfad	262	{
80cabfad FB	263	return !(s->lsr & UART_LSR_DR);
	264	}
	265
82c643ff	266	static void serial_receive_byte(SerialState *s, int ch)
80cabfad	267	{
80cabfad FB	268	s->rbr = ch;
80cabfad FB	269	s->lsr \|= UART_LSR_DR;
b41a2cd1	270	serial_update_irq(s);
80cabfad FB	271	}
80cabfad FB	272
82c643ff	273	static void serial_receive_break(SerialState *s)
80cabfad	274	{
80cabfad FB	275	s->rbr = 0;
80cabfad FB	276	s->lsr \|= UART_LSR_BI \| UART_LSR_DR;
b41a2cd1	277	serial_update_irq(s);
80cabfad FB	278	}
80cabfad FB	279
b41a2cd1	280	static int serial_can_receive1(void *opaque)
80cabfad	281	{
b41a2cd1 FB	282	SerialState *s = opaque;
	283	return serial_can_receive(s);
	284	}
	285
	286	static void serial_receive1(void opaque, const uint8_t buf, int size)
	287	{
	288	SerialState *s = opaque;
	289	serial_receive_byte(s, buf[0]);
	290	}
80cabfad	291
82c643ff FB	292	static void serial_event(void *opaque, int event)
	293	{
	294	SerialState *s = opaque;
	295	if (event == CHR_EVENT_BREAK)
	296	serial_receive_break(s);
	297	}
	298
8738a8d0 FB	299	static void serial_save(QEMUFile f, void opaque)
	300	{
	301	SerialState *s = opaque;
	302
	303	qemu_put_8s(f,&s->divider);
	304	qemu_put_8s(f,&s->rbr);
	305	qemu_put_8s(f,&s->ier);
	306	qemu_put_8s(f,&s->iir);
	307	qemu_put_8s(f,&s->lcr);
	308	qemu_put_8s(f,&s->mcr);
	309	qemu_put_8s(f,&s->lsr);
	310	qemu_put_8s(f,&s->msr);
	311	qemu_put_8s(f,&s->scr);
	312	}
	313
	314	static int serial_load(QEMUFile f, void opaque, int version_id)
	315	{
	316	SerialState *s = opaque;
	317
	318	if(version_id != 1)
	319	return -EINVAL;
	320
	321	qemu_get_8s(f,&s->divider);
	322	qemu_get_8s(f,&s->rbr);
	323	qemu_get_8s(f,&s->ier);
	324	qemu_get_8s(f,&s->iir);
	325	qemu_get_8s(f,&s->lcr);
	326	qemu_get_8s(f,&s->mcr);
	327	qemu_get_8s(f,&s->lsr);
	328	qemu_get_8s(f,&s->msr);
	329	qemu_get_8s(f,&s->scr);
	330
	331	return 0;
	332	}
	333
b41a2cd1	334	/* If fd is zero, it means that the serial device uses the console */
82c643ff	335	SerialState serial_init(int base, int irq, CharDriverState chr)
b41a2cd1 FB	336	{
	337	SerialState *s;
	338
	339	s = qemu_mallocz(sizeof(SerialState));
	340	if (!s)
	341	return NULL;
80cabfad FB	342	s->irq = irq;
	343	s->lsr = UART_LSR_TEMT \| UART_LSR_THRE;
	344	s->iir = UART_IIR_NO_INT;
b41a2cd1	345
8738a8d0 FB	346	register_savevm("serial", base, 1, serial_save, serial_load, s);
8738a8d0 FB	347
b41a2cd1 FB	348	register_ioport_write(base, 8, 1, serial_ioport_write, s);
b41a2cd1 FB	349	register_ioport_read(base, 8, 1, serial_ioport_read, s);
82c643ff FB	350	s->chr = chr;
	351	qemu_chr_add_read_handler(chr, serial_can_receive1, serial_receive1, s);
	352	qemu_chr_add_event_handler(chr, serial_event);
b41a2cd1	353	return s;
80cabfad	354	}