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ae0f5e9e AF |
1 | /* |
2 | * QEMU UniCore32 CPU | |
3 | * | |
d48813dd | 4 | * Copyright (c) 2010-2012 Guan Xuetao |
ae0f5e9e AF |
5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * Contributions from 2012-04-01 on are considered under GPL version 2, | |
12 | * or (at your option) any later version. | |
13 | */ | |
14 | ||
3993c6bd | 15 | #include "cpu.h" |
ae0f5e9e | 16 | #include "qemu-common.h" |
88e28512 | 17 | #include "migration/vmstate.h" |
ae0f5e9e | 18 | |
b42eab27 AF |
19 | static void uc32_cpu_set_pc(CPUState *cs, vaddr value) |
20 | { | |
21 | UniCore32CPU *cpu = UNICORE32_CPU(cs); | |
22 | ||
23 | cpu->env.regs[31] = value; | |
24 | } | |
25 | ||
8c2e1b00 AF |
26 | static bool uc32_cpu_has_work(CPUState *cs) |
27 | { | |
28 | return cs->interrupt_request & | |
29 | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); | |
30 | } | |
31 | ||
8df9082d AF |
32 | static inline void set_feature(CPUUniCore32State *env, int feature) |
33 | { | |
34 | env->features |= feature; | |
35 | } | |
36 | ||
ae0f5e9e AF |
37 | /* CPU models */ |
38 | ||
d89e1218 AF |
39 | static ObjectClass *uc32_cpu_class_by_name(const char *cpu_model) |
40 | { | |
41 | ObjectClass *oc; | |
eeb266de | 42 | char *typename; |
d89e1218 AF |
43 | |
44 | if (cpu_model == NULL) { | |
45 | return NULL; | |
46 | } | |
47 | ||
eeb266de AF |
48 | typename = g_strdup_printf("%s-" TYPE_UNICORE32_CPU, cpu_model); |
49 | oc = object_class_by_name(typename); | |
50 | g_free(typename); | |
4933908a AF |
51 | if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_UNICORE32_CPU) || |
52 | object_class_is_abstract(oc))) { | |
d89e1218 AF |
53 | oc = NULL; |
54 | } | |
55 | return oc; | |
56 | } | |
57 | ||
ae0f5e9e AF |
58 | typedef struct UniCore32CPUInfo { |
59 | const char *name; | |
60 | void (*instance_init)(Object *obj); | |
61 | } UniCore32CPUInfo; | |
62 | ||
63 | static void unicore_ii_cpu_initfn(Object *obj) | |
64 | { | |
65 | UniCore32CPU *cpu = UNICORE32_CPU(obj); | |
66 | CPUUniCore32State *env = &cpu->env; | |
67 | ||
d48813dd GX |
68 | env->cp0.c0_cpuid = 0x4d000863; |
69 | env->cp0.c0_cachetype = 0x0d152152; | |
70 | env->cp0.c1_sys = 0x2000; | |
71 | env->cp0.c2_base = 0x0; | |
72 | env->cp0.c3_faultstatus = 0x0; | |
73 | env->cp0.c4_faultaddr = 0x0; | |
74 | env->ucf64.xregs[UC32_UCF64_FPSCR] = 0; | |
8df9082d AF |
75 | |
76 | set_feature(env, UC32_HWCAP_CMOV); | |
77 | set_feature(env, UC32_HWCAP_UCF64); | |
ae0f5e9e AF |
78 | } |
79 | ||
80 | static void uc32_any_cpu_initfn(Object *obj) | |
81 | { | |
82 | UniCore32CPU *cpu = UNICORE32_CPU(obj); | |
83 | CPUUniCore32State *env = &cpu->env; | |
84 | ||
85 | env->cp0.c0_cpuid = 0xffffffff; | |
d48813dd | 86 | env->ucf64.xregs[UC32_UCF64_FPSCR] = 0; |
8df9082d AF |
87 | |
88 | set_feature(env, UC32_HWCAP_CMOV); | |
89 | set_feature(env, UC32_HWCAP_UCF64); | |
ae0f5e9e AF |
90 | } |
91 | ||
92 | static const UniCore32CPUInfo uc32_cpus[] = { | |
93 | { .name = "UniCore-II", .instance_init = unicore_ii_cpu_initfn }, | |
94 | { .name = "any", .instance_init = uc32_any_cpu_initfn }, | |
95 | }; | |
96 | ||
088383e3 AF |
97 | static void uc32_cpu_realizefn(DeviceState *dev, Error **errp) |
98 | { | |
088383e3 AF |
99 | UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev); |
100 | ||
14a10fc3 AF |
101 | qemu_init_vcpu(CPU(dev)); |
102 | ||
088383e3 AF |
103 | ucc->parent_realize(dev, errp); |
104 | } | |
105 | ||
ae0f5e9e AF |
106 | static void uc32_cpu_initfn(Object *obj) |
107 | { | |
c05efcb1 | 108 | CPUState *cs = CPU(obj); |
ae0f5e9e AF |
109 | UniCore32CPU *cpu = UNICORE32_CPU(obj); |
110 | CPUUniCore32State *env = &cpu->env; | |
d9c27f00 | 111 | static bool inited; |
ae0f5e9e | 112 | |
c05efcb1 | 113 | cs->env_ptr = env; |
ae0f5e9e | 114 | cpu_exec_init(env); |
ae0f5e9e | 115 | |
d48813dd | 116 | #ifdef CONFIG_USER_ONLY |
ae0f5e9e AF |
117 | env->uncached_asr = ASR_MODE_USER; |
118 | env->regs[31] = 0; | |
d48813dd GX |
119 | #else |
120 | env->uncached_asr = ASR_MODE_PRIV; | |
121 | env->regs[31] = 0x03000000; | |
122 | #endif | |
ae0f5e9e | 123 | |
00c8cb0a | 124 | tlb_flush(cs, 1); |
d9c27f00 AF |
125 | |
126 | if (tcg_enabled() && !inited) { | |
127 | inited = true; | |
128 | uc32_translate_init(); | |
129 | } | |
ae0f5e9e AF |
130 | } |
131 | ||
88e28512 AF |
132 | static const VMStateDescription vmstate_uc32_cpu = { |
133 | .name = "cpu", | |
134 | .unmigratable = 1, | |
135 | }; | |
136 | ||
d89e1218 AF |
137 | static void uc32_cpu_class_init(ObjectClass *oc, void *data) |
138 | { | |
88e28512 | 139 | DeviceClass *dc = DEVICE_CLASS(oc); |
d89e1218 | 140 | CPUClass *cc = CPU_CLASS(oc); |
088383e3 AF |
141 | UniCore32CPUClass *ucc = UNICORE32_CPU_CLASS(oc); |
142 | ||
143 | ucc->parent_realize = dc->realize; | |
144 | dc->realize = uc32_cpu_realizefn; | |
d89e1218 AF |
145 | |
146 | cc->class_by_name = uc32_cpu_class_by_name; | |
8c2e1b00 | 147 | cc->has_work = uc32_cpu_has_work; |
97a8ea5a | 148 | cc->do_interrupt = uc32_cpu_do_interrupt; |
d8bb9159 | 149 | cc->cpu_exec_interrupt = uc32_cpu_exec_interrupt; |
878096ee | 150 | cc->dump_state = uc32_cpu_dump_state; |
b42eab27 | 151 | cc->set_pc = uc32_cpu_set_pc; |
7510454e AF |
152 | #ifdef CONFIG_USER_ONLY |
153 | cc->handle_mmu_fault = uc32_cpu_handle_mmu_fault; | |
154 | #else | |
00b941e5 AF |
155 | cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug; |
156 | #endif | |
88e28512 | 157 | dc->vmsd = &vmstate_uc32_cpu; |
d89e1218 AF |
158 | } |
159 | ||
ae0f5e9e AF |
160 | static void uc32_register_cpu_type(const UniCore32CPUInfo *info) |
161 | { | |
162 | TypeInfo type_info = { | |
ae0f5e9e AF |
163 | .parent = TYPE_UNICORE32_CPU, |
164 | .instance_init = info->instance_init, | |
165 | }; | |
166 | ||
eeb266de | 167 | type_info.name = g_strdup_printf("%s-" TYPE_UNICORE32_CPU, info->name); |
87fb5811 | 168 | type_register(&type_info); |
eeb266de | 169 | g_free((void *)type_info.name); |
ae0f5e9e AF |
170 | } |
171 | ||
172 | static const TypeInfo uc32_cpu_type_info = { | |
173 | .name = TYPE_UNICORE32_CPU, | |
174 | .parent = TYPE_CPU, | |
175 | .instance_size = sizeof(UniCore32CPU), | |
176 | .instance_init = uc32_cpu_initfn, | |
177 | .abstract = true, | |
178 | .class_size = sizeof(UniCore32CPUClass), | |
d89e1218 | 179 | .class_init = uc32_cpu_class_init, |
ae0f5e9e AF |
180 | }; |
181 | ||
182 | static void uc32_cpu_register_types(void) | |
183 | { | |
184 | int i; | |
185 | ||
186 | type_register_static(&uc32_cpu_type_info); | |
187 | for (i = 0; i < ARRAY_SIZE(uc32_cpus); i++) { | |
188 | uc32_register_cpu_type(&uc32_cpus[i]); | |
189 | } | |
190 | } | |
191 | ||
192 | type_init(uc32_cpu_register_types) |