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hw/usb/tusb6010: Convert away from old_mmio
[qemu.git] / hw / pci / pci.c
CommitLineData
69b91039
FB		 1/*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5fafdf24 5 *
69b91039
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
e688df6b 24
97d5408f 25#include "qemu/osdep.h"
c759b24f
MT		 26#include "hw/hw.h"
27#include "hw/pci/pci.h"
28#include "hw/pci/pci_bridge.h"
06aac7bd 29#include "hw/pci/pci_bus.h"
568f0690 30#include "hw/pci/pci_host.h"
83c9089e 31#include "monitor/monitor.h"
1422e32d 32#include "net/net.h"
9c17d615 33#include "sysemu/sysemu.h"
c759b24f 34#include "hw/loader.h"
d49b6836 35#include "qemu/error-report.h"
1de7afc9 36#include "qemu/range.h"
7828d750 37#include "trace.h"
c759b24f
MT		 38#include "hw/pci/msi.h"
39#include "hw/pci/msix.h"
022c62cb 40#include "exec/address-spaces.h"
5e954943 41#include "hw/hotplug.h"
e4024630 42#include "hw/boards.h"
e688df6b 43#include "qapi/error.h"
112ed241 44#include "qapi/qapi-commands-misc.h"
f348b6d1 45#include "qemu/cutils.h"
69b91039
FB		 46
47//#define DEBUG_PCI
d8d2e079 48#ifdef DEBUG_PCI
2e49d64a 49# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
d8d2e079
IY		 50#else
51# define PCI_DPRINTF(format, ...) do { } while (0)
52#endif
69b91039 53
88c725c7
CH		 54bool pci_available = true;
55
10c4c98a 56static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
4f43c1ff 57static char *pcibus_get_dev_path(DeviceState *dev);
5e0259e7 58static char *pcibus_get_fw_dev_path(DeviceState *dev);
dcc20931 59static void pcibus_reset(BusState *qbus);
10c4c98a 60
3cb75a7c
PB		 61static Property pci_props[] = {
62 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
63 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
64 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
65 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
66 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
67 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
68 QEMU_PCI_CAP_SERR_BITNR, true),
6b449540
MT		 69 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
70 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),
f03d8ea3
MA		 71 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
72 QEMU_PCIE_EXTCAP_INIT_BITNR, true),
3cb75a7c
PB		 73 DEFINE_PROP_END_OF_LIST()
74};
75
d2f69df7
BD		 76static const VMStateDescription vmstate_pcibus = {
77 .name = "PCIBUS",
78 .version_id = 1,
79 .minimum_version_id = 1,
d49805ae 80 .fields = (VMStateField[]) {
d2164ad3 81 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL),
d2f69df7
BD		 82 VMSTATE_VARRAY_INT32(irq_count, PCIBus,
83 nirq, 0, vmstate_info_int32,
84 int32_t),
85 VMSTATE_END_OF_LIST()
86 }
87};
88
b86eacb8
MA		 89static void pci_init_bus_master(PCIDevice *pci_dev)
90{
91 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev);
92
93 memory_region_init_alias(&pci_dev->bus_master_enable_region,
94 OBJECT(pci_dev), "bus master",
95 dma_as->root, 0, memory_region_size(dma_as->root));
96 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
3716d590
JW		 97 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0,
98 &pci_dev->bus_master_enable_region);
b86eacb8
MA		 99}
100
101static void pcibus_machine_done(Notifier *notifier, void *data)
102{
103 PCIBus *bus = container_of(notifier, PCIBus, machine_done);
104 int i;
105
106 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
107 if (bus->devices[i]) {
108 pci_init_bus_master(bus->devices[i]);
109 }
110 }
111}
112
d2f69df7
BD		 113static void pci_bus_realize(BusState *qbus, Error **errp)
114{
115 PCIBus *bus = PCI_BUS(qbus);
116
b86eacb8
MA		 117 bus->machine_done.notify = pcibus_machine_done;
118 qemu_add_machine_init_done_notifier(&bus->machine_done);
119
d2f69df7
BD		 120 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
121}
122
123static void pci_bus_unrealize(BusState *qbus, Error **errp)
124{
125 PCIBus *bus = PCI_BUS(qbus);
126
b86eacb8
MA		 127 qemu_remove_machine_init_done_notifier(&bus->machine_done);
128
d2f69df7
BD		 129 vmstate_unregister(NULL, &vmstate_pcibus, bus);
130}
131
ce6a28ee
MA		 132static bool pcibus_is_root(PCIBus *bus)
133{
134 return !bus->parent_dev;
135}
136
602141d9
MA		 137static int pcibus_num(PCIBus *bus)
138{
139 if (pcibus_is_root(bus)) {
140 return 0; /* pci host bridge */
141 }
142 return bus->parent_dev->config[PCI_SECONDARY_BUS];
143}
144
6a3042b2
MA		 145static uint16_t pcibus_numa_node(PCIBus *bus)
146{
147 return NUMA_NODE_UNASSIGNED;
148}
149
0d936928
AL		 150static void pci_bus_class_init(ObjectClass *klass, void *data)
151{
152 BusClass *k = BUS_CLASS(klass);
ce6a28ee 153 PCIBusClass *pbc = PCI_BUS_CLASS(klass);
0d936928
AL		 154
155 k->print_dev = pcibus_dev_print;
156 k->get_dev_path = pcibus_get_dev_path;
157 k->get_fw_dev_path = pcibus_get_fw_dev_path;
d2f69df7
BD		 158 k->realize = pci_bus_realize;
159 k->unrealize = pci_bus_unrealize;
0d936928 160 k->reset = pcibus_reset;
ce6a28ee
MA		 161
162 pbc->is_root = pcibus_is_root;
602141d9 163 pbc->bus_num = pcibus_num;
6a3042b2 164 pbc->numa_node = pcibus_numa_node;
0d936928
AL		 165}
166
167static const TypeInfo pci_bus_info = {
168 .name = TYPE_PCI_BUS,
169 .parent = TYPE_BUS,
170 .instance_size = sizeof(PCIBus),
ce6a28ee 171 .class_size = sizeof(PCIBusClass),
0d936928 172 .class_init = pci_bus_class_init,
30468f78 173};
69b91039 174
619f02ae
EH		 175static const TypeInfo pcie_interface_info = {
176 .name = INTERFACE_PCIE_DEVICE,
177 .parent = TYPE_INTERFACE,
178};
179
180static const TypeInfo conventional_pci_interface_info = {
181 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE,
182 .parent = TYPE_INTERFACE,
183};
184
3a861c46
AW		 185static const TypeInfo pcie_bus_info = {
186 .name = TYPE_PCIE_BUS,
187 .parent = TYPE_PCI_BUS,
188};
189
d662210a 190static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
1941d19c 191static void pci_update_mappings(PCIDevice *d);
d98f08f5 192static void pci_irq_handler(void *opaque, int irq_num, int level);
133e9b22 193static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
230741dc 194static void pci_del_option_rom(PCIDevice *pdev);
1941d19c 195
d350d97d
AL		 196static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
197static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
e822a52a 198
7588e2b0 199static QLIST_HEAD(, PCIHostState) pci_host_bridges;
30468f78 200
cf8c704d 201int pci_bar(PCIDevice *d, int reg)
5330de09 202{
b3b11697
IY		 203 uint8_t type;
204
205 if (reg != PCI_ROM_SLOT)
206 return PCI_BASE_ADDRESS_0 + reg * 4;
207
208 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
209 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
5330de09
MT		 210}
211
d036bb21
MT		 212static inline int pci_irq_state(PCIDevice *d, int irq_num)
213{
214 return (d->irq_state >> irq_num) & 0x1;
215}
216
217static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
218{
219 d->irq_state &= ~(0x1 << irq_num);
220 d->irq_state |= level << irq_num;
221}
222
223static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
224{
225 PCIBus *bus;
226 for (;;) {
fd56e061 227 bus = pci_get_bus(pci_dev);
d036bb21
MT		 228 irq_num = bus->map_irq(pci_dev, irq_num);
229 if (bus->set_irq)
230 break;
231 pci_dev = bus->parent_dev;
232 }
233 bus->irq_count[irq_num] += change;
234 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
235}
236
9ddf8437
IY		 237int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
238{
239 assert(irq_num >= 0);
240 assert(irq_num < bus->nirq);
241 return !!bus->irq_count[irq_num];
242}
243
f9bf77dd
MT		 244/* Update interrupt status bit in config space on interrupt
245 * state change. */
246static void pci_update_irq_status(PCIDevice *dev)
247{
248 if (dev->irq_state) {
249 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
250 } else {
251 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
252 }
253}
254
4c92325b
IY		 255void pci_device_deassert_intx(PCIDevice *dev)
256{
257 int i;
258 for (i = 0; i < PCI_NUM_PINS; ++i) {
d98f08f5 259 pci_irq_handler(dev, i, 0);
4c92325b
IY		 260 }
261}
262
dcc20931 263static void pci_do_device_reset(PCIDevice *dev)
5330de09 264{
c0b1905b 265 int r;
6fc4925b 266
4c92325b 267 pci_device_deassert_intx(dev);
58b59014
CR		 268 assert(dev->irq_state == 0);
269
ebabb67a 270 /* Clear all writable bits */
99443c21 271 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
f9aebe2e
MT		 272 pci_get_word(dev->wmask + PCI_COMMAND) |
273 pci_get_word(dev->w1cmask + PCI_COMMAND));
89d437df
IY		 274 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
275 pci_get_word(dev->wmask + PCI_STATUS) |
276 pci_get_word(dev->w1cmask + PCI_STATUS));
c0b1905b
MT		 277 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
278 dev->config[PCI_INTERRUPT_LINE] = 0x0;
279 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
71ebd6dc
IY		 280 PCIIORegion *region = &dev->io_regions[r];
281 if (!region->size) {
c0b1905b
MT		 282 continue;
283 }
71ebd6dc
IY		 284
285 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
286 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
287 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
288 } else {
289 pci_set_long(dev->config + pci_bar(dev, r), region->type);
290 }
c0b1905b
MT		 291 }
292 pci_update_mappings(dev);
cbd2d434
JK		 293
294 msi_reset(dev);
295 msix_reset(dev);
5330de09
MT		 296}
297
dcc20931
PB		 298/*
299 * This function is called on #RST and FLR.
300 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
301 */
302void pci_device_reset(PCIDevice *dev)
303{
304 qdev_reset_all(&dev->qdev);
305 pci_do_device_reset(dev);
306}
307
9bb33586
IY		 308/*
309 * Trigger pci bus reset under a given bus.
dcc20931
PB		 310 * Called via qbus_reset_all on RST# assert, after the devices
311 * have been reset qdev_reset_all-ed already.
9bb33586 312 */
dcc20931 313static void pcibus_reset(BusState *qbus)
6eaa6847 314{
81e3e75b 315 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
6eaa6847
GN		 316 int i;
317
5330de09
MT		 318 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
319 if (bus->devices[i]) {
dcc20931 320 pci_do_device_reset(bus->devices[i]);
5330de09 321 }
6eaa6847 322 }
9bb33586 323
9bdbbfc3
PB		 324 for (i = 0; i < bus->nirq; i++) {
325 assert(bus->irq_count[i] == 0);
326 }
9bb33586
IY		 327}
328
3dbc01ae 329static void pci_host_bus_register(DeviceState *host)
e822a52a 330{
3dbc01ae 331 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
7588e2b0
DG		 332
333 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
e822a52a
IY		 334}
335
c473d18d 336PCIBus *pci_device_root_bus(const PCIDevice *d)
e075e788 337{
fd56e061 338 PCIBus *bus = pci_get_bus(d);
e075e788 339
ce6a28ee
MA		 340 while (!pci_bus_is_root(bus)) {
341 d = bus->parent_dev;
342 assert(d != NULL);
343
fd56e061 344 bus = pci_get_bus(d);
e075e788
IY		 345 }
346
c473d18d
DG		 347 return bus;
348}
349
568f0690 350const char *pci_root_bus_path(PCIDevice *dev)
c473d18d 351{
568f0690
DG		 352 PCIBus *rootbus = pci_device_root_bus(dev);
353 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
354 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
c473d18d 355
568f0690
DG		 356 assert(host_bridge->bus == rootbus);
357
358 if (hc->root_bus_path) {
359 return (*hc->root_bus_path)(host_bridge, rootbus);
e075e788
IY		 360 }
361
568f0690 362 return rootbus->qbus.name;
e075e788
IY		 363}
364
1115ff6d
DG		 365static void pci_root_bus_init(PCIBus *bus, DeviceState *parent,
366 MemoryRegion *address_space_mem,
367 MemoryRegion *address_space_io,
368 uint8_t devfn_min)
30468f78 369{
6fa84913 370 assert(PCI_FUNC(devfn_min) == 0);
502a5395 371 bus->devfn_min = devfn_min;
8b884984 372 bus->slot_reserved_mask = 0x0;
5968eca3
AK		 373 bus->address_space_mem = address_space_mem;
374 bus->address_space_io = address_space_io;
e822a52a
IY		 375
376 /* host bridge */
377 QLIST_INIT(&bus->child);
2b8cc89a 378
3dbc01ae 379 pci_host_bus_register(parent);
21eea4b3
GH		 380}
381
8c0bf9e2
AW		 382bool pci_bus_is_express(PCIBus *bus)
383{
384 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
385}
386
0889464a
AW		 387bool pci_bus_is_root(PCIBus *bus)
388{
ce6a28ee 389 return PCI_BUS_GET_CLASS(bus)->is_root(bus);
0889464a
AW		 390}
391
1115ff6d
DG		 392void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
393 const char *name,
394 MemoryRegion *address_space_mem,
395 MemoryRegion *address_space_io,
396 uint8_t devfn_min, const char *typename)
4fec6404 397{
fb17dfe0 398 qbus_create_inplace(bus, bus_size, typename, parent, name);
1115ff6d
DG		 399 pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
400 devfn_min);
4fec6404
PB		 401}
402
1115ff6d
DG		 403PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
404 MemoryRegion *address_space_mem,
405 MemoryRegion *address_space_io,
406 uint8_t devfn_min, const char *typename)
21eea4b3
GH		 407{
408 PCIBus *bus;
409
60a0e443 410 bus = PCI_BUS(qbus_create(typename, parent, name));
1115ff6d
DG		 411 pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
412 devfn_min);
21eea4b3
GH		 413 return bus;
414}
415
416void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
417 void *irq_opaque, int nirq)
418{
419 bus->set_irq = set_irq;
420 bus->map_irq = map_irq;
421 bus->irq_opaque = irq_opaque;
422 bus->nirq = nirq;
7267c094 423 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
21eea4b3
GH		 424}
425
1115ff6d
DG		 426PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
427 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
428 void *irq_opaque,
429 MemoryRegion *address_space_mem,
430 MemoryRegion *address_space_io,
431 uint8_t devfn_min, int nirq,
432 const char *typename)
21eea4b3
GH		 433{
434 PCIBus *bus;
435
1115ff6d
DG		 436 bus = pci_root_bus_new(parent, name, address_space_mem,
437 address_space_io, devfn_min, typename);
21eea4b3 438 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
30468f78
FB		 439 return bus;
440}
69b91039 441
502a5395
PB		 442int pci_bus_num(PCIBus *s)
443{
602141d9 444 return PCI_BUS_GET_CLASS(s)->bus_num(s);
502a5395
PB		 445}
446
6a3042b2
MA		 447int pci_bus_numa_node(PCIBus *bus)
448{
449 return PCI_BUS_GET_CLASS(bus)->numa_node(bus);
502a5395
PB		 450}
451
2c21ee76
JD		 452static int get_pci_config_device(QEMUFile *f, void *pv, size_t size,
453 VMStateField *field)
30ca2aab 454{
73534f2f 455 PCIDevice *s = container_of(pv, PCIDevice, config);
e78e9ae4 456 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
a9f49946 457 uint8_t *config;
52fc1d83
AZ		 458 int i;
459
a9f49946 460 assert(size == pci_config_size(s));
7267c094 461 config = g_malloc(size);
a9f49946
IY		 462
463 qemu_get_buffer(f, config, size);
464 for (i = 0; i < size; ++i) {
f9aebe2e
MT		 465 if ((config[i] ^ s->config[i]) &
466 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
7c59364d
DDAG		 467 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
468 "cmask: %x wmask: %x w1cmask:%x", __func__,
469 i, config[i], s->config[i],
470 s->cmask[i], s->wmask[i], s->w1cmask[i]);
7267c094 471 g_free(config);
bd4b65ee 472 return -EINVAL;
a9f49946
IY		 473 }
474 }
475 memcpy(s->config, config, size);
bd4b65ee 476
1941d19c 477 pci_update_mappings(s);
e78e9ae4 478 if (pc->is_bridge) {
f055e96b 479 PCIBridge *b = PCI_BRIDGE(s);
e78e9ae4
DK		 480 pci_bridge_update_mappings(b);
481 }
52fc1d83 482
4ea375bf
GH		 483 memory_region_set_enabled(&s->bus_master_enable_region,
484 pci_get_word(s->config + PCI_COMMAND)
485 & PCI_COMMAND_MASTER);
486
7267c094 487 g_free(config);
30ca2aab
FB		 488 return 0;
489}
490
73534f2f 491/* just put buffer */
2c21ee76
JD		 492static int put_pci_config_device(QEMUFile *f, void *pv, size_t size,
493 VMStateField *field, QJSON *vmdesc)
73534f2f 494{
dbe73d7f 495 const uint8_t **v = pv;
a9f49946 496 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
dbe73d7f 497 qemu_put_buffer(f, *v, size);
2c21ee76
JD		 498
499 return 0;
73534f2f
JQ		 500}
501
502static VMStateInfo vmstate_info_pci_config = {
503 .name = "pci config",
504 .get = get_pci_config_device,
505 .put = put_pci_config_device,
506};
507
2c21ee76
JD		 508static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size,
509 VMStateField *field)
d036bb21 510{
c3f8f611 511 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
d036bb21
MT		 512 uint32_t irq_state[PCI_NUM_PINS];
513 int i;
514 for (i = 0; i < PCI_NUM_PINS; ++i) {
515 irq_state[i] = qemu_get_be32(f);
516 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
517 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
518 irq_state[i]);
519 return -EINVAL;
520 }
521 }
522
523 for (i = 0; i < PCI_NUM_PINS; ++i) {
524 pci_set_irq_state(s, i, irq_state[i]);
525 }
526
527 return 0;
528}
529
2c21ee76
JD		 530static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size,
531 VMStateField *field, QJSON *vmdesc)
d036bb21
MT		 532{
533 int i;
c3f8f611 534 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
d036bb21
MT		 535
536 for (i = 0; i < PCI_NUM_PINS; ++i) {
537 qemu_put_be32(f, pci_irq_state(s, i));
538 }
2c21ee76
JD		 539
540 return 0;
d036bb21
MT		 541}
542
543static VMStateInfo vmstate_info_pci_irq_state = {
544 .name = "pci irq state",
545 .get = get_pci_irq_state,
546 .put = put_pci_irq_state,
547};
548
20daa90a
DDAG		 549static bool migrate_is_pcie(void *opaque, int version_id)
550{
551 return pci_is_express((PCIDevice *)opaque);
552}
553
554static bool migrate_is_not_pcie(void *opaque, int version_id)
555{
556 return !pci_is_express((PCIDevice *)opaque);
557}
558
73534f2f
JQ		 559const VMStateDescription vmstate_pci_device = {
560 .name = "PCIDevice",
561 .version_id = 2,
562 .minimum_version_id = 1,
d49805ae 563 .fields = (VMStateField[]) {
3476436a 564 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
20daa90a
DDAG		 565 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
566 migrate_is_not_pcie,
567 0, vmstate_info_pci_config,
a9f49946 568 PCI_CONFIG_SPACE_SIZE),
20daa90a
DDAG		 569 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
570 migrate_is_pcie,
571 0, vmstate_info_pci_config,
a9f49946 572 PCIE_CONFIG_SPACE_SIZE),
d036bb21
MT		 573 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
574 vmstate_info_pci_irq_state,
575 PCI_NUM_PINS * sizeof(int32_t)),
73534f2f
JQ		 576 VMSTATE_END_OF_LIST()
577 }
578};
579
a9f49946 580
73534f2f
JQ		 581void pci_device_save(PCIDevice *s, QEMUFile *f)
582{
f9bf77dd
MT		 583 /* Clear interrupt status bit: it is implicit
584 * in irq_state which we are saving.
585 * This makes us compatible with old devices
586 * which never set or clear this bit. */
587 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
20daa90a 588 vmstate_save_state(f, &vmstate_pci_device, s, NULL);
f9bf77dd
MT		 589 /* Restore the interrupt status bit. */
590 pci_update_irq_status(s);
73534f2f
JQ		 591}
592
593int pci_device_load(PCIDevice *s, QEMUFile *f)
594{
f9bf77dd 595 int ret;
20daa90a 596 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
f9bf77dd
MT		 597 /* Restore the interrupt status bit. */
598 pci_update_irq_status(s);
599 return ret;
73534f2f
JQ		 600}
601
5e434f4e 602static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
d350d97d 603{
5e434f4e
IY		 604 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
605 pci_default_sub_vendor_id);
606 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
607 pci_default_sub_device_id);
d350d97d
AL		 608}
609
880345c4 610/*
43c945f1
IY		 611 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
612 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
880345c4 613 */
6dbcb819
MA		 614static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
615 unsigned int *slotp, unsigned int *funcp)
880345c4
AL		 616{
617 const char *p;
618 char *e;
619 unsigned long val;
620 unsigned long dom = 0, bus = 0;
43c945f1
IY		 621 unsigned int slot = 0;
622 unsigned int func = 0;
880345c4
AL		 623
624 p = addr;
625 val = strtoul(p, &e, 16);
626 if (e == p)
627 return -1;
628 if (*e == ':') {
629 bus = val;
630 p = e + 1;
631 val = strtoul(p, &e, 16);
632 if (e == p)
633 return -1;
634 if (*e == ':') {
635 dom = bus;
636 bus = val;
637 p = e + 1;
638 val = strtoul(p, &e, 16);
639 if (e == p)
640 return -1;
641 }
642 }
643
880345c4
AL		 644 slot = val;
645
43c945f1
IY		 646 if (funcp != NULL) {
647 if (*e != '.')
648 return -1;
649
650 p = e + 1;
651 val = strtoul(p, &e, 16);
652 if (e == p)
653 return -1;
654
655 func = val;
656 }
657
658 /* if funcp == NULL func is 0 */
659 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
660 return -1;
661
880345c4
AL		 662 if (*e)
663 return -1;
664
880345c4
AL		 665 *domp = dom;
666 *busp = bus;
667 *slotp = slot;
43c945f1
IY		 668 if (funcp != NULL)
669 *funcp = func;
880345c4
AL		 670 return 0;
671}
672
6dbcb819
MA		 673static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root,
674 const char *devaddr)
5607c388
MA		 675{
676 int dom, bus;
677 unsigned slot;
678
1ef7a2a2
DG		 679 if (!root) {
680 fprintf(stderr, "No primary PCI bus\n");
681 return NULL;
682 }
683
b645000e
S		 684 assert(!root->parent_dev);
685
5607c388
MA		 686 if (!devaddr) {
687 *devfnp = -1;
1ef7a2a2 688 return pci_find_bus_nr(root, 0);
5607c388
MA		 689 }
690
43c945f1 691 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
5607c388
MA		 692 return NULL;
693 }
694
1ef7a2a2
DG		 695 if (dom != 0) {
696 fprintf(stderr, "No support for non-zero PCI domains\n");
697 return NULL;
698 }
699
6ff534b6 700 *devfnp = PCI_DEVFN(slot, 0);
1ef7a2a2 701 return pci_find_bus_nr(root, bus);
5607c388
MA		 702}
703
bd4b65ee
MT		 704static void pci_init_cmask(PCIDevice *dev)
705{
706 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
707 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
708 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
709 dev->cmask[PCI_REVISION_ID] = 0xff;
710 dev->cmask[PCI_CLASS_PROG] = 0xff;
711 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
712 dev->cmask[PCI_HEADER_TYPE] = 0xff;
713 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
714}
715
b7ee1603
MT		 716static void pci_init_wmask(PCIDevice *dev)
717{
a9f49946
IY		 718 int config_size = pci_config_size(dev);
719
b7ee1603
MT		 720 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
721 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
67a51b48 722 pci_set_word(dev->wmask + PCI_COMMAND,
a7b15a5c
MT		 723 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
724 PCI_COMMAND_INTX_DISABLE);
b1aeb926
IY		 725 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
726 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
727 }
3e21ffc9
IY		 728
729 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
730 config_size - PCI_CONFIG_HEADER_SIZE);
b7ee1603
MT		 731}
732
89d437df
IY		 733static void pci_init_w1cmask(PCIDevice *dev)
734{
735 /*
f6bdfcc9 736 * Note: It's okay to set w1cmask even for readonly bits as
89d437df
IY		 737 * long as their value is hardwired to 0.
738 */
739 pci_set_word(dev->w1cmask + PCI_STATUS,
740 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
741 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
742 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
743}
744
d5f27e88 745static void pci_init_mask_bridge(PCIDevice *d)
fb231628
IY		 746{
747 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
748 PCI_SEC_LETENCY_TIMER */
749 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
750
751 /* base and limit */
752 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
753 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
754 pci_set_word(d->wmask + PCI_MEMORY_BASE,
755 PCI_MEMORY_RANGE_MASK & 0xffff);
756 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
757 PCI_MEMORY_RANGE_MASK & 0xffff);
758 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
759 PCI_PREF_RANGE_MASK & 0xffff);
760 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
761 PCI_PREF_RANGE_MASK & 0xffff);
762
763 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
764 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
765
d5f27e88 766 /* Supported memory and i/o types */
68917102
MT		 767 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
768 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
d5f27e88
MT		 769 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
770 PCI_PREF_RANGE_TYPE_64);
771 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
772 PCI_PREF_RANGE_TYPE_64);
773
45eb768c
MT		 774 /*
775 * TODO: Bridges default to 10-bit VGA decoding but we currently only
776 * implement 16-bit decoding (no alias support).
777 */
f6bdfcc9
MT		 778 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
779 PCI_BRIDGE_CTL_PARITY |
780 PCI_BRIDGE_CTL_SERR |
781 PCI_BRIDGE_CTL_ISA |
782 PCI_BRIDGE_CTL_VGA |
783 PCI_BRIDGE_CTL_VGA_16BIT |
784 PCI_BRIDGE_CTL_MASTER_ABORT |
785 PCI_BRIDGE_CTL_BUS_RESET |
786 PCI_BRIDGE_CTL_FAST_BACK |
787 PCI_BRIDGE_CTL_DISCARD |
788 PCI_BRIDGE_CTL_SEC_DISCARD |
f6bdfcc9
MT		 789 PCI_BRIDGE_CTL_DISCARD_SERR);
790 /* Below does not do anything as we never set this bit, put here for
791 * completeness. */
792 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
793 PCI_BRIDGE_CTL_DISCARD_STATUS);
d5f27e88 794 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
15ab7a75 795 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
d5f27e88
MT		 796 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
797 PCI_PREF_RANGE_TYPE_MASK);
15ab7a75
MT		 798 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
799 PCI_PREF_RANGE_TYPE_MASK);
fb231628
IY		 800}
801
133e9b22 802static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
6eab3de1
IY		 803{
804 uint8_t slot = PCI_SLOT(dev->devfn);
805 uint8_t func;
806
807 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
808 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
809 }
810
811 /*
b0cd712c 812 * multifunction bit is interpreted in two ways as follows.
6eab3de1
IY		 813 * - all functions must set the bit to 1.
814 * Example: Intel X53
815 * - function 0 must set the bit, but the rest function (> 0)
816 * is allowed to leave the bit to 0.
817 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
818 *
819 * So OS (at least Linux) checks the bit of only function 0,
820 * and doesn't see the bit of function > 0.
821 *
822 * The below check allows both interpretation.
823 */
824 if (PCI_FUNC(dev->devfn)) {
825 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
826 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
827 /* function 0 should set multifunction bit */
133e9b22
MA		 828 error_setg(errp, "PCI: single function device can't be populated "
829 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
830 return;
6eab3de1 831 }
133e9b22 832 return;
6eab3de1
IY		 833 }
834
835 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
133e9b22 836 return;
6eab3de1
IY		 837 }
838 /* function 0 indicates single function, so function > 0 must be NULL */
839 for (func = 1; func < PCI_FUNC_MAX; ++func) {
840 if (bus->devices[PCI_DEVFN(slot, func)]) {
133e9b22
MA		 841 error_setg(errp, "PCI: %x.0 indicates single function, "
842 "but %x.%x is already populated.",
843 slot, slot, func);
844 return;
6eab3de1
IY		 845 }
846 }
6eab3de1
IY		 847}
848
a9f49946
IY		 849static void pci_config_alloc(PCIDevice *pci_dev)
850{
851 int config_size = pci_config_size(pci_dev);
852
7267c094
AL		 853 pci_dev->config = g_malloc0(config_size);
854 pci_dev->cmask = g_malloc0(config_size);
855 pci_dev->wmask = g_malloc0(config_size);
856 pci_dev->w1cmask = g_malloc0(config_size);
857 pci_dev->used = g_malloc0(config_size);
a9f49946
IY		 858}
859
860static void pci_config_free(PCIDevice *pci_dev)
861{
7267c094
AL		 862 g_free(pci_dev->config);
863 g_free(pci_dev->cmask);
864 g_free(pci_dev->wmask);
865 g_free(pci_dev->w1cmask);
866 g_free(pci_dev->used);
a9f49946
IY		 867}
868
30607764
MA		 869static void do_pci_unregister_device(PCIDevice *pci_dev)
870{
fd56e061 871 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL;
30607764
MA		 872 pci_config_free(pci_dev);
873
193982c6
AK		 874 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) {
875 memory_region_del_subregion(&pci_dev->bus_master_container_region,
876 &pci_dev->bus_master_enable_region);
877 }
30607764 878 address_space_destroy(&pci_dev->bus_master_as);
30607764
MA		 879}
880
4a94b3aa
PX		 881/* Extract PCIReqIDCache into BDF format */
882static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache)
883{
884 uint8_t bus_n;
885 uint16_t result;
886
887 switch (cache->type) {
888 case PCI_REQ_ID_BDF:
889 result = pci_get_bdf(cache->dev);
890 break;
891 case PCI_REQ_ID_SECONDARY_BUS:
fd56e061 892 bus_n = pci_dev_bus_num(cache->dev);
4a94b3aa
PX		 893 result = PCI_BUILD_BDF(bus_n, 0);
894 break;
895 default:
896 error_printf("Invalid PCI requester ID cache type: %d\n",
897 cache->type);
898 exit(1);
899 break;
900 }
901
902 return result;
903}
904
905/* Parse bridges up to the root complex and return requester ID
906 * cache for specific device. For full PCIe topology, the cache
907 * result would be exactly the same as getting BDF of the device.
908 * However, several tricks are required when system mixed up with
909 * legacy PCI devices and PCIe-to-PCI bridges.
910 *
911 * Here we cache the proxy device (and type) not requester ID since
912 * bus number might change from time to time.
913 */
914static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev)
915{
916 PCIDevice *parent;
917 PCIReqIDCache cache = {
918 .dev = dev,
919 .type = PCI_REQ_ID_BDF,
920 };
921
fd56e061 922 while (!pci_bus_is_root(pci_get_bus(dev))) {
4a94b3aa 923 /* We are under PCI/PCIe bridges */
fd56e061 924 parent = pci_get_bus(dev)->parent_dev;
4a94b3aa
PX		 925 if (pci_is_express(parent)) {
926 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
927 /* When we pass through PCIe-to-PCI/PCIX bridges, we
928 * override the requester ID using secondary bus
929 * number of parent bridge with zeroed devfn
930 * (pcie-to-pci bridge spec chap 2.3). */
931 cache.type = PCI_REQ_ID_SECONDARY_BUS;
932 cache.dev = dev;
933 }
934 } else {
935 /* Legacy PCI, override requester ID with the bridge's
936 * BDF upstream. When the root complex connects to
937 * legacy PCI devices (including buses), it can only
938 * obtain requester ID info from directly attached
939 * devices. If devices are attached under bridges, only
940 * the requester ID of the bridge that is directly
941 * attached to the root complex can be recognized. */
942 cache.type = PCI_REQ_ID_BDF;
943 cache.dev = parent;
944 }
945 dev = parent;
946 }
947
948 return cache;
949}
950
951uint16_t pci_requester_id(PCIDevice *dev)
952{
953 return pci_req_id_cache_extract(&dev->requester_id_cache);
954}
955
9b717a3a
MCA		 956static bool pci_bus_devfn_available(PCIBus *bus, int devfn)
957{
958 return !(bus->devices[devfn]);
959}
960
8b884984
MCA		 961static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn)
962{
963 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn));
964}
965
69b91039 966/* -1 for devfn means auto assign */
fd56e061 967static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
133e9b22
MA		 968 const char *name, int devfn,
969 Error **errp)
69b91039 970{
40021f08
AL		 971 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
972 PCIConfigReadFunc *config_read = pc->config_read;
973 PCIConfigWriteFunc *config_write = pc->config_write;
133e9b22 974 Error *local_err = NULL;
3f1e1478 975 DeviceState *dev = DEVICE(pci_dev);
fd56e061 976 PCIBus *bus = pci_get_bus(pci_dev);
3f1e1478 977
0144f6f1
MA		 978 /* Only pci bridges can be attached to extra PCI root buses */
979 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) {
980 error_setg(errp,
981 "PCI: Only PCI/PCIe bridges can be plugged into %s",
982 bus->parent_dev->name);
983 return NULL;
984 }
113f89df 985
69b91039 986 if (devfn < 0) {
b47b0706 987 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
6fa84913 988 devfn += PCI_FUNC_MAX) {
8b884984
MCA		 989 if (pci_bus_devfn_available(bus, devfn) &&
990 !pci_bus_devfn_reserved(bus, devfn)) {
69b91039 991 goto found;
9b717a3a 992 }
69b91039 993 }
8b884984
MCA		 994 error_setg(errp, "PCI: no slot/function available for %s, all in use "
995 "or reserved", name);
09e3acc6 996 return NULL;
69b91039 997 found: ;
8b884984
MCA		 998 } else if (pci_bus_devfn_reserved(bus, devfn)) {
999 error_setg(errp, "PCI: slot %d function %d not available for %s,"
1000 " reserved",
1001 PCI_SLOT(devfn), PCI_FUNC(devfn), name);
1002 return NULL;
9b717a3a 1003 } else if (!pci_bus_devfn_available(bus, devfn)) {
133e9b22
MA		 1004 error_setg(errp, "PCI: slot %d function %d not available for %s,"
1005 " in use by %s",
1006 PCI_SLOT(devfn), PCI_FUNC(devfn), name,
1007 bus->devices[devfn]->name);
09e3acc6 1008 return NULL;
3f1e1478
C		 1009 } else if (dev->hotplugged &&
1010 pci_get_function_0(pci_dev)) {
1011 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s,"
1012 " new func %s cannot be exposed to guest.",
d93ddfb1
MT		 1013 PCI_SLOT(pci_get_function_0(pci_dev)->devfn),
1014 pci_get_function_0(pci_dev)->name,
3f1e1478
C		 1015 name);
1016
1017 return NULL;
69b91039 1018 }
e00387d5 1019
efc8188e 1020 pci_dev->devfn = devfn;
4a94b3aa 1021 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev);
d06bce95 1022 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
e00387d5 1023
3716d590
JW		 1024 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
1025 "bus master container", UINT64_MAX);
1026 address_space_init(&pci_dev->bus_master_as,
1027 &pci_dev->bus_master_container_region, pci_dev->name);
1028
b86eacb8
MA		 1029 if (qdev_hotplug) {
1030 pci_init_bus_master(pci_dev);
1031 }
d036bb21 1032 pci_dev->irq_state = 0;
a9f49946 1033 pci_config_alloc(pci_dev);
fb231628 1034
40021f08
AL		 1035 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
1036 pci_config_set_device_id(pci_dev->config, pc->device_id);
1037 pci_config_set_revision(pci_dev->config, pc->revision);
1038 pci_config_set_class(pci_dev->config, pc->class_id);
113f89df 1039
40021f08
AL		 1040 if (!pc->is_bridge) {
1041 if (pc->subsystem_vendor_id || pc->subsystem_id) {
113f89df 1042 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
40021f08 1043 pc->subsystem_vendor_id);
113f89df 1044 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
40021f08 1045 pc->subsystem_id);
113f89df
IY		 1046 } else {
1047 pci_set_default_subsystem_id(pci_dev);
1048 }
1049 } else {
1050 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
40021f08
AL		 1051 assert(!pc->subsystem_vendor_id);
1052 assert(!pc->subsystem_id);
fb231628 1053 }
bd4b65ee 1054 pci_init_cmask(pci_dev);
b7ee1603 1055 pci_init_wmask(pci_dev);
89d437df 1056 pci_init_w1cmask(pci_dev);
40021f08 1057 if (pc->is_bridge) {
d5f27e88 1058 pci_init_mask_bridge(pci_dev);
fb231628 1059 }
133e9b22
MA		 1060 pci_init_multifunction(bus, pci_dev, &local_err);
1061 if (local_err) {
1062 error_propagate(errp, local_err);
30607764 1063 do_pci_unregister_device(pci_dev);
6eab3de1
IY		 1064 return NULL;
1065 }
0ac32c83
FB		 1066
1067 if (!config_read)
1068 config_read = pci_default_read_config;
1069 if (!config_write)
1070 config_write = pci_default_write_config;
69b91039
FB		 1071 pci_dev->config_read = config_read;
1072 pci_dev->config_write = config_write;
30468f78 1073 bus->devices[devfn] = pci_dev;
f16c4abf 1074 pci_dev->version_id = 2; /* Current pci device vmstate version */
69b91039
FB		 1075 return pci_dev;
1076}
1077
5851e08c
AL		 1078static void pci_unregister_io_regions(PCIDevice *pci_dev)
1079{
1080 PCIIORegion *r;
1081 int i;
1082
1083 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1084 r = &pci_dev->io_regions[i];
182f9c8a 1085 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
5851e08c 1086 continue;
03952339 1087 memory_region_del_subregion(r->address_space, r->memory);
5851e08c 1088 }
e01fd687
AW		 1089
1090 pci_unregister_vga(pci_dev);
5851e08c
AL		 1091}
1092
133e9b22 1093static void pci_qdev_unrealize(DeviceState *dev, Error **errp)
5851e08c 1094{
40021f08
AL		 1095 PCIDevice *pci_dev = PCI_DEVICE(dev);
1096 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
5851e08c
AL		 1097
1098 pci_unregister_io_regions(pci_dev);
230741dc 1099 pci_del_option_rom(pci_dev);
7cf1b0fd 1100
f90c2bcd
AW		 1101 if (pc->exit) {
1102 pc->exit(pci_dev);
1103 }
5851e08c 1104
3936161f 1105 pci_device_deassert_intx(pci_dev);
925fe64a 1106 do_pci_unregister_device(pci_dev);
5851e08c
AL		 1107}
1108
e824b2cc
AK		 1109void pci_register_bar(PCIDevice *pci_dev, int region_num,
1110 uint8_t type, MemoryRegion *memory)
69b91039
FB		 1111{
1112 PCIIORegion *r;
5178ecd8 1113 uint32_t addr; /* offset in pci config space */
5a9ff381 1114 uint64_t wmask;
cfc0be25 1115 pcibus_t size = memory_region_size(memory);
a4c20c6a 1116
2bbb9c2f
IY		 1117 assert(region_num >= 0);
1118 assert(region_num < PCI_NUM_REGIONS);
a4c20c6a 1119 if (size & (size-1)) {
0151abe4
AF		 1120 error_report("ERROR: PCI region size must be pow2 "
1121 "type=0x%x, size=0x%"FMT_PCIBUS"", type, size);
a4c20c6a
AL		 1122 exit(1);
1123 }
1124
69b91039 1125 r = &pci_dev->io_regions[region_num];
182f9c8a 1126 r->addr = PCI_BAR_UNMAPPED;
69b91039
FB		 1127 r->size = size;
1128 r->type = type;
5178ecd8
C		 1129 r->memory = memory;
1130 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO
fd56e061
DG		 1131 ? pci_get_bus(pci_dev)->address_space_io
1132 : pci_get_bus(pci_dev)->address_space_mem;
b7ee1603
MT		 1133
1134 wmask = ~(size - 1);
d7ce493a 1135 if (region_num == PCI_ROM_SLOT) {
ebabb67a 1136 /* ROM enable bit is writable */
5330de09 1137 wmask |= PCI_ROM_ADDRESS_ENABLE;
d7ce493a 1138 }
5178ecd8
C		 1139
1140 addr = pci_bar(pci_dev, region_num);
b0ff8eb2 1141 pci_set_long(pci_dev->config + addr, type);
5178ecd8 1142
14421258
IY		 1143 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
1144 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1145 pci_set_quad(pci_dev->wmask + addr, wmask);
1146 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
1147 } else {
1148 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
1149 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
1150 }
79ff8cb0
AK		 1151}
1152
e01fd687
AW		 1153static void pci_update_vga(PCIDevice *pci_dev)
1154{
1155 uint16_t cmd;
1156
1157 if (!pci_dev->has_vga) {
1158 return;
1159 }
1160
1161 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
1162
1163 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
1164 cmd & PCI_COMMAND_MEMORY);
1165 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
1166 cmd & PCI_COMMAND_IO);
1167 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
1168 cmd & PCI_COMMAND_IO);
1169}
1170
1171void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
1172 MemoryRegion *io_lo, MemoryRegion *io_hi)
1173{
fd56e061
DG		 1174 PCIBus *bus = pci_get_bus(pci_dev);
1175
e01fd687
AW		 1176 assert(!pci_dev->has_vga);
1177
1178 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
1179 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
fd56e061 1180 memory_region_add_subregion_overlap(bus->address_space_mem,
e01fd687
AW		 1181 QEMU_PCI_VGA_MEM_BASE, mem, 1);
1182
1183 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
1184 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
fd56e061 1185 memory_region_add_subregion_overlap(bus->address_space_io,
e01fd687
AW		 1186 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
1187
1188 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
1189 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
fd56e061 1190 memory_region_add_subregion_overlap(bus->address_space_io,
e01fd687
AW		 1191 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
1192 pci_dev->has_vga = true;
1193
1194 pci_update_vga(pci_dev);
1195}
1196
1197void pci_unregister_vga(PCIDevice *pci_dev)
1198{
fd56e061
DG		 1199 PCIBus *bus = pci_get_bus(pci_dev);
1200
e01fd687
AW		 1201 if (!pci_dev->has_vga) {
1202 return;
1203 }
1204
fd56e061 1205 memory_region_del_subregion(bus->address_space_mem,
e01fd687 1206 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
fd56e061 1207 memory_region_del_subregion(bus->address_space_io,
e01fd687 1208 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
fd56e061 1209 memory_region_del_subregion(bus->address_space_io,
e01fd687
AW		 1210 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1211 pci_dev->has_vga = false;
1212}
1213
16a96f28
AK		 1214pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1215{
1216 return pci_dev->io_regions[region_num].addr;
1217}
1218
876a350d
MT		 1219static pcibus_t pci_bar_address(PCIDevice *d,
1220 int reg, uint8_t type, pcibus_t size)
1221{
1222 pcibus_t new_addr, last_addr;
1223 int bar = pci_bar(d, reg);
1224 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
e4024630
LV		 1225 Object *machine = qdev_get_machine();
1226 ObjectClass *oc = object_get_class(machine);
1227 MachineClass *mc = MACHINE_CLASS(oc);
1228 bool allow_0_address = mc->pci_allow_0_address;
876a350d
MT		 1229
1230 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1231 if (!(cmd & PCI_COMMAND_IO)) {
1232 return PCI_BAR_UNMAPPED;
1233 }
1234 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1235 last_addr = new_addr + size - 1;
9f1a029a
HP		 1236 /* Check if 32 bit BAR wraps around explicitly.
1237 * TODO: make priorities correct and remove this work around.
1238 */
e4024630
LV		 1239 if (last_addr <= new_addr || last_addr >= UINT32_MAX ||
1240 (!allow_0_address && new_addr == 0)) {
876a350d
MT		 1241 return PCI_BAR_UNMAPPED;
1242 }
1243 return new_addr;
1244 }
1245
1246 if (!(cmd & PCI_COMMAND_MEMORY)) {
1247 return PCI_BAR_UNMAPPED;
1248 }
1249 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1250 new_addr = pci_get_quad(d->config + bar);
1251 } else {
1252 new_addr = pci_get_long(d->config + bar);
1253 }
1254 /* the ROM slot has a specific enable bit */
1255 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1256 return PCI_BAR_UNMAPPED;
1257 }
1258 new_addr &= ~(size - 1);
1259 last_addr = new_addr + size - 1;
1260 /* NOTE: we do not support wrapping */
1261 /* XXX: as we cannot support really dynamic
1262 mappings, we handle specific values as invalid
1263 mappings. */
e4024630
LV		 1264 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED ||
1265 (!allow_0_address && new_addr == 0)) {
876a350d
MT		 1266 return PCI_BAR_UNMAPPED;
1267 }
1268
1269 /* Now pcibus_t is 64bit.
1270 * Check if 32 bit BAR wraps around explicitly.
1271 * Without this, PC ide doesn't work well.
1272 * TODO: remove this work around.
1273 */
1274 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1275 return PCI_BAR_UNMAPPED;
1276 }
1277
1278 /*
1279 * OS is allowed to set BAR beyond its addressable
1280 * bits. For example, 32 bit OS can set 64bit bar
1281 * to >4G. Check it. TODO: we might need to support
1282 * it in the future for e.g. PAE.
1283 */
a8170e5e 1284 if (last_addr >= HWADDR_MAX) {
876a350d
MT		 1285 return PCI_BAR_UNMAPPED;
1286 }
1287
1288 return new_addr;
1289}
1290
0ac32c83
FB		 1291static void pci_update_mappings(PCIDevice *d)
1292{
1293 PCIIORegion *r;
876a350d 1294 int i;
7df32ca0 1295 pcibus_t new_addr;
3b46e624 1296
8a8696a3 1297 for(i = 0; i < PCI_NUM_REGIONS; i++) {
0ac32c83 1298 r = &d->io_regions[i];
a9688570
IY		 1299
1300 /* this region isn't registered */
ec503442 1301 if (!r->size)
a9688570
IY		 1302 continue;
1303
876a350d 1304 new_addr = pci_bar_address(d, i, r->type, r->size);
a9688570
IY		 1305
1306 /* This bar isn't changed */
7df32ca0 1307 if (new_addr == r->addr)
a9688570
IY		 1308 continue;
1309
1310 /* now do the real mapping */
1311 if (r->addr != PCI_BAR_UNMAPPED) {
fd56e061 1312 trace_pci_update_mappings_del(d, pci_dev_bus_num(d),
7828d750 1313 PCI_SLOT(d->devfn),
0f288f85 1314 PCI_FUNC(d->devfn),
7828d750 1315 i, r->addr, r->size);
03952339 1316 memory_region_del_subregion(r->address_space, r->memory);
0ac32c83 1317 }
a9688570
IY		 1318 r->addr = new_addr;
1319 if (r->addr != PCI_BAR_UNMAPPED) {
fd56e061 1320 trace_pci_update_mappings_add(d, pci_dev_bus_num(d),
7828d750 1321 PCI_SLOT(d->devfn),
0f288f85 1322 PCI_FUNC(d->devfn),
7828d750 1323 i, r->addr, r->size);
8b881e77
AK		 1324 memory_region_add_subregion_overlap(r->address_space,
1325 r->addr, r->memory, 1);
a9688570 1326 }
0ac32c83 1327 }
e01fd687
AW		 1328
1329 pci_update_vga(d);
0ac32c83
FB		 1330}
1331
a7b15a5c
MT		 1332static inline int pci_irq_disabled(PCIDevice *d)
1333{
1334 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1335}
1336
1337/* Called after interrupt disabled field update in config space,
1338 * assert/deassert interrupts if necessary.
1339 * Gets original interrupt disable bit value (before update). */
1340static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1341{
1342 int i, disabled = pci_irq_disabled(d);
1343 if (disabled == was_irq_disabled)
1344 return;
1345 for (i = 0; i < PCI_NUM_PINS; ++i) {
1346 int state = pci_irq_state(d, i);
1347 pci_change_irq_level(d, i, disabled ? -state : state);
1348 }
1349}
1350
5fafdf24 1351uint32_t pci_default_read_config(PCIDevice *d,
0ac32c83 1352 uint32_t address, int len)
69b91039 1353{
5029fe12 1354 uint32_t val = 0;
42e4126b 1355
5029fe12
IY		 1356 memcpy(&val, d->config + address, len);
1357 return le32_to_cpu(val);
0ac32c83
FB		 1358}
1359
d7efb7e0 1360void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
0ac32c83 1361{
a7b15a5c 1362 int i, was_irq_disabled = pci_irq_disabled(d);
d7efb7e0 1363 uint32_t val = val_in;
0ac32c83 1364
42e4126b 1365 for (i = 0; i < l; val >>= 8, ++i) {
91011d4f 1366 uint8_t wmask = d->wmask[addr + i];
92ba5f51
IY		 1367 uint8_t w1cmask = d->w1cmask[addr + i];
1368 assert(!(wmask & w1cmask));
91011d4f 1369 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
92ba5f51 1370 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
0ac32c83 1371 }
260c0cd3 1372 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
edb00035
IY		 1373 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1374 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
260c0cd3 1375 range_covers_byte(addr, l, PCI_COMMAND))
0ac32c83 1376 pci_update_mappings(d);
a7b15a5c 1377
1c380f94 1378 if (range_covers_byte(addr, l, PCI_COMMAND)) {
a7b15a5c 1379 pci_update_irq_disabled(d, was_irq_disabled);
1c380f94
AK		 1380 memory_region_set_enabled(&d->bus_master_enable_region,
1381 pci_get_word(d->config + PCI_COMMAND)
1382 & PCI_COMMAND_MASTER);
1383 }
95d65800 1384
d7efb7e0
KO		 1385 msi_write_config(d, addr, val_in, l);
1386 msix_write_config(d, addr, val_in, l);
69b91039
FB		 1387}
1388
502a5395
PB		 1389/***********************************************************/
1390/* generic PCI irq support */
30468f78 1391
502a5395 1392/* 0 <= irq_num <= 3. level must be 0 or 1 */
d98f08f5 1393static void pci_irq_handler(void *opaque, int irq_num, int level)
69b91039 1394{
a60380a5 1395 PCIDevice *pci_dev = opaque;
80b3ada7 1396 int change;
3b46e624 1397
d036bb21 1398 change = level - pci_irq_state(pci_dev, irq_num);
80b3ada7
PB		 1399 if (!change)
1400 return;
d2b59317 1401
d036bb21 1402 pci_set_irq_state(pci_dev, irq_num, level);
f9bf77dd 1403 pci_update_irq_status(pci_dev);
a7b15a5c
MT		 1404 if (pci_irq_disabled(pci_dev))
1405 return;
d036bb21 1406 pci_change_irq_level(pci_dev, irq_num, change);
69b91039
FB		 1407}
1408
d98f08f5
MA		 1409static inline int pci_intx(PCIDevice *pci_dev)
1410{
1411 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1412}
1413
1414qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1415{
1416 int intx = pci_intx(pci_dev);
1417
1418 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1419}
1420
1421void pci_set_irq(PCIDevice *pci_dev, int level)
1422{
1423 int intx = pci_intx(pci_dev);
1424 pci_irq_handler(pci_dev, intx, level);
1425}
1426
3afa9bb4
MT		 1427/* Special hooks used by device assignment */
1428void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1429{
0889464a 1430 assert(pci_bus_is_root(bus));
3afa9bb4
MT		 1431 bus->route_intx_to_irq = route_intx_to_irq;
1432}
1433
1434PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1435{
1436 PCIBus *bus;
1437
1438 do {
fd56e061
DG		 1439 bus = pci_get_bus(dev);
1440 pin = bus->map_irq(dev, pin);
1441 dev = bus->parent_dev;
3afa9bb4 1442 } while (dev);
05c0621e
AW		 1443
1444 if (!bus->route_intx_to_irq) {
312fd5f2 1445 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
05c0621e
AW		 1446 object_get_typename(OBJECT(bus->qbus.parent)));
1447 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1448 }
1449
3afa9bb4 1450 return bus->route_intx_to_irq(bus->irq_opaque, pin);
0ae16251
JK		 1451}
1452
d6e65d54
AW		 1453bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1454{
1455 return old->mode != new->mode || old->irq != new->irq;
1456}
1457
0ae16251
JK		 1458void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1459{
1460 PCIDevice *dev;
1461 PCIBus *sec;
1462 int i;
1463
1464 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1465 dev = bus->devices[i];
1466 if (dev && dev->intx_routing_notifier) {
1467 dev->intx_routing_notifier(dev);
1468 }
e5368f0d
AW		 1469 }
1470
1471 QLIST_FOREACH(sec, &bus->child, sibling) {
1472 pci_bus_fire_intx_routing_notifier(sec);
0ae16251
JK		 1473 }
1474}
1475
1476void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1477 PCIINTxRoutingNotifier notifier)
1478{
1479 dev->intx_routing_notifier = notifier;
69b91039
FB		 1480}
1481
91e56159
IY		 1482/*
1483 * PCI-to-PCI bridge specification
1484 * 9.1: Interrupt routing. Table 9-1
1485 *
1486 * the PCI Express Base Specification, Revision 2.1
1487 * 2.2.8.1: INTx interrutp signaling - Rules
1488 * the Implementation Note
1489 * Table 2-20
1490 */
1491/*
1492 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1493 * 0-origin unlike PCI interrupt pin register.
1494 */
1495int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1496{
1497 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
1498}
1499
502a5395
PB		 1500/***********************************************************/
1501/* monitor info on PCI */
0ac32c83 1502
6650ee6d
PB		 1503typedef struct {
1504 uint16_t class;
1505 const char *desc;
5e0259e7
GN		 1506 const char *fw_name;
1507 uint16_t fw_ign_bits;
6650ee6d
PB		 1508} pci_class_desc;
1509
09bc878a 1510static const pci_class_desc pci_class_descriptions[] =
6650ee6d 1511{
5e0259e7
GN		 1512 { 0x0001, "VGA controller", "display"},
1513 { 0x0100, "SCSI controller", "scsi"},
1514 { 0x0101, "IDE controller", "ide"},
1515 { 0x0102, "Floppy controller", "fdc"},
1516 { 0x0103, "IPI controller", "ipi"},
1517 { 0x0104, "RAID controller", "raid"},
dcb5b19a
TS		 1518 { 0x0106, "SATA controller"},
1519 { 0x0107, "SAS controller"},
1520 { 0x0180, "Storage controller"},
5e0259e7
GN		 1521 { 0x0200, "Ethernet controller", "ethernet"},
1522 { 0x0201, "Token Ring controller", "token-ring"},
1523 { 0x0202, "FDDI controller", "fddi"},
1524 { 0x0203, "ATM controller", "atm"},
dcb5b19a 1525 { 0x0280, "Network controller"},
5e0259e7 1526 { 0x0300, "VGA controller", "display", 0x00ff},
dcb5b19a
TS		 1527 { 0x0301, "XGA controller"},
1528 { 0x0302, "3D controller"},
1529 { 0x0380, "Display controller"},
5e0259e7
GN		 1530 { 0x0400, "Video controller", "video"},
1531 { 0x0401, "Audio controller", "sound"},
dcb5b19a 1532 { 0x0402, "Phone"},
602ef4d9 1533 { 0x0403, "Audio controller", "sound"},
dcb5b19a 1534 { 0x0480, "Multimedia controller"},
5e0259e7
GN		 1535 { 0x0500, "RAM controller", "memory"},
1536 { 0x0501, "Flash controller", "flash"},
dcb5b19a 1537 { 0x0580, "Memory controller"},
5e0259e7
GN		 1538 { 0x0600, "Host bridge", "host"},
1539 { 0x0601, "ISA bridge", "isa"},
1540 { 0x0602, "EISA bridge", "eisa"},
1541 { 0x0603, "MC bridge", "mca"},
4c41425d 1542 { 0x0604, "PCI bridge", "pci-bridge"},
5e0259e7
GN		 1543 { 0x0605, "PCMCIA bridge", "pcmcia"},
1544 { 0x0606, "NUBUS bridge", "nubus"},
1545 { 0x0607, "CARDBUS bridge", "cardbus"},
dcb5b19a
TS		 1546 { 0x0608, "RACEWAY bridge"},
1547 { 0x0680, "Bridge"},
5e0259e7
GN		 1548 { 0x0700, "Serial port", "serial"},
1549 { 0x0701, "Parallel port", "parallel"},
1550 { 0x0800, "Interrupt controller", "interrupt-controller"},
1551 { 0x0801, "DMA controller", "dma-controller"},
1552 { 0x0802, "Timer", "timer"},
1553 { 0x0803, "RTC", "rtc"},
1554 { 0x0900, "Keyboard", "keyboard"},
1555 { 0x0901, "Pen", "pen"},
1556 { 0x0902, "Mouse", "mouse"},
1557 { 0x0A00, "Dock station", "dock", 0x00ff},
1558 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1559 { 0x0c00, "Fireware contorller", "fireware"},
1560 { 0x0c01, "Access bus controller", "access-bus"},
1561 { 0x0c02, "SSA controller", "ssa"},
1562 { 0x0c03, "USB controller", "usb"},
1563 { 0x0c04, "Fibre channel controller", "fibre-channel"},
f7748569 1564 { 0x0c05, "SMBus"},
6650ee6d
PB		 1565 { 0, NULL}
1566};
1567
a8eeafda
GK		 1568static void pci_for_each_device_under_bus_reverse(PCIBus *bus,
1569 void (*fn)(PCIBus *b,
1570 PCIDevice *d,
1571 void *opaque),
1572 void *opaque)
1573{
1574 PCIDevice *d;
1575 int devfn;
1576
1577 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1578 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn];
1579 if (d) {
1580 fn(bus, d, opaque);
1581 }
1582 }
1583}
1584
1585void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
1586 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1587 void *opaque)
1588{
1589 bus = pci_find_bus_nr(bus, bus_num);
1590
1591 if (bus) {
1592 pci_for_each_device_under_bus_reverse(bus, fn, opaque);
1593 }
1594}
1595
163c8a59 1596static void pci_for_each_device_under_bus(PCIBus *bus,
7aa8cbb9
AP		 1597 void (*fn)(PCIBus *b, PCIDevice *d,
1598 void *opaque),
1599 void *opaque)
30468f78 1600{
163c8a59
LC		 1601 PCIDevice *d;
1602 int devfn;
30468f78 1603
163c8a59
LC		 1604 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1605 d = bus->devices[devfn];
1606 if (d) {
7aa8cbb9 1607 fn(bus, d, opaque);
163c8a59
LC		 1608 }
1609 }
1610}
1611
1612void pci_for_each_device(PCIBus *bus, int bus_num,
7aa8cbb9
AP		 1613 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1614 void *opaque)
163c8a59 1615{
d662210a 1616 bus = pci_find_bus_nr(bus, bus_num);
163c8a59
LC		 1617
1618 if (bus) {
7aa8cbb9 1619 pci_for_each_device_under_bus(bus, fn, opaque);
163c8a59
LC		 1620 }
1621}
1622
79627472 1623static const pci_class_desc *get_class_desc(int class)
163c8a59 1624{
79627472 1625 const pci_class_desc *desc;
163c8a59 1626
79627472
LC		 1627 desc = pci_class_descriptions;
1628 while (desc->desc && class != desc->class) {
1629 desc++;
30468f78 1630 }
b4dccd8d 1631
79627472
LC		 1632 return desc;
1633}
14421258 1634
79627472 1635static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
163c8a59 1636
79627472
LC		 1637static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1638{
1639 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1640 int i;
163c8a59 1641
79627472
LC		 1642 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1643 const PCIIORegion *r = &dev->io_regions[i];
1644 PciMemoryRegionList *region;
1645
1646 if (!r->size) {
1647 continue;
502a5395 1648 }
163c8a59 1649
79627472
LC		 1650 region = g_malloc0(sizeof(*region));
1651 region->value = g_malloc0(sizeof(*region->value));
163c8a59 1652
79627472
LC		 1653 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1654 region->value->type = g_strdup("io");
1655 } else {
1656 region->value->type = g_strdup("memory");
1657 region->value->has_prefetch = true;
1658 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1659 region->value->has_mem_type_64 = true;
1660 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
d5e4acf7 1661 }
163c8a59 1662
79627472
LC		 1663 region->value->bar = i;
1664 region->value->address = r->addr;
1665 region->value->size = r->size;
163c8a59 1666
79627472
LC		 1667 /* XXX: waiting for the qapi to support GSList */
1668 if (!cur_item) {
1669 head = cur_item = region;
1670 } else {
1671 cur_item->next = region;
1672 cur_item = region;
163c8a59 1673 }
80b3ada7 1674 }
384d8876 1675
79627472 1676 return head;
163c8a59
LC		 1677}
1678
79627472
LC		 1679static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1680 int bus_num)
163c8a59 1681{
79627472 1682 PciBridgeInfo *info;
9fa02cd1 1683 PciMemoryRange *range;
163c8a59 1684
9fa02cd1 1685 info = g_new0(PciBridgeInfo, 1);
163c8a59 1686
9fa02cd1
EB		 1687 info->bus = g_new0(PciBusInfo, 1);
1688 info->bus->number = dev->config[PCI_PRIMARY_BUS];
1689 info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
1690 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
163c8a59 1691
9fa02cd1
EB		 1692 range = info->bus->io_range = g_new0(PciMemoryRange, 1);
1693 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1694 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
163c8a59 1695
9fa02cd1
EB		 1696 range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
1697 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1698 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
163c8a59 1699
9fa02cd1
EB		 1700 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
1701 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1702 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
163c8a59 1703
79627472 1704 if (dev->config[PCI_SECONDARY_BUS] != 0) {
d662210a 1705 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
79627472
LC		 1706 if (child_bus) {
1707 info->has_devices = true;
1708 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1709 }
163c8a59
LC		 1710 }
1711
79627472 1712 return info;
163c8a59
LC		 1713}
1714
79627472
LC		 1715static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1716 int bus_num)
163c8a59 1717{
79627472
LC		 1718 const pci_class_desc *desc;
1719 PciDeviceInfo *info;
b5937f29 1720 uint8_t type;
79627472 1721 int class;
163c8a59 1722
9fa02cd1 1723 info = g_new0(PciDeviceInfo, 1);
79627472
LC		 1724 info->bus = bus_num;
1725 info->slot = PCI_SLOT(dev->devfn);
1726 info->function = PCI_FUNC(dev->devfn);
1727
9fa02cd1 1728 info->class_info = g_new0(PciDeviceClass, 1);
79627472 1729 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
9fa02cd1 1730 info->class_info->q_class = class;
79627472
LC		 1731 desc = get_class_desc(class);
1732 if (desc->desc) {
9fa02cd1
EB		 1733 info->class_info->has_desc = true;
1734 info->class_info->desc = g_strdup(desc->desc);
79627472
LC		 1735 }
1736
9fa02cd1
EB		 1737 info->id = g_new0(PciDeviceId, 1);
1738 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1739 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
79627472
LC		 1740 info->regions = qmp_query_pci_regions(dev);
1741 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
163c8a59
LC		 1742
1743 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
79627472
LC		 1744 info->has_irq = true;
1745 info->irq = dev->config[PCI_INTERRUPT_LINE];
163c8a59
LC		 1746 }
1747
b5937f29
IY		 1748 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1749 if (type == PCI_HEADER_TYPE_BRIDGE) {
79627472
LC		 1750 info->has_pci_bridge = true;
1751 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
163c8a59
LC		 1752 }
1753
79627472 1754 return info;
163c8a59
LC		 1755}
1756
79627472 1757static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
384d8876 1758{
79627472 1759 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
163c8a59 1760 PCIDevice *dev;
79627472 1761 int devfn;
163c8a59
LC		 1762
1763 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1764 dev = bus->devices[devfn];
1765 if (dev) {
79627472
LC		 1766 info = g_malloc0(sizeof(*info));
1767 info->value = qmp_query_pci_device(dev, bus, bus_num);
1768
1769 /* XXX: waiting for the qapi to support GSList */
1770 if (!cur_item) {
1771 head = cur_item = info;
1772 } else {
1773 cur_item->next = info;
1774 cur_item = info;
1775 }
163c8a59 1776 }
1074df4f 1777 }
163c8a59 1778
79627472 1779 return head;
1074df4f
IY		 1780}
1781
79627472 1782static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1074df4f 1783{
79627472
LC		 1784 PciInfo *info = NULL;
1785
d662210a 1786 bus = pci_find_bus_nr(bus, bus_num);
502a5395 1787 if (bus) {
79627472
LC		 1788 info = g_malloc0(sizeof(*info));
1789 info->bus = bus_num;
1790 info->devices = qmp_query_pci_devices(bus, bus_num);
f2aa58c6 1791 }
163c8a59 1792
79627472 1793 return info;
f2aa58c6
FB		 1794}
1795
79627472 1796PciInfoList *qmp_query_pci(Error **errp)
f2aa58c6 1797{
79627472 1798 PciInfoList *info, *head = NULL, *cur_item = NULL;
7588e2b0 1799 PCIHostState *host_bridge;
163c8a59 1800
7588e2b0 1801 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
79627472 1802 info = g_malloc0(sizeof(*info));
cb2ed8b3
MA		 1803 info->value = qmp_query_pci_bus(host_bridge->bus,
1804 pci_bus_num(host_bridge->bus));
79627472
LC		 1805
1806 /* XXX: waiting for the qapi to support GSList */
1807 if (!cur_item) {
1808 head = cur_item = info;
1809 } else {
1810 cur_item->next = info;
1811 cur_item = info;
163c8a59 1812 }
e822a52a 1813 }
163c8a59 1814
79627472 1815 return head;
77d4bc34 1816}
a41b2ff2
PB		 1817
1818/* Initialize a PCI NIC. */
51f7cb97 1819PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
6dbcb819 1820 const char *default_model,
51f7cb97 1821 const char *default_devaddr)
a41b2ff2 1822{
5607c388 1823 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
52310c3f
PB		 1824 GSList *list;
1825 GPtrArray *pci_nic_models;
07caea31 1826 PCIBus *bus;
5607c388 1827 PCIDevice *pci_dev;
9d07d757 1828 DeviceState *dev;
51f7cb97 1829 int devfn;
cb457d76
AL		 1830 int i;
1831
52310c3f
PB		 1832 if (nd->model && !strcmp(nd->model, "virtio")) {
1833 g_free(nd->model);
1834 nd->model = g_strdup("virtio-net-pci");
1835 }
1836
1837 list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false);
1838 pci_nic_models = g_ptr_array_new();
1839 while (list) {
1840 DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data,
1841 TYPE_DEVICE);
1842 GSList *next;
1843 if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) &&
1844 dc->user_creatable) {
1845 const char *name = object_class_get_name(list->data);
1846 g_ptr_array_add(pci_nic_models, (gpointer)name);
1847 }
1848 next = list->next;
1849 g_slist_free_1(list);
1850 list = next;
1851 }
1852 g_ptr_array_add(pci_nic_models, NULL);
1853
1854 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) {
51f7cb97
TH		 1855 exit(0);
1856 }
1857
52310c3f
PB		 1858 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata,
1859 default_model);
51f7cb97
TH		 1860 if (i < 0) {
1861 exit(1);
1862 }
07caea31 1863
29b358f9 1864 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
07caea31 1865 if (!bus) {
1ecda02b 1866 error_report("Invalid PCI device address %s for device %s",
52310c3f 1867 devaddr, nd->model);
51f7cb97 1868 exit(1);
07caea31
MA		 1869 }
1870
52310c3f 1871 pci_dev = pci_create(bus, devfn, nd->model);
9ee05825 1872 dev = &pci_dev->qdev;
1cc33683 1873 qdev_set_nic_properties(dev, nd);
a023b7ac 1874 qdev_init_nofail(dev);
52310c3f 1875 g_ptr_array_free(pci_nic_models, true);
51f7cb97 1876 return pci_dev;
07caea31
MA		 1877}
1878
129d42fb
AJ		 1879PCIDevice *pci_vga_init(PCIBus *bus)
1880{
1881 switch (vga_interface_type) {
1882 case VGA_CIRRUS:
1883 return pci_create_simple(bus, -1, "cirrus-vga");
1884 case VGA_QXL:
1885 return pci_create_simple(bus, -1, "qxl-vga");
1886 case VGA_STD:
1887 return pci_create_simple(bus, -1, "VGA");
1888 case VGA_VMWARE:
1889 return pci_create_simple(bus, -1, "vmware-svga");
a94f0c5c
GH		 1890 case VGA_VIRTIO:
1891 return pci_create_simple(bus, -1, "virtio-vga");
129d42fb
AJ		 1892 case VGA_NONE:
1893 default: /* Other non-PCI types. Checking for unsupported types is already
1894 done in vl.c. */
1895 return NULL;
1896 }
1897}
1898
929176c3
MT		 1899/* Whether a given bus number is in range of the secondary
1900 * bus of the given bridge device. */
1901static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1902{
1903 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1904 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
09e5b819 1905 dev->config[PCI_SECONDARY_BUS] <= bus_num &&
929176c3
MT		 1906 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1907}
1908
09e5b819
MA		 1909/* Whether a given bus number is in a range of a root bus */
1910static bool pci_root_bus_in_range(PCIBus *bus, int bus_num)
1911{
1912 int i;
1913
1914 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1915 PCIDevice *dev = bus->devices[i];
1916
1917 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) {
1918 if (pci_secondary_bus_in_range(dev, bus_num)) {
1919 return true;
1920 }
1921 }
1922 }
1923
1924 return false;
1925}
1926
d662210a 1927static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
3ae80618 1928{
470e6363 1929 PCIBus *sec;
3ae80618 1930
470e6363 1931 if (!bus) {
e822a52a 1932 return NULL;
470e6363 1933 }
3ae80618 1934
e822a52a
IY		 1935 if (pci_bus_num(bus) == bus_num) {
1936 return bus;
1937 }
1938
929176c3 1939 /* Consider all bus numbers in range for the host pci bridge. */
0889464a 1940 if (!pci_bus_is_root(bus) &&
929176c3
MT		 1941 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1942 return NULL;
1943 }
1944
e822a52a 1945 /* try child bus */
929176c3
MT		 1946 for (; bus; bus = sec) {
1947 QLIST_FOREACH(sec, &bus->child, sibling) {
09e5b819 1948 if (pci_bus_num(sec) == bus_num) {
929176c3
MT		 1949 return sec;
1950 }
09e5b819
MA		 1951 /* PXB buses assumed to be children of bus 0 */
1952 if (pci_bus_is_root(sec)) {
1953 if (pci_root_bus_in_range(sec, bus_num)) {
1954 break;
1955 }
1956 } else {
1957 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1958 break;
1959 }
c021f8e6 1960 }
e822a52a
IY		 1961 }
1962 }
1963
1964 return NULL;
3ae80618
AL		 1965}
1966
eb0acfdd
MT		 1967void pci_for_each_bus_depth_first(PCIBus *bus,
1968 void *(*begin)(PCIBus *bus, void *parent_state),
1969 void (*end)(PCIBus *bus, void *state),
1970 void *parent_state)
1971{
1972 PCIBus *sec;
1973 void *state;
1974
1975 if (!bus) {
1976 return;
1977 }
1978
1979 if (begin) {
1980 state = begin(bus, parent_state);
1981 } else {
1982 state = parent_state;
1983 }
1984
1985 QLIST_FOREACH(sec, &bus->child, sibling) {
1986 pci_for_each_bus_depth_first(sec, begin, end, state);
1987 }
1988
1989 if (end) {
1990 end(bus, state);
1991 }
1992}
1993
1994
5256d8bf 1995PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
3ae80618 1996{
d662210a 1997 bus = pci_find_bus_nr(bus, bus_num);
3ae80618
AL		 1998
1999 if (!bus)
2000 return NULL;
2001
5256d8bf 2002 return bus->devices[devfn];
3ae80618
AL		 2003}
2004
133e9b22 2005static void pci_qdev_realize(DeviceState *qdev, Error **errp)
6b1b92d3
PB		 2006{
2007 PCIDevice *pci_dev = (PCIDevice *)qdev;
40021f08 2008 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
d61a363d 2009 ObjectClass *klass = OBJECT_CLASS(pc);
133e9b22 2010 Error *local_err = NULL;
ab85ceb1 2011 bool is_default_rom;
6b1b92d3 2012
d61a363d
YB		 2013 /* initialize cap_present for pci_is_express() and pci_config_size(),
2014 * Note that hybrid PCIs are not set automatically and need to manage
2015 * QEMU_PCI_CAP_EXPRESS manually */
2016 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) &&
2017 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) {
a9f49946
IY		 2018 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2019 }
2020
fd56e061 2021 pci_dev = do_pci_register_device(pci_dev,
6e008585 2022 object_get_typename(OBJECT(qdev)),
133e9b22 2023 pci_dev->devfn, errp);
09e3acc6 2024 if (pci_dev == NULL)
133e9b22 2025 return;
2897ae02 2026
7ee6c1e1
MA		 2027 if (pc->realize) {
2028 pc->realize(pci_dev, &local_err);
2029 if (local_err) {
2030 error_propagate(errp, local_err);
c2afc922 2031 do_pci_unregister_device(pci_dev);
133e9b22 2032 return;
c2afc922 2033 }
925fe64a 2034 }
8c52c8f3
GH		 2035
2036 /* rom loading */
ab85ceb1 2037 is_default_rom = false;
40021f08
AL		 2038 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
2039 pci_dev->romfile = g_strdup(pc->romfile);
ab85ceb1
SW		 2040 is_default_rom = true;
2041 }
178e785f 2042
133e9b22
MA		 2043 pci_add_option_rom(pci_dev, is_default_rom, &local_err);
2044 if (local_err) {
2045 error_propagate(errp, local_err);
2046 pci_qdev_unrealize(DEVICE(pci_dev), NULL);
2047 return;
178e785f 2048 }
ee995ffb
GH		 2049}
2050
49823868
IY		 2051PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
2052 const char *name)
6b1b92d3
PB		 2053{
2054 DeviceState *dev;
2055
02e2da45 2056 dev = qdev_create(&bus->qbus, name);
09f1bbcd 2057 qdev_prop_set_int32(dev, "addr", devfn);
49823868 2058 qdev_prop_set_bit(dev, "multifunction", multifunction);
40021f08 2059 return PCI_DEVICE(dev);
71077c1c 2060}
6b1b92d3 2061
49823868
IY		 2062PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
2063 bool multifunction,
2064 const char *name)
71077c1c 2065{
49823868 2066 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
e23a1b33 2067 qdev_init_nofail(&dev->qdev);
71077c1c 2068 return dev;
6b1b92d3 2069}
6f4cbd39 2070
49823868
IY		 2071PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
2072{
2073 return pci_create_multifunction(bus, devfn, false, name);
2074}
2075
2076PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
2077{
2078 return pci_create_simple_multifunction(bus, devfn, false, name);
2079}
2080
b56d701f 2081static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
6f4cbd39
MT		 2082{
2083 int offset = PCI_CONFIG_HEADER_SIZE;
2084 int i;
b56d701f 2085 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
6f4cbd39
MT		 2086 if (pdev->used[i])
2087 offset = i + 1;
2088 else if (i - offset + 1 == size)
2089 return offset;
b56d701f 2090 }
6f4cbd39
MT		 2091 return 0;
2092}
2093
2094static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
2095 uint8_t *prev_p)
2096{
2097 uint8_t next, prev;
2098
2099 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
2100 return 0;
2101
2102 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2103 prev = next + PCI_CAP_LIST_NEXT)
2104 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
2105 break;
2106
2107 if (prev_p)
2108 *prev_p = prev;
2109 return next;
2110}
2111
c9abe111
JK		 2112static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
2113{
2114 uint8_t next, prev, found = 0;
2115
2116 if (!(pdev->used[offset])) {
2117 return 0;
2118 }
2119
2120 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
2121
2122 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2123 prev = next + PCI_CAP_LIST_NEXT) {
2124 if (next <= offset && next > found) {
2125 found = next;
2126 }
2127 }
2128 return found;
2129}
2130
ab85ceb1
SW		 2131/* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2132 This is needed for an option rom which is used for more than one device. */
2133static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
2134{
2135 uint16_t vendor_id;
2136 uint16_t device_id;
2137 uint16_t rom_vendor_id;
2138 uint16_t rom_device_id;
2139 uint16_t rom_magic;
2140 uint16_t pcir_offset;
2141 uint8_t checksum;
2142
2143 /* Words in rom data are little endian (like in PCI configuration),
2144 so they can be read / written with pci_get_word / pci_set_word. */
2145
2146 /* Only a valid rom will be patched. */
2147 rom_magic = pci_get_word(ptr);
2148 if (rom_magic != 0xaa55) {
2149 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
2150 return;
2151 }
2152 pcir_offset = pci_get_word(ptr + 0x18);
2153 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
2154 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
2155 return;
2156 }
2157
2158 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
2159 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
2160 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
2161 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
2162
2163 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
2164 vendor_id, device_id, rom_vendor_id, rom_device_id);
2165
2166 checksum = ptr[6];
2167
2168 if (vendor_id != rom_vendor_id) {
2169 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2170 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
2171 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
2172 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2173 ptr[6] = checksum;
2174 pci_set_word(ptr + pcir_offset + 4, vendor_id);
2175 }
2176
2177 if (device_id != rom_device_id) {
2178 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2179 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
2180 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
2181 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2182 ptr[6] = checksum;
2183 pci_set_word(ptr + pcir_offset + 6, device_id);
2184 }
2185}
2186
c2039bd0 2187/* Add an option rom for the device */
133e9b22
MA		 2188static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
2189 Error **errp)
c2039bd0
AL		 2190{
2191 int size;
2192 char *path;
2193 void *ptr;
1724f049 2194 char name[32];
4be9f0d1 2195 const VMStateDescription *vmsd;
c2039bd0 2196
8c52c8f3 2197 if (!pdev->romfile)
133e9b22 2198 return;
8c52c8f3 2199 if (strlen(pdev->romfile) == 0)
133e9b22 2200 return;
8c52c8f3 2201
88169ddf
GH		 2202 if (!pdev->rom_bar) {
2203 /*
2204 * Load rom via fw_cfg instead of creating a rom bar,
2205 * for 0.11 compatibility.
2206 */
2207 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
db80c7b9
MA		 2208
2209 /*
2210 * Hot-plugged devices can't use the option ROM
2211 * if the rom bar is disabled.
2212 */
2213 if (DEVICE(pdev)->hotplugged) {
133e9b22
MA		 2214 error_setg(errp, "Hot-plugged device without ROM bar"
2215 " can't have an option ROM");
2216 return;
db80c7b9
MA		 2217 }
2218
88169ddf
GH		 2219 if (class == 0x0300) {
2220 rom_add_vga(pdev->romfile);
2221 } else {
2e55e842 2222 rom_add_option(pdev->romfile, -1);
88169ddf 2223 }
133e9b22 2224 return;
88169ddf
GH		 2225 }
2226
8c52c8f3 2227 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
c2039bd0 2228 if (path == NULL) {
7267c094 2229 path = g_strdup(pdev->romfile);
c2039bd0
AL		 2230 }
2231
2232 size = get_image_size(path);
8c52c8f3 2233 if (size < 0) {
133e9b22 2234 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile);
8c7f3dd0 2235 g_free(path);
133e9b22 2236 return;
8c7f3dd0 2237 } else if (size == 0) {
133e9b22 2238 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
7267c094 2239 g_free(path);
133e9b22 2240 return;
8c52c8f3 2241 }
9bff5d81 2242 size = pow2ceil(size);
c2039bd0 2243
4be9f0d1
AL		 2244 vmsd = qdev_get_vmsd(DEVICE(pdev));
2245
2246 if (vmsd) {
2247 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
2248 } else {
f79f2bfc 2249 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
4be9f0d1 2250 }
14caaf7f 2251 pdev->has_rom = true;
fefa9256 2252 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal);
14caaf7f 2253 ptr = memory_region_get_ram_ptr(&pdev->rom);
c2039bd0 2254 load_image(path, ptr);
7267c094 2255 g_free(path);
c2039bd0 2256
ab85ceb1
SW		 2257 if (is_default_rom) {
2258 /* Only the default rom images will be patched (if needed). */
2259 pci_patch_ids(pdev, ptr, size);
2260 }
2261
e824b2cc 2262 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
c2039bd0
AL		 2263}
2264
230741dc
AW		 2265static void pci_del_option_rom(PCIDevice *pdev)
2266{
14caaf7f 2267 if (!pdev->has_rom)
230741dc
AW		 2268 return;
2269
c5705a77 2270 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
14caaf7f 2271 pdev->has_rom = false;
230741dc
AW		 2272}
2273
ca77089d 2274/*
27841278 2275 * On success, pci_add_capability() returns a positive value
eacbc632
MZ		 2276 * that the offset of the pci capability.
2277 * On failure, it sets an error and returns a negative error
2278 * code.
2279 */
27841278 2280int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
cd9aa33e
LE		 2281 uint8_t offset, uint8_t size,
2282 Error **errp)
6f4cbd39 2283{
ca77089d 2284 uint8_t *config;
c9abe111
JK		 2285 int i, overlapping_cap;
2286
ca77089d
IY		 2287 if (!offset) {
2288 offset = pci_find_space(pdev, size);
97fe42f1
C		 2289 /* out of PCI config space is programming error */
2290 assert(offset);
c9abe111
JK		 2291 } else {
2292 /* Verify that capabilities don't overlap. Note: device assignment
2293 * depends on this check to verify that the device is not broken.
2294 * Should never trigger for emulated devices, but it's helpful
2295 * for debugging these. */
2296 for (i = offset; i < offset + size; i++) {
2297 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2298 if (overlapping_cap) {
cd9aa33e
LE		 2299 error_setg(errp, "%s:%02x:%02x.%x "
2300 "Attempt to add PCI capability %x at offset "
2301 "%x overlaps existing capability %x at offset %x",
fd56e061 2302 pci_root_bus_path(pdev), pci_dev_bus_num(pdev),
cd9aa33e
LE		 2303 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2304 cap_id, offset, overlapping_cap, i);
c9abe111
JK		 2305 return -EINVAL;
2306 }
2307 }
ca77089d
IY		 2308 }
2309
2310 config = pdev->config + offset;
6f4cbd39
MT		 2311 config[PCI_CAP_LIST_ID] = cap_id;
2312 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2313 pdev->config[PCI_CAPABILITY_LIST] = offset;
2314 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
e26631b7 2315 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
6f4cbd39
MT		 2316 /* Make capability read-only by default */
2317 memset(pdev->wmask + offset, 0, size);
bd4b65ee
MT		 2318 /* Check capability by default */
2319 memset(pdev->cmask + offset, 0xFF, size);
6f4cbd39
MT		 2320 return offset;
2321}
2322
2323/* Unlink capability from the pci config space. */
2324void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2325{
2326 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2327 if (!offset)
2328 return;
2329 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
ebabb67a 2330 /* Make capability writable again */
6f4cbd39 2331 memset(pdev->wmask + offset, 0xff, size);
1a4f5971 2332 memset(pdev->w1cmask + offset, 0, size);
bd4b65ee
MT		 2333 /* Clear cmask as device-specific registers can't be checked */
2334 memset(pdev->cmask + offset, 0, size);
e26631b7 2335 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
6f4cbd39
MT		 2336
2337 if (!pdev->config[PCI_CAPABILITY_LIST])
2338 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2339}
2340
6f4cbd39
MT		 2341uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2342{
2343 return pci_find_capability_list(pdev, cap_id, NULL);
2344}
10c4c98a
GH		 2345
2346static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2347{
2348 PCIDevice *d = (PCIDevice *)dev;
2349 const pci_class_desc *desc;
2350 char ctxt[64];
2351 PCIIORegion *r;
2352 int i, class;
2353
b0ff8eb2 2354 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
10c4c98a
GH		 2355 desc = pci_class_descriptions;
2356 while (desc->desc && class != desc->class)
2357 desc++;
2358 if (desc->desc) {
2359 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2360 } else {
2361 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2362 }
2363
2364 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2365 "pci id %04x:%04x (sub %04x:%04x)\n",
fd56e061 2366 indent, "", ctxt, pci_dev_bus_num(d),
e822a52a 2367 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
b0ff8eb2
IY		 2368 pci_get_word(d->config + PCI_VENDOR_ID),
2369 pci_get_word(d->config + PCI_DEVICE_ID),
2370 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2371 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
10c4c98a
GH		 2372 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2373 r = &d->io_regions[i];
2374 if (!r->size)
2375 continue;
89e8b13c
IY		 2376 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2377 " [0x%"FMT_PCIBUS"]\n",
2378 indent, "",
0392a017 2379 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
10c4c98a
GH		 2380 r->addr, r->addr + r->size - 1);
2381 }
2382}
03587182 2383
5e0259e7
GN		 2384static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2385{
2386 PCIDevice *d = (PCIDevice *)dev;
2387 const char *name = NULL;
2388 const pci_class_desc *desc = pci_class_descriptions;
2389 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2390
2391 while (desc->desc &&
2392 (class & ~desc->fw_ign_bits) !=
2393 (desc->class & ~desc->fw_ign_bits)) {
2394 desc++;
2395 }
2396
2397 if (desc->desc) {
2398 name = desc->fw_name;
2399 }
2400
2401 if (name) {
2402 pstrcpy(buf, len, name);
2403 } else {
2404 snprintf(buf, len, "pci%04x,%04x",
2405 pci_get_word(d->config + PCI_VENDOR_ID),
2406 pci_get_word(d->config + PCI_DEVICE_ID));
2407 }
2408
2409 return buf;
2410}
2411
2412static char *pcibus_get_fw_dev_path(DeviceState *dev)
2413{
2414 PCIDevice *d = (PCIDevice *)dev;
2415 char path[50], name[33];
2416 int off;
2417
2418 off = snprintf(path, sizeof(path), "%s@%x",
2419 pci_dev_fw_name(dev, name, sizeof name),
2420 PCI_SLOT(d->devfn));
2421 if (PCI_FUNC(d->devfn))
2422 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
a5cf8262 2423 return g_strdup(path);
5e0259e7
GN		 2424}
2425
4f43c1ff
AW		 2426static char *pcibus_get_dev_path(DeviceState *dev)
2427{
a6a7005d
MT		 2428 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2429 PCIDevice *t;
2430 int slot_depth;
2431 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2432 * 00 is added here to make this format compatible with
2433 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2434 * Slot.Function list specifies the slot and function numbers for all
2435 * devices on the path from root to the specific device. */
568f0690
DG		 2436 const char *root_bus_path;
2437 int root_bus_len;
2991181a 2438 char slot[] = ":SS.F";
2991181a 2439 int slot_len = sizeof slot - 1 /* For '\0' */;
a6a7005d
MT		 2440 int path_len;
2441 char *path, *p;
2991181a 2442 int s;
a6a7005d 2443
568f0690
DG		 2444 root_bus_path = pci_root_bus_path(d);
2445 root_bus_len = strlen(root_bus_path);
2446
a6a7005d
MT		 2447 /* Calculate # of slots on path between device and root. */;
2448 slot_depth = 0;
fd56e061 2449 for (t = d; t; t = pci_get_bus(t)->parent_dev) {
a6a7005d
MT		 2450 ++slot_depth;
2451 }
2452
568f0690 2453 path_len = root_bus_len + slot_len * slot_depth;
a6a7005d
MT		 2454
2455 /* Allocate memory, fill in the terminating null byte. */
7267c094 2456 path = g_malloc(path_len + 1 /* For '\0' */);
a6a7005d
MT		 2457 path[path_len] = '\0';
2458
568f0690 2459 memcpy(path, root_bus_path, root_bus_len);
a6a7005d
MT		 2460
2461 /* Fill in slot numbers. We walk up from device to root, so need to print
2462 * them in the reverse order, last to first. */
2463 p = path + path_len;
fd56e061 2464 for (t = d; t; t = pci_get_bus(t)->parent_dev) {
a6a7005d 2465 p -= slot_len;
2991181a 2466 s = snprintf(slot, sizeof slot, ":%02x.%x",
4c900518 2467 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2991181a
MT		 2468 assert(s == slot_len);
2469 memcpy(p, slot, slot_len);
a6a7005d
MT		 2470 }
2471
2472 return path;
4f43c1ff
AW		 2473}
2474
f3006dd1
IY		 2475static int pci_qdev_find_recursive(PCIBus *bus,
2476 const char *id, PCIDevice **pdev)
2477{
2478 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2479 if (!qdev) {
2480 return -ENODEV;
2481 }
2482
2483 /* roughly check if given qdev is pci device */
4be9f0d1 2484 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
40021f08 2485 *pdev = PCI_DEVICE(qdev);
f3006dd1
IY		 2486 return 0;
2487 }
2488 return -EINVAL;
2489}
2490
2491int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2492{
7588e2b0 2493 PCIHostState *host_bridge;
f3006dd1
IY		 2494 int rc = -ENODEV;
2495
7588e2b0
DG		 2496 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2497 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
f3006dd1
IY		 2498 if (!tmp) {
2499 rc = 0;
2500 break;
2501 }
2502 if (tmp != -ENODEV) {
2503 rc = tmp;
2504 }
2505 }
2506
2507 return rc;
2508}
f5e6fed8
AK		 2509
2510MemoryRegion *pci_address_space(PCIDevice *dev)
2511{
fd56e061 2512 return pci_get_bus(dev)->address_space_mem;
f5e6fed8 2513}
e11d6439
RH		 2514
2515MemoryRegion *pci_address_space_io(PCIDevice *dev)
2516{
fd56e061 2517 return pci_get_bus(dev)->address_space_io;
e11d6439 2518}
40021f08 2519
39bffca2
AL		 2520static void pci_device_class_init(ObjectClass *klass, void *data)
2521{
2522 DeviceClass *k = DEVICE_CLASS(klass);
7ee6c1e1 2523
133e9b22
MA		 2524 k->realize = pci_qdev_realize;
2525 k->unrealize = pci_qdev_unrealize;
0d936928 2526 k->bus_type = TYPE_PCI_BUS;
bce54474 2527 k->props = pci_props;
39bffca2
AL		 2528}
2529
2fefa16c
EH		 2530static void pci_device_class_base_init(ObjectClass *klass, void *data)
2531{
2532 if (!object_class_is_abstract(klass)) {
2533 ObjectClass *conventional =
2534 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE);
2535 ObjectClass *pcie =
2536 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE);
2537 assert(conventional || pcie);
2538 }
2539}
2540
9eda7d37
AK		 2541AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2542{
fd56e061 2543 PCIBus *bus = pci_get_bus(dev);
5af2ae23 2544 PCIBus *iommu_bus = bus;
9eda7d37 2545
5af2ae23 2546 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) {
fd56e061 2547 iommu_bus = pci_get_bus(iommu_bus->parent_dev);
9eda7d37 2548 }
5af2ae23
BH		 2549 if (iommu_bus && iommu_bus->iommu_fn) {
2550 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn);
9eda7d37 2551 }
9eda7d37
AK		 2552 return &address_space_memory;
2553}
2554
e00387d5 2555void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
5fa45de5 2556{
e00387d5
AK		 2557 bus->iommu_fn = fn;
2558 bus->iommu_opaque = opaque;
5fa45de5
DG		 2559}
2560
43864069
MT		 2561static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2562{
2563 Range *range = opaque;
2564 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2565 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
77d6f4ea 2566 int i;
43864069
MT		 2567
2568 if (!(cmd & PCI_COMMAND_MEMORY)) {
2569 return;
2570 }
2571
2572 if (pc->is_bridge) {
2573 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2574 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2575
2576 base = MAX(base, 0x1ULL << 32);
2577
2578 if (limit >= base) {
2579 Range pref_range;
a0efbf16 2580 range_set_bounds(&pref_range, base, limit);
43864069
MT		 2581 range_extend(range, &pref_range);
2582 }
2583 }
77d6f4ea
MT		 2584 for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2585 PCIIORegion *r = &dev->io_regions[i];
a0efbf16 2586 pcibus_t lob, upb;
43864069
MT		 2587 Range region_range;
2588
77d6f4ea
MT		 2589 if (!r->size ||
2590 (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2591 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2592 continue;
2593 }
77d6f4ea 2594
a0efbf16
MA		 2595 lob = pci_bar_address(dev, i, r->type, r->size);
2596 upb = lob + r->size - 1;
2597 if (lob == PCI_BAR_UNMAPPED) {
43864069
MT		 2598 continue;
2599 }
43864069 2600
a0efbf16 2601 lob = MAX(lob, 0x1ULL << 32);
43864069 2602
a0efbf16
MA		 2603 if (upb >= lob) {
2604 range_set_bounds(&region_range, lob, upb);
43864069
MT		 2605 range_extend(range, &region_range);
2606 }
2607 }
2608}
2609
2610void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2611{
a0efbf16 2612 range_make_empty(range);
43864069
MT		 2613 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2614}
2615
3f1e1478
C		 2616static bool pcie_has_upstream_port(PCIDevice *dev)
2617{
fd56e061 2618 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev));
3f1e1478
C		 2619
2620 /* Device associated with an upstream port.
2621 * As there are several types of these, it's easier to check the
2622 * parent device: upstream ports are always connected to
2623 * root or downstream ports.
2624 */
2625 return parent_dev &&
2626 pci_is_express(parent_dev) &&
2627 parent_dev->exp.exp_cap &&
2628 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT ||
2629 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM);
2630}
2631
2632PCIDevice *pci_get_function_0(PCIDevice *pci_dev)
2633{
fd56e061
DG		 2634 PCIBus *bus = pci_get_bus(pci_dev);
2635
3f1e1478
C		 2636 if(pcie_has_upstream_port(pci_dev)) {
2637 /* With an upstream PCIe port, we only support 1 device at slot 0 */
fd56e061 2638 return bus->devices[0];
3f1e1478
C		 2639 } else {
2640 /* Other bus types might support multiple devices at slots 0-31 */
fd56e061 2641 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)];
3f1e1478
C		 2642 }
2643}
2644
e1d4fb2d
PX		 2645MSIMessage pci_get_msi_message(PCIDevice *dev, int vector)
2646{
2647 MSIMessage msg;
2648 if (msix_enabled(dev)) {
2649 msg = msix_get_message(dev, vector);
2650 } else if (msi_enabled(dev)) {
2651 msg = msi_get_message(dev, vector);
2652 } else {
2653 /* Should never happen */
2654 error_report("%s: unknown interrupt type", __func__);
2655 abort();
2656 }
2657 return msg;
2658}
2659
8c43a6f0 2660static const TypeInfo pci_device_type_info = {
40021f08
AL		 2661 .name = TYPE_PCI_DEVICE,
2662 .parent = TYPE_DEVICE,
2663 .instance_size = sizeof(PCIDevice),
2664 .abstract = true,
2665 .class_size = sizeof(PCIDeviceClass),
39bffca2 2666 .class_init = pci_device_class_init,
2fefa16c 2667 .class_base_init = pci_device_class_base_init,
40021f08
AL		 2668};
2669
83f7d43a 2670static void pci_register_types(void)
40021f08 2671{
0d936928 2672 type_register_static(&pci_bus_info);
3a861c46 2673 type_register_static(&pcie_bus_info);
619f02ae
EH		 2674 type_register_static(&conventional_pci_interface_info);
2675 type_register_static(&pcie_interface_info);
40021f08
AL		 2676 type_register_static(&pci_device_type_info);
2677}
2678
83f7d43a 2679type_init(pci_register_types)
Empty description
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