]>
Commit | Line | Data |
---|---|---|
94a420b1 SH |
1 | # Trace events for debugging and performance instrumentation |
2 | # | |
3 | # This file is processed by the tracetool script during the build. | |
4 | # | |
5 | # To add a new trace event: | |
6 | # | |
7 | # 1. Choose a name for the trace event. Declare its arguments and format | |
8 | # string. | |
9 | # | |
10 | # 2. Call the trace event from code using trace_##name, e.g. multiwrite_cb() -> | |
11 | # trace_multiwrite_cb(). The source file must #include "trace.h". | |
12 | # | |
13 | # Format of a trace event: | |
14 | # | |
1e2cf2bc | 15 | # [disable] <name>(<type1> <arg1>[, <type2> <arg2>] ...) "<format-string>" |
94a420b1 | 16 | # |
a74cd8cc | 17 | # Example: g_malloc(size_t size) "size %zu" |
94a420b1 | 18 | # |
1e2cf2bc | 19 | # The "disable" keyword will build without the trace event. |
1e2cf2bc | 20 | # |
94a420b1 SH |
21 | # The <name> must be a valid as a C function name. |
22 | # | |
23 | # Types should be standard C types. Use void * for pointers because the trace | |
24 | # system may not have the necessary headers included. | |
25 | # | |
26 | # The <format-string> should be a sprintf()-compatible format string. | |
cd245a19 SH |
27 | |
28 | # qemu-malloc.c | |
a74cd8cc FZ |
29 | g_malloc(size_t size, void *ptr) "size %zu ptr %p" |
30 | g_realloc(void *ptr, size_t size, void *newptr) "ptr %p size %zu newptr %p" | |
31 | g_free(void *ptr) "ptr %p" | |
cd245a19 SH |
32 | |
33 | # osdep.c | |
47f08d7a LV |
34 | qemu_memalign(size_t alignment, size_t size, void *ptr) "alignment %zu size %zu ptr %p" |
35 | qemu_vmalloc(size_t size, void *ptr) "size %zu ptr %p" | |
36 | qemu_vfree(void *ptr) "ptr %p" | |
6d519a5f | 37 | |
64979a4d | 38 | # hw/virtio.c |
47f08d7a LV |
39 | virtqueue_fill(void *vq, const void *elem, unsigned int len, unsigned int idx) "vq %p elem %p len %u idx %u" |
40 | virtqueue_flush(void *vq, unsigned int count) "vq %p count %u" | |
41 | virtqueue_pop(void *vq, void *elem, unsigned int in_num, unsigned int out_num) "vq %p elem %p in_num %u out_num %u" | |
42 | virtio_queue_notify(void *vdev, int n, void *vq) "vdev %p n %d vq %p" | |
43 | virtio_irq(void *vq) "vq %p" | |
44 | virtio_notify(void *vdev, void *vq) "vdev %p vq %p" | |
4e1837f8 | 45 | virtio_set_status(void *vdev, uint8_t val) "vdev %p val %u" |
64979a4d | 46 | |
49e3fdd7 | 47 | # hw/virtio-serial-bus.c |
47f08d7a LV |
48 | virtio_serial_send_control_event(unsigned int port, uint16_t event, uint16_t value) "port %u, event %u, value %u" |
49 | virtio_serial_throttle_port(unsigned int port, bool throttle) "port %u, throttle %d" | |
50 | virtio_serial_handle_control_message(uint16_t event, uint16_t value) "event %u, value %u" | |
51 | virtio_serial_handle_control_message_port(unsigned int port) "port %u" | |
49e3fdd7 | 52 | |
d02e4fa4 | 53 | # hw/virtio-console.c |
47f08d7a LV |
54 | virtio_console_flush_buf(unsigned int port, size_t len, ssize_t ret) "port %u, in_len %zu, out_len %zd" |
55 | virtio_console_chr_read(unsigned int port, int size) "port %u, size %d" | |
56 | virtio_console_chr_event(unsigned int port, int event) "port %u, event %d" | |
d02e4fa4 | 57 | |
6d519a5f | 58 | # block.c |
47f08d7a LV |
59 | multiwrite_cb(void *mcb, int ret) "mcb %p ret %d" |
60 | bdrv_aio_multiwrite(void *mcb, int num_callbacks, int num_reqs) "mcb %p num_callbacks %d num_reqs %d" | |
61 | bdrv_aio_multiwrite_earlyfail(void *mcb) "mcb %p" | |
62 | bdrv_aio_multiwrite_latefail(void *mcb, int i) "mcb %p i %d" | |
63 | bdrv_aio_flush(void *bs, void *opaque) "bs %p opaque %p" | |
64 | bdrv_aio_readv(void *bs, int64_t sector_num, int nb_sectors, void *opaque) "bs %p sector_num %"PRId64" nb_sectors %d opaque %p" | |
65 | bdrv_aio_writev(void *bs, int64_t sector_num, int nb_sectors, void *opaque) "bs %p sector_num %"PRId64" nb_sectors %d opaque %p" | |
025e849a | 66 | bdrv_lock_medium(void *bs, bool locked) "bs %p locked %d" |
47f08d7a LV |
67 | bdrv_co_readv(void *bs, int64_t sector_num, int nb_sector) "bs %p sector_num %"PRId64" nb_sectors %d" |
68 | bdrv_co_writev(void *bs, int64_t sector_num, int nb_sector) "bs %p sector_num %"PRId64" nb_sectors %d" | |
69 | bdrv_co_io(int is_write, void *acb) "is_write %d acb %p" | |
6d519a5f SH |
70 | |
71 | # hw/virtio-blk.c | |
47f08d7a LV |
72 | virtio_blk_req_complete(void *req, int status) "req %p status %d" |
73 | virtio_blk_rw_complete(void *req, int ret) "req %p ret %d" | |
74 | virtio_blk_handle_write(void *req, uint64_t sector, size_t nsectors) "req %p sector %"PRIu64" nsectors %zu" | |
6d519a5f SH |
75 | |
76 | # posix-aio-compat.c | |
47f08d7a LV |
77 | paio_submit(void *acb, void *opaque, int64_t sector_num, int nb_sectors, int type) "acb %p opaque %p sector_num %"PRId64" nb_sectors %d type %d" |
78 | paio_complete(void *acb, void *opaque, int ret) "acb %p opaque %p ret %d" | |
79 | paio_cancel(void *acb, void *opaque) "acb %p opaque %p" | |
bd3c9aa5 PS |
80 | |
81 | # ioport.c | |
47f08d7a LV |
82 | cpu_in(unsigned int addr, unsigned int val) "addr %#x value %u" |
83 | cpu_out(unsigned int addr, unsigned int val) "addr %#x value %u" | |
62dd89de PS |
84 | |
85 | # balloon.c | |
86 | # Since requests are raised via monitor, not many tracepoints are needed. | |
47f08d7a | 87 | balloon_event(void *opaque, unsigned long addr) "opaque %p addr %lu" |
d8023f31 BS |
88 | |
89 | # hw/apic.c | |
47f08d7a LV |
90 | apic_local_deliver(int vector, uint32_t lvt) "vector %d delivery mode %d" |
91 | apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d trigger_mode %d" | |
689d7e2f SH |
92 | cpu_set_apic_base(uint64_t val) "%016"PRIx64 |
93 | cpu_get_apic_base(uint64_t val) "%016"PRIx64 | |
47f08d7a LV |
94 | apic_mem_readl(uint64_t addr, uint32_t val) "%"PRIx64" = %08x" |
95 | apic_mem_writel(uint64_t addr, uint32_t val) "%"PRIx64" = %08x" | |
d8023f31 | 96 | # coalescing |
47f08d7a LV |
97 | apic_reset_irq_delivered(int apic_irq_delivered) "old coalescing %d" |
98 | apic_get_irq_delivered(int apic_irq_delivered) "returning coalescing %d" | |
99 | apic_set_irq(int apic_irq_delivered) "coalescing %d" | |
97bf4851 BS |
100 | |
101 | # hw/cs4231.c | |
47f08d7a LV |
102 | cs4231_mem_readl_dreg(uint32_t reg, uint32_t ret) "read dreg %d: 0x%02x" |
103 | cs4231_mem_readl_reg(uint32_t reg, uint32_t ret) "read reg %d: 0x%08x" | |
104 | cs4231_mem_writel_reg(uint32_t reg, uint32_t old, uint32_t val) "write reg %d: 0x%08x -> 0x%08x" | |
105 | cs4231_mem_writel_dreg(uint32_t reg, uint32_t old, uint32_t val) "write dreg %d: 0x%02x -> 0x%02x" | |
97bf4851 | 106 | |
d43ed9ec | 107 | # hw/ds1225y.c |
47f08d7a LV |
108 | nvram_read(uint32_t addr, uint32_t ret) "read addr %d: 0x%02x" |
109 | nvram_write(uint32_t addr, uint32_t old, uint32_t val) "write addr %d: 0x%02x -> 0x%02x" | |
d43ed9ec | 110 | |
97bf4851 | 111 | # hw/eccmemctl.c |
47f08d7a LV |
112 | ecc_mem_writel_mer(uint32_t val) "Write memory enable %08x" |
113 | ecc_mem_writel_mdr(uint32_t val) "Write memory delay %08x" | |
114 | ecc_mem_writel_mfsr(uint32_t val) "Write memory fault status %08x" | |
115 | ecc_mem_writel_vcr(uint32_t val) "Write slot configuration %08x" | |
116 | ecc_mem_writel_dr(uint32_t val) "Write diagnostic %08x" | |
117 | ecc_mem_writel_ecr0(uint32_t val) "Write event count 1 %08x" | |
118 | ecc_mem_writel_ecr1(uint32_t val) "Write event count 2 %08x" | |
119 | ecc_mem_readl_mer(uint32_t ret) "Read memory enable %08x" | |
120 | ecc_mem_readl_mdr(uint32_t ret) "Read memory delay %08x" | |
121 | ecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status %08x" | |
122 | ecc_mem_readl_vcr(uint32_t ret) "Read slot configuration %08x" | |
123 | ecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 %08x" | |
124 | ecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 %08x" | |
125 | ecc_mem_readl_dr(uint32_t ret) "Read diagnostic %08x" | |
126 | ecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 %08x" | |
127 | ecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 %08x" | |
128 | ecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = %02x" | |
129 | ecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= %02x" | |
97bf4851 BS |
130 | |
131 | # hw/lance.c | |
47f08d7a LV |
132 | lance_mem_readw(uint64_t addr, uint32_t ret) "addr=%"PRIx64"val=0x%04x" |
133 | lance_mem_writew(uint64_t addr, uint32_t val) "addr=%"PRIx64"val=0x%04x" | |
97bf4851 BS |
134 | |
135 | # hw/slavio_intctl.c | |
47f08d7a LV |
136 | slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = %x" |
137 | slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" = %x" | |
138 | slavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Cleared cpu %d irq mask %x, curmask %x" | |
139 | slavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Set cpu %d irq mask %x, curmask %x" | |
140 | slavio_intctlm_mem_readl(uint64_t addr, uint32_t ret) "read system reg 0x%"PRIx64" = %x" | |
141 | slavio_intctlm_mem_writel(uint64_t addr, uint32_t val) "write system reg 0x%"PRIx64" = %x" | |
142 | slavio_intctlm_mem_writel_enable(uint32_t val, uint32_t intregm_disabled) "Enabled master irq mask %x, curmask %x" | |
143 | slavio_intctlm_mem_writel_disable(uint32_t val, uint32_t intregm_disabled) "Disabled master irq mask %x, curmask %x" | |
144 | slavio_intctlm_mem_writel_target(uint32_t cpu) "Set master irq cpu %d" | |
145 | slavio_check_interrupts(uint32_t pending, uint32_t intregm_disabled) "pending %x disabled %x" | |
146 | slavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) "Set cpu %d irq %d -> pil %d level %d" | |
147 | slavio_set_timer_irq_cpu(int cpu, int level) "Set cpu %d local timer level %d" | |
97bf4851 BS |
148 | |
149 | # hw/slavio_misc.c | |
47f08d7a LV |
150 | slavio_misc_update_irq_raise(void) "Raise IRQ" |
151 | slavio_misc_update_irq_lower(void) "Lower IRQ" | |
152 | slavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d" | |
153 | slavio_cfg_mem_writeb(uint32_t val) "Write config %02x" | |
154 | slavio_cfg_mem_readb(uint32_t ret) "Read config %02x" | |
155 | slavio_diag_mem_writeb(uint32_t val) "Write diag %02x" | |
156 | slavio_diag_mem_readb(uint32_t ret) "Read diag %02x" | |
157 | slavio_mdm_mem_writeb(uint32_t val) "Write modem control %02x" | |
158 | slavio_mdm_mem_readb(uint32_t ret) "Read modem control %02x" | |
159 | slavio_aux1_mem_writeb(uint32_t val) "Write aux1 %02x" | |
160 | slavio_aux1_mem_readb(uint32_t ret) "Read aux1 %02x" | |
161 | slavio_aux2_mem_writeb(uint32_t val) "Write aux2 %02x" | |
162 | slavio_aux2_mem_readb(uint32_t ret) "Read aux2 %02x" | |
163 | apc_mem_writeb(uint32_t val) "Write power management %02x" | |
164 | apc_mem_readb(uint32_t ret) "Read power management %02x" | |
165 | slavio_sysctrl_mem_writel(uint32_t val) "Write system control %08x" | |
166 | slavio_sysctrl_mem_readl(uint32_t ret) "Read system control %08x" | |
167 | slavio_led_mem_writew(uint32_t val) "Write diagnostic LED %04x" | |
168 | slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED %04x" | |
97bf4851 BS |
169 | |
170 | # hw/slavio_timer.c | |
47f08d7a LV |
171 | slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count) "limit %"PRIx64" count %x%08x" |
172 | slavio_timer_irq(uint32_t counthigh, uint32_t count) "callback: count %x%08x" | |
689d7e2f | 173 | slavio_timer_mem_readl_invalid(uint64_t addr) "invalid read address %"PRIx64 |
47f08d7a LV |
174 | slavio_timer_mem_readl(uint64_t addr, uint32_t ret) "read %"PRIx64" = %08x" |
175 | slavio_timer_mem_writel(uint64_t addr, uint32_t val) "write %"PRIx64" = %08x" | |
689d7e2f | 176 | slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer set to %016"PRIx64 |
47f08d7a LV |
177 | slavio_timer_mem_writel_counter_invalid(void) "not user timer" |
178 | slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started" | |
179 | slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped" | |
180 | slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer" | |
181 | slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter" | |
182 | slavio_timer_mem_writel_mode_invalid(void) "not system timer" | |
689d7e2f | 183 | slavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address %"PRIx64 |
97bf4851 BS |
184 | |
185 | # hw/sparc32_dma.c | |
689d7e2f SH |
186 | ledma_memory_read(uint64_t addr) "DMA read addr 0x%"PRIx64 |
187 | ledma_memory_write(uint64_t addr) "DMA write addr 0x%"PRIx64 | |
47f08d7a LV |
188 | sparc32_dma_set_irq_raise(void) "Raise IRQ" |
189 | sparc32_dma_set_irq_lower(void) "Lower IRQ" | |
190 | espdma_memory_read(uint32_t addr) "DMA read addr 0x%08x" | |
191 | espdma_memory_write(uint32_t addr) "DMA write addr 0x%08x" | |
192 | sparc32_dma_mem_readl(uint64_t addr, uint32_t ret) "read dmareg %"PRIx64": 0x%08x" | |
193 | sparc32_dma_mem_writel(uint64_t addr, uint32_t old, uint32_t val) "write dmareg %"PRIx64": 0x%08x -> 0x%08x" | |
194 | sparc32_dma_enable_raise(void) "Raise DMA enable" | |
195 | sparc32_dma_enable_lower(void) "Lower DMA enable" | |
97bf4851 BS |
196 | |
197 | # hw/sun4m.c | |
47f08d7a LV |
198 | sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d" |
199 | sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d" | |
200 | sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d" | |
201 | sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d" | |
97bf4851 BS |
202 | |
203 | # hw/sun4m_iommu.c | |
47f08d7a LV |
204 | sun4m_iommu_mem_readl(uint64_t addr, uint32_t ret) "read reg[%"PRIx64"] = %x" |
205 | sun4m_iommu_mem_writel(uint64_t addr, uint32_t val) "write reg[%"PRIx64"] = %x" | |
689d7e2f | 206 | sun4m_iommu_mem_writel_ctrl(uint64_t iostart) "iostart = %"PRIx64 |
47f08d7a LV |
207 | sun4m_iommu_mem_writel_tlbflush(uint32_t val) "tlb flush %x" |
208 | sun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush %x" | |
209 | sun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get flags addr %"PRIx64" => pte %"PRIx64", *pte = %x" | |
210 | sun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlate dva %"PRIx64" => pa %"PRIx64" iopte = %x" | |
689d7e2f | 211 | sun4m_iommu_bad_addr(uint64_t addr) "bad addr %"PRIx64 |
94b0b5ff | 212 | |
891fb2cd GH |
213 | # hw/usb-bus.c |
214 | usb_port_claim(int bus, const char *port) "bus %d, port %s" | |
215 | usb_port_attach(int bus, const char *port) "bus %d, port %s" | |
216 | usb_port_detach(int bus, const char *port) "bus %d, port %s" | |
217 | usb_port_release(int bus, const char *port) "bus %d, port %s" | |
218 | ||
439a97cc | 219 | # hw/usb-ehci.c |
47f08d7a LV |
220 | usb_ehci_reset(void) "=== RESET ===" |
221 | usb_ehci_mmio_readl(uint32_t addr, const char *str, uint32_t val) "rd mmio %04x [%s] = %x" | |
222 | usb_ehci_mmio_writel(uint32_t addr, const char *str, uint32_t val) "wr mmio %04x [%s] = %x" | |
223 | usb_ehci_mmio_change(uint32_t addr, const char *str, uint32_t new, uint32_t old) "ch mmio %04x [%s] = %x (old: %x)" | |
224 | usb_ehci_usbsts(const char *sts, int state) "usbsts %s %d" | |
225 | usb_ehci_state(const char *schedule, const char *state) "%s schedule %s" | |
226 | usb_ehci_qh_ptrs(void *q, uint32_t addr, uint32_t nxt, uint32_t c_qtd, uint32_t n_qtd, uint32_t a_qtd) "q %p - QH @ %08x: next %08x qtds %08x,%08x,%08x" | |
227 | usb_ehci_qh_fields(uint32_t addr, int rl, int mplen, int eps, int ep, int devaddr) "QH @ %08x - rl %d, mplen %d, eps %d, ep %d, dev %d" | |
228 | usb_ehci_qh_bits(uint32_t addr, int c, int h, int dtc, int i) "QH @ %08x - c %d, h %d, dtc %d, i %d" | |
229 | usb_ehci_qtd_ptrs(void *q, uint32_t addr, uint32_t nxt, uint32_t altnext) "q %p - QTD @ %08x: next %08x altnext %08x" | |
230 | usb_ehci_qtd_fields(uint32_t addr, int tbytes, int cpage, int cerr, int pid) "QTD @ %08x - tbytes %d, cpage %d, cerr %d, pid %d" | |
231 | usb_ehci_qtd_bits(uint32_t addr, int ioc, int active, int halt, int babble, int xacterr) "QTD @ %08x - ioc %d, active %d, halt %d, babble %d, xacterr %d" | |
232 | usb_ehci_itd(uint32_t addr, uint32_t nxt, uint32_t mplen, uint32_t mult, uint32_t ep, uint32_t devaddr) "ITD @ %08x: next %08x - mplen %d, mult %d, ep %d, dev %d" | |
2fe80192 | 233 | usb_ehci_sitd(uint32_t addr, uint32_t nxt, uint32_t active) "ITD @ %08x: next %08x - active %d" |
47f08d7a LV |
234 | usb_ehci_port_attach(uint32_t port, const char *device) "attach port #%d - %s" |
235 | usb_ehci_port_detach(uint32_t port) "detach port #%d" | |
236 | usb_ehci_port_reset(uint32_t port, int enable) "reset port #%d - %d" | |
237 | usb_ehci_data(int rw, uint32_t cpage, uint32_t offset, uint32_t addr, uint32_t len, uint32_t bufpos) "write %d, cpage %d, offset 0x%03x, addr 0x%08x, len %d, bufpos %d" | |
238 | usb_ehci_queue_action(void *q, const char *action) "q %p: %s" | |
439a97cc | 239 | |
37fb59d3 | 240 | # hw/usb-desc.c |
47f08d7a LV |
241 | usb_desc_device(int addr, int len, int ret) "dev %d query device, len %d, ret %d" |
242 | usb_desc_device_qualifier(int addr, int len, int ret) "dev %d query device qualifier, len %d, ret %d" | |
243 | usb_desc_config(int addr, int index, int len, int ret) "dev %d query config %d, len %d, ret %d" | |
244 | usb_desc_other_speed_config(int addr, int index, int len, int ret) "dev %d query config %d, len %d, ret %d" | |
245 | usb_desc_string(int addr, int index, int len, int ret) "dev %d query string %d, len %d, ret %d" | |
246 | usb_set_addr(int addr) "dev %d" | |
247 | usb_set_config(int addr, int config, int ret) "dev %d, config %d, ret %d" | |
248 | usb_clear_device_feature(int addr, int feature, int ret) "dev %d, feature %d, ret %d" | |
249 | usb_set_device_feature(int addr, int feature, int ret) "dev %d, feature %d, ret %d" | |
37fb59d3 | 250 | |
e6a2f500 GH |
251 | # usb-linux.c |
252 | usb_host_open_started(int bus, int addr) "dev %d:%d" | |
253 | usb_host_open_success(int bus, int addr) "dev %d:%d" | |
254 | usb_host_open_failure(int bus, int addr) "dev %d:%d" | |
255 | usb_host_disconnect(int bus, int addr) "dev %d:%d" | |
256 | usb_host_close(int bus, int addr) "dev %d:%d" | |
257 | usb_host_set_address(int bus, int addr, int config) "dev %d:%d, address %d" | |
258 | usb_host_set_config(int bus, int addr, int config) "dev %d:%d, config %d" | |
259 | usb_host_set_interface(int bus, int addr, int interface, int alt) "dev %d:%d, interface %d, alt %d" | |
260 | usb_host_claim_interfaces(int bus, int addr, int config, int nif) "dev %d:%d, config %d, nif %d" | |
261 | usb_host_release_interfaces(int bus, int addr) "dev %d:%d" | |
262 | usb_host_req_control(int bus, int addr, int req, int value, int index) "dev %d:%d, req 0x%x, value %d, index %d" | |
263 | usb_host_req_data(int bus, int addr, int in, int ep, int size) "dev %d:%d, in %d, ep %d, size %d" | |
264 | usb_host_req_complete(int bus, int addr, int status) "dev %d:%d, status %d" | |
265 | usb_host_urb_submit(int bus, int addr, void *aurb, int length, int more) "dev %d:%d, aurb %p, length %d, more %d" | |
266 | usb_host_urb_complete(int bus, int addr, void *aurb, int status, int length, int more) "dev %d:%d, aurb %p, status %d, length %d, more %d" | |
267 | usb_host_ep_set_halt(int bus, int addr, int ep) "dev %d:%d, ep %d" | |
268 | usb_host_ep_clear_halt(int bus, int addr, int ep) "dev %d:%d, ep %d" | |
269 | usb_host_ep_start_iso(int bus, int addr, int ep) "dev %d:%d, ep %d" | |
270 | usb_host_ep_stop_iso(int bus, int addr, int ep) "dev %d:%d, ep %d" | |
271 | usb_host_reset(int bus, int addr) "dev %d:%d" | |
272 | usb_host_auto_scan_enabled(void) | |
273 | usb_host_auto_scan_disabled(void) | |
9516bb47 | 274 | usb_host_claim_port(int bus, int hub, int port) "bus %d, hub addr %d, port %d" |
e6a2f500 | 275 | |
5138efec | 276 | # hw/scsi-bus.c |
47f08d7a LV |
277 | scsi_req_alloc(int target, int lun, int tag) "target %d lun %d tag %d" |
278 | scsi_req_data(int target, int lun, int tag, int len) "target %d lun %d tag %d len %d" | |
279 | scsi_req_dequeue(int target, int lun, int tag) "target %d lun %d tag %d" | |
280 | scsi_req_continue(int target, int lun, int tag) "target %d lun %d tag %d" | |
281 | scsi_req_parsed(int target, int lun, int tag, int cmd, int mode, int xfer) "target %d lun %d tag %d command %d dir %d length %d" | |
689d7e2f | 282 | scsi_req_parsed_lba(int target, int lun, int tag, int cmd, uint64_t lba) "target %d lun %d tag %d command %d lba %"PRIu64 |
47f08d7a LV |
283 | scsi_req_parse_bad(int target, int lun, int tag, int cmd) "target %d lun %d tag %d command %d" |
284 | scsi_req_build_sense(int target, int lun, int tag, int key, int asc, int ascq) "target %d lun %d tag %d key %#02x asc %#02x ascq %#02x" | |
285 | scsi_report_luns(int target, int lun, int tag) "target %d lun %d tag %d" | |
286 | scsi_inquiry(int target, int lun, int tag, int cdb1, int cdb2) "target %d lun %d tag %d page %#02x/%#02x" | |
287 | scsi_test_unit_ready(int target, int lun, int tag) "target %d lun %d tag %d" | |
288 | scsi_request_sense(int target, int lun, int tag) "target %d lun %d tag %d" | |
5138efec | 289 | |
94b0b5ff | 290 | # vl.c |
47f08d7a | 291 | vm_state_notify(int running, int reason) "running %d reason %d" |
298800ca SH |
292 | |
293 | # block/qed-l2-cache.c | |
47f08d7a LV |
294 | qed_alloc_l2_cache_entry(void *l2_cache, void *entry) "l2_cache %p entry %p" |
295 | qed_unref_l2_cache_entry(void *entry, int ref) "entry %p ref %d" | |
296 | qed_find_l2_cache_entry(void *l2_cache, void *entry, uint64_t offset, int ref) "l2_cache %p entry %p offset %"PRIu64" ref %d" | |
298800ca SH |
297 | |
298 | # block/qed-table.c | |
47f08d7a LV |
299 | qed_read_table(void *s, uint64_t offset, void *table) "s %p offset %"PRIu64" table %p" |
300 | qed_read_table_cb(void *s, void *table, int ret) "s %p table %p ret %d" | |
301 | qed_write_table(void *s, uint64_t offset, void *table, unsigned int index, unsigned int n) "s %p offset %"PRIu64" table %p index %u n %u" | |
302 | qed_write_table_cb(void *s, void *table, int flush, int ret) "s %p table %p flush %d ret %d" | |
eabba580 SH |
303 | |
304 | # block/qed.c | |
47f08d7a LV |
305 | qed_need_check_timer_cb(void *s) "s %p" |
306 | qed_start_need_check_timer(void *s) "s %p" | |
307 | qed_cancel_need_check_timer(void *s) "s %p" | |
308 | qed_aio_complete(void *s, void *acb, int ret) "s %p acb %p ret %d" | |
309 | qed_aio_setup(void *s, void *acb, int64_t sector_num, int nb_sectors, void *opaque, int is_write) "s %p acb %p sector_num %"PRId64" nb_sectors %d opaque %p is_write %d" | |
689d7e2f | 310 | qed_aio_next_io(void *s, void *acb, int ret, uint64_t cur_pos) "s %p acb %p ret %d cur_pos %"PRIu64 |
47f08d7a LV |
311 | qed_aio_read_data(void *s, void *acb, int ret, uint64_t offset, size_t len) "s %p acb %p ret %d offset %"PRIu64" len %zu" |
312 | qed_aio_write_data(void *s, void *acb, int ret, uint64_t offset, size_t len) "s %p acb %p ret %d offset %"PRIu64" len %zu" | |
689d7e2f SH |
313 | qed_aio_write_prefill(void *s, void *acb, uint64_t start, size_t len, uint64_t offset) "s %p acb %p start %"PRIu64" len %zu offset %"PRIu64 |
314 | qed_aio_write_postfill(void *s, void *acb, uint64_t start, size_t len, uint64_t offset) "s %p acb %p start %"PRIu64" len %zu offset %"PRIu64 | |
47f08d7a | 315 | qed_aio_write_main(void *s, void *acb, int ret, uint64_t offset, size_t len) "s %p acb %p ret %d offset %"PRIu64" len %zu" |
0f3a4a01 | 316 | |
b213b370 | 317 | # hw/g364fb.c |
47f08d7a LV |
318 | g364fb_read(uint64_t addr, uint32_t val) "read addr=0x%"PRIx64": 0x%x" |
319 | g364fb_write(uint64_t addr, uint32_t new) "write addr=0x%"PRIx64": 0x%x" | |
b213b370 | 320 | |
0f3a4a01 | 321 | # hw/grlib_gptimer.c |
47f08d7a LV |
322 | grlib_gptimer_enable(int id, uint32_t count) "timer:%d set count 0x%x and run" |
323 | grlib_gptimer_disabled(int id, uint32_t config) "timer:%d Timer disable config 0x%x" | |
324 | grlib_gptimer_restart(int id, uint32_t reload) "timer:%d reload val: 0x%x" | |
325 | grlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq) "scaler:0x%x freq: 0x%x" | |
326 | grlib_gptimer_hit(int id) "timer:%d HIT" | |
327 | grlib_gptimer_readl(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x" | |
328 | grlib_gptimer_writel(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x" | |
3f10bcbb FC |
329 | |
330 | # hw/grlib_irqmp.c | |
2f4a725b | 331 | grlib_irqmp_check_irqs(uint32_t pend, uint32_t force, uint32_t mask, uint32_t lvl1, uint32_t lvl2) "pend:0x%04x force:0x%04x mask:0x%04x lvl1:0x%04x lvl0:0x%04x" |
47f08d7a LV |
332 | grlib_irqmp_ack(int intno) "interrupt:%d" |
333 | grlib_irqmp_set_irq(int irq) "Raise CPU IRQ %d" | |
689d7e2f | 334 | grlib_irqmp_readl_unknown(uint64_t addr) "addr 0x%"PRIx64 |
47f08d7a | 335 | grlib_irqmp_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" value 0x%x" |
8b1e1320 FC |
336 | |
337 | # hw/grlib_apbuart.c | |
47f08d7a LV |
338 | grlib_apbuart_event(int event) "event:%d" |
339 | grlib_apbuart_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" value 0x%x" | |
b04d9890 FC |
340 | |
341 | # hw/leon3.c | |
47f08d7a LV |
342 | leon3_set_irq(int intno) "Set CPU IRQ %d" |
343 | leon3_reset_irq(int intno) "Reset CPU IRQ %d" | |
9363ee31 | 344 | |
cbcc6336 | 345 | # spice-qemu-char.c |
47f08d7a LV |
346 | spice_vmc_write(ssize_t out, int len) "spice wrottn %zd of requested %d" |
347 | spice_vmc_read(int bytes, int len) "spice read %d of requested %d" | |
348 | spice_vmc_register_interface(void *scd) "spice vmc registered interface %p" | |
349 | spice_vmc_unregister_interface(void *scd) "spice vmc unregistered interface %p" | |
4ef66fa7 MW |
350 | |
351 | # hw/lm32_pic.c | |
47f08d7a LV |
352 | lm32_pic_raise_irq(void) "Raise CPU interrupt" |
353 | lm32_pic_lower_irq(void) "Lower CPU interrupt" | |
354 | lm32_pic_interrupt(int irq, int level) "Set IRQ%d %d" | |
355 | lm32_pic_set_im(uint32_t im) "im 0x%08x" | |
356 | lm32_pic_set_ip(uint32_t ip) "ip 0x%08x" | |
357 | lm32_pic_get_im(uint32_t im) "im 0x%08x" | |
358 | lm32_pic_get_ip(uint32_t ip) "ip 0x%08x" | |
15d7dc4f MW |
359 | |
360 | # hw/lm32_juart.c | |
47f08d7a LV |
361 | lm32_juart_get_jtx(uint32_t value) "jtx 0x%08x" |
362 | lm32_juart_set_jtx(uint32_t value) "jtx 0x%08x" | |
363 | lm32_juart_get_jrx(uint32_t value) "jrx 0x%08x" | |
364 | lm32_juart_set_jrx(uint32_t value) "jrx 0x%08x" | |
ea7924dc MW |
365 | |
366 | # hw/lm32_timer.c | |
47f08d7a LV |
367 | lm32_timer_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" |
368 | lm32_timer_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" | |
369 | lm32_timer_hit(void) "timer hit" | |
370 | lm32_timer_irq_state(int level) "irq state %d" | |
770ae571 MW |
371 | |
372 | # hw/lm32_uart.c | |
47f08d7a LV |
373 | lm32_uart_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" |
374 | lm32_uart_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" | |
375 | lm32_uart_irq_state(int level) "irq state %d" | |
f19410ca MW |
376 | |
377 | # hw/lm32_sys.c | |
47f08d7a | 378 | lm32_sys_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" |
25a8bb96 MW |
379 | |
380 | # hw/milkymist-ac97.c | |
47f08d7a LV |
381 | milkymist_ac97_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" |
382 | milkymist_ac97_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" | |
383 | milkymist_ac97_pulse_irq_crrequest(void) "Pulse IRQ CR request" | |
384 | milkymist_ac97_pulse_irq_crreply(void) "Pulse IRQ CR reply" | |
385 | milkymist_ac97_pulse_irq_dmaw(void) "Pulse IRQ DMA write" | |
386 | milkymist_ac97_pulse_irq_dmar(void) "Pulse IRQ DMA read" | |
387 | milkymist_ac97_in_cb(int avail, uint32_t remaining) "avail %d remaining %u" | |
388 | milkymist_ac97_in_cb_transferred(int transferred) "transferred %d" | |
389 | milkymist_ac97_out_cb(int free, uint32_t remaining) "free %d remaining %u" | |
390 | milkymist_ac97_out_cb_transferred(int transferred) "transferred %d" | |
e4dc6d2c MW |
391 | |
392 | # hw/milkymist-hpdmc.c | |
47f08d7a LV |
393 | milkymist_hpdmc_memory_read(uint32_t addr, uint32_t value) "addr=%08x value=%08x" |
394 | milkymist_hpdmc_memory_write(uint32_t addr, uint32_t value) "addr=%08x value=%08x" | |
b4e37d98 MW |
395 | |
396 | # hw/milkymist-memcard.c | |
47f08d7a LV |
397 | milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" |
398 | milkymist_memcard_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" | |
07424544 | 399 | |
57aa265d | 400 | # hw/milkymist-minimac2.c |
47f08d7a LV |
401 | milkymist_minimac2_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" |
402 | milkymist_minimac2_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" | |
403 | milkymist_minimac2_mdio_write(uint8_t phy_addr, uint8_t addr, uint16_t value) "phy_addr %02x addr %02x value %04x" | |
404 | milkymist_minimac2_mdio_read(uint8_t phy_addr, uint8_t addr, uint16_t value) "phy_addr %02x addr %02x value %04x" | |
405 | milkymist_minimac2_tx_frame(uint32_t length) "length %u" | |
406 | milkymist_minimac2_rx_frame(const void *buf, uint32_t length) "buf %p length %u" | |
407 | milkymist_minimac2_drop_rx_frame(const void *buf) "buf %p" | |
408 | milkymist_minimac2_rx_transfer(const void *buf, uint32_t length) "buf %p length %d" | |
409 | milkymist_minimac2_raise_irq_rx(void) "Raise IRQ RX" | |
410 | milkymist_minimac2_lower_irq_rx(void) "Lower IRQ RX" | |
411 | milkymist_minimac2_pulse_irq_tx(void) "Pulse IRQ TX" | |
5ee18b9c MW |
412 | |
413 | # hw/milkymist-pfpu.c | |
47f08d7a LV |
414 | milkymist_pfpu_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" |
415 | milkymist_pfpu_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" | |
416 | milkymist_pfpu_vectout(uint32_t a, uint32_t b, uint32_t dma_ptr) "a %08x b %08x dma_ptr %08x" | |
417 | milkymist_pfpu_pulse_irq(void) "Pulse IRQ" | |
87a381ec MW |
418 | |
419 | # hw/milkymist-softusb.c | |
47f08d7a LV |
420 | milkymist_softusb_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" |
421 | milkymist_softusb_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" | |
422 | milkymist_softusb_mevt(uint8_t m) "m %d" | |
423 | milkymist_softusb_kevt(uint8_t m) "m %d" | |
424 | milkymist_softusb_mouse_event(int dx, int dy, int dz, int bs) "dx %d dy %d dz %d bs %02x" | |
425 | milkymist_softusb_pulse_irq(void) "Pulse IRQ" | |
96832424 MW |
426 | |
427 | # hw/milkymist-sysctl.c | |
47f08d7a LV |
428 | milkymist_sysctl_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" |
429 | milkymist_sysctl_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" | |
430 | milkymist_sysctl_icap_write(uint32_t value) "value %08x" | |
431 | milkymist_sysctl_start_timer0(void) "Start timer0" | |
432 | milkymist_sysctl_stop_timer0(void) "Stop timer0" | |
433 | milkymist_sysctl_start_timer1(void) "Start timer1" | |
434 | milkymist_sysctl_stop_timer1(void) "Stop timer1" | |
435 | milkymist_sysctl_pulse_irq_timer0(void) "Pulse IRQ Timer0" | |
436 | milkymist_sysctl_pulse_irq_timer1(void) "Pulse IRQ Timer1" | |
0670dadd MW |
437 | |
438 | # hw/milkymist-tmu2.c | |
47f08d7a LV |
439 | milkymist_tmu2_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" |
440 | milkymist_tmu2_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" | |
441 | milkymist_tmu2_start(void) "Start TMU" | |
442 | milkymist_tmu2_pulse_irq(void) "Pulse IRQ" | |
883de16b MW |
443 | |
444 | # hw/milkymist-uart.c | |
47f08d7a LV |
445 | milkymist_uart_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" |
446 | milkymist_uart_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" | |
447 | milkymist_uart_pulse_irq_rx(void) "Pulse IRQ RX" | |
448 | milkymist_uart_pulse_irq_tx(void) "Pulse IRQ TX" | |
d23948b1 MW |
449 | |
450 | # hw/milkymist-vgafb.c | |
47f08d7a LV |
451 | milkymist_vgafb_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" |
452 | milkymist_vgafb_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" | |
432d268c | 453 | |
83818f7c HP |
454 | # hw/mipsnet.c |
455 | mipsnet_send(uint32_t size) "sending len=%u" | |
456 | mipsnet_receive(uint32_t size) "receiving len=%u" | |
457 | mipsnet_read(uint64_t addr, uint32_t val) "read addr=0x%" PRIx64 " val=0x%x" | |
458 | mipsnet_write(uint64_t addr, uint64_t val) "write addr=0x%" PRIx64 " val=0x%" PRIx64 | |
459 | mipsnet_irq(uint32_t isr, uint32_t intctl) "set irq to %d (%02x)" | |
460 | ||
432d268c | 461 | # xen-all.c |
47f08d7a LV |
462 | xen_ram_alloc(unsigned long ram_addr, unsigned long size) "requested: %#lx, size %#lx" |
463 | xen_client_set_memory(uint64_t start_addr, unsigned long size, unsigned long phys_offset, bool log_dirty) "%#"PRIx64" size %#lx, offset %#lx, log_dirty %i" | |
432d268c JN |
464 | |
465 | # xen-mapcache.c | |
689d7e2f SH |
466 | xen_map_cache(uint64_t phys_addr) "want %#"PRIx64 |
467 | xen_remap_bucket(uint64_t index) "index %#"PRIx64 | |
47f08d7a | 468 | xen_map_cache_return(void* ptr) "%p" |
689d7e2f | 469 | xen_map_block(uint64_t phys_addr, uint64_t size) "%#"PRIx64", size %#"PRIx64 |
47f08d7a | 470 | xen_unmap_block(void* addr, unsigned long size) "%p, size %#lx" |
050a0ddf AP |
471 | |
472 | # exec.c | |
47f08d7a | 473 | qemu_put_ram_ptr(void* addr) "%p" |
01195b73 SS |
474 | |
475 | # hw/xen_platform.c | |
47f08d7a | 476 | xen_platform_log(char *s) "xen platform: %s" |
00dccaf1 KW |
477 | |
478 | # qemu-coroutine.c | |
47f08d7a LV |
479 | qemu_coroutine_enter(void *from, void *to, void *opaque) "from %p to %p opaque %p" |
480 | qemu_coroutine_yield(void *from, void *to) "from %p to %p" | |
481 | qemu_coroutine_terminate(void *co) "self %p" | |
b96e9247 KW |
482 | |
483 | # qemu-coroutine-lock.c | |
47f08d7a LV |
484 | qemu_co_queue_next_bh(void) "" |
485 | qemu_co_queue_next(void *next) "next %p" | |
486 | qemu_co_mutex_lock_entry(void *mutex, void *self) "mutex %p self %p" | |
487 | qemu_co_mutex_lock_return(void *mutex, void *self) "mutex %p self %p" | |
488 | qemu_co_mutex_unlock_entry(void *mutex, void *self) "mutex %p self %p" | |
489 | qemu_co_mutex_unlock_return(void *mutex, void *self) "mutex %p self %p" | |
30c2f238 BS |
490 | |
491 | # hw/escc.c | |
47f08d7a LV |
492 | escc_put_queue(char channel, int b) "channel %c put: 0x%02x" |
493 | escc_get_queue(char channel, int val) "channel %c get 0x%02x" | |
494 | escc_update_irq(int irq) "IRQ = %d" | |
495 | escc_update_parameters(char channel, int speed, int parity, int data_bits, int stop_bits) "channel %c: speed=%d parity=%c data=%d stop=%d" | |
496 | escc_mem_writeb_ctrl(char channel, uint32_t reg, uint32_t val) "Write channel %c, reg[%d] = %2.2x" | |
497 | escc_mem_writeb_data(char channel, uint32_t val) "Write channel %c, ch %d" | |
498 | escc_mem_readb_ctrl(char channel, uint32_t reg, uint8_t val) "Read channel %c, reg[%d] = %2.2x" | |
499 | escc_mem_readb_data(char channel, uint32_t ret) "Read channel %c, ch %d" | |
500 | escc_serial_receive_byte(char channel, int ch) "channel %c put ch %d" | |
501 | escc_sunkbd_event_in(int ch) "Untranslated keycode %2.2x" | |
502 | escc_sunkbd_event_out(int ch) "Translated keycode %2.2x" | |
503 | escc_kbd_command(int val) "Command %d" | |
504 | escc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d dy=%d buttons=%01x" |