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a41b2ff2 PB |
1 | /** |
2 | * QEMU RTL8139 emulation | |
5fafdf24 | 3 | * |
a41b2ff2 | 4 | * Copyright (c) 2006 Igor Kovalenko |
5fafdf24 | 5 | * |
a41b2ff2 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
5fafdf24 | 23 | |
a41b2ff2 PB |
24 | * Modifications: |
25 | * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver) | |
5fafdf24 | 26 | * |
6cadb320 FB |
27 | * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver |
28 | * HW revision ID changes for FreeBSD driver | |
5fafdf24 | 29 | * |
6cadb320 FB |
30 | * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver |
31 | * Corrected packet transfer reassembly routine for 8139C+ mode | |
32 | * Rearranged debugging print statements | |
33 | * Implemented PCI timer interrupt (disabled by default) | |
34 | * Implemented Tally Counters, increased VM load/save version | |
35 | * Implemented IP/TCP/UDP checksum task offloading | |
718da2b9 FB |
36 | * |
37 | * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading | |
38 | * Fixed MTU=1500 for produced ethernet frames | |
39 | * | |
40 | * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing | |
41 | * segmentation offloading | |
42 | * Removed slirp.h dependency | |
43 | * Added rx/tx buffer reset when enabling rx/tx operation | |
05447803 FZ |
44 | * |
45 | * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only | |
46 | * when strictly needed (required for for | |
47 | * Darwin) | |
bf6b87a8 | 48 | * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading |
a41b2ff2 PB |
49 | */ |
50 | ||
2c406b8f BP |
51 | /* For crc32 */ |
52 | #include <zlib.h> | |
53 | ||
83c9f4ca PB |
54 | #include "hw/hw.h" |
55 | #include "hw/pci/pci.h" | |
9c17d615 | 56 | #include "sysemu/dma.h" |
1de7afc9 | 57 | #include "qemu/timer.h" |
1422e32d | 58 | #include "net/net.h" |
83c9f4ca | 59 | #include "hw/loader.h" |
9c17d615 | 60 | #include "sysemu/sysemu.h" |
1de7afc9 | 61 | #include "qemu/iov.h" |
a41b2ff2 | 62 | |
a41b2ff2 PB |
63 | /* debug RTL8139 card */ |
64 | //#define DEBUG_RTL8139 1 | |
65 | ||
6cadb320 FB |
66 | #define PCI_FREQUENCY 33000000L |
67 | ||
a41b2ff2 PB |
68 | #define SET_MASKED(input, mask, curr) \ |
69 | ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) | |
70 | ||
71 | /* arg % size for size which is a power of 2 */ | |
72 | #define MOD2(input, size) \ | |
73 | ( ( input ) & ( size - 1 ) ) | |
74 | ||
18dabfd1 BP |
75 | #define ETHER_ADDR_LEN 6 |
76 | #define ETHER_TYPE_LEN 2 | |
77 | #define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN) | |
78 | #define ETH_P_IP 0x0800 /* Internet Protocol packet */ | |
79 | #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ | |
80 | #define ETH_MTU 1500 | |
81 | ||
82 | #define VLAN_TCI_LEN 2 | |
83 | #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN) | |
84 | ||
6cadb320 | 85 | #if defined (DEBUG_RTL8139) |
7cdeb319 BP |
86 | # define DPRINTF(fmt, ...) \ |
87 | do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0) | |
6cadb320 | 88 | #else |
c6a0487b | 89 | static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...) |
ec48c774 BP |
90 | { |
91 | return 0; | |
92 | } | |
6cadb320 FB |
93 | #endif |
94 | ||
39257515 PC |
95 | #define TYPE_RTL8139 "rtl8139" |
96 | ||
97 | #define RTL8139(obj) \ | |
98 | OBJECT_CHECK(RTL8139State, (obj), TYPE_RTL8139) | |
99 | ||
a41b2ff2 PB |
100 | /* Symbolic offsets to registers. */ |
101 | enum RTL8139_registers { | |
102 | MAC0 = 0, /* Ethernet hardware address. */ | |
103 | MAR0 = 8, /* Multicast filter. */ | |
6cadb320 FB |
104 | TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */ |
105 | /* Dump Tally Conter control register(64bit). C+ mode only */ | |
106 | TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ | |
a41b2ff2 PB |
107 | RxBuf = 0x30, |
108 | ChipCmd = 0x37, | |
109 | RxBufPtr = 0x38, | |
110 | RxBufAddr = 0x3A, | |
111 | IntrMask = 0x3C, | |
112 | IntrStatus = 0x3E, | |
113 | TxConfig = 0x40, | |
114 | RxConfig = 0x44, | |
115 | Timer = 0x48, /* A general-purpose counter. */ | |
116 | RxMissed = 0x4C, /* 24 bits valid, write clears. */ | |
117 | Cfg9346 = 0x50, | |
118 | Config0 = 0x51, | |
119 | Config1 = 0x52, | |
120 | FlashReg = 0x54, | |
121 | MediaStatus = 0x58, | |
122 | Config3 = 0x59, | |
123 | Config4 = 0x5A, /* absent on RTL-8139A */ | |
124 | HltClk = 0x5B, | |
125 | MultiIntr = 0x5C, | |
126 | PCIRevisionID = 0x5E, | |
127 | TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ | |
128 | BasicModeCtrl = 0x62, | |
129 | BasicModeStatus = 0x64, | |
130 | NWayAdvert = 0x66, | |
131 | NWayLPAR = 0x68, | |
132 | NWayExpansion = 0x6A, | |
133 | /* Undocumented registers, but required for proper operation. */ | |
134 | FIFOTMS = 0x70, /* FIFO Control and test. */ | |
135 | CSCR = 0x74, /* Chip Status and Configuration Register. */ | |
136 | PARA78 = 0x78, | |
137 | PARA7c = 0x7c, /* Magic transceiver parameter register. */ | |
138 | Config5 = 0xD8, /* absent on RTL-8139A */ | |
139 | /* C+ mode */ | |
140 | TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ | |
141 | RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ | |
142 | CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ | |
143 | IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ | |
144 | RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ | |
145 | RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ | |
146 | TxThresh = 0xEC, /* Early Tx threshold */ | |
147 | }; | |
148 | ||
149 | enum ClearBitMasks { | |
150 | MultiIntrClear = 0xF000, | |
151 | ChipCmdClear = 0xE2, | |
152 | Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), | |
153 | }; | |
154 | ||
155 | enum ChipCmdBits { | |
156 | CmdReset = 0x10, | |
157 | CmdRxEnb = 0x08, | |
158 | CmdTxEnb = 0x04, | |
159 | RxBufEmpty = 0x01, | |
160 | }; | |
161 | ||
162 | /* C+ mode */ | |
163 | enum CplusCmdBits { | |
6cadb320 FB |
164 | CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */ |
165 | CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */ | |
166 | CPlusRxEnb = 0x0002, | |
167 | CPlusTxEnb = 0x0001, | |
a41b2ff2 PB |
168 | }; |
169 | ||
170 | /* Interrupt register bits, using my own meaningful names. */ | |
171 | enum IntrStatusBits { | |
172 | PCIErr = 0x8000, | |
173 | PCSTimeout = 0x4000, | |
174 | RxFIFOOver = 0x40, | |
9e12c5af | 175 | RxUnderrun = 0x20, /* Packet Underrun / Link Change */ |
a41b2ff2 PB |
176 | RxOverflow = 0x10, |
177 | TxErr = 0x08, | |
178 | TxOK = 0x04, | |
179 | RxErr = 0x02, | |
180 | RxOK = 0x01, | |
181 | ||
182 | RxAckBits = RxFIFOOver | RxOverflow | RxOK, | |
183 | }; | |
184 | ||
185 | enum TxStatusBits { | |
186 | TxHostOwns = 0x2000, | |
187 | TxUnderrun = 0x4000, | |
188 | TxStatOK = 0x8000, | |
189 | TxOutOfWindow = 0x20000000, | |
190 | TxAborted = 0x40000000, | |
191 | TxCarrierLost = 0x80000000, | |
192 | }; | |
193 | enum RxStatusBits { | |
194 | RxMulticast = 0x8000, | |
195 | RxPhysical = 0x4000, | |
196 | RxBroadcast = 0x2000, | |
197 | RxBadSymbol = 0x0020, | |
198 | RxRunt = 0x0010, | |
199 | RxTooLong = 0x0008, | |
200 | RxCRCErr = 0x0004, | |
201 | RxBadAlign = 0x0002, | |
202 | RxStatusOK = 0x0001, | |
203 | }; | |
204 | ||
205 | /* Bits in RxConfig. */ | |
206 | enum rx_mode_bits { | |
207 | AcceptErr = 0x20, | |
208 | AcceptRunt = 0x10, | |
209 | AcceptBroadcast = 0x08, | |
210 | AcceptMulticast = 0x04, | |
211 | AcceptMyPhys = 0x02, | |
212 | AcceptAllPhys = 0x01, | |
213 | }; | |
214 | ||
215 | /* Bits in TxConfig. */ | |
216 | enum tx_config_bits { | |
217 | ||
218 | /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ | |
219 | TxIFGShift = 24, | |
220 | TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ | |
221 | TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ | |
222 | TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ | |
223 | TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ | |
224 | ||
225 | TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ | |
226 | TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ | |
227 | TxClearAbt = (1 << 0), /* Clear abort (WO) */ | |
228 | TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ | |
229 | TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ | |
230 | ||
231 | TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ | |
232 | }; | |
233 | ||
234 | ||
235 | /* Transmit Status of All Descriptors (TSAD) Register */ | |
236 | enum TSAD_bits { | |
237 | TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 | |
238 | TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 | |
239 | TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 | |
240 | TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 | |
241 | TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 | |
242 | TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 | |
243 | TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 | |
244 | TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 | |
245 | TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 | |
246 | TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 | |
247 | TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 | |
248 | TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 | |
249 | TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 | |
250 | TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 | |
251 | TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 | |
252 | TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 | |
253 | }; | |
254 | ||
255 | ||
256 | /* Bits in Config1 */ | |
257 | enum Config1Bits { | |
258 | Cfg1_PM_Enable = 0x01, | |
259 | Cfg1_VPD_Enable = 0x02, | |
260 | Cfg1_PIO = 0x04, | |
261 | Cfg1_MMIO = 0x08, | |
262 | LWAKE = 0x10, /* not on 8139, 8139A */ | |
263 | Cfg1_Driver_Load = 0x20, | |
264 | Cfg1_LED0 = 0x40, | |
265 | Cfg1_LED1 = 0x80, | |
266 | SLEEP = (1 << 1), /* only on 8139, 8139A */ | |
267 | PWRDN = (1 << 0), /* only on 8139, 8139A */ | |
268 | }; | |
269 | ||
270 | /* Bits in Config3 */ | |
271 | enum Config3Bits { | |
272 | Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ | |
273 | Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ | |
274 | Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ | |
275 | Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ | |
276 | Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ | |
277 | Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ | |
278 | Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ | |
279 | Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ | |
280 | }; | |
281 | ||
282 | /* Bits in Config4 */ | |
283 | enum Config4Bits { | |
284 | LWPTN = (1 << 2), /* not on 8139, 8139A */ | |
285 | }; | |
286 | ||
287 | /* Bits in Config5 */ | |
288 | enum Config5Bits { | |
289 | Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ | |
290 | Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ | |
291 | Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ | |
292 | Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */ | |
293 | Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ | |
294 | Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ | |
295 | Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ | |
296 | }; | |
297 | ||
298 | enum RxConfigBits { | |
299 | /* rx fifo threshold */ | |
300 | RxCfgFIFOShift = 13, | |
301 | RxCfgFIFONone = (7 << RxCfgFIFOShift), | |
302 | ||
303 | /* Max DMA burst */ | |
304 | RxCfgDMAShift = 8, | |
305 | RxCfgDMAUnlimited = (7 << RxCfgDMAShift), | |
306 | ||
307 | /* rx ring buffer length */ | |
308 | RxCfgRcv8K = 0, | |
309 | RxCfgRcv16K = (1 << 11), | |
310 | RxCfgRcv32K = (1 << 12), | |
311 | RxCfgRcv64K = (1 << 11) | (1 << 12), | |
312 | ||
313 | /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ | |
314 | RxNoWrap = (1 << 7), | |
315 | }; | |
316 | ||
317 | /* Twister tuning parameters from RealTek. | |
318 | Completely undocumented, but required to tune bad links on some boards. */ | |
319 | /* | |
320 | enum CSCRBits { | |
321 | CSCR_LinkOKBit = 0x0400, | |
322 | CSCR_LinkChangeBit = 0x0800, | |
323 | CSCR_LinkStatusBits = 0x0f000, | |
324 | CSCR_LinkDownOffCmd = 0x003c0, | |
325 | CSCR_LinkDownCmd = 0x0f3c0, | |
326 | */ | |
327 | enum CSCRBits { | |
5fafdf24 | 328 | CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ |
a41b2ff2 PB |
329 | CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ |
330 | CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ | |
331 | CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ | |
5fafdf24 | 332 | CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ |
a41b2ff2 PB |
333 | CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ |
334 | CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ | |
335 | CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ | |
336 | CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ | |
337 | }; | |
338 | ||
339 | enum Cfg9346Bits { | |
eb46c5ed JW |
340 | Cfg9346_Normal = 0x00, |
341 | Cfg9346_Autoload = 0x40, | |
342 | Cfg9346_Programming = 0x80, | |
343 | Cfg9346_ConfigWrite = 0xC0, | |
a41b2ff2 PB |
344 | }; |
345 | ||
346 | typedef enum { | |
347 | CH_8139 = 0, | |
348 | CH_8139_K, | |
349 | CH_8139A, | |
350 | CH_8139A_G, | |
351 | CH_8139B, | |
352 | CH_8130, | |
353 | CH_8139C, | |
354 | CH_8100, | |
355 | CH_8100B_8139D, | |
356 | CH_8101, | |
c227f099 | 357 | } chip_t; |
a41b2ff2 PB |
358 | |
359 | enum chip_flags { | |
360 | HasHltClk = (1 << 0), | |
361 | HasLWake = (1 << 1), | |
362 | }; | |
363 | ||
364 | #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ | |
365 | (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) | |
366 | #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) | |
367 | ||
6cadb320 FB |
368 | #define RTL8139_PCI_REVID_8139 0x10 |
369 | #define RTL8139_PCI_REVID_8139CPLUS 0x20 | |
370 | ||
371 | #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS | |
372 | ||
a41b2ff2 PB |
373 | /* Size is 64 * 16bit words */ |
374 | #define EEPROM_9346_ADDR_BITS 6 | |
375 | #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) | |
376 | #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) | |
377 | ||
378 | enum Chip9346Operation | |
379 | { | |
380 | Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ | |
381 | Chip9346_op_read = 0x80, /* 10 AAAAAA */ | |
382 | Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ | |
383 | Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ | |
384 | Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ | |
385 | Chip9346_op_write_all = 0x10, /* 00 01zzzz */ | |
386 | Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ | |
387 | }; | |
388 | ||
389 | enum Chip9346Mode | |
390 | { | |
391 | Chip9346_none = 0, | |
392 | Chip9346_enter_command_mode, | |
393 | Chip9346_read_command, | |
394 | Chip9346_data_read, /* from output register */ | |
395 | Chip9346_data_write, /* to input register, then to contents at specified address */ | |
396 | Chip9346_data_write_all, /* to input register, then filling contents */ | |
397 | }; | |
398 | ||
399 | typedef struct EEprom9346 | |
400 | { | |
401 | uint16_t contents[EEPROM_9346_SIZE]; | |
402 | int mode; | |
403 | uint32_t tick; | |
404 | uint8_t address; | |
405 | uint16_t input; | |
406 | uint16_t output; | |
407 | ||
408 | uint8_t eecs; | |
409 | uint8_t eesk; | |
410 | uint8_t eedi; | |
411 | uint8_t eedo; | |
412 | } EEprom9346; | |
413 | ||
6cadb320 FB |
414 | typedef struct RTL8139TallyCounters |
415 | { | |
416 | /* Tally counters */ | |
417 | uint64_t TxOk; | |
418 | uint64_t RxOk; | |
419 | uint64_t TxERR; | |
420 | uint32_t RxERR; | |
421 | uint16_t MissPkt; | |
422 | uint16_t FAE; | |
423 | uint32_t Tx1Col; | |
424 | uint32_t TxMCol; | |
425 | uint64_t RxOkPhy; | |
426 | uint64_t RxOkBrd; | |
427 | uint32_t RxOkMul; | |
428 | uint16_t TxAbt; | |
429 | uint16_t TxUndrn; | |
430 | } RTL8139TallyCounters; | |
431 | ||
432 | /* Clears all tally counters */ | |
433 | static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters); | |
434 | ||
a41b2ff2 | 435 | typedef struct RTL8139State { |
88a411a8 AF |
436 | /*< private >*/ |
437 | PCIDevice parent_obj; | |
438 | /*< public >*/ | |
439 | ||
a41b2ff2 PB |
440 | uint8_t phys[8]; /* mac address */ |
441 | uint8_t mult[8]; /* multicast mask array */ | |
442 | ||
6cadb320 | 443 | uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */ |
a41b2ff2 PB |
444 | uint32_t TxAddr[4]; /* TxAddr0 */ |
445 | uint32_t RxBuf; /* Receive buffer */ | |
446 | uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */ | |
447 | uint32_t RxBufPtr; | |
448 | uint32_t RxBufAddr; | |
449 | ||
450 | uint16_t IntrStatus; | |
451 | uint16_t IntrMask; | |
452 | ||
453 | uint32_t TxConfig; | |
454 | uint32_t RxConfig; | |
455 | uint32_t RxMissed; | |
456 | ||
457 | uint16_t CSCR; | |
458 | ||
459 | uint8_t Cfg9346; | |
460 | uint8_t Config0; | |
461 | uint8_t Config1; | |
462 | uint8_t Config3; | |
463 | uint8_t Config4; | |
464 | uint8_t Config5; | |
465 | ||
466 | uint8_t clock_enabled; | |
467 | uint8_t bChipCmdState; | |
468 | ||
469 | uint16_t MultiIntr; | |
470 | ||
471 | uint16_t BasicModeCtrl; | |
472 | uint16_t BasicModeStatus; | |
473 | uint16_t NWayAdvert; | |
474 | uint16_t NWayLPAR; | |
475 | uint16_t NWayExpansion; | |
476 | ||
477 | uint16_t CpCmd; | |
478 | uint8_t TxThresh; | |
479 | ||
1673ad51 | 480 | NICState *nic; |
254111ec | 481 | NICConf conf; |
a41b2ff2 PB |
482 | |
483 | /* C ring mode */ | |
484 | uint32_t currTxDesc; | |
485 | ||
486 | /* C+ mode */ | |
2c3891ab AL |
487 | uint32_t cplus_enabled; |
488 | ||
a41b2ff2 PB |
489 | uint32_t currCPlusRxDesc; |
490 | uint32_t currCPlusTxDesc; | |
491 | ||
492 | uint32_t RxRingAddrLO; | |
493 | uint32_t RxRingAddrHI; | |
494 | ||
495 | EEprom9346 eeprom; | |
6cadb320 FB |
496 | |
497 | uint32_t TCTR; | |
498 | uint32_t TimerInt; | |
499 | int64_t TCTR_base; | |
500 | ||
501 | /* Tally counters */ | |
502 | RTL8139TallyCounters tally_counters; | |
503 | ||
504 | /* Non-persistent data */ | |
505 | uint8_t *cplus_txbuffer; | |
506 | int cplus_txbuffer_len; | |
507 | int cplus_txbuffer_offset; | |
508 | ||
509 | /* PCI interrupt timer */ | |
510 | QEMUTimer *timer; | |
05447803 | 511 | int64_t TimerExpire; |
6cadb320 | 512 | |
bd80f3fc AK |
513 | MemoryRegion bar_io; |
514 | MemoryRegion bar_mem; | |
515 | ||
c574ba5a AW |
516 | /* Support migration to/from old versions */ |
517 | int rtl8139_mmio_io_addr_dummy; | |
a41b2ff2 PB |
518 | } RTL8139State; |
519 | ||
3ada003a EGM |
520 | /* Writes tally counters to memory via DMA */ |
521 | static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr); | |
522 | ||
05447803 FZ |
523 | static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time); |
524 | ||
9596ebb7 | 525 | static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) |
a41b2ff2 | 526 | { |
7cdeb319 | 527 | DPRINTF("eeprom command 0x%02x\n", command); |
a41b2ff2 PB |
528 | |
529 | switch (command & Chip9346_op_mask) | |
530 | { | |
531 | case Chip9346_op_read: | |
532 | { | |
533 | eeprom->address = command & EEPROM_9346_ADDR_MASK; | |
534 | eeprom->output = eeprom->contents[eeprom->address]; | |
535 | eeprom->eedo = 0; | |
536 | eeprom->tick = 0; | |
537 | eeprom->mode = Chip9346_data_read; | |
7cdeb319 BP |
538 | DPRINTF("eeprom read from address 0x%02x data=0x%04x\n", |
539 | eeprom->address, eeprom->output); | |
a41b2ff2 PB |
540 | } |
541 | break; | |
542 | ||
543 | case Chip9346_op_write: | |
544 | { | |
545 | eeprom->address = command & EEPROM_9346_ADDR_MASK; | |
546 | eeprom->input = 0; | |
547 | eeprom->tick = 0; | |
548 | eeprom->mode = Chip9346_none; /* Chip9346_data_write */ | |
7cdeb319 BP |
549 | DPRINTF("eeprom begin write to address 0x%02x\n", |
550 | eeprom->address); | |
a41b2ff2 PB |
551 | } |
552 | break; | |
553 | default: | |
554 | eeprom->mode = Chip9346_none; | |
555 | switch (command & Chip9346_op_ext_mask) | |
556 | { | |
557 | case Chip9346_op_write_enable: | |
7cdeb319 | 558 | DPRINTF("eeprom write enabled\n"); |
a41b2ff2 PB |
559 | break; |
560 | case Chip9346_op_write_all: | |
7cdeb319 | 561 | DPRINTF("eeprom begin write all\n"); |
a41b2ff2 PB |
562 | break; |
563 | case Chip9346_op_write_disable: | |
7cdeb319 | 564 | DPRINTF("eeprom write disabled\n"); |
a41b2ff2 PB |
565 | break; |
566 | } | |
567 | break; | |
568 | } | |
569 | } | |
570 | ||
9596ebb7 | 571 | static void prom9346_shift_clock(EEprom9346 *eeprom) |
a41b2ff2 PB |
572 | { |
573 | int bit = eeprom->eedi?1:0; | |
574 | ||
575 | ++ eeprom->tick; | |
576 | ||
7cdeb319 BP |
577 | DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, |
578 | eeprom->eedo); | |
a41b2ff2 PB |
579 | |
580 | switch (eeprom->mode) | |
581 | { | |
582 | case Chip9346_enter_command_mode: | |
583 | if (bit) | |
584 | { | |
585 | eeprom->mode = Chip9346_read_command; | |
586 | eeprom->tick = 0; | |
587 | eeprom->input = 0; | |
7cdeb319 | 588 | DPRINTF("eeprom: +++ synchronized, begin command read\n"); |
a41b2ff2 PB |
589 | } |
590 | break; | |
591 | ||
592 | case Chip9346_read_command: | |
593 | eeprom->input = (eeprom->input << 1) | (bit & 1); | |
594 | if (eeprom->tick == 8) | |
595 | { | |
596 | prom9346_decode_command(eeprom, eeprom->input & 0xff); | |
597 | } | |
598 | break; | |
599 | ||
600 | case Chip9346_data_read: | |
601 | eeprom->eedo = (eeprom->output & 0x8000)?1:0; | |
602 | eeprom->output <<= 1; | |
603 | if (eeprom->tick == 16) | |
604 | { | |
6cadb320 FB |
605 | #if 1 |
606 | // the FreeBSD drivers (rl and re) don't explicitly toggle | |
607 | // CS between reads (or does setting Cfg9346 to 0 count too?), | |
608 | // so we need to enter wait-for-command state here | |
609 | eeprom->mode = Chip9346_enter_command_mode; | |
610 | eeprom->input = 0; | |
611 | eeprom->tick = 0; | |
612 | ||
7cdeb319 | 613 | DPRINTF("eeprom: +++ end of read, awaiting next command\n"); |
6cadb320 FB |
614 | #else |
615 | // original behaviour | |
a41b2ff2 PB |
616 | ++eeprom->address; |
617 | eeprom->address &= EEPROM_9346_ADDR_MASK; | |
618 | eeprom->output = eeprom->contents[eeprom->address]; | |
619 | eeprom->tick = 0; | |
620 | ||
7cdeb319 BP |
621 | DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n", |
622 | eeprom->address, eeprom->output); | |
a41b2ff2 PB |
623 | #endif |
624 | } | |
625 | break; | |
626 | ||
627 | case Chip9346_data_write: | |
628 | eeprom->input = (eeprom->input << 1) | (bit & 1); | |
629 | if (eeprom->tick == 16) | |
630 | { | |
7cdeb319 BP |
631 | DPRINTF("eeprom write to address 0x%02x data=0x%04x\n", |
632 | eeprom->address, eeprom->input); | |
6cadb320 | 633 | |
a41b2ff2 PB |
634 | eeprom->contents[eeprom->address] = eeprom->input; |
635 | eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */ | |
636 | eeprom->tick = 0; | |
637 | eeprom->input = 0; | |
638 | } | |
639 | break; | |
640 | ||
641 | case Chip9346_data_write_all: | |
642 | eeprom->input = (eeprom->input << 1) | (bit & 1); | |
643 | if (eeprom->tick == 16) | |
644 | { | |
645 | int i; | |
646 | for (i = 0; i < EEPROM_9346_SIZE; i++) | |
647 | { | |
648 | eeprom->contents[i] = eeprom->input; | |
649 | } | |
7cdeb319 | 650 | DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input); |
6cadb320 | 651 | |
a41b2ff2 PB |
652 | eeprom->mode = Chip9346_enter_command_mode; |
653 | eeprom->tick = 0; | |
654 | eeprom->input = 0; | |
655 | } | |
656 | break; | |
657 | ||
658 | default: | |
659 | break; | |
660 | } | |
661 | } | |
662 | ||
9596ebb7 | 663 | static int prom9346_get_wire(RTL8139State *s) |
a41b2ff2 PB |
664 | { |
665 | EEprom9346 *eeprom = &s->eeprom; | |
666 | if (!eeprom->eecs) | |
667 | return 0; | |
668 | ||
669 | return eeprom->eedo; | |
670 | } | |
671 | ||
9596ebb7 PB |
672 | /* FIXME: This should be merged into/replaced by eeprom93xx.c. */ |
673 | static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) | |
a41b2ff2 PB |
674 | { |
675 | EEprom9346 *eeprom = &s->eeprom; | |
676 | uint8_t old_eecs = eeprom->eecs; | |
677 | uint8_t old_eesk = eeprom->eesk; | |
678 | ||
679 | eeprom->eecs = eecs; | |
680 | eeprom->eesk = eesk; | |
681 | eeprom->eedi = eedi; | |
682 | ||
7cdeb319 BP |
683 | DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs, |
684 | eeprom->eesk, eeprom->eedi, eeprom->eedo); | |
a41b2ff2 PB |
685 | |
686 | if (!old_eecs && eecs) | |
687 | { | |
688 | /* Synchronize start */ | |
689 | eeprom->tick = 0; | |
690 | eeprom->input = 0; | |
691 | eeprom->output = 0; | |
692 | eeprom->mode = Chip9346_enter_command_mode; | |
693 | ||
7cdeb319 | 694 | DPRINTF("=== eeprom: begin access, enter command mode\n"); |
a41b2ff2 PB |
695 | } |
696 | ||
697 | if (!eecs) | |
698 | { | |
7cdeb319 | 699 | DPRINTF("=== eeprom: end access\n"); |
a41b2ff2 PB |
700 | return; |
701 | } | |
702 | ||
703 | if (!old_eesk && eesk) | |
704 | { | |
705 | /* SK front rules */ | |
706 | prom9346_shift_clock(eeprom); | |
707 | } | |
708 | } | |
709 | ||
710 | static void rtl8139_update_irq(RTL8139State *s) | |
711 | { | |
88a411a8 | 712 | PCIDevice *d = PCI_DEVICE(s); |
a41b2ff2 PB |
713 | int isr; |
714 | isr = (s->IntrStatus & s->IntrMask) & 0xffff; | |
6cadb320 | 715 | |
7cdeb319 BP |
716 | DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus, |
717 | s->IntrMask); | |
6cadb320 | 718 | |
9e64f8a3 | 719 | pci_set_irq(d, (isr != 0)); |
a41b2ff2 PB |
720 | } |
721 | ||
a41b2ff2 PB |
722 | static int rtl8139_RxWrap(RTL8139State *s) |
723 | { | |
724 | /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */ | |
725 | return (s->RxConfig & (1 << 7)); | |
726 | } | |
727 | ||
728 | static int rtl8139_receiver_enabled(RTL8139State *s) | |
729 | { | |
730 | return s->bChipCmdState & CmdRxEnb; | |
731 | } | |
732 | ||
733 | static int rtl8139_transmitter_enabled(RTL8139State *s) | |
734 | { | |
735 | return s->bChipCmdState & CmdTxEnb; | |
736 | } | |
737 | ||
738 | static int rtl8139_cp_receiver_enabled(RTL8139State *s) | |
739 | { | |
740 | return s->CpCmd & CPlusRxEnb; | |
741 | } | |
742 | ||
743 | static int rtl8139_cp_transmitter_enabled(RTL8139State *s) | |
744 | { | |
745 | return s->CpCmd & CPlusTxEnb; | |
746 | } | |
747 | ||
748 | static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) | |
749 | { | |
88a411a8 AF |
750 | PCIDevice *d = PCI_DEVICE(s); |
751 | ||
a41b2ff2 PB |
752 | if (s->RxBufAddr + size > s->RxBufferSize) |
753 | { | |
754 | int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize); | |
755 | ||
756 | /* write packet data */ | |
ccf1d14a | 757 | if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s))) |
a41b2ff2 | 758 | { |
7cdeb319 | 759 | DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped); |
a41b2ff2 PB |
760 | |
761 | if (size > wrapped) | |
762 | { | |
88a411a8 | 763 | pci_dma_write(d, s->RxBuf + s->RxBufAddr, |
3ada003a | 764 | buf, size-wrapped); |
a41b2ff2 PB |
765 | } |
766 | ||
767 | /* reset buffer pointer */ | |
768 | s->RxBufAddr = 0; | |
769 | ||
88a411a8 | 770 | pci_dma_write(d, s->RxBuf + s->RxBufAddr, |
3ada003a | 771 | buf + (size-wrapped), wrapped); |
a41b2ff2 PB |
772 | |
773 | s->RxBufAddr = wrapped; | |
774 | ||
775 | return; | |
776 | } | |
777 | } | |
778 | ||
779 | /* non-wrapping path or overwrapping enabled */ | |
88a411a8 | 780 | pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size); |
a41b2ff2 PB |
781 | |
782 | s->RxBufAddr += size; | |
783 | } | |
784 | ||
785 | #define MIN_BUF_SIZE 60 | |
3ada003a | 786 | static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high) |
a41b2ff2 | 787 | { |
4be403c8 | 788 | return low | ((uint64_t)high << 32); |
a41b2ff2 PB |
789 | } |
790 | ||
fcce6fd2 JW |
791 | /* Workaround for buggy guest driver such as linux who allocates rx |
792 | * rings after the receiver were enabled. */ | |
793 | static bool rtl8139_cp_rx_valid(RTL8139State *s) | |
794 | { | |
795 | return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0); | |
796 | } | |
797 | ||
4e68f7a0 | 798 | static int rtl8139_can_receive(NetClientState *nc) |
a41b2ff2 | 799 | { |
cc1f0f45 | 800 | RTL8139State *s = qemu_get_nic_opaque(nc); |
a41b2ff2 PB |
801 | int avail; |
802 | ||
aa1f17c1 | 803 | /* Receive (drop) packets if card is disabled. */ |
a41b2ff2 PB |
804 | if (!s->clock_enabled) |
805 | return 1; | |
806 | if (!rtl8139_receiver_enabled(s)) | |
807 | return 1; | |
808 | ||
fcce6fd2 | 809 | if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) { |
a41b2ff2 PB |
810 | /* ??? Flow control not implemented in c+ mode. |
811 | This is a hack to work around slirp deficiencies anyway. */ | |
812 | return 1; | |
813 | } else { | |
814 | avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, | |
815 | s->RxBufferSize); | |
fee9d348 | 816 | return (avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow)); |
a41b2ff2 PB |
817 | } |
818 | } | |
819 | ||
4e68f7a0 | 820 | static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt) |
a41b2ff2 | 821 | { |
cc1f0f45 | 822 | RTL8139State *s = qemu_get_nic_opaque(nc); |
88a411a8 | 823 | PCIDevice *d = PCI_DEVICE(s); |
18dabfd1 | 824 | /* size is the length of the buffer passed to the driver */ |
4f1c942b | 825 | int size = size_; |
18dabfd1 | 826 | const uint8_t *dot1q_buf = NULL; |
a41b2ff2 PB |
827 | |
828 | uint32_t packet_header = 0; | |
829 | ||
18dabfd1 | 830 | uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN]; |
5fafdf24 | 831 | static const uint8_t broadcast_macaddr[6] = |
a41b2ff2 PB |
832 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
833 | ||
7cdeb319 | 834 | DPRINTF(">>> received len=%d\n", size); |
a41b2ff2 PB |
835 | |
836 | /* test if board clock is stopped */ | |
837 | if (!s->clock_enabled) | |
838 | { | |
7cdeb319 | 839 | DPRINTF("stopped ==========================\n"); |
4f1c942b | 840 | return -1; |
a41b2ff2 PB |
841 | } |
842 | ||
843 | /* first check if receiver is enabled */ | |
844 | ||
845 | if (!rtl8139_receiver_enabled(s)) | |
846 | { | |
7cdeb319 | 847 | DPRINTF("receiver disabled ================\n"); |
4f1c942b | 848 | return -1; |
a41b2ff2 PB |
849 | } |
850 | ||
851 | /* XXX: check this */ | |
852 | if (s->RxConfig & AcceptAllPhys) { | |
853 | /* promiscuous: receive all */ | |
7cdeb319 | 854 | DPRINTF(">>> packet received in promiscuous mode\n"); |
a41b2ff2 PB |
855 | |
856 | } else { | |
857 | if (!memcmp(buf, broadcast_macaddr, 6)) { | |
858 | /* broadcast address */ | |
859 | if (!(s->RxConfig & AcceptBroadcast)) | |
860 | { | |
7cdeb319 | 861 | DPRINTF(">>> broadcast packet rejected\n"); |
6cadb320 FB |
862 | |
863 | /* update tally counter */ | |
864 | ++s->tally_counters.RxERR; | |
865 | ||
4f1c942b | 866 | return size; |
a41b2ff2 PB |
867 | } |
868 | ||
869 | packet_header |= RxBroadcast; | |
870 | ||
7cdeb319 | 871 | DPRINTF(">>> broadcast packet received\n"); |
6cadb320 FB |
872 | |
873 | /* update tally counter */ | |
874 | ++s->tally_counters.RxOkBrd; | |
875 | ||
a41b2ff2 PB |
876 | } else if (buf[0] & 0x01) { |
877 | /* multicast */ | |
878 | if (!(s->RxConfig & AcceptMulticast)) | |
879 | { | |
7cdeb319 | 880 | DPRINTF(">>> multicast packet rejected\n"); |
6cadb320 FB |
881 | |
882 | /* update tally counter */ | |
883 | ++s->tally_counters.RxERR; | |
884 | ||
4f1c942b | 885 | return size; |
a41b2ff2 PB |
886 | } |
887 | ||
888 | int mcast_idx = compute_mcast_idx(buf); | |
889 | ||
890 | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) | |
891 | { | |
7cdeb319 | 892 | DPRINTF(">>> multicast address mismatch\n"); |
6cadb320 FB |
893 | |
894 | /* update tally counter */ | |
895 | ++s->tally_counters.RxERR; | |
896 | ||
4f1c942b | 897 | return size; |
a41b2ff2 PB |
898 | } |
899 | ||
900 | packet_header |= RxMulticast; | |
901 | ||
7cdeb319 | 902 | DPRINTF(">>> multicast packet received\n"); |
6cadb320 FB |
903 | |
904 | /* update tally counter */ | |
905 | ++s->tally_counters.RxOkMul; | |
906 | ||
a41b2ff2 | 907 | } else if (s->phys[0] == buf[0] && |
3b46e624 TS |
908 | s->phys[1] == buf[1] && |
909 | s->phys[2] == buf[2] && | |
910 | s->phys[3] == buf[3] && | |
911 | s->phys[4] == buf[4] && | |
a41b2ff2 PB |
912 | s->phys[5] == buf[5]) { |
913 | /* match */ | |
914 | if (!(s->RxConfig & AcceptMyPhys)) | |
915 | { | |
7cdeb319 | 916 | DPRINTF(">>> rejecting physical address matching packet\n"); |
6cadb320 FB |
917 | |
918 | /* update tally counter */ | |
919 | ++s->tally_counters.RxERR; | |
920 | ||
4f1c942b | 921 | return size; |
a41b2ff2 PB |
922 | } |
923 | ||
924 | packet_header |= RxPhysical; | |
925 | ||
7cdeb319 | 926 | DPRINTF(">>> physical address matching packet received\n"); |
6cadb320 FB |
927 | |
928 | /* update tally counter */ | |
929 | ++s->tally_counters.RxOkPhy; | |
a41b2ff2 PB |
930 | |
931 | } else { | |
932 | ||
7cdeb319 | 933 | DPRINTF(">>> unknown packet\n"); |
6cadb320 FB |
934 | |
935 | /* update tally counter */ | |
936 | ++s->tally_counters.RxERR; | |
937 | ||
4f1c942b | 938 | return size; |
a41b2ff2 PB |
939 | } |
940 | } | |
941 | ||
18dabfd1 BP |
942 | /* if too small buffer, then expand it |
943 | * Include some tailroom in case a vlan tag is later removed. */ | |
944 | if (size < MIN_BUF_SIZE + VLAN_HLEN) { | |
a41b2ff2 | 945 | memcpy(buf1, buf, size); |
18dabfd1 | 946 | memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size); |
a41b2ff2 | 947 | buf = buf1; |
18dabfd1 BP |
948 | if (size < MIN_BUF_SIZE) { |
949 | size = MIN_BUF_SIZE; | |
950 | } | |
a41b2ff2 PB |
951 | } |
952 | ||
953 | if (rtl8139_cp_receiver_enabled(s)) | |
954 | { | |
fcce6fd2 JW |
955 | if (!rtl8139_cp_rx_valid(s)) { |
956 | return size; | |
957 | } | |
958 | ||
7cdeb319 | 959 | DPRINTF("in C+ Rx mode ================\n"); |
a41b2ff2 PB |
960 | |
961 | /* begin C+ receiver mode */ | |
962 | ||
963 | /* w0 ownership flag */ | |
964 | #define CP_RX_OWN (1<<31) | |
965 | /* w0 end of ring flag */ | |
966 | #define CP_RX_EOR (1<<30) | |
967 | /* w0 bits 0...12 : buffer size */ | |
968 | #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) | |
969 | /* w1 tag available flag */ | |
970 | #define CP_RX_TAVA (1<<16) | |
971 | /* w1 bits 0...15 : VLAN tag */ | |
972 | #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) | |
973 | /* w2 low 32bit of Rx buffer ptr */ | |
974 | /* w3 high 32bit of Rx buffer ptr */ | |
975 | ||
976 | int descriptor = s->currCPlusRxDesc; | |
3ada003a | 977 | dma_addr_t cplus_rx_ring_desc; |
a41b2ff2 PB |
978 | |
979 | cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); | |
980 | cplus_rx_ring_desc += 16 * descriptor; | |
981 | ||
7cdeb319 | 982 | DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at " |
3ada003a | 983 | "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI, |
7cdeb319 | 984 | s->RxRingAddrLO, cplus_rx_ring_desc); |
a41b2ff2 PB |
985 | |
986 | uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI; | |
987 | ||
88a411a8 | 988 | pci_dma_read(d, cplus_rx_ring_desc, &val, 4); |
a41b2ff2 | 989 | rxdw0 = le32_to_cpu(val); |
88a411a8 | 990 | pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4); |
a41b2ff2 | 991 | rxdw1 = le32_to_cpu(val); |
88a411a8 | 992 | pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4); |
a41b2ff2 | 993 | rxbufLO = le32_to_cpu(val); |
88a411a8 | 994 | pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4); |
a41b2ff2 PB |
995 | rxbufHI = le32_to_cpu(val); |
996 | ||
7cdeb319 BP |
997 | DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n", |
998 | descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI); | |
a41b2ff2 PB |
999 | |
1000 | if (!(rxdw0 & CP_RX_OWN)) | |
1001 | { | |
7cdeb319 BP |
1002 | DPRINTF("C+ Rx mode : descriptor %d is owned by host\n", |
1003 | descriptor); | |
6cadb320 | 1004 | |
a41b2ff2 PB |
1005 | s->IntrStatus |= RxOverflow; |
1006 | ++s->RxMissed; | |
6cadb320 FB |
1007 | |
1008 | /* update tally counter */ | |
1009 | ++s->tally_counters.RxERR; | |
1010 | ++s->tally_counters.MissPkt; | |
1011 | ||
a41b2ff2 | 1012 | rtl8139_update_irq(s); |
4f1c942b | 1013 | return size_; |
a41b2ff2 PB |
1014 | } |
1015 | ||
1016 | uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; | |
1017 | ||
18dabfd1 BP |
1018 | /* write VLAN info to descriptor variables. */ |
1019 | if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *) | |
1020 | &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) { | |
1021 | dot1q_buf = &buf[ETHER_ADDR_LEN * 2]; | |
1022 | size -= VLAN_HLEN; | |
1023 | /* if too small buffer, use the tailroom added duing expansion */ | |
1024 | if (size < MIN_BUF_SIZE) { | |
1025 | size = MIN_BUF_SIZE; | |
1026 | } | |
1027 | ||
1028 | rxdw1 &= ~CP_RX_VLAN_TAG_MASK; | |
1029 | /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */ | |
1030 | rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *) | |
1031 | &dot1q_buf[ETHER_TYPE_LEN]); | |
1032 | ||
7cdeb319 BP |
1033 | DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n", |
1034 | be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN])); | |
18dabfd1 BP |
1035 | } else { |
1036 | /* reset VLAN tag flag */ | |
1037 | rxdw1 &= ~CP_RX_TAVA; | |
1038 | } | |
1039 | ||
6cadb320 FB |
1040 | /* TODO: scatter the packet over available receive ring descriptors space */ |
1041 | ||
a41b2ff2 PB |
1042 | if (size+4 > rx_space) |
1043 | { | |
7cdeb319 BP |
1044 | DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n", |
1045 | descriptor, rx_space, size); | |
6cadb320 | 1046 | |
a41b2ff2 PB |
1047 | s->IntrStatus |= RxOverflow; |
1048 | ++s->RxMissed; | |
6cadb320 FB |
1049 | |
1050 | /* update tally counter */ | |
1051 | ++s->tally_counters.RxERR; | |
1052 | ++s->tally_counters.MissPkt; | |
1053 | ||
a41b2ff2 | 1054 | rtl8139_update_irq(s); |
4f1c942b | 1055 | return size_; |
a41b2ff2 PB |
1056 | } |
1057 | ||
3ada003a | 1058 | dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); |
a41b2ff2 PB |
1059 | |
1060 | /* receive/copy to target memory */ | |
18dabfd1 | 1061 | if (dot1q_buf) { |
88a411a8 AF |
1062 | pci_dma_write(d, rx_addr, buf, 2 * ETHER_ADDR_LEN); |
1063 | pci_dma_write(d, rx_addr + 2 * ETHER_ADDR_LEN, | |
3ada003a EGM |
1064 | buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN, |
1065 | size - 2 * ETHER_ADDR_LEN); | |
18dabfd1 | 1066 | } else { |
88a411a8 | 1067 | pci_dma_write(d, rx_addr, buf, size); |
18dabfd1 | 1068 | } |
a41b2ff2 | 1069 | |
6cadb320 FB |
1070 | if (s->CpCmd & CPlusRxChkSum) |
1071 | { | |
1072 | /* do some packet checksumming */ | |
1073 | } | |
1074 | ||
a41b2ff2 | 1075 | /* write checksum */ |
18dabfd1 | 1076 | val = cpu_to_le32(crc32(0, buf, size_)); |
88a411a8 | 1077 | pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4); |
a41b2ff2 PB |
1078 | |
1079 | /* first segment of received packet flag */ | |
1080 | #define CP_RX_STATUS_FS (1<<29) | |
1081 | /* last segment of received packet flag */ | |
1082 | #define CP_RX_STATUS_LS (1<<28) | |
1083 | /* multicast packet flag */ | |
1084 | #define CP_RX_STATUS_MAR (1<<26) | |
1085 | /* physical-matching packet flag */ | |
1086 | #define CP_RX_STATUS_PAM (1<<25) | |
1087 | /* broadcast packet flag */ | |
1088 | #define CP_RX_STATUS_BAR (1<<24) | |
1089 | /* runt packet flag */ | |
1090 | #define CP_RX_STATUS_RUNT (1<<19) | |
1091 | /* crc error flag */ | |
1092 | #define CP_RX_STATUS_CRC (1<<18) | |
1093 | /* IP checksum error flag */ | |
1094 | #define CP_RX_STATUS_IPF (1<<15) | |
1095 | /* UDP checksum error flag */ | |
1096 | #define CP_RX_STATUS_UDPF (1<<14) | |
1097 | /* TCP checksum error flag */ | |
1098 | #define CP_RX_STATUS_TCPF (1<<13) | |
1099 | ||
1100 | /* transfer ownership to target */ | |
1101 | rxdw0 &= ~CP_RX_OWN; | |
1102 | ||
1103 | /* set first segment bit */ | |
1104 | rxdw0 |= CP_RX_STATUS_FS; | |
1105 | ||
1106 | /* set last segment bit */ | |
1107 | rxdw0 |= CP_RX_STATUS_LS; | |
1108 | ||
1109 | /* set received packet type flags */ | |
1110 | if (packet_header & RxBroadcast) | |
1111 | rxdw0 |= CP_RX_STATUS_BAR; | |
1112 | if (packet_header & RxMulticast) | |
1113 | rxdw0 |= CP_RX_STATUS_MAR; | |
1114 | if (packet_header & RxPhysical) | |
1115 | rxdw0 |= CP_RX_STATUS_PAM; | |
1116 | ||
1117 | /* set received size */ | |
1118 | rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; | |
1119 | rxdw0 |= (size+4); | |
1120 | ||
a41b2ff2 PB |
1121 | /* update ring data */ |
1122 | val = cpu_to_le32(rxdw0); | |
88a411a8 | 1123 | pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4); |
a41b2ff2 | 1124 | val = cpu_to_le32(rxdw1); |
88a411a8 | 1125 | pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4); |
a41b2ff2 | 1126 | |
6cadb320 FB |
1127 | /* update tally counter */ |
1128 | ++s->tally_counters.RxOk; | |
1129 | ||
a41b2ff2 PB |
1130 | /* seek to next Rx descriptor */ |
1131 | if (rxdw0 & CP_RX_EOR) | |
1132 | { | |
1133 | s->currCPlusRxDesc = 0; | |
1134 | } | |
1135 | else | |
1136 | { | |
1137 | ++s->currCPlusRxDesc; | |
1138 | } | |
1139 | ||
7cdeb319 | 1140 | DPRINTF("done C+ Rx mode ----------------\n"); |
a41b2ff2 PB |
1141 | |
1142 | } | |
1143 | else | |
1144 | { | |
7cdeb319 | 1145 | DPRINTF("in ring Rx mode ================\n"); |
6cadb320 | 1146 | |
a41b2ff2 PB |
1147 | /* begin ring receiver mode */ |
1148 | int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize); | |
1149 | ||
1150 | /* if receiver buffer is empty then avail == 0 */ | |
1151 | ||
1152 | if (avail != 0 && size + 8 >= avail) | |
1153 | { | |
7cdeb319 BP |
1154 | DPRINTF("rx overflow: rx buffer length %d head 0x%04x " |
1155 | "read 0x%04x === available 0x%04x need 0x%04x\n", | |
1156 | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8); | |
6cadb320 | 1157 | |
a41b2ff2 PB |
1158 | s->IntrStatus |= RxOverflow; |
1159 | ++s->RxMissed; | |
1160 | rtl8139_update_irq(s); | |
4f1c942b | 1161 | return size_; |
a41b2ff2 PB |
1162 | } |
1163 | ||
1164 | packet_header |= RxStatusOK; | |
1165 | ||
1166 | packet_header |= (((size+4) << 16) & 0xffff0000); | |
1167 | ||
1168 | /* write header */ | |
1169 | uint32_t val = cpu_to_le32(packet_header); | |
1170 | ||
1171 | rtl8139_write_buffer(s, (uint8_t *)&val, 4); | |
1172 | ||
1173 | rtl8139_write_buffer(s, buf, size); | |
1174 | ||
1175 | /* write checksum */ | |
ccf1d14a | 1176 | val = cpu_to_le32(crc32(0, buf, size)); |
a41b2ff2 PB |
1177 | rtl8139_write_buffer(s, (uint8_t *)&val, 4); |
1178 | ||
1179 | /* correct buffer write pointer */ | |
1180 | s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize); | |
1181 | ||
1182 | /* now we can signal we have received something */ | |
1183 | ||
7cdeb319 BP |
1184 | DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n", |
1185 | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); | |
a41b2ff2 PB |
1186 | } |
1187 | ||
1188 | s->IntrStatus |= RxOK; | |
6cadb320 FB |
1189 | |
1190 | if (do_interrupt) | |
1191 | { | |
1192 | rtl8139_update_irq(s); | |
1193 | } | |
4f1c942b MM |
1194 | |
1195 | return size_; | |
6cadb320 FB |
1196 | } |
1197 | ||
4e68f7a0 | 1198 | static ssize_t rtl8139_receive(NetClientState *nc, const uint8_t *buf, size_t size) |
6cadb320 | 1199 | { |
1673ad51 | 1200 | return rtl8139_do_receive(nc, buf, size, 1); |
a41b2ff2 PB |
1201 | } |
1202 | ||
1203 | static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) | |
1204 | { | |
1205 | s->RxBufferSize = bufferSize; | |
1206 | s->RxBufPtr = 0; | |
1207 | s->RxBufAddr = 0; | |
1208 | } | |
1209 | ||
7f23f812 | 1210 | static void rtl8139_reset(DeviceState *d) |
a41b2ff2 | 1211 | { |
39257515 | 1212 | RTL8139State *s = RTL8139(d); |
a41b2ff2 PB |
1213 | int i; |
1214 | ||
1215 | /* restore MAC address */ | |
254111ec | 1216 | memcpy(s->phys, s->conf.macaddr.a, 6); |
a41b2ff2 PB |
1217 | |
1218 | /* reset interrupt mask */ | |
1219 | s->IntrStatus = 0; | |
1220 | s->IntrMask = 0; | |
1221 | ||
1222 | rtl8139_update_irq(s); | |
1223 | ||
a41b2ff2 PB |
1224 | /* mark all status registers as owned by host */ |
1225 | for (i = 0; i < 4; ++i) | |
1226 | { | |
1227 | s->TxStatus[i] = TxHostOwns; | |
1228 | } | |
1229 | ||
1230 | s->currTxDesc = 0; | |
1231 | s->currCPlusRxDesc = 0; | |
1232 | s->currCPlusTxDesc = 0; | |
1233 | ||
1234 | s->RxRingAddrLO = 0; | |
1235 | s->RxRingAddrHI = 0; | |
1236 | ||
1237 | s->RxBuf = 0; | |
1238 | ||
1239 | rtl8139_reset_rxring(s, 8192); | |
1240 | ||
1241 | /* ACK the reset */ | |
1242 | s->TxConfig = 0; | |
1243 | ||
1244 | #if 0 | |
1245 | // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk | |
1246 | s->clock_enabled = 0; | |
1247 | #else | |
6cadb320 | 1248 | s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake |
a41b2ff2 PB |
1249 | s->clock_enabled = 1; |
1250 | #endif | |
1251 | ||
1252 | s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */; | |
1253 | ||
1254 | /* set initial state data */ | |
1255 | s->Config0 = 0x0; /* No boot ROM */ | |
1256 | s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ | |
1257 | s->Config3 = 0x1; /* fast back-to-back compatible */ | |
1258 | s->Config5 = 0x0; | |
1259 | ||
5fafdf24 | 1260 | s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; |
a41b2ff2 PB |
1261 | |
1262 | s->CpCmd = 0x0; /* reset C+ mode */ | |
2c3891ab AL |
1263 | s->cplus_enabled = 0; |
1264 | ||
a41b2ff2 PB |
1265 | |
1266 | // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation | |
1267 | // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex | |
1268 | s->BasicModeCtrl = 0x1000; // autonegotiation | |
1269 | ||
1270 | s->BasicModeStatus = 0x7809; | |
1271 | //s->BasicModeStatus |= 0x0040; /* UTP medium */ | |
1272 | s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ | |
83f58e57 | 1273 | /* preserve link state */ |
b356f76d | 1274 | s->BasicModeStatus |= qemu_get_queue(s->nic)->link_down ? 0 : 0x04; |
a41b2ff2 PB |
1275 | |
1276 | s->NWayAdvert = 0x05e1; /* all modes, full duplex */ | |
1277 | s->NWayLPAR = 0x05e1; /* all modes, full duplex */ | |
1278 | s->NWayExpansion = 0x0001; /* autonegotiation supported */ | |
6cadb320 FB |
1279 | |
1280 | /* also reset timer and disable timer interrupt */ | |
1281 | s->TCTR = 0; | |
1282 | s->TimerInt = 0; | |
1283 | s->TCTR_base = 0; | |
1284 | ||
1285 | /* reset tally counters */ | |
1286 | RTL8139TallyCounters_clear(&s->tally_counters); | |
1287 | } | |
1288 | ||
b1d8e52e | 1289 | static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters) |
6cadb320 FB |
1290 | { |
1291 | counters->TxOk = 0; | |
1292 | counters->RxOk = 0; | |
1293 | counters->TxERR = 0; | |
1294 | counters->RxERR = 0; | |
1295 | counters->MissPkt = 0; | |
1296 | counters->FAE = 0; | |
1297 | counters->Tx1Col = 0; | |
1298 | counters->TxMCol = 0; | |
1299 | counters->RxOkPhy = 0; | |
1300 | counters->RxOkBrd = 0; | |
1301 | counters->RxOkMul = 0; | |
1302 | counters->TxAbt = 0; | |
1303 | counters->TxUndrn = 0; | |
1304 | } | |
1305 | ||
3ada003a | 1306 | static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr) |
6cadb320 | 1307 | { |
88a411a8 | 1308 | PCIDevice *d = PCI_DEVICE(s); |
3ada003a | 1309 | RTL8139TallyCounters *tally_counters = &s->tally_counters; |
6cadb320 FB |
1310 | uint16_t val16; |
1311 | uint32_t val32; | |
1312 | uint64_t val64; | |
1313 | ||
1314 | val64 = cpu_to_le64(tally_counters->TxOk); | |
88a411a8 | 1315 | pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8); |
6cadb320 FB |
1316 | |
1317 | val64 = cpu_to_le64(tally_counters->RxOk); | |
88a411a8 | 1318 | pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8); |
6cadb320 FB |
1319 | |
1320 | val64 = cpu_to_le64(tally_counters->TxERR); | |
88a411a8 | 1321 | pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8); |
6cadb320 FB |
1322 | |
1323 | val32 = cpu_to_le32(tally_counters->RxERR); | |
88a411a8 | 1324 | pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4); |
6cadb320 FB |
1325 | |
1326 | val16 = cpu_to_le16(tally_counters->MissPkt); | |
88a411a8 | 1327 | pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2); |
6cadb320 FB |
1328 | |
1329 | val16 = cpu_to_le16(tally_counters->FAE); | |
88a411a8 | 1330 | pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2); |
6cadb320 FB |
1331 | |
1332 | val32 = cpu_to_le32(tally_counters->Tx1Col); | |
88a411a8 | 1333 | pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4); |
6cadb320 FB |
1334 | |
1335 | val32 = cpu_to_le32(tally_counters->TxMCol); | |
88a411a8 | 1336 | pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4); |
6cadb320 FB |
1337 | |
1338 | val64 = cpu_to_le64(tally_counters->RxOkPhy); | |
88a411a8 | 1339 | pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8); |
6cadb320 FB |
1340 | |
1341 | val64 = cpu_to_le64(tally_counters->RxOkBrd); | |
88a411a8 | 1342 | pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8); |
6cadb320 FB |
1343 | |
1344 | val32 = cpu_to_le32(tally_counters->RxOkMul); | |
88a411a8 | 1345 | pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4); |
6cadb320 FB |
1346 | |
1347 | val16 = cpu_to_le16(tally_counters->TxAbt); | |
88a411a8 | 1348 | pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2); |
6cadb320 FB |
1349 | |
1350 | val16 = cpu_to_le16(tally_counters->TxUndrn); | |
88a411a8 | 1351 | pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2); |
6cadb320 FB |
1352 | } |
1353 | ||
1354 | /* Loads values of tally counters from VM state file */ | |
9d29cdea JQ |
1355 | |
1356 | static const VMStateDescription vmstate_tally_counters = { | |
1357 | .name = "tally_counters", | |
1358 | .version_id = 1, | |
1359 | .minimum_version_id = 1, | |
1360 | .minimum_version_id_old = 1, | |
1361 | .fields = (VMStateField []) { | |
1362 | VMSTATE_UINT64(TxOk, RTL8139TallyCounters), | |
1363 | VMSTATE_UINT64(RxOk, RTL8139TallyCounters), | |
1364 | VMSTATE_UINT64(TxERR, RTL8139TallyCounters), | |
1365 | VMSTATE_UINT32(RxERR, RTL8139TallyCounters), | |
1366 | VMSTATE_UINT16(MissPkt, RTL8139TallyCounters), | |
1367 | VMSTATE_UINT16(FAE, RTL8139TallyCounters), | |
1368 | VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters), | |
1369 | VMSTATE_UINT32(TxMCol, RTL8139TallyCounters), | |
1370 | VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters), | |
1371 | VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters), | |
1372 | VMSTATE_UINT16(TxAbt, RTL8139TallyCounters), | |
1373 | VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters), | |
1374 | VMSTATE_END_OF_LIST() | |
1375 | } | |
1376 | }; | |
a41b2ff2 PB |
1377 | |
1378 | static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val) | |
1379 | { | |
39257515 PC |
1380 | DeviceState *d = DEVICE(s); |
1381 | ||
a41b2ff2 PB |
1382 | val &= 0xff; |
1383 | ||
7cdeb319 | 1384 | DPRINTF("ChipCmd write val=0x%08x\n", val); |
a41b2ff2 PB |
1385 | |
1386 | if (val & CmdReset) | |
1387 | { | |
7cdeb319 | 1388 | DPRINTF("ChipCmd reset\n"); |
39257515 | 1389 | rtl8139_reset(d); |
a41b2ff2 PB |
1390 | } |
1391 | if (val & CmdRxEnb) | |
1392 | { | |
7cdeb319 | 1393 | DPRINTF("ChipCmd enable receiver\n"); |
718da2b9 FB |
1394 | |
1395 | s->currCPlusRxDesc = 0; | |
a41b2ff2 PB |
1396 | } |
1397 | if (val & CmdTxEnb) | |
1398 | { | |
7cdeb319 | 1399 | DPRINTF("ChipCmd enable transmitter\n"); |
718da2b9 FB |
1400 | |
1401 | s->currCPlusTxDesc = 0; | |
a41b2ff2 PB |
1402 | } |
1403 | ||
ebabb67a | 1404 | /* mask unwritable bits */ |
a41b2ff2 PB |
1405 | val = SET_MASKED(val, 0xe3, s->bChipCmdState); |
1406 | ||
1407 | /* Deassert reset pin before next read */ | |
1408 | val &= ~CmdReset; | |
1409 | ||
1410 | s->bChipCmdState = val; | |
1411 | } | |
1412 | ||
1413 | static int rtl8139_RxBufferEmpty(RTL8139State *s) | |
1414 | { | |
1415 | int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize); | |
1416 | ||
1417 | if (unread != 0) | |
1418 | { | |
7cdeb319 | 1419 | DPRINTF("receiver buffer data available 0x%04x\n", unread); |
a41b2ff2 PB |
1420 | return 0; |
1421 | } | |
1422 | ||
7cdeb319 | 1423 | DPRINTF("receiver buffer is empty\n"); |
a41b2ff2 PB |
1424 | |
1425 | return 1; | |
1426 | } | |
1427 | ||
1428 | static uint32_t rtl8139_ChipCmd_read(RTL8139State *s) | |
1429 | { | |
1430 | uint32_t ret = s->bChipCmdState; | |
1431 | ||
1432 | if (rtl8139_RxBufferEmpty(s)) | |
1433 | ret |= RxBufEmpty; | |
1434 | ||
7cdeb319 | 1435 | DPRINTF("ChipCmd read val=0x%04x\n", ret); |
a41b2ff2 PB |
1436 | |
1437 | return ret; | |
1438 | } | |
1439 | ||
1440 | static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val) | |
1441 | { | |
1442 | val &= 0xffff; | |
1443 | ||
7cdeb319 | 1444 | DPRINTF("C+ command register write(w) val=0x%04x\n", val); |
a41b2ff2 | 1445 | |
2c3891ab AL |
1446 | s->cplus_enabled = 1; |
1447 | ||
ebabb67a | 1448 | /* mask unwritable bits */ |
a41b2ff2 PB |
1449 | val = SET_MASKED(val, 0xff84, s->CpCmd); |
1450 | ||
1451 | s->CpCmd = val; | |
1452 | } | |
1453 | ||
1454 | static uint32_t rtl8139_CpCmd_read(RTL8139State *s) | |
1455 | { | |
1456 | uint32_t ret = s->CpCmd; | |
1457 | ||
7cdeb319 | 1458 | DPRINTF("C+ command register read(w) val=0x%04x\n", ret); |
6cadb320 FB |
1459 | |
1460 | return ret; | |
1461 | } | |
1462 | ||
1463 | static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val) | |
1464 | { | |
7cdeb319 | 1465 | DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val); |
6cadb320 FB |
1466 | } |
1467 | ||
1468 | static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s) | |
1469 | { | |
1470 | uint32_t ret = 0; | |
1471 | ||
7cdeb319 | 1472 | DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret); |
a41b2ff2 PB |
1473 | |
1474 | return ret; | |
1475 | } | |
1476 | ||
ebabb67a | 1477 | static int rtl8139_config_writable(RTL8139State *s) |
a41b2ff2 | 1478 | { |
eb46c5ed | 1479 | if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite) |
a41b2ff2 PB |
1480 | { |
1481 | return 1; | |
1482 | } | |
1483 | ||
7cdeb319 | 1484 | DPRINTF("Configuration registers are write-protected\n"); |
a41b2ff2 PB |
1485 | |
1486 | return 0; | |
1487 | } | |
1488 | ||
1489 | static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val) | |
1490 | { | |
1491 | val &= 0xffff; | |
1492 | ||
7cdeb319 | 1493 | DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val); |
a41b2ff2 | 1494 | |
ebabb67a | 1495 | /* mask unwritable bits */ |
e3d7e843 | 1496 | uint32_t mask = 0x4cff; |
a41b2ff2 | 1497 | |
ebabb67a | 1498 | if (1 || !rtl8139_config_writable(s)) |
a41b2ff2 PB |
1499 | { |
1500 | /* Speed setting and autonegotiation enable bits are read-only */ | |
1501 | mask |= 0x3000; | |
1502 | /* Duplex mode setting is read-only */ | |
1503 | mask |= 0x0100; | |
1504 | } | |
1505 | ||
1506 | val = SET_MASKED(val, mask, s->BasicModeCtrl); | |
1507 | ||
1508 | s->BasicModeCtrl = val; | |
1509 | } | |
1510 | ||
1511 | static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s) | |
1512 | { | |
1513 | uint32_t ret = s->BasicModeCtrl; | |
1514 | ||
7cdeb319 | 1515 | DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret); |
a41b2ff2 PB |
1516 | |
1517 | return ret; | |
1518 | } | |
1519 | ||
1520 | static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val) | |
1521 | { | |
1522 | val &= 0xffff; | |
1523 | ||
7cdeb319 | 1524 | DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val); |
a41b2ff2 | 1525 | |
ebabb67a | 1526 | /* mask unwritable bits */ |
a41b2ff2 PB |
1527 | val = SET_MASKED(val, 0xff3f, s->BasicModeStatus); |
1528 | ||
1529 | s->BasicModeStatus = val; | |
1530 | } | |
1531 | ||
1532 | static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s) | |
1533 | { | |
1534 | uint32_t ret = s->BasicModeStatus; | |
1535 | ||
7cdeb319 | 1536 | DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret); |
a41b2ff2 PB |
1537 | |
1538 | return ret; | |
1539 | } | |
1540 | ||
1541 | static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) | |
1542 | { | |
39257515 PC |
1543 | DeviceState *d = DEVICE(s); |
1544 | ||
a41b2ff2 PB |
1545 | val &= 0xff; |
1546 | ||
7cdeb319 | 1547 | DPRINTF("Cfg9346 write val=0x%02x\n", val); |
a41b2ff2 | 1548 | |
ebabb67a | 1549 | /* mask unwritable bits */ |
a41b2ff2 PB |
1550 | val = SET_MASKED(val, 0x31, s->Cfg9346); |
1551 | ||
1552 | uint32_t opmode = val & 0xc0; | |
1553 | uint32_t eeprom_val = val & 0xf; | |
1554 | ||
1555 | if (opmode == 0x80) { | |
1556 | /* eeprom access */ | |
1557 | int eecs = (eeprom_val & 0x08)?1:0; | |
1558 | int eesk = (eeprom_val & 0x04)?1:0; | |
1559 | int eedi = (eeprom_val & 0x02)?1:0; | |
1560 | prom9346_set_wire(s, eecs, eesk, eedi); | |
1561 | } else if (opmode == 0x40) { | |
1562 | /* Reset. */ | |
1563 | val = 0; | |
39257515 | 1564 | rtl8139_reset(d); |
a41b2ff2 PB |
1565 | } |
1566 | ||
1567 | s->Cfg9346 = val; | |
1568 | } | |
1569 | ||
1570 | static uint32_t rtl8139_Cfg9346_read(RTL8139State *s) | |
1571 | { | |
1572 | uint32_t ret = s->Cfg9346; | |
1573 | ||
1574 | uint32_t opmode = ret & 0xc0; | |
1575 | ||
1576 | if (opmode == 0x80) | |
1577 | { | |
1578 | /* eeprom access */ | |
1579 | int eedo = prom9346_get_wire(s); | |
1580 | if (eedo) | |
1581 | { | |
1582 | ret |= 0x01; | |
1583 | } | |
1584 | else | |
1585 | { | |
1586 | ret &= ~0x01; | |
1587 | } | |
1588 | } | |
1589 | ||
7cdeb319 | 1590 | DPRINTF("Cfg9346 read val=0x%02x\n", ret); |
a41b2ff2 PB |
1591 | |
1592 | return ret; | |
1593 | } | |
1594 | ||
1595 | static void rtl8139_Config0_write(RTL8139State *s, uint32_t val) | |
1596 | { | |
1597 | val &= 0xff; | |
1598 | ||
7cdeb319 | 1599 | DPRINTF("Config0 write val=0x%02x\n", val); |
a41b2ff2 | 1600 | |
ebabb67a | 1601 | if (!rtl8139_config_writable(s)) { |
a41b2ff2 | 1602 | return; |
ebabb67a | 1603 | } |
a41b2ff2 | 1604 | |
ebabb67a | 1605 | /* mask unwritable bits */ |
a41b2ff2 PB |
1606 | val = SET_MASKED(val, 0xf8, s->Config0); |
1607 | ||
1608 | s->Config0 = val; | |
1609 | } | |
1610 | ||
1611 | static uint32_t rtl8139_Config0_read(RTL8139State *s) | |
1612 | { | |
1613 | uint32_t ret = s->Config0; | |
1614 | ||
7cdeb319 | 1615 | DPRINTF("Config0 read val=0x%02x\n", ret); |
a41b2ff2 PB |
1616 | |
1617 | return ret; | |
1618 | } | |
1619 | ||
1620 | static void rtl8139_Config1_write(RTL8139State *s, uint32_t val) | |
1621 | { | |
1622 | val &= 0xff; | |
1623 | ||
7cdeb319 | 1624 | DPRINTF("Config1 write val=0x%02x\n", val); |
a41b2ff2 | 1625 | |
ebabb67a | 1626 | if (!rtl8139_config_writable(s)) { |
a41b2ff2 | 1627 | return; |
ebabb67a | 1628 | } |
a41b2ff2 | 1629 | |
ebabb67a | 1630 | /* mask unwritable bits */ |
a41b2ff2 PB |
1631 | val = SET_MASKED(val, 0xC, s->Config1); |
1632 | ||
1633 | s->Config1 = val; | |
1634 | } | |
1635 | ||
1636 | static uint32_t rtl8139_Config1_read(RTL8139State *s) | |
1637 | { | |
1638 | uint32_t ret = s->Config1; | |
1639 | ||
7cdeb319 | 1640 | DPRINTF("Config1 read val=0x%02x\n", ret); |
a41b2ff2 PB |
1641 | |
1642 | return ret; | |
1643 | } | |
1644 | ||
1645 | static void rtl8139_Config3_write(RTL8139State *s, uint32_t val) | |
1646 | { | |
1647 | val &= 0xff; | |
1648 | ||
7cdeb319 | 1649 | DPRINTF("Config3 write val=0x%02x\n", val); |
a41b2ff2 | 1650 | |
ebabb67a | 1651 | if (!rtl8139_config_writable(s)) { |
a41b2ff2 | 1652 | return; |
ebabb67a | 1653 | } |
a41b2ff2 | 1654 | |
ebabb67a | 1655 | /* mask unwritable bits */ |
a41b2ff2 PB |
1656 | val = SET_MASKED(val, 0x8F, s->Config3); |
1657 | ||
1658 | s->Config3 = val; | |
1659 | } | |
1660 | ||
1661 | static uint32_t rtl8139_Config3_read(RTL8139State *s) | |
1662 | { | |
1663 | uint32_t ret = s->Config3; | |
1664 | ||
7cdeb319 | 1665 | DPRINTF("Config3 read val=0x%02x\n", ret); |
a41b2ff2 PB |
1666 | |
1667 | return ret; | |
1668 | } | |
1669 | ||
1670 | static void rtl8139_Config4_write(RTL8139State *s, uint32_t val) | |
1671 | { | |
1672 | val &= 0xff; | |
1673 | ||
7cdeb319 | 1674 | DPRINTF("Config4 write val=0x%02x\n", val); |
a41b2ff2 | 1675 | |
ebabb67a | 1676 | if (!rtl8139_config_writable(s)) { |
a41b2ff2 | 1677 | return; |
ebabb67a | 1678 | } |
a41b2ff2 | 1679 | |
ebabb67a | 1680 | /* mask unwritable bits */ |
a41b2ff2 PB |
1681 | val = SET_MASKED(val, 0x0a, s->Config4); |
1682 | ||
1683 | s->Config4 = val; | |
1684 | } | |
1685 | ||
1686 | static uint32_t rtl8139_Config4_read(RTL8139State *s) | |
1687 | { | |
1688 | uint32_t ret = s->Config4; | |
1689 | ||
7cdeb319 | 1690 | DPRINTF("Config4 read val=0x%02x\n", ret); |
a41b2ff2 PB |
1691 | |
1692 | return ret; | |
1693 | } | |
1694 | ||
1695 | static void rtl8139_Config5_write(RTL8139State *s, uint32_t val) | |
1696 | { | |
1697 | val &= 0xff; | |
1698 | ||
7cdeb319 | 1699 | DPRINTF("Config5 write val=0x%02x\n", val); |
a41b2ff2 | 1700 | |
ebabb67a | 1701 | /* mask unwritable bits */ |
a41b2ff2 PB |
1702 | val = SET_MASKED(val, 0x80, s->Config5); |
1703 | ||
1704 | s->Config5 = val; | |
1705 | } | |
1706 | ||
1707 | static uint32_t rtl8139_Config5_read(RTL8139State *s) | |
1708 | { | |
1709 | uint32_t ret = s->Config5; | |
1710 | ||
7cdeb319 | 1711 | DPRINTF("Config5 read val=0x%02x\n", ret); |
a41b2ff2 PB |
1712 | |
1713 | return ret; | |
1714 | } | |
1715 | ||
1716 | static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val) | |
1717 | { | |
1718 | if (!rtl8139_transmitter_enabled(s)) | |
1719 | { | |
7cdeb319 | 1720 | DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val); |
a41b2ff2 PB |
1721 | return; |
1722 | } | |
1723 | ||
7cdeb319 | 1724 | DPRINTF("TxConfig write val=0x%08x\n", val); |
a41b2ff2 PB |
1725 | |
1726 | val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig); | |
1727 | ||
1728 | s->TxConfig = val; | |
1729 | } | |
1730 | ||
1731 | static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val) | |
1732 | { | |
7cdeb319 | 1733 | DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val); |
6cadb320 FB |
1734 | |
1735 | uint32_t tc = s->TxConfig; | |
1736 | tc &= 0xFFFFFF00; | |
1737 | tc |= (val & 0x000000FF); | |
1738 | rtl8139_TxConfig_write(s, tc); | |
a41b2ff2 PB |
1739 | } |
1740 | ||
1741 | static uint32_t rtl8139_TxConfig_read(RTL8139State *s) | |
1742 | { | |
1743 | uint32_t ret = s->TxConfig; | |
1744 | ||
7cdeb319 | 1745 | DPRINTF("TxConfig read val=0x%04x\n", ret); |
a41b2ff2 PB |
1746 | |
1747 | return ret; | |
1748 | } | |
1749 | ||
1750 | static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val) | |
1751 | { | |
7cdeb319 | 1752 | DPRINTF("RxConfig write val=0x%08x\n", val); |
a41b2ff2 | 1753 | |
ebabb67a | 1754 | /* mask unwritable bits */ |
a41b2ff2 PB |
1755 | val = SET_MASKED(val, 0xf0fc0040, s->RxConfig); |
1756 | ||
1757 | s->RxConfig = val; | |
1758 | ||
1759 | /* reset buffer size and read/write pointers */ | |
1760 | rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); | |
1761 | ||
7cdeb319 | 1762 | DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize); |
a41b2ff2 PB |
1763 | } |
1764 | ||
1765 | static uint32_t rtl8139_RxConfig_read(RTL8139State *s) | |
1766 | { | |
1767 | uint32_t ret = s->RxConfig; | |
1768 | ||
7cdeb319 | 1769 | DPRINTF("RxConfig read val=0x%08x\n", ret); |
a41b2ff2 PB |
1770 | |
1771 | return ret; | |
1772 | } | |
1773 | ||
bf6b87a8 BP |
1774 | static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size, |
1775 | int do_interrupt, const uint8_t *dot1q_buf) | |
718da2b9 | 1776 | { |
bf6b87a8 BP |
1777 | struct iovec *iov = NULL; |
1778 | ||
718da2b9 FB |
1779 | if (!size) |
1780 | { | |
7cdeb319 | 1781 | DPRINTF("+++ empty ethernet frame\n"); |
718da2b9 FB |
1782 | return; |
1783 | } | |
1784 | ||
bf6b87a8 BP |
1785 | if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) { |
1786 | iov = (struct iovec[3]) { | |
1787 | { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 }, | |
1788 | { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN }, | |
1789 | { .iov_base = buf + ETHER_ADDR_LEN * 2, | |
1790 | .iov_len = size - ETHER_ADDR_LEN * 2 }, | |
1791 | }; | |
1792 | } | |
1793 | ||
718da2b9 FB |
1794 | if (TxLoopBack == (s->TxConfig & TxLoopBack)) |
1795 | { | |
bf6b87a8 BP |
1796 | size_t buf2_size; |
1797 | uint8_t *buf2; | |
1798 | ||
1799 | if (iov) { | |
1800 | buf2_size = iov_size(iov, 3); | |
7267c094 | 1801 | buf2 = g_malloc(buf2_size); |
dcf6f5e1 | 1802 | iov_to_buf(iov, 3, 0, buf2, buf2_size); |
bf6b87a8 BP |
1803 | buf = buf2; |
1804 | } | |
1805 | ||
7cdeb319 | 1806 | DPRINTF("+++ transmit loopback mode\n"); |
b356f76d | 1807 | rtl8139_do_receive(qemu_get_queue(s->nic), buf, size, do_interrupt); |
bf6b87a8 BP |
1808 | |
1809 | if (iov) { | |
7267c094 | 1810 | g_free(buf2); |
bf6b87a8 | 1811 | } |
718da2b9 FB |
1812 | } |
1813 | else | |
1814 | { | |
bf6b87a8 | 1815 | if (iov) { |
b356f76d | 1816 | qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3); |
bf6b87a8 | 1817 | } else { |
b356f76d | 1818 | qemu_send_packet(qemu_get_queue(s->nic), buf, size); |
bf6b87a8 | 1819 | } |
718da2b9 FB |
1820 | } |
1821 | } | |
1822 | ||
a41b2ff2 PB |
1823 | static int rtl8139_transmit_one(RTL8139State *s, int descriptor) |
1824 | { | |
1825 | if (!rtl8139_transmitter_enabled(s)) | |
1826 | { | |
7cdeb319 BP |
1827 | DPRINTF("+++ cannot transmit from descriptor %d: transmitter " |
1828 | "disabled\n", descriptor); | |
a41b2ff2 PB |
1829 | return 0; |
1830 | } | |
1831 | ||
1832 | if (s->TxStatus[descriptor] & TxHostOwns) | |
1833 | { | |
7cdeb319 BP |
1834 | DPRINTF("+++ cannot transmit from descriptor %d: owned by host " |
1835 | "(%08x)\n", descriptor, s->TxStatus[descriptor]); | |
a41b2ff2 PB |
1836 | return 0; |
1837 | } | |
1838 | ||
7cdeb319 | 1839 | DPRINTF("+++ transmitting from descriptor %d\n", descriptor); |
a41b2ff2 | 1840 | |
88a411a8 | 1841 | PCIDevice *d = PCI_DEVICE(s); |
a41b2ff2 PB |
1842 | int txsize = s->TxStatus[descriptor] & 0x1fff; |
1843 | uint8_t txbuffer[0x2000]; | |
1844 | ||
7cdeb319 BP |
1845 | DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n", |
1846 | txsize, s->TxAddr[descriptor]); | |
a41b2ff2 | 1847 | |
88a411a8 | 1848 | pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize); |
a41b2ff2 PB |
1849 | |
1850 | /* Mark descriptor as transferred */ | |
1851 | s->TxStatus[descriptor] |= TxHostOwns; | |
1852 | s->TxStatus[descriptor] |= TxStatOK; | |
1853 | ||
bf6b87a8 | 1854 | rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL); |
6cadb320 | 1855 | |
7cdeb319 BP |
1856 | DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize, |
1857 | descriptor); | |
a41b2ff2 PB |
1858 | |
1859 | /* update interrupt */ | |
1860 | s->IntrStatus |= TxOK; | |
1861 | rtl8139_update_irq(s); | |
1862 | ||
1863 | return 1; | |
1864 | } | |
1865 | ||
718da2b9 FB |
1866 | /* structures and macros for task offloading */ |
1867 | typedef struct ip_header | |
1868 | { | |
1869 | uint8_t ip_ver_len; /* version and header length */ | |
1870 | uint8_t ip_tos; /* type of service */ | |
1871 | uint16_t ip_len; /* total length */ | |
1872 | uint16_t ip_id; /* identification */ | |
1873 | uint16_t ip_off; /* fragment offset field */ | |
1874 | uint8_t ip_ttl; /* time to live */ | |
1875 | uint8_t ip_p; /* protocol */ | |
1876 | uint16_t ip_sum; /* checksum */ | |
1877 | uint32_t ip_src,ip_dst; /* source and dest address */ | |
1878 | } ip_header; | |
1879 | ||
1880 | #define IP_HEADER_VERSION_4 4 | |
1881 | #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf) | |
1882 | #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2) | |
1883 | ||
1884 | typedef struct tcp_header | |
1885 | { | |
1886 | uint16_t th_sport; /* source port */ | |
1887 | uint16_t th_dport; /* destination port */ | |
1888 | uint32_t th_seq; /* sequence number */ | |
1889 | uint32_t th_ack; /* acknowledgement number */ | |
1890 | uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */ | |
1891 | uint16_t th_win; /* window */ | |
1892 | uint16_t th_sum; /* checksum */ | |
1893 | uint16_t th_urp; /* urgent pointer */ | |
1894 | } tcp_header; | |
1895 | ||
1896 | typedef struct udp_header | |
1897 | { | |
1898 | uint16_t uh_sport; /* source port */ | |
1899 | uint16_t uh_dport; /* destination port */ | |
1900 | uint16_t uh_ulen; /* udp length */ | |
1901 | uint16_t uh_sum; /* udp checksum */ | |
1902 | } udp_header; | |
1903 | ||
1904 | typedef struct ip_pseudo_header | |
1905 | { | |
1906 | uint32_t ip_src; | |
1907 | uint32_t ip_dst; | |
1908 | uint8_t zeros; | |
1909 | uint8_t ip_proto; | |
1910 | uint16_t ip_payload; | |
1911 | } ip_pseudo_header; | |
1912 | ||
1913 | #define IP_PROTO_TCP 6 | |
1914 | #define IP_PROTO_UDP 17 | |
1915 | ||
1916 | #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2) | |
1917 | #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f) | |
1918 | #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags)) | |
1919 | ||
1920 | #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off))) | |
1921 | ||
1922 | #define TCP_FLAG_FIN 0x01 | |
1923 | #define TCP_FLAG_PUSH 0x08 | |
1924 | ||
1925 | /* produces ones' complement sum of data */ | |
1926 | static uint16_t ones_complement_sum(uint8_t *data, size_t len) | |
1927 | { | |
1928 | uint32_t result = 0; | |
1929 | ||
1930 | for (; len > 1; data+=2, len-=2) | |
1931 | { | |
1932 | result += *(uint16_t*)data; | |
1933 | } | |
1934 | ||
1935 | /* add the remainder byte */ | |
1936 | if (len) | |
1937 | { | |
1938 | uint8_t odd[2] = {*data, 0}; | |
1939 | result += *(uint16_t*)odd; | |
1940 | } | |
1941 | ||
1942 | while (result>>16) | |
1943 | result = (result & 0xffff) + (result >> 16); | |
1944 | ||
1945 | return result; | |
1946 | } | |
1947 | ||
1948 | static uint16_t ip_checksum(void *data, size_t len) | |
1949 | { | |
1950 | return ~ones_complement_sum((uint8_t*)data, len); | |
1951 | } | |
1952 | ||
a41b2ff2 PB |
1953 | static int rtl8139_cplus_transmit_one(RTL8139State *s) |
1954 | { | |
1955 | if (!rtl8139_transmitter_enabled(s)) | |
1956 | { | |
7cdeb319 | 1957 | DPRINTF("+++ C+ mode: transmitter disabled\n"); |
a41b2ff2 PB |
1958 | return 0; |
1959 | } | |
1960 | ||
1961 | if (!rtl8139_cp_transmitter_enabled(s)) | |
1962 | { | |
7cdeb319 | 1963 | DPRINTF("+++ C+ mode: C+ transmitter disabled\n"); |
a41b2ff2 PB |
1964 | return 0 ; |
1965 | } | |
1966 | ||
88a411a8 | 1967 | PCIDevice *d = PCI_DEVICE(s); |
a41b2ff2 PB |
1968 | int descriptor = s->currCPlusTxDesc; |
1969 | ||
3ada003a | 1970 | dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); |
a41b2ff2 PB |
1971 | |
1972 | /* Normal priority ring */ | |
1973 | cplus_tx_ring_desc += 16 * descriptor; | |
1974 | ||
7cdeb319 | 1975 | DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at " |
4abf12f4 | 1976 | "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1], |
7cdeb319 | 1977 | s->TxAddr[0], cplus_tx_ring_desc); |
a41b2ff2 PB |
1978 | |
1979 | uint32_t val, txdw0,txdw1,txbufLO,txbufHI; | |
1980 | ||
88a411a8 | 1981 | pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4); |
a41b2ff2 | 1982 | txdw0 = le32_to_cpu(val); |
88a411a8 | 1983 | pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4); |
a41b2ff2 | 1984 | txdw1 = le32_to_cpu(val); |
88a411a8 | 1985 | pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4); |
a41b2ff2 | 1986 | txbufLO = le32_to_cpu(val); |
88a411a8 | 1987 | pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4); |
a41b2ff2 PB |
1988 | txbufHI = le32_to_cpu(val); |
1989 | ||
7cdeb319 BP |
1990 | DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor, |
1991 | txdw0, txdw1, txbufLO, txbufHI); | |
a41b2ff2 PB |
1992 | |
1993 | /* w0 ownership flag */ | |
1994 | #define CP_TX_OWN (1<<31) | |
1995 | /* w0 end of ring flag */ | |
1996 | #define CP_TX_EOR (1<<30) | |
1997 | /* first segment of received packet flag */ | |
1998 | #define CP_TX_FS (1<<29) | |
1999 | /* last segment of received packet flag */ | |
2000 | #define CP_TX_LS (1<<28) | |
2001 | /* large send packet flag */ | |
2002 | #define CP_TX_LGSEN (1<<27) | |
718da2b9 FB |
2003 | /* large send MSS mask, bits 16...25 */ |
2004 | #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1) | |
2005 | ||
a41b2ff2 PB |
2006 | /* IP checksum offload flag */ |
2007 | #define CP_TX_IPCS (1<<18) | |
2008 | /* UDP checksum offload flag */ | |
2009 | #define CP_TX_UDPCS (1<<17) | |
2010 | /* TCP checksum offload flag */ | |
2011 | #define CP_TX_TCPCS (1<<16) | |
2012 | ||
2013 | /* w0 bits 0...15 : buffer size */ | |
2014 | #define CP_TX_BUFFER_SIZE (1<<16) | |
2015 | #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) | |
bf6b87a8 BP |
2016 | /* w1 add tag flag */ |
2017 | #define CP_TX_TAGC (1<<17) | |
2018 | /* w1 bits 0...15 : VLAN tag (big endian) */ | |
a41b2ff2 PB |
2019 | #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) |
2020 | /* w2 low 32bit of Rx buffer ptr */ | |
2021 | /* w3 high 32bit of Rx buffer ptr */ | |
2022 | ||
2023 | /* set after transmission */ | |
2024 | /* FIFO underrun flag */ | |
2025 | #define CP_TX_STATUS_UNF (1<<25) | |
2026 | /* transmit error summary flag, valid if set any of three below */ | |
2027 | #define CP_TX_STATUS_TES (1<<23) | |
2028 | /* out-of-window collision flag */ | |
2029 | #define CP_TX_STATUS_OWC (1<<22) | |
2030 | /* link failure flag */ | |
2031 | #define CP_TX_STATUS_LNKF (1<<21) | |
2032 | /* excessive collisions flag */ | |
2033 | #define CP_TX_STATUS_EXC (1<<20) | |
2034 | ||
2035 | if (!(txdw0 & CP_TX_OWN)) | |
2036 | { | |
7cdeb319 | 2037 | DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor); |
a41b2ff2 PB |
2038 | return 0 ; |
2039 | } | |
2040 | ||
7cdeb319 | 2041 | DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor); |
6cadb320 FB |
2042 | |
2043 | if (txdw0 & CP_TX_FS) | |
2044 | { | |
7cdeb319 BP |
2045 | DPRINTF("+++ C+ Tx mode : descriptor %d is first segment " |
2046 | "descriptor\n", descriptor); | |
6cadb320 FB |
2047 | |
2048 | /* reset internal buffer offset */ | |
2049 | s->cplus_txbuffer_offset = 0; | |
2050 | } | |
a41b2ff2 PB |
2051 | |
2052 | int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK; | |
3ada003a | 2053 | dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); |
a41b2ff2 | 2054 | |
6cadb320 FB |
2055 | /* make sure we have enough space to assemble the packet */ |
2056 | if (!s->cplus_txbuffer) | |
2057 | { | |
2058 | s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; | |
7267c094 | 2059 | s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len); |
6cadb320 | 2060 | s->cplus_txbuffer_offset = 0; |
718da2b9 | 2061 | |
7cdeb319 BP |
2062 | DPRINTF("+++ C+ mode transmission buffer allocated space %d\n", |
2063 | s->cplus_txbuffer_len); | |
6cadb320 FB |
2064 | } |
2065 | ||
cde31a0e | 2066 | if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len) |
6cadb320 | 2067 | { |
cde31a0e JW |
2068 | /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */ |
2069 | txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset; | |
2070 | DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor" | |
2071 | "length to %d\n", txsize); | |
6cadb320 FB |
2072 | } |
2073 | ||
2074 | if (!s->cplus_txbuffer) | |
2075 | { | |
2076 | /* out of memory */ | |
a41b2ff2 | 2077 | |
7cdeb319 BP |
2078 | DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n", |
2079 | s->cplus_txbuffer_len); | |
6cadb320 FB |
2080 | |
2081 | /* update tally counter */ | |
2082 | ++s->tally_counters.TxERR; | |
2083 | ++s->tally_counters.TxAbt; | |
2084 | ||
2085 | return 0; | |
2086 | } | |
2087 | ||
2088 | /* append more data to the packet */ | |
2089 | ||
7cdeb319 | 2090 | DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at " |
3ada003a EGM |
2091 | DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr, |
2092 | s->cplus_txbuffer_offset); | |
6cadb320 | 2093 | |
88a411a8 | 2094 | pci_dma_read(d, tx_addr, |
3ada003a | 2095 | s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize); |
6cadb320 FB |
2096 | s->cplus_txbuffer_offset += txsize; |
2097 | ||
2098 | /* seek to next Rx descriptor */ | |
2099 | if (txdw0 & CP_TX_EOR) | |
2100 | { | |
2101 | s->currCPlusTxDesc = 0; | |
2102 | } | |
2103 | else | |
2104 | { | |
2105 | ++s->currCPlusTxDesc; | |
2106 | if (s->currCPlusTxDesc >= 64) | |
2107 | s->currCPlusTxDesc = 0; | |
2108 | } | |
a41b2ff2 PB |
2109 | |
2110 | /* transfer ownership to target */ | |
2111 | txdw0 &= ~CP_RX_OWN; | |
2112 | ||
2113 | /* reset error indicator bits */ | |
2114 | txdw0 &= ~CP_TX_STATUS_UNF; | |
2115 | txdw0 &= ~CP_TX_STATUS_TES; | |
2116 | txdw0 &= ~CP_TX_STATUS_OWC; | |
2117 | txdw0 &= ~CP_TX_STATUS_LNKF; | |
2118 | txdw0 &= ~CP_TX_STATUS_EXC; | |
2119 | ||
2120 | /* update ring data */ | |
2121 | val = cpu_to_le32(txdw0); | |
88a411a8 | 2122 | pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4); |
a41b2ff2 | 2123 | |
6cadb320 FB |
2124 | /* Now decide if descriptor being processed is holding the last segment of packet */ |
2125 | if (txdw0 & CP_TX_LS) | |
a41b2ff2 | 2126 | { |
bf6b87a8 BP |
2127 | uint8_t dot1q_buffer_space[VLAN_HLEN]; |
2128 | uint16_t *dot1q_buffer; | |
2129 | ||
7cdeb319 BP |
2130 | DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n", |
2131 | descriptor); | |
6cadb320 FB |
2132 | |
2133 | /* can transfer fully assembled packet */ | |
2134 | ||
2135 | uint8_t *saved_buffer = s->cplus_txbuffer; | |
2136 | int saved_size = s->cplus_txbuffer_offset; | |
2137 | int saved_buffer_len = s->cplus_txbuffer_len; | |
2138 | ||
bf6b87a8 BP |
2139 | /* create vlan tag */ |
2140 | if (txdw1 & CP_TX_TAGC) { | |
2141 | /* the vlan tag is in BE byte order in the descriptor | |
2142 | * BE + le_to_cpu() + ~swap()~ = cpu */ | |
7cdeb319 BP |
2143 | DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n", |
2144 | bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)); | |
bf6b87a8 BP |
2145 | |
2146 | dot1q_buffer = (uint16_t *) dot1q_buffer_space; | |
2147 | dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q); | |
2148 | /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */ | |
2149 | dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK); | |
2150 | } else { | |
2151 | dot1q_buffer = NULL; | |
2152 | } | |
2153 | ||
6cadb320 FB |
2154 | /* reset the card space to protect from recursive call */ |
2155 | s->cplus_txbuffer = NULL; | |
2156 | s->cplus_txbuffer_offset = 0; | |
2157 | s->cplus_txbuffer_len = 0; | |
2158 | ||
718da2b9 | 2159 | if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN)) |
6cadb320 | 2160 | { |
7cdeb319 | 2161 | DPRINTF("+++ C+ mode offloaded task checksum\n"); |
6cadb320 | 2162 | |
6cadb320 | 2163 | /* ip packet header */ |
660f11be | 2164 | ip_header *ip = NULL; |
6cadb320 | 2165 | int hlen = 0; |
718da2b9 FB |
2166 | uint8_t ip_protocol = 0; |
2167 | uint16_t ip_data_len = 0; | |
6cadb320 | 2168 | |
660f11be | 2169 | uint8_t *eth_payload_data = NULL; |
718da2b9 | 2170 | size_t eth_payload_len = 0; |
6cadb320 | 2171 | |
718da2b9 | 2172 | int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12)); |
6cadb320 FB |
2173 | if (proto == ETH_P_IP) |
2174 | { | |
7cdeb319 | 2175 | DPRINTF("+++ C+ mode has IP packet\n"); |
6cadb320 FB |
2176 | |
2177 | /* not aligned */ | |
718da2b9 FB |
2178 | eth_payload_data = saved_buffer + ETH_HLEN; |
2179 | eth_payload_len = saved_size - ETH_HLEN; | |
6cadb320 | 2180 | |
718da2b9 | 2181 | ip = (ip_header*)eth_payload_data; |
6cadb320 | 2182 | |
718da2b9 | 2183 | if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) { |
7cdeb319 BP |
2184 | DPRINTF("+++ C+ mode packet has bad IP version %d " |
2185 | "expected %d\n", IP_HEADER_VERSION(ip), | |
2186 | IP_HEADER_VERSION_4); | |
6cadb320 FB |
2187 | ip = NULL; |
2188 | } else { | |
718da2b9 FB |
2189 | hlen = IP_HEADER_LENGTH(ip); |
2190 | ip_protocol = ip->ip_p; | |
2191 | ip_data_len = be16_to_cpu(ip->ip_len) - hlen; | |
6cadb320 FB |
2192 | } |
2193 | } | |
2194 | ||
2195 | if (ip) | |
2196 | { | |
2197 | if (txdw0 & CP_TX_IPCS) | |
2198 | { | |
7cdeb319 | 2199 | DPRINTF("+++ C+ mode need IP checksum\n"); |
6cadb320 | 2200 | |
718da2b9 | 2201 | if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */ |
6cadb320 FB |
2202 | /* bad packet header len */ |
2203 | /* or packet too short */ | |
2204 | } | |
2205 | else | |
2206 | { | |
2207 | ip->ip_sum = 0; | |
718da2b9 | 2208 | ip->ip_sum = ip_checksum(ip, hlen); |
7cdeb319 BP |
2209 | DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n", |
2210 | hlen, ip->ip_sum); | |
6cadb320 FB |
2211 | } |
2212 | } | |
2213 | ||
718da2b9 | 2214 | if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP) |
6cadb320 | 2215 | { |
718da2b9 | 2216 | int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK; |
ec48c774 | 2217 | |
7cdeb319 BP |
2218 | DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d " |
2219 | "frame data %d specified MSS=%d\n", ETH_MTU, | |
2220 | ip_data_len, saved_size - ETH_HLEN, large_send_mss); | |
6cadb320 | 2221 | |
718da2b9 FB |
2222 | int tcp_send_offset = 0; |
2223 | int send_count = 0; | |
6cadb320 FB |
2224 | |
2225 | /* maximum IP header length is 60 bytes */ | |
2226 | uint8_t saved_ip_header[60]; | |
6cadb320 | 2227 | |
718da2b9 FB |
2228 | /* save IP header template; data area is used in tcp checksum calculation */ |
2229 | memcpy(saved_ip_header, eth_payload_data, hlen); | |
2230 | ||
2231 | /* a placeholder for checksum calculation routine in tcp case */ | |
2232 | uint8_t *data_to_checksum = eth_payload_data + hlen - 12; | |
2233 | // size_t data_to_checksum_len = eth_payload_len - hlen + 12; | |
2234 | ||
2235 | /* pointer to TCP header */ | |
2236 | tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen); | |
2237 | ||
2238 | int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr); | |
2239 | ||
2240 | /* ETH_MTU = ip header len + tcp header len + payload */ | |
2241 | int tcp_data_len = ip_data_len - tcp_hlen; | |
2242 | int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen; | |
2243 | ||
7cdeb319 BP |
2244 | DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP " |
2245 | "data len %d TCP chunk size %d\n", ip_data_len, | |
2246 | tcp_hlen, tcp_data_len, tcp_chunk_size); | |
718da2b9 FB |
2247 | |
2248 | /* note the cycle below overwrites IP header data, | |
2249 | but restores it from saved_ip_header before sending packet */ | |
2250 | ||
2251 | int is_last_frame = 0; | |
2252 | ||
2253 | for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size) | |
2254 | { | |
2255 | uint16_t chunk_size = tcp_chunk_size; | |
2256 | ||
2257 | /* check if this is the last frame */ | |
2258 | if (tcp_send_offset + tcp_chunk_size >= tcp_data_len) | |
2259 | { | |
2260 | is_last_frame = 1; | |
2261 | chunk_size = tcp_data_len - tcp_send_offset; | |
2262 | } | |
2263 | ||
7cdeb319 BP |
2264 | DPRINTF("+++ C+ mode TSO TCP seqno %08x\n", |
2265 | be32_to_cpu(p_tcp_hdr->th_seq)); | |
718da2b9 FB |
2266 | |
2267 | /* add 4 TCP pseudoheader fields */ | |
2268 | /* copy IP source and destination fields */ | |
2269 | memcpy(data_to_checksum, saved_ip_header + 12, 8); | |
2270 | ||
7cdeb319 BP |
2271 | DPRINTF("+++ C+ mode TSO calculating TCP checksum for " |
2272 | "packet with %d bytes data\n", tcp_hlen + | |
2273 | chunk_size); | |
718da2b9 FB |
2274 | |
2275 | if (tcp_send_offset) | |
2276 | { | |
2277 | memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size); | |
2278 | } | |
2279 | ||
2280 | /* keep PUSH and FIN flags only for the last frame */ | |
2281 | if (!is_last_frame) | |
2282 | { | |
2283 | TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN); | |
2284 | } | |
6cadb320 | 2285 | |
718da2b9 FB |
2286 | /* recalculate TCP checksum */ |
2287 | ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; | |
2288 | p_tcpip_hdr->zeros = 0; | |
2289 | p_tcpip_hdr->ip_proto = IP_PROTO_TCP; | |
2290 | p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); | |
2291 | ||
2292 | p_tcp_hdr->th_sum = 0; | |
2293 | ||
2294 | int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12); | |
7cdeb319 BP |
2295 | DPRINTF("+++ C+ mode TSO TCP checksum %04x\n", |
2296 | tcp_checksum); | |
718da2b9 FB |
2297 | |
2298 | p_tcp_hdr->th_sum = tcp_checksum; | |
2299 | ||
2300 | /* restore IP header */ | |
2301 | memcpy(eth_payload_data, saved_ip_header, hlen); | |
2302 | ||
2303 | /* set IP data length and recalculate IP checksum */ | |
2304 | ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size); | |
2305 | ||
2306 | /* increment IP id for subsequent frames */ | |
2307 | ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id)); | |
2308 | ||
2309 | ip->ip_sum = 0; | |
2310 | ip->ip_sum = ip_checksum(eth_payload_data, hlen); | |
7cdeb319 BP |
2311 | DPRINTF("+++ C+ mode TSO IP header len=%d " |
2312 | "checksum=%04x\n", hlen, ip->ip_sum); | |
718da2b9 FB |
2313 | |
2314 | int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size; | |
7cdeb319 BP |
2315 | DPRINTF("+++ C+ mode TSO transferring packet size " |
2316 | "%d\n", tso_send_size); | |
bf6b87a8 BP |
2317 | rtl8139_transfer_frame(s, saved_buffer, tso_send_size, |
2318 | 0, (uint8_t *) dot1q_buffer); | |
718da2b9 FB |
2319 | |
2320 | /* add transferred count to TCP sequence number */ | |
2321 | p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq)); | |
2322 | ++send_count; | |
2323 | } | |
2324 | ||
2325 | /* Stop sending this frame */ | |
2326 | saved_size = 0; | |
2327 | } | |
2328 | else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS)) | |
2329 | { | |
7cdeb319 | 2330 | DPRINTF("+++ C+ mode need TCP or UDP checksum\n"); |
718da2b9 FB |
2331 | |
2332 | /* maximum IP header length is 60 bytes */ | |
2333 | uint8_t saved_ip_header[60]; | |
2334 | memcpy(saved_ip_header, eth_payload_data, hlen); | |
2335 | ||
2336 | uint8_t *data_to_checksum = eth_payload_data + hlen - 12; | |
2337 | // size_t data_to_checksum_len = eth_payload_len - hlen + 12; | |
6cadb320 FB |
2338 | |
2339 | /* add 4 TCP pseudoheader fields */ | |
2340 | /* copy IP source and destination fields */ | |
718da2b9 | 2341 | memcpy(data_to_checksum, saved_ip_header + 12, 8); |
6cadb320 | 2342 | |
718da2b9 | 2343 | if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP) |
6cadb320 | 2344 | { |
7cdeb319 BP |
2345 | DPRINTF("+++ C+ mode calculating TCP checksum for " |
2346 | "packet with %d bytes data\n", ip_data_len); | |
6cadb320 | 2347 | |
718da2b9 FB |
2348 | ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; |
2349 | p_tcpip_hdr->zeros = 0; | |
2350 | p_tcpip_hdr->ip_proto = IP_PROTO_TCP; | |
2351 | p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); | |
6cadb320 | 2352 | |
718da2b9 | 2353 | tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12); |
6cadb320 FB |
2354 | |
2355 | p_tcp_hdr->th_sum = 0; | |
2356 | ||
718da2b9 | 2357 | int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); |
7cdeb319 BP |
2358 | DPRINTF("+++ C+ mode TCP checksum %04x\n", |
2359 | tcp_checksum); | |
6cadb320 FB |
2360 | |
2361 | p_tcp_hdr->th_sum = tcp_checksum; | |
2362 | } | |
718da2b9 | 2363 | else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP) |
6cadb320 | 2364 | { |
7cdeb319 BP |
2365 | DPRINTF("+++ C+ mode calculating UDP checksum for " |
2366 | "packet with %d bytes data\n", ip_data_len); | |
6cadb320 | 2367 | |
718da2b9 FB |
2368 | ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum; |
2369 | p_udpip_hdr->zeros = 0; | |
2370 | p_udpip_hdr->ip_proto = IP_PROTO_UDP; | |
2371 | p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); | |
6cadb320 | 2372 | |
718da2b9 | 2373 | udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12); |
6cadb320 | 2374 | |
6cadb320 FB |
2375 | p_udp_hdr->uh_sum = 0; |
2376 | ||
718da2b9 | 2377 | int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); |
7cdeb319 BP |
2378 | DPRINTF("+++ C+ mode UDP checksum %04x\n", |
2379 | udp_checksum); | |
6cadb320 | 2380 | |
6cadb320 FB |
2381 | p_udp_hdr->uh_sum = udp_checksum; |
2382 | } | |
2383 | ||
2384 | /* restore IP header */ | |
718da2b9 | 2385 | memcpy(eth_payload_data, saved_ip_header, hlen); |
6cadb320 FB |
2386 | } |
2387 | } | |
2388 | } | |
2389 | ||
2390 | /* update tally counter */ | |
2391 | ++s->tally_counters.TxOk; | |
2392 | ||
7cdeb319 | 2393 | DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size); |
6cadb320 | 2394 | |
bf6b87a8 BP |
2395 | rtl8139_transfer_frame(s, saved_buffer, saved_size, 1, |
2396 | (uint8_t *) dot1q_buffer); | |
6cadb320 FB |
2397 | |
2398 | /* restore card space if there was no recursion and reset offset */ | |
2399 | if (!s->cplus_txbuffer) | |
2400 | { | |
2401 | s->cplus_txbuffer = saved_buffer; | |
2402 | s->cplus_txbuffer_len = saved_buffer_len; | |
2403 | s->cplus_txbuffer_offset = 0; | |
2404 | } | |
2405 | else | |
2406 | { | |
7267c094 | 2407 | g_free(saved_buffer); |
6cadb320 | 2408 | } |
a41b2ff2 PB |
2409 | } |
2410 | else | |
2411 | { | |
7cdeb319 | 2412 | DPRINTF("+++ C+ mode transmission continue to next descriptor\n"); |
a41b2ff2 PB |
2413 | } |
2414 | ||
a41b2ff2 PB |
2415 | return 1; |
2416 | } | |
2417 | ||
2418 | static void rtl8139_cplus_transmit(RTL8139State *s) | |
2419 | { | |
2420 | int txcount = 0; | |
2421 | ||
2422 | while (rtl8139_cplus_transmit_one(s)) | |
2423 | { | |
2424 | ++txcount; | |
2425 | } | |
2426 | ||
2427 | /* Mark transfer completed */ | |
2428 | if (!txcount) | |
2429 | { | |
7cdeb319 BP |
2430 | DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n", |
2431 | s->currCPlusTxDesc); | |
a41b2ff2 PB |
2432 | } |
2433 | else | |
2434 | { | |
2435 | /* update interrupt status */ | |
2436 | s->IntrStatus |= TxOK; | |
2437 | rtl8139_update_irq(s); | |
2438 | } | |
2439 | } | |
2440 | ||
2441 | static void rtl8139_transmit(RTL8139State *s) | |
2442 | { | |
2443 | int descriptor = s->currTxDesc, txcount = 0; | |
2444 | ||
2445 | /*while*/ | |
2446 | if (rtl8139_transmit_one(s, descriptor)) | |
2447 | { | |
2448 | ++s->currTxDesc; | |
2449 | s->currTxDesc %= 4; | |
2450 | ++txcount; | |
2451 | } | |
2452 | ||
2453 | /* Mark transfer completed */ | |
2454 | if (!txcount) | |
2455 | { | |
7cdeb319 BP |
2456 | DPRINTF("transmitter queue stalled, current TxDesc = %d\n", |
2457 | s->currTxDesc); | |
a41b2ff2 PB |
2458 | } |
2459 | } | |
2460 | ||
2461 | static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) | |
2462 | { | |
2463 | ||
2464 | int descriptor = txRegOffset/4; | |
6cadb320 FB |
2465 | |
2466 | /* handle C+ transmit mode register configuration */ | |
2467 | ||
2c3891ab | 2468 | if (s->cplus_enabled) |
6cadb320 | 2469 | { |
7cdeb319 BP |
2470 | DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x " |
2471 | "descriptor=%d\n", txRegOffset, val, descriptor); | |
6cadb320 FB |
2472 | |
2473 | /* handle Dump Tally Counters command */ | |
2474 | s->TxStatus[descriptor] = val; | |
2475 | ||
2476 | if (descriptor == 0 && (val & 0x8)) | |
2477 | { | |
a8170e5e | 2478 | hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); |
6cadb320 FB |
2479 | |
2480 | /* dump tally counters to specified memory location */ | |
3ada003a | 2481 | RTL8139TallyCounters_dma_write(s, tc_addr); |
6cadb320 FB |
2482 | |
2483 | /* mark dump completed */ | |
2484 | s->TxStatus[0] &= ~0x8; | |
2485 | } | |
2486 | ||
2487 | return; | |
2488 | } | |
2489 | ||
7cdeb319 BP |
2490 | DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", |
2491 | txRegOffset, val, descriptor); | |
a41b2ff2 PB |
2492 | |
2493 | /* mask only reserved bits */ | |
2494 | val &= ~0xff00c000; /* these bits are reset on write */ | |
2495 | val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]); | |
2496 | ||
2497 | s->TxStatus[descriptor] = val; | |
2498 | ||
2499 | /* attempt to start transmission */ | |
2500 | rtl8139_transmit(s); | |
2501 | } | |
2502 | ||
3e48dd4a SH |
2503 | static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[], |
2504 | uint32_t base, uint8_t addr, | |
2505 | int size) | |
a41b2ff2 | 2506 | { |
3e48dd4a | 2507 | uint32_t reg = (addr - base) / 4; |
afe0a595 JW |
2508 | uint32_t offset = addr & 0x3; |
2509 | uint32_t ret = 0; | |
2510 | ||
2511 | if (addr & (size - 1)) { | |
3e48dd4a SH |
2512 | DPRINTF("not implemented read for TxStatus/TxAddr " |
2513 | "addr=0x%x size=0x%x\n", addr, size); | |
afe0a595 JW |
2514 | return ret; |
2515 | } | |
a41b2ff2 | 2516 | |
afe0a595 JW |
2517 | switch (size) { |
2518 | case 1: /* fall through */ | |
2519 | case 2: /* fall through */ | |
2520 | case 4: | |
bdc62e62 | 2521 | ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1); |
3e48dd4a SH |
2522 | DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n", |
2523 | reg, addr, size, ret); | |
afe0a595 JW |
2524 | break; |
2525 | default: | |
3e48dd4a | 2526 | DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size); |
afe0a595 JW |
2527 | break; |
2528 | } | |
a41b2ff2 PB |
2529 | |
2530 | return ret; | |
2531 | } | |
2532 | ||
2533 | static uint16_t rtl8139_TSAD_read(RTL8139State *s) | |
2534 | { | |
2535 | uint16_t ret = 0; | |
2536 | ||
2537 | /* Simulate TSAD, it is read only anyway */ | |
2538 | ||
2539 | ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) | |
2540 | |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) | |
2541 | |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) | |
2542 | |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) | |
2543 | ||
2544 | |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) | |
2545 | |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) | |
2546 | |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) | |
2547 | |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) | |
3b46e624 | 2548 | |
a41b2ff2 PB |
2549 | |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) |
2550 | |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) | |
2551 | |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) | |
2552 | |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) | |
3b46e624 | 2553 | |
a41b2ff2 PB |
2554 | |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) |
2555 | |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) | |
2556 | |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) | |
2557 | |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; | |
3b46e624 | 2558 | |
a41b2ff2 | 2559 | |
7cdeb319 | 2560 | DPRINTF("TSAD read val=0x%04x\n", ret); |
a41b2ff2 PB |
2561 | |
2562 | return ret; | |
2563 | } | |
2564 | ||
2565 | static uint16_t rtl8139_CSCR_read(RTL8139State *s) | |
2566 | { | |
2567 | uint16_t ret = s->CSCR; | |
2568 | ||
7cdeb319 | 2569 | DPRINTF("CSCR read val=0x%04x\n", ret); |
a41b2ff2 PB |
2570 | |
2571 | return ret; | |
2572 | } | |
2573 | ||
2574 | static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) | |
2575 | { | |
7cdeb319 | 2576 | DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val); |
a41b2ff2 | 2577 | |
290a0933 | 2578 | s->TxAddr[txAddrOffset/4] = val; |
a41b2ff2 PB |
2579 | } |
2580 | ||
2581 | static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset) | |
2582 | { | |
290a0933 | 2583 | uint32_t ret = s->TxAddr[txAddrOffset/4]; |
a41b2ff2 | 2584 | |
7cdeb319 | 2585 | DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret); |
a41b2ff2 PB |
2586 | |
2587 | return ret; | |
2588 | } | |
2589 | ||
2590 | static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) | |
2591 | { | |
7cdeb319 | 2592 | DPRINTF("RxBufPtr write val=0x%04x\n", val); |
a41b2ff2 PB |
2593 | |
2594 | /* this value is off by 16 */ | |
2595 | s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize); | |
2596 | ||
00b7ade8 SH |
2597 | /* more buffer space may be available so try to receive */ |
2598 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); | |
2599 | ||
7cdeb319 BP |
2600 | DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n", |
2601 | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); | |
a41b2ff2 PB |
2602 | } |
2603 | ||
2604 | static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s) | |
2605 | { | |
2606 | /* this value is off by 16 */ | |
2607 | uint32_t ret = s->RxBufPtr - 0x10; | |
2608 | ||
7cdeb319 | 2609 | DPRINTF("RxBufPtr read val=0x%04x\n", ret); |
6cadb320 FB |
2610 | |
2611 | return ret; | |
2612 | } | |
2613 | ||
2614 | static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s) | |
2615 | { | |
2616 | /* this value is NOT off by 16 */ | |
2617 | uint32_t ret = s->RxBufAddr; | |
2618 | ||
7cdeb319 | 2619 | DPRINTF("RxBufAddr read val=0x%04x\n", ret); |
a41b2ff2 PB |
2620 | |
2621 | return ret; | |
2622 | } | |
2623 | ||
2624 | static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val) | |
2625 | { | |
7cdeb319 | 2626 | DPRINTF("RxBuf write val=0x%08x\n", val); |
a41b2ff2 PB |
2627 | |
2628 | s->RxBuf = val; | |
2629 | ||
2630 | /* may need to reset rxring here */ | |
2631 | } | |
2632 | ||
2633 | static uint32_t rtl8139_RxBuf_read(RTL8139State *s) | |
2634 | { | |
2635 | uint32_t ret = s->RxBuf; | |
2636 | ||
7cdeb319 | 2637 | DPRINTF("RxBuf read val=0x%08x\n", ret); |
a41b2ff2 PB |
2638 | |
2639 | return ret; | |
2640 | } | |
2641 | ||
2642 | static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) | |
2643 | { | |
7cdeb319 | 2644 | DPRINTF("IntrMask write(w) val=0x%04x\n", val); |
a41b2ff2 | 2645 | |
ebabb67a | 2646 | /* mask unwritable bits */ |
a41b2ff2 PB |
2647 | val = SET_MASKED(val, 0x1e00, s->IntrMask); |
2648 | ||
2649 | s->IntrMask = val; | |
2650 | ||
bc72ad67 | 2651 | rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
a41b2ff2 | 2652 | rtl8139_update_irq(s); |
05447803 | 2653 | |
a41b2ff2 PB |
2654 | } |
2655 | ||
2656 | static uint32_t rtl8139_IntrMask_read(RTL8139State *s) | |
2657 | { | |
2658 | uint32_t ret = s->IntrMask; | |
2659 | ||
7cdeb319 | 2660 | DPRINTF("IntrMask read(w) val=0x%04x\n", ret); |
a41b2ff2 PB |
2661 | |
2662 | return ret; | |
2663 | } | |
2664 | ||
2665 | static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val) | |
2666 | { | |
7cdeb319 | 2667 | DPRINTF("IntrStatus write(w) val=0x%04x\n", val); |
a41b2ff2 PB |
2668 | |
2669 | #if 0 | |
2670 | ||
2671 | /* writing to ISR has no effect */ | |
2672 | ||
2673 | return; | |
2674 | ||
2675 | #else | |
2676 | uint16_t newStatus = s->IntrStatus & ~val; | |
2677 | ||
ebabb67a | 2678 | /* mask unwritable bits */ |
a41b2ff2 PB |
2679 | newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus); |
2680 | ||
2681 | /* writing 1 to interrupt status register bit clears it */ | |
2682 | s->IntrStatus = 0; | |
2683 | rtl8139_update_irq(s); | |
2684 | ||
2685 | s->IntrStatus = newStatus; | |
05447803 FZ |
2686 | /* |
2687 | * Computing if we miss an interrupt here is not that correct but | |
2688 | * considered that we should have had already an interrupt | |
2689 | * and probably emulated is slower is better to assume this resetting was | |
26404edc | 2690 | * done before testing on previous rtl8139_update_irq lead to IRQ losing |
05447803 | 2691 | */ |
bc72ad67 | 2692 | rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
a41b2ff2 | 2693 | rtl8139_update_irq(s); |
05447803 | 2694 | |
a41b2ff2 PB |
2695 | #endif |
2696 | } | |
2697 | ||
2698 | static uint32_t rtl8139_IntrStatus_read(RTL8139State *s) | |
2699 | { | |
bc72ad67 | 2700 | rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
05447803 | 2701 | |
a41b2ff2 PB |
2702 | uint32_t ret = s->IntrStatus; |
2703 | ||
7cdeb319 | 2704 | DPRINTF("IntrStatus read(w) val=0x%04x\n", ret); |
a41b2ff2 PB |
2705 | |
2706 | #if 0 | |
2707 | ||
2708 | /* reading ISR clears all interrupts */ | |
2709 | s->IntrStatus = 0; | |
2710 | ||
2711 | rtl8139_update_irq(s); | |
2712 | ||
2713 | #endif | |
2714 | ||
2715 | return ret; | |
2716 | } | |
2717 | ||
2718 | static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val) | |
2719 | { | |
7cdeb319 | 2720 | DPRINTF("MultiIntr write(w) val=0x%04x\n", val); |
a41b2ff2 | 2721 | |
ebabb67a | 2722 | /* mask unwritable bits */ |
a41b2ff2 PB |
2723 | val = SET_MASKED(val, 0xf000, s->MultiIntr); |
2724 | ||
2725 | s->MultiIntr = val; | |
2726 | } | |
2727 | ||
2728 | static uint32_t rtl8139_MultiIntr_read(RTL8139State *s) | |
2729 | { | |
2730 | uint32_t ret = s->MultiIntr; | |
2731 | ||
7cdeb319 | 2732 | DPRINTF("MultiIntr read(w) val=0x%04x\n", ret); |
a41b2ff2 PB |
2733 | |
2734 | return ret; | |
2735 | } | |
2736 | ||
2737 | static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) | |
2738 | { | |
2739 | RTL8139State *s = opaque; | |
2740 | ||
a41b2ff2 PB |
2741 | switch (addr) |
2742 | { | |
2743 | case MAC0 ... MAC0+5: | |
2744 | s->phys[addr - MAC0] = val; | |
2745 | break; | |
2746 | case MAC0+6 ... MAC0+7: | |
2747 | /* reserved */ | |
2748 | break; | |
2749 | case MAR0 ... MAR0+7: | |
2750 | s->mult[addr - MAR0] = val; | |
2751 | break; | |
2752 | case ChipCmd: | |
2753 | rtl8139_ChipCmd_write(s, val); | |
2754 | break; | |
2755 | case Cfg9346: | |
2756 | rtl8139_Cfg9346_write(s, val); | |
2757 | break; | |
2758 | case TxConfig: /* windows driver sometimes writes using byte-lenth call */ | |
2759 | rtl8139_TxConfig_writeb(s, val); | |
2760 | break; | |
2761 | case Config0: | |
2762 | rtl8139_Config0_write(s, val); | |
2763 | break; | |
2764 | case Config1: | |
2765 | rtl8139_Config1_write(s, val); | |
2766 | break; | |
2767 | case Config3: | |
2768 | rtl8139_Config3_write(s, val); | |
2769 | break; | |
2770 | case Config4: | |
2771 | rtl8139_Config4_write(s, val); | |
2772 | break; | |
2773 | case Config5: | |
2774 | rtl8139_Config5_write(s, val); | |
2775 | break; | |
2776 | case MediaStatus: | |
2777 | /* ignore */ | |
7cdeb319 BP |
2778 | DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n", |
2779 | val); | |
a41b2ff2 PB |
2780 | break; |
2781 | ||
2782 | case HltClk: | |
7cdeb319 | 2783 | DPRINTF("HltClk write val=0x%08x\n", val); |
a41b2ff2 PB |
2784 | if (val == 'R') |
2785 | { | |
2786 | s->clock_enabled = 1; | |
2787 | } | |
2788 | else if (val == 'H') | |
2789 | { | |
2790 | s->clock_enabled = 0; | |
2791 | } | |
2792 | break; | |
2793 | ||
2794 | case TxThresh: | |
7cdeb319 | 2795 | DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val); |
a41b2ff2 PB |
2796 | s->TxThresh = val; |
2797 | break; | |
2798 | ||
2799 | case TxPoll: | |
7cdeb319 | 2800 | DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val); |
a41b2ff2 PB |
2801 | if (val & (1 << 7)) |
2802 | { | |
7cdeb319 BP |
2803 | DPRINTF("C+ TxPoll high priority transmission (not " |
2804 | "implemented)\n"); | |
a41b2ff2 PB |
2805 | //rtl8139_cplus_transmit(s); |
2806 | } | |
2807 | if (val & (1 << 6)) | |
2808 | { | |
7cdeb319 | 2809 | DPRINTF("C+ TxPoll normal priority transmission\n"); |
a41b2ff2 PB |
2810 | rtl8139_cplus_transmit(s); |
2811 | } | |
2812 | ||
2813 | break; | |
2814 | ||
2815 | default: | |
7cdeb319 BP |
2816 | DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr, |
2817 | val); | |
a41b2ff2 PB |
2818 | break; |
2819 | } | |
2820 | } | |
2821 | ||
2822 | static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) | |
2823 | { | |
2824 | RTL8139State *s = opaque; | |
2825 | ||
a41b2ff2 PB |
2826 | switch (addr) |
2827 | { | |
2828 | case IntrMask: | |
2829 | rtl8139_IntrMask_write(s, val); | |
2830 | break; | |
2831 | ||
2832 | case IntrStatus: | |
2833 | rtl8139_IntrStatus_write(s, val); | |
2834 | break; | |
2835 | ||
2836 | case MultiIntr: | |
2837 | rtl8139_MultiIntr_write(s, val); | |
2838 | break; | |
2839 | ||
2840 | case RxBufPtr: | |
2841 | rtl8139_RxBufPtr_write(s, val); | |
2842 | break; | |
2843 | ||
2844 | case BasicModeCtrl: | |
2845 | rtl8139_BasicModeCtrl_write(s, val); | |
2846 | break; | |
2847 | case BasicModeStatus: | |
2848 | rtl8139_BasicModeStatus_write(s, val); | |
2849 | break; | |
2850 | case NWayAdvert: | |
7cdeb319 | 2851 | DPRINTF("NWayAdvert write(w) val=0x%04x\n", val); |
a41b2ff2 PB |
2852 | s->NWayAdvert = val; |
2853 | break; | |
2854 | case NWayLPAR: | |
7cdeb319 | 2855 | DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val); |
a41b2ff2 PB |
2856 | break; |
2857 | case NWayExpansion: | |
7cdeb319 | 2858 | DPRINTF("NWayExpansion write(w) val=0x%04x\n", val); |
a41b2ff2 PB |
2859 | s->NWayExpansion = val; |
2860 | break; | |
2861 | ||
2862 | case CpCmd: | |
2863 | rtl8139_CpCmd_write(s, val); | |
2864 | break; | |
2865 | ||
6cadb320 FB |
2866 | case IntrMitigate: |
2867 | rtl8139_IntrMitigate_write(s, val); | |
2868 | break; | |
2869 | ||
a41b2ff2 | 2870 | default: |
7cdeb319 BP |
2871 | DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n", |
2872 | addr, val); | |
a41b2ff2 | 2873 | |
a41b2ff2 PB |
2874 | rtl8139_io_writeb(opaque, addr, val & 0xff); |
2875 | rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); | |
a41b2ff2 PB |
2876 | break; |
2877 | } | |
2878 | } | |
2879 | ||
05447803 FZ |
2880 | static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time) |
2881 | { | |
2882 | int64_t pci_time, next_time; | |
2883 | uint32_t low_pci; | |
2884 | ||
7cdeb319 | 2885 | DPRINTF("entered rtl8139_set_next_tctr_time\n"); |
05447803 FZ |
2886 | |
2887 | if (s->TimerExpire && current_time >= s->TimerExpire) { | |
2888 | s->IntrStatus |= PCSTimeout; | |
2889 | rtl8139_update_irq(s); | |
2890 | } | |
2891 | ||
2892 | /* Set QEMU timer only if needed that is | |
2893 | * - TimerInt <> 0 (we have a timer) | |
2894 | * - mask = 1 (we want an interrupt timer) | |
2895 | * - irq = 0 (irq is not already active) | |
2896 | * If any of above change we need to compute timer again | |
2897 | * Also we must check if timer is passed without QEMU timer | |
2898 | */ | |
2899 | s->TimerExpire = 0; | |
2900 | if (!s->TimerInt) { | |
2901 | return; | |
2902 | } | |
2903 | ||
2904 | pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY, | |
2905 | get_ticks_per_sec()); | |
2906 | low_pci = pci_time & 0xffffffff; | |
2907 | pci_time = pci_time - low_pci + s->TimerInt; | |
2908 | if (low_pci >= s->TimerInt) { | |
2909 | pci_time += 0x100000000LL; | |
2910 | } | |
2911 | next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(), | |
2912 | PCI_FREQUENCY); | |
2913 | s->TimerExpire = next_time; | |
2914 | ||
2915 | if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) { | |
bc72ad67 | 2916 | timer_mod(s->timer, next_time); |
05447803 FZ |
2917 | } |
2918 | } | |
2919 | ||
a41b2ff2 PB |
2920 | static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) |
2921 | { | |
2922 | RTL8139State *s = opaque; | |
2923 | ||
a41b2ff2 PB |
2924 | switch (addr) |
2925 | { | |
2926 | case RxMissed: | |
7cdeb319 | 2927 | DPRINTF("RxMissed clearing on write\n"); |
a41b2ff2 PB |
2928 | s->RxMissed = 0; |
2929 | break; | |
2930 | ||
2931 | case TxConfig: | |
2932 | rtl8139_TxConfig_write(s, val); | |
2933 | break; | |
2934 | ||
2935 | case RxConfig: | |
2936 | rtl8139_RxConfig_write(s, val); | |
2937 | break; | |
2938 | ||
2939 | case TxStatus0 ... TxStatus0+4*4-1: | |
2940 | rtl8139_TxStatus_write(s, addr-TxStatus0, val); | |
2941 | break; | |
2942 | ||
2943 | case TxAddr0 ... TxAddr0+4*4-1: | |
2944 | rtl8139_TxAddr_write(s, addr-TxAddr0, val); | |
2945 | break; | |
2946 | ||
2947 | case RxBuf: | |
2948 | rtl8139_RxBuf_write(s, val); | |
2949 | break; | |
2950 | ||
2951 | case RxRingAddrLO: | |
7cdeb319 | 2952 | DPRINTF("C+ RxRing low bits write val=0x%08x\n", val); |
a41b2ff2 PB |
2953 | s->RxRingAddrLO = val; |
2954 | break; | |
2955 | ||
2956 | case RxRingAddrHI: | |
7cdeb319 | 2957 | DPRINTF("C+ RxRing high bits write val=0x%08x\n", val); |
a41b2ff2 PB |
2958 | s->RxRingAddrHI = val; |
2959 | break; | |
2960 | ||
6cadb320 | 2961 | case Timer: |
7cdeb319 | 2962 | DPRINTF("TCTR Timer reset on write\n"); |
bc72ad67 | 2963 | s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
05447803 | 2964 | rtl8139_set_next_tctr_time(s, s->TCTR_base); |
6cadb320 FB |
2965 | break; |
2966 | ||
2967 | case FlashReg: | |
7cdeb319 | 2968 | DPRINTF("FlashReg TimerInt write val=0x%08x\n", val); |
05447803 FZ |
2969 | if (s->TimerInt != val) { |
2970 | s->TimerInt = val; | |
bc72ad67 | 2971 | rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
05447803 | 2972 | } |
6cadb320 FB |
2973 | break; |
2974 | ||
a41b2ff2 | 2975 | default: |
7cdeb319 BP |
2976 | DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n", |
2977 | addr, val); | |
a41b2ff2 PB |
2978 | rtl8139_io_writeb(opaque, addr, val & 0xff); |
2979 | rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); | |
2980 | rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); | |
2981 | rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff); | |
a41b2ff2 PB |
2982 | break; |
2983 | } | |
2984 | } | |
2985 | ||
2986 | static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) | |
2987 | { | |
2988 | RTL8139State *s = opaque; | |
2989 | int ret; | |
2990 | ||
a41b2ff2 PB |
2991 | switch (addr) |
2992 | { | |
2993 | case MAC0 ... MAC0+5: | |
2994 | ret = s->phys[addr - MAC0]; | |
2995 | break; | |
2996 | case MAC0+6 ... MAC0+7: | |
2997 | ret = 0; | |
2998 | break; | |
2999 | case MAR0 ... MAR0+7: | |
3000 | ret = s->mult[addr - MAR0]; | |
3001 | break; | |
afe0a595 | 3002 | case TxStatus0 ... TxStatus0+4*4-1: |
3e48dd4a SH |
3003 | ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, |
3004 | addr, 1); | |
afe0a595 | 3005 | break; |
a41b2ff2 PB |
3006 | case ChipCmd: |
3007 | ret = rtl8139_ChipCmd_read(s); | |
3008 | break; | |
3009 | case Cfg9346: | |
3010 | ret = rtl8139_Cfg9346_read(s); | |
3011 | break; | |
3012 | case Config0: | |
3013 | ret = rtl8139_Config0_read(s); | |
3014 | break; | |
3015 | case Config1: | |
3016 | ret = rtl8139_Config1_read(s); | |
3017 | break; | |
3018 | case Config3: | |
3019 | ret = rtl8139_Config3_read(s); | |
3020 | break; | |
3021 | case Config4: | |
3022 | ret = rtl8139_Config4_read(s); | |
3023 | break; | |
3024 | case Config5: | |
3025 | ret = rtl8139_Config5_read(s); | |
3026 | break; | |
3027 | ||
3028 | case MediaStatus: | |
9e12c5af JW |
3029 | /* The LinkDown bit of MediaStatus is inverse with link status */ |
3030 | ret = 0xd0 | (~s->BasicModeStatus & 0x04); | |
7cdeb319 | 3031 | DPRINTF("MediaStatus read 0x%x\n", ret); |
a41b2ff2 PB |
3032 | break; |
3033 | ||
3034 | case HltClk: | |
3035 | ret = s->clock_enabled; | |
7cdeb319 | 3036 | DPRINTF("HltClk read 0x%x\n", ret); |
a41b2ff2 PB |
3037 | break; |
3038 | ||
3039 | case PCIRevisionID: | |
6cadb320 | 3040 | ret = RTL8139_PCI_REVID; |
7cdeb319 | 3041 | DPRINTF("PCI Revision ID read 0x%x\n", ret); |
a41b2ff2 PB |
3042 | break; |
3043 | ||
3044 | case TxThresh: | |
3045 | ret = s->TxThresh; | |
7cdeb319 | 3046 | DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret); |
a41b2ff2 PB |
3047 | break; |
3048 | ||
3049 | case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ | |
3050 | ret = s->TxConfig >> 24; | |
7cdeb319 | 3051 | DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret); |
a41b2ff2 PB |
3052 | break; |
3053 | ||
3054 | default: | |
7cdeb319 | 3055 | DPRINTF("not implemented read(b) addr=0x%x\n", addr); |
a41b2ff2 PB |
3056 | ret = 0; |
3057 | break; | |
3058 | } | |
3059 | ||
3060 | return ret; | |
3061 | } | |
3062 | ||
3063 | static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) | |
3064 | { | |
3065 | RTL8139State *s = opaque; | |
3066 | uint32_t ret; | |
3067 | ||
a41b2ff2 PB |
3068 | switch (addr) |
3069 | { | |
afe0a595 | 3070 | case TxAddr0 ... TxAddr0+4*4-1: |
3e48dd4a | 3071 | ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2); |
afe0a595 | 3072 | break; |
a41b2ff2 PB |
3073 | case IntrMask: |
3074 | ret = rtl8139_IntrMask_read(s); | |
3075 | break; | |
3076 | ||
3077 | case IntrStatus: | |
3078 | ret = rtl8139_IntrStatus_read(s); | |
3079 | break; | |
3080 | ||
3081 | case MultiIntr: | |
3082 | ret = rtl8139_MultiIntr_read(s); | |
3083 | break; | |
3084 | ||
3085 | case RxBufPtr: | |
3086 | ret = rtl8139_RxBufPtr_read(s); | |
3087 | break; | |
3088 | ||
6cadb320 FB |
3089 | case RxBufAddr: |
3090 | ret = rtl8139_RxBufAddr_read(s); | |
3091 | break; | |
3092 | ||
a41b2ff2 PB |
3093 | case BasicModeCtrl: |
3094 | ret = rtl8139_BasicModeCtrl_read(s); | |
3095 | break; | |
3096 | case BasicModeStatus: | |
3097 | ret = rtl8139_BasicModeStatus_read(s); | |
3098 | break; | |
3099 | case NWayAdvert: | |
3100 | ret = s->NWayAdvert; | |
7cdeb319 | 3101 | DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret); |
a41b2ff2 PB |
3102 | break; |
3103 | case NWayLPAR: | |
3104 | ret = s->NWayLPAR; | |
7cdeb319 | 3105 | DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret); |
a41b2ff2 PB |
3106 | break; |
3107 | case NWayExpansion: | |
3108 | ret = s->NWayExpansion; | |
7cdeb319 | 3109 | DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret); |
a41b2ff2 PB |
3110 | break; |
3111 | ||
3112 | case CpCmd: | |
3113 | ret = rtl8139_CpCmd_read(s); | |
3114 | break; | |
3115 | ||
6cadb320 FB |
3116 | case IntrMitigate: |
3117 | ret = rtl8139_IntrMitigate_read(s); | |
3118 | break; | |
3119 | ||
a41b2ff2 PB |
3120 | case TxSummary: |
3121 | ret = rtl8139_TSAD_read(s); | |
3122 | break; | |
3123 | ||
3124 | case CSCR: | |
3125 | ret = rtl8139_CSCR_read(s); | |
3126 | break; | |
3127 | ||
3128 | default: | |
7cdeb319 | 3129 | DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr); |
a41b2ff2 | 3130 | |
a41b2ff2 PB |
3131 | ret = rtl8139_io_readb(opaque, addr); |
3132 | ret |= rtl8139_io_readb(opaque, addr + 1) << 8; | |
a41b2ff2 | 3133 | |
7cdeb319 | 3134 | DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret); |
a41b2ff2 PB |
3135 | break; |
3136 | } | |
3137 | ||
3138 | return ret; | |
3139 | } | |
3140 | ||
3141 | static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) | |
3142 | { | |
3143 | RTL8139State *s = opaque; | |
3144 | uint32_t ret; | |
3145 | ||
a41b2ff2 PB |
3146 | switch (addr) |
3147 | { | |
3148 | case RxMissed: | |
3149 | ret = s->RxMissed; | |
3150 | ||
7cdeb319 | 3151 | DPRINTF("RxMissed read val=0x%08x\n", ret); |
a41b2ff2 PB |
3152 | break; |
3153 | ||
3154 | case TxConfig: | |
3155 | ret = rtl8139_TxConfig_read(s); | |
3156 | break; | |
3157 | ||
3158 | case RxConfig: | |
3159 | ret = rtl8139_RxConfig_read(s); | |
3160 | break; | |
3161 | ||
3162 | case TxStatus0 ... TxStatus0+4*4-1: | |
3e48dd4a SH |
3163 | ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, |
3164 | addr, 4); | |
a41b2ff2 PB |
3165 | break; |
3166 | ||
3167 | case TxAddr0 ... TxAddr0+4*4-1: | |
3168 | ret = rtl8139_TxAddr_read(s, addr-TxAddr0); | |
3169 | break; | |
3170 | ||
3171 | case RxBuf: | |
3172 | ret = rtl8139_RxBuf_read(s); | |
3173 | break; | |
3174 | ||
3175 | case RxRingAddrLO: | |
3176 | ret = s->RxRingAddrLO; | |
7cdeb319 | 3177 | DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret); |
a41b2ff2 PB |
3178 | break; |
3179 | ||
3180 | case RxRingAddrHI: | |
3181 | ret = s->RxRingAddrHI; | |
7cdeb319 | 3182 | DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret); |
6cadb320 FB |
3183 | break; |
3184 | ||
3185 | case Timer: | |
bc72ad67 | 3186 | ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base, |
05447803 | 3187 | PCI_FREQUENCY, get_ticks_per_sec()); |
7cdeb319 | 3188 | DPRINTF("TCTR Timer read val=0x%08x\n", ret); |
6cadb320 FB |
3189 | break; |
3190 | ||
3191 | case FlashReg: | |
3192 | ret = s->TimerInt; | |
7cdeb319 | 3193 | DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret); |
a41b2ff2 PB |
3194 | break; |
3195 | ||
3196 | default: | |
7cdeb319 | 3197 | DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr); |
a41b2ff2 | 3198 | |
a41b2ff2 PB |
3199 | ret = rtl8139_io_readb(opaque, addr); |
3200 | ret |= rtl8139_io_readb(opaque, addr + 1) << 8; | |
3201 | ret |= rtl8139_io_readb(opaque, addr + 2) << 16; | |
3202 | ret |= rtl8139_io_readb(opaque, addr + 3) << 24; | |
a41b2ff2 | 3203 | |
7cdeb319 | 3204 | DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret); |
a41b2ff2 PB |
3205 | break; |
3206 | } | |
3207 | ||
3208 | return ret; | |
3209 | } | |
3210 | ||
3211 | /* */ | |
3212 | ||
a8170e5e | 3213 | static void rtl8139_mmio_writeb(void *opaque, hwaddr addr, uint32_t val) |
a41b2ff2 PB |
3214 | { |
3215 | rtl8139_io_writeb(opaque, addr & 0xFF, val); | |
3216 | } | |
3217 | ||
a8170e5e | 3218 | static void rtl8139_mmio_writew(void *opaque, hwaddr addr, uint32_t val) |
a41b2ff2 PB |
3219 | { |
3220 | rtl8139_io_writew(opaque, addr & 0xFF, val); | |
3221 | } | |
3222 | ||
a8170e5e | 3223 | static void rtl8139_mmio_writel(void *opaque, hwaddr addr, uint32_t val) |
a41b2ff2 PB |
3224 | { |
3225 | rtl8139_io_writel(opaque, addr & 0xFF, val); | |
3226 | } | |
3227 | ||
a8170e5e | 3228 | static uint32_t rtl8139_mmio_readb(void *opaque, hwaddr addr) |
a41b2ff2 PB |
3229 | { |
3230 | return rtl8139_io_readb(opaque, addr & 0xFF); | |
3231 | } | |
3232 | ||
a8170e5e | 3233 | static uint32_t rtl8139_mmio_readw(void *opaque, hwaddr addr) |
a41b2ff2 | 3234 | { |
5fedc612 | 3235 | uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF); |
5fedc612 | 3236 | return val; |
a41b2ff2 PB |
3237 | } |
3238 | ||
a8170e5e | 3239 | static uint32_t rtl8139_mmio_readl(void *opaque, hwaddr addr) |
a41b2ff2 | 3240 | { |
5fedc612 | 3241 | uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF); |
5fedc612 | 3242 | return val; |
a41b2ff2 PB |
3243 | } |
3244 | ||
060110c3 | 3245 | static int rtl8139_post_load(void *opaque, int version_id) |
a41b2ff2 | 3246 | { |
6597ebbb | 3247 | RTL8139State* s = opaque; |
bc72ad67 | 3248 | rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
060110c3 | 3249 | if (version_id < 4) { |
2c3891ab AL |
3250 | s->cplus_enabled = s->CpCmd != 0; |
3251 | } | |
3252 | ||
9e12c5af JW |
3253 | /* nc.link_down can't be migrated, so infer link_down according |
3254 | * to link status bit in BasicModeStatus */ | |
b356f76d | 3255 | qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0; |
9e12c5af | 3256 | |
a41b2ff2 PB |
3257 | return 0; |
3258 | } | |
3259 | ||
c574ba5a AW |
3260 | static bool rtl8139_hotplug_ready_needed(void *opaque) |
3261 | { | |
3262 | return qdev_machine_modified(); | |
3263 | } | |
3264 | ||
3265 | static const VMStateDescription vmstate_rtl8139_hotplug_ready ={ | |
3266 | .name = "rtl8139/hotplug_ready", | |
3267 | .version_id = 1, | |
3268 | .minimum_version_id = 1, | |
3269 | .minimum_version_id_old = 1, | |
3270 | .fields = (VMStateField []) { | |
3271 | VMSTATE_END_OF_LIST() | |
3272 | } | |
3273 | }; | |
3274 | ||
05447803 FZ |
3275 | static void rtl8139_pre_save(void *opaque) |
3276 | { | |
3277 | RTL8139State* s = opaque; | |
bc72ad67 | 3278 | int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
05447803 FZ |
3279 | |
3280 | /* set IntrStatus correctly */ | |
3281 | rtl8139_set_next_tctr_time(s, current_time); | |
3282 | s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY, | |
3283 | get_ticks_per_sec()); | |
bd80f3fc | 3284 | s->rtl8139_mmio_io_addr_dummy = 0; |
05447803 FZ |
3285 | } |
3286 | ||
060110c3 JQ |
3287 | static const VMStateDescription vmstate_rtl8139 = { |
3288 | .name = "rtl8139", | |
3289 | .version_id = 4, | |
3290 | .minimum_version_id = 3, | |
3291 | .minimum_version_id_old = 3, | |
3292 | .post_load = rtl8139_post_load, | |
05447803 | 3293 | .pre_save = rtl8139_pre_save, |
060110c3 | 3294 | .fields = (VMStateField []) { |
88a411a8 | 3295 | VMSTATE_PCI_DEVICE(parent_obj, RTL8139State), |
060110c3 JQ |
3296 | VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6), |
3297 | VMSTATE_BUFFER(mult, RTL8139State), | |
3298 | VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4), | |
3299 | VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4), | |
3300 | ||
3301 | VMSTATE_UINT32(RxBuf, RTL8139State), | |
3302 | VMSTATE_UINT32(RxBufferSize, RTL8139State), | |
3303 | VMSTATE_UINT32(RxBufPtr, RTL8139State), | |
3304 | VMSTATE_UINT32(RxBufAddr, RTL8139State), | |
3305 | ||
3306 | VMSTATE_UINT16(IntrStatus, RTL8139State), | |
3307 | VMSTATE_UINT16(IntrMask, RTL8139State), | |
3308 | ||
3309 | VMSTATE_UINT32(TxConfig, RTL8139State), | |
3310 | VMSTATE_UINT32(RxConfig, RTL8139State), | |
3311 | VMSTATE_UINT32(RxMissed, RTL8139State), | |
3312 | VMSTATE_UINT16(CSCR, RTL8139State), | |
3313 | ||
3314 | VMSTATE_UINT8(Cfg9346, RTL8139State), | |
3315 | VMSTATE_UINT8(Config0, RTL8139State), | |
3316 | VMSTATE_UINT8(Config1, RTL8139State), | |
3317 | VMSTATE_UINT8(Config3, RTL8139State), | |
3318 | VMSTATE_UINT8(Config4, RTL8139State), | |
3319 | VMSTATE_UINT8(Config5, RTL8139State), | |
3320 | ||
3321 | VMSTATE_UINT8(clock_enabled, RTL8139State), | |
3322 | VMSTATE_UINT8(bChipCmdState, RTL8139State), | |
3323 | ||
3324 | VMSTATE_UINT16(MultiIntr, RTL8139State), | |
3325 | ||
3326 | VMSTATE_UINT16(BasicModeCtrl, RTL8139State), | |
3327 | VMSTATE_UINT16(BasicModeStatus, RTL8139State), | |
3328 | VMSTATE_UINT16(NWayAdvert, RTL8139State), | |
3329 | VMSTATE_UINT16(NWayLPAR, RTL8139State), | |
3330 | VMSTATE_UINT16(NWayExpansion, RTL8139State), | |
3331 | ||
3332 | VMSTATE_UINT16(CpCmd, RTL8139State), | |
3333 | VMSTATE_UINT8(TxThresh, RTL8139State), | |
3334 | ||
3335 | VMSTATE_UNUSED(4), | |
3336 | VMSTATE_MACADDR(conf.macaddr, RTL8139State), | |
c574ba5a | 3337 | VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State), |
060110c3 JQ |
3338 | |
3339 | VMSTATE_UINT32(currTxDesc, RTL8139State), | |
3340 | VMSTATE_UINT32(currCPlusRxDesc, RTL8139State), | |
3341 | VMSTATE_UINT32(currCPlusTxDesc, RTL8139State), | |
3342 | VMSTATE_UINT32(RxRingAddrLO, RTL8139State), | |
3343 | VMSTATE_UINT32(RxRingAddrHI, RTL8139State), | |
3344 | ||
3345 | VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE), | |
3346 | VMSTATE_INT32(eeprom.mode, RTL8139State), | |
3347 | VMSTATE_UINT32(eeprom.tick, RTL8139State), | |
3348 | VMSTATE_UINT8(eeprom.address, RTL8139State), | |
3349 | VMSTATE_UINT16(eeprom.input, RTL8139State), | |
3350 | VMSTATE_UINT16(eeprom.output, RTL8139State), | |
3351 | ||
3352 | VMSTATE_UINT8(eeprom.eecs, RTL8139State), | |
3353 | VMSTATE_UINT8(eeprom.eesk, RTL8139State), | |
3354 | VMSTATE_UINT8(eeprom.eedi, RTL8139State), | |
3355 | VMSTATE_UINT8(eeprom.eedo, RTL8139State), | |
3356 | ||
3357 | VMSTATE_UINT32(TCTR, RTL8139State), | |
3358 | VMSTATE_UINT32(TimerInt, RTL8139State), | |
3359 | VMSTATE_INT64(TCTR_base, RTL8139State), | |
3360 | ||
3361 | VMSTATE_STRUCT(tally_counters, RTL8139State, 0, | |
3362 | vmstate_tally_counters, RTL8139TallyCounters), | |
3363 | ||
3364 | VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4), | |
3365 | VMSTATE_END_OF_LIST() | |
c574ba5a AW |
3366 | }, |
3367 | .subsections = (VMStateSubsection []) { | |
3368 | { | |
3369 | .vmsd = &vmstate_rtl8139_hotplug_ready, | |
3370 | .needed = rtl8139_hotplug_ready_needed, | |
3371 | }, { | |
3372 | /* empty */ | |
3373 | } | |
060110c3 JQ |
3374 | } |
3375 | }; | |
3376 | ||
a41b2ff2 PB |
3377 | /***********************************************************/ |
3378 | /* PCI RTL8139 definitions */ | |
3379 | ||
1bebb0ad AG |
3380 | static void rtl8139_ioport_write(void *opaque, hwaddr addr, |
3381 | uint64_t val, unsigned size) | |
3382 | { | |
3383 | switch (size) { | |
3384 | case 1: | |
3385 | rtl8139_io_writeb(opaque, addr, val); | |
3386 | break; | |
3387 | case 2: | |
3388 | rtl8139_io_writew(opaque, addr, val); | |
3389 | break; | |
3390 | case 4: | |
3391 | rtl8139_io_writel(opaque, addr, val); | |
3392 | break; | |
3393 | } | |
3394 | } | |
3395 | ||
3396 | static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr, | |
3397 | unsigned size) | |
3398 | { | |
3399 | switch (size) { | |
3400 | case 1: | |
3401 | return rtl8139_io_readb(opaque, addr); | |
3402 | case 2: | |
3403 | return rtl8139_io_readw(opaque, addr); | |
3404 | case 4: | |
3405 | return rtl8139_io_readl(opaque, addr); | |
3406 | } | |
3407 | ||
3408 | return -1; | |
3409 | } | |
a41b2ff2 | 3410 | |
bd80f3fc | 3411 | static const MemoryRegionOps rtl8139_io_ops = { |
1bebb0ad AG |
3412 | .read = rtl8139_ioport_read, |
3413 | .write = rtl8139_ioport_write, | |
3414 | .impl = { | |
3415 | .min_access_size = 1, | |
3416 | .max_access_size = 4, | |
3417 | }, | |
bd80f3fc | 3418 | .endianness = DEVICE_LITTLE_ENDIAN, |
a41b2ff2 PB |
3419 | }; |
3420 | ||
bd80f3fc AK |
3421 | static const MemoryRegionOps rtl8139_mmio_ops = { |
3422 | .old_mmio = { | |
3423 | .read = { | |
3424 | rtl8139_mmio_readb, | |
3425 | rtl8139_mmio_readw, | |
3426 | rtl8139_mmio_readl, | |
3427 | }, | |
3428 | .write = { | |
3429 | rtl8139_mmio_writeb, | |
3430 | rtl8139_mmio_writew, | |
3431 | rtl8139_mmio_writel, | |
3432 | }, | |
3433 | }, | |
3434 | .endianness = DEVICE_LITTLE_ENDIAN, | |
a41b2ff2 PB |
3435 | }; |
3436 | ||
6cadb320 FB |
3437 | static void rtl8139_timer(void *opaque) |
3438 | { | |
3439 | RTL8139State *s = opaque; | |
3440 | ||
6cadb320 FB |
3441 | if (!s->clock_enabled) |
3442 | { | |
7cdeb319 | 3443 | DPRINTF(">>> timer: clock is not running\n"); |
6cadb320 FB |
3444 | return; |
3445 | } | |
3446 | ||
05447803 FZ |
3447 | s->IntrStatus |= PCSTimeout; |
3448 | rtl8139_update_irq(s); | |
bc72ad67 | 3449 | rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
6cadb320 | 3450 | } |
6cadb320 | 3451 | |
4e68f7a0 | 3452 | static void rtl8139_cleanup(NetClientState *nc) |
b946a153 | 3453 | { |
cc1f0f45 | 3454 | RTL8139State *s = qemu_get_nic_opaque(nc); |
b946a153 | 3455 | |
1673ad51 | 3456 | s->nic = NULL; |
254111ec GH |
3457 | } |
3458 | ||
f90c2bcd | 3459 | static void pci_rtl8139_uninit(PCIDevice *dev) |
254111ec | 3460 | { |
39257515 | 3461 | RTL8139State *s = RTL8139(dev); |
254111ec | 3462 | |
bd80f3fc AK |
3463 | memory_region_destroy(&s->bar_io); |
3464 | memory_region_destroy(&s->bar_mem); | |
b946a153 | 3465 | if (s->cplus_txbuffer) { |
7267c094 | 3466 | g_free(s->cplus_txbuffer); |
b946a153 AL |
3467 | s->cplus_txbuffer = NULL; |
3468 | } | |
bc72ad67 AB |
3469 | timer_del(s->timer); |
3470 | timer_free(s->timer); | |
948ecf21 | 3471 | qemu_del_nic(s->nic); |
b946a153 AL |
3472 | } |
3473 | ||
9e12c5af JW |
3474 | static void rtl8139_set_link_status(NetClientState *nc) |
3475 | { | |
cc1f0f45 | 3476 | RTL8139State *s = qemu_get_nic_opaque(nc); |
9e12c5af JW |
3477 | |
3478 | if (nc->link_down) { | |
3479 | s->BasicModeStatus &= ~0x04; | |
3480 | } else { | |
3481 | s->BasicModeStatus |= 0x04; | |
3482 | } | |
3483 | ||
3484 | s->IntrStatus |= RxUnderrun; | |
3485 | rtl8139_update_irq(s); | |
3486 | } | |
3487 | ||
1673ad51 | 3488 | static NetClientInfo net_rtl8139_info = { |
2be64a68 | 3489 | .type = NET_CLIENT_OPTIONS_KIND_NIC, |
1673ad51 MM |
3490 | .size = sizeof(NICState), |
3491 | .can_receive = rtl8139_can_receive, | |
3492 | .receive = rtl8139_receive, | |
3493 | .cleanup = rtl8139_cleanup, | |
9e12c5af | 3494 | .link_status_changed = rtl8139_set_link_status, |
1673ad51 MM |
3495 | }; |
3496 | ||
81a322d4 | 3497 | static int pci_rtl8139_init(PCIDevice *dev) |
a41b2ff2 | 3498 | { |
39257515 PC |
3499 | RTL8139State *s = RTL8139(dev); |
3500 | DeviceState *d = DEVICE(dev); | |
a41b2ff2 | 3501 | uint8_t *pci_conf; |
3b46e624 | 3502 | |
88a411a8 | 3503 | pci_conf = dev->config; |
817e0b6f | 3504 | pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ |
0b5b3547 MT |
3505 | /* TODO: start of capability list, but no capability |
3506 | * list bit in status register, and offset 0xdc seems unused. */ | |
3507 | pci_conf[PCI_CAPABILITY_LIST] = 0xdc; | |
a41b2ff2 | 3508 | |
eedfac6f PB |
3509 | memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s, |
3510 | "rtl8139", 0x100); | |
3511 | memory_region_init_io(&s->bar_mem, OBJECT(s), &rtl8139_mmio_ops, s, | |
3512 | "rtl8139", 0x100); | |
88a411a8 AF |
3513 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io); |
3514 | pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem); | |
a41b2ff2 | 3515 | |
254111ec | 3516 | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
c1699988 | 3517 | |
7165448a WD |
3518 | /* prepare eeprom */ |
3519 | s->eeprom.contents[0] = 0x8129; | |
3520 | #if 1 | |
3521 | /* PCI vendor and device ID should be mirrored here */ | |
3522 | s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK; | |
3523 | s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139; | |
3524 | #endif | |
3525 | s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8; | |
3526 | s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8; | |
3527 | s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8; | |
3528 | ||
1673ad51 | 3529 | s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf, |
39257515 | 3530 | object_get_typename(OBJECT(dev)), d->id, s); |
b356f76d | 3531 | qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
6cadb320 FB |
3532 | |
3533 | s->cplus_txbuffer = NULL; | |
3534 | s->cplus_txbuffer_len = 0; | |
3535 | s->cplus_txbuffer_offset = 0; | |
3b46e624 | 3536 | |
05447803 | 3537 | s->TimerExpire = 0; |
bc72ad67 AB |
3538 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s); |
3539 | rtl8139_set_next_tctr_time(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); | |
1ca4d09a | 3540 | |
39257515 | 3541 | add_boot_device_path(s->conf.bootindex, d, "/ethernet-phy@0"); |
1ca4d09a | 3542 | |
81a322d4 | 3543 | return 0; |
a41b2ff2 | 3544 | } |
9d07d757 | 3545 | |
40021f08 AL |
3546 | static Property rtl8139_properties[] = { |
3547 | DEFINE_NIC_PROPERTIES(RTL8139State, conf), | |
3548 | DEFINE_PROP_END_OF_LIST(), | |
3549 | }; | |
3550 | ||
3551 | static void rtl8139_class_init(ObjectClass *klass, void *data) | |
3552 | { | |
39bffca2 | 3553 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
3554 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
3555 | ||
3556 | k->init = pci_rtl8139_init; | |
3557 | k->exit = pci_rtl8139_uninit; | |
c45e5b5b | 3558 | k->romfile = "efi-rtl8139.rom"; |
40021f08 AL |
3559 | k->vendor_id = PCI_VENDOR_ID_REALTEK; |
3560 | k->device_id = PCI_DEVICE_ID_REALTEK_8139; | |
3561 | k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */ | |
3562 | k->class_id = PCI_CLASS_NETWORK_ETHERNET; | |
39bffca2 AL |
3563 | dc->reset = rtl8139_reset; |
3564 | dc->vmsd = &vmstate_rtl8139; | |
3565 | dc->props = rtl8139_properties; | |
125ee0ed | 3566 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); |
40021f08 AL |
3567 | } |
3568 | ||
8c43a6f0 | 3569 | static const TypeInfo rtl8139_info = { |
39257515 | 3570 | .name = TYPE_RTL8139, |
39bffca2 AL |
3571 | .parent = TYPE_PCI_DEVICE, |
3572 | .instance_size = sizeof(RTL8139State), | |
3573 | .class_init = rtl8139_class_init, | |
0aab0d3a GH |
3574 | }; |
3575 | ||
83f7d43a | 3576 | static void rtl8139_register_types(void) |
9d07d757 | 3577 | { |
39bffca2 | 3578 | type_register_static(&rtl8139_info); |
9d07d757 PB |
3579 | } |
3580 | ||
83f7d43a | 3581 | type_init(rtl8139_register_types) |