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99f575ed JL |
1 | /* |
2 | * QEMU OpenRISC timer support | |
3 | * | |
4 | * Copyright (c) 2011-2012 Jia Liu <[email protected]> | |
5 | * Zhizhou Zhang <[email protected]> | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
198a2d21 | 10 | * version 2.1 of the License, or (at your option) any later version. |
99f575ed JL |
11 | * |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
ed2decc6 | 21 | #include "qemu/osdep.h" |
99f575ed | 22 | #include "cpu.h" |
83c9f4ca | 23 | #include "hw/hw.h" |
1de7afc9 | 24 | #include "qemu/timer.h" |
99f575ed | 25 | |
ccaf1749 | 26 | #define TIMER_PERIOD 50 /* 50 ns period for 20 MHz timer */ |
99f575ed | 27 | |
6b4bbd6a SH |
28 | /* Tick Timer global state to allow all cores to be in sync */ |
29 | typedef struct OR1KTimerState { | |
30 | uint32_t ttcr; | |
31 | uint64_t last_clk; | |
32 | } OR1KTimerState; | |
99f575ed | 33 | |
6b4bbd6a SH |
34 | static OR1KTimerState *or1k_timer; |
35 | ||
36 | void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val) | |
37 | { | |
38 | or1k_timer->ttcr = val; | |
39 | } | |
40 | ||
41 | uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu) | |
42 | { | |
43 | return or1k_timer->ttcr; | |
44 | } | |
45 | ||
46 | /* Add elapsed ticks to ttcr */ | |
99f575ed JL |
47 | void cpu_openrisc_count_update(OpenRISCCPU *cpu) |
48 | { | |
d5155217 | 49 | uint64_t now; |
99f575ed | 50 | |
6b4bbd6a | 51 | if (!cpu->env.is_counting) { |
99f575ed JL |
52 | return; |
53 | } | |
d5155217 | 54 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
6b4bbd6a SH |
55 | or1k_timer->ttcr += (uint32_t)((now - or1k_timer->last_clk) |
56 | / TIMER_PERIOD); | |
57 | or1k_timer->last_clk = now; | |
d5155217 SM |
58 | } |
59 | ||
6b4bbd6a | 60 | /* Update the next timeout time as difference between ttmr and ttcr */ |
d5155217 SM |
61 | void cpu_openrisc_timer_update(OpenRISCCPU *cpu) |
62 | { | |
63 | uint32_t wait; | |
64 | uint64_t now, next; | |
65 | ||
6b4bbd6a | 66 | if (!cpu->env.is_counting) { |
d5155217 SM |
67 | return; |
68 | } | |
69 | ||
70 | cpu_openrisc_count_update(cpu); | |
6b4bbd6a | 71 | now = or1k_timer->last_clk; |
99f575ed | 72 | |
6b4bbd6a SH |
73 | if ((cpu->env.ttmr & TTMR_TP) <= (or1k_timer->ttcr & TTMR_TP)) { |
74 | wait = TTMR_TP - (or1k_timer->ttcr & TTMR_TP) + 1; | |
99f575ed JL |
75 | wait += cpu->env.ttmr & TTMR_TP; |
76 | } else { | |
6b4bbd6a | 77 | wait = (cpu->env.ttmr & TTMR_TP) - (or1k_timer->ttcr & TTMR_TP); |
99f575ed | 78 | } |
ccaf1749 | 79 | next = now + (uint64_t)wait * TIMER_PERIOD; |
bc72ad67 | 80 | timer_mod(cpu->env.timer, next); |
99f575ed JL |
81 | } |
82 | ||
83 | void cpu_openrisc_count_start(OpenRISCCPU *cpu) | |
84 | { | |
6b4bbd6a | 85 | cpu->env.is_counting = 1; |
99f575ed JL |
86 | cpu_openrisc_count_update(cpu); |
87 | } | |
88 | ||
89 | void cpu_openrisc_count_stop(OpenRISCCPU *cpu) | |
90 | { | |
d5155217 | 91 | timer_del(cpu->env.timer); |
99f575ed | 92 | cpu_openrisc_count_update(cpu); |
6b4bbd6a | 93 | cpu->env.is_counting = 0; |
99f575ed JL |
94 | } |
95 | ||
96 | static void openrisc_timer_cb(void *opaque) | |
97 | { | |
98 | OpenRISCCPU *cpu = opaque; | |
99 | ||
100 | if ((cpu->env.ttmr & TTMR_IE) && | |
bc72ad67 | 101 | timer_expired(cpu->env.timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL))) { |
259186a7 AF |
102 | CPUState *cs = CPU(cpu); |
103 | ||
99f575ed | 104 | cpu->env.ttmr |= TTMR_IP; |
259186a7 | 105 | cs->interrupt_request |= CPU_INTERRUPT_TIMER; |
99f575ed JL |
106 | } |
107 | ||
108 | switch (cpu->env.ttmr & TTMR_M) { | |
109 | case TIMER_NONE: | |
110 | break; | |
111 | case TIMER_INTR: | |
6b4bbd6a | 112 | or1k_timer->ttcr = 0; |
99f575ed JL |
113 | break; |
114 | case TIMER_SHOT: | |
115 | cpu_openrisc_count_stop(cpu); | |
116 | break; | |
117 | case TIMER_CONT: | |
99f575ed JL |
118 | break; |
119 | } | |
d5155217 SM |
120 | |
121 | cpu_openrisc_timer_update(cpu); | |
373b259b | 122 | qemu_cpu_kick(CPU(cpu)); |
99f575ed JL |
123 | } |
124 | ||
6b4bbd6a SH |
125 | static const VMStateDescription vmstate_or1k_timer = { |
126 | .name = "or1k_timer", | |
127 | .version_id = 1, | |
128 | .minimum_version_id = 1, | |
129 | .fields = (VMStateField[]) { | |
130 | VMSTATE_UINT32(ttcr, OR1KTimerState), | |
131 | VMSTATE_UINT64(last_clk, OR1KTimerState), | |
132 | VMSTATE_END_OF_LIST() | |
133 | } | |
134 | }; | |
135 | ||
99f575ed JL |
136 | void cpu_openrisc_clock_init(OpenRISCCPU *cpu) |
137 | { | |
bc72ad67 | 138 | cpu->env.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &openrisc_timer_cb, cpu); |
99f575ed | 139 | cpu->env.ttmr = 0x00000000; |
6b4bbd6a SH |
140 | |
141 | if (or1k_timer == NULL) { | |
142 | or1k_timer = g_new0(OR1KTimerState, 1); | |
143 | vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer); | |
144 | } | |
99f575ed | 145 | } |