[qemu.git] / hw / arm / armv7m.c

/*
 * ARMV7M System emulation.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "hw/arm/armv7m.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/arm/arm.h"
#include "hw/loader.h"
#include "elf.h"
#include "sysemu/qtest.h"
#include "qemu/error-report.h"
#include "exec/address-spaces.h"
#include "target/arm/idau.h"

/* Bitbanded IO.  Each word corresponds to a single bit.  */

/* Get the byte address of the real memory for a bitband access.  */
static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
{
    return s->base | (offset & 0x1ffffff) >> 5;
}

static MemTxResult bitband_read(void *opaque, hwaddr offset,
                                uint64_t *data, unsigned size, MemTxAttrs attrs)
{
    BitBandState *s = opaque;
    uint8_t buf[4];
    MemTxResult res;
    int bitpos, bit;
    hwaddr addr;

    assert(size <= 4);

    /* Find address in underlying memory and round down to multiple of size */
    addr = bitband_addr(s, offset) & (-size);
    res = address_space_read(&s->source_as, addr, attrs, buf, size);
    if (res) {
        return res;
    }
    /* Bit position in the N bytes read... */
    bitpos = (offset >> 2) & ((size * 8) - 1);
    /* ...converted to byte in buffer and bit in byte */
    bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
    *data = bit;
    return MEMTX_OK;
}

static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
                                 unsigned size, MemTxAttrs attrs)
{
    BitBandState *s = opaque;
    uint8_t buf[4];
    MemTxResult res;
    int bitpos, bit;
    hwaddr addr;

    assert(size <= 4);

    /* Find address in underlying memory and round down to multiple of size */
    addr = bitband_addr(s, offset) & (-size);
    res = address_space_read(&s->source_as, addr, attrs, buf, size);
    if (res) {
        return res;
    }
    /* Bit position in the N bytes read... */
    bitpos = (offset >> 2) & ((size * 8) - 1);
    /* ...converted to byte in buffer and bit in byte */
    bit = 1 << (bitpos & 7);
    if (value & 1) {
        buf[bitpos >> 3] |= bit;
    } else {
        buf[bitpos >> 3] &= ~bit;
    }
    return address_space_write(&s->source_as, addr, attrs, buf, size);
}

static const MemoryRegionOps bitband_ops = {
    .read_with_attrs = bitband_read,
    .write_with_attrs = bitband_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .impl.min_access_size = 1,
    .impl.max_access_size = 4,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
};

static void bitband_init(Object *obj)
{
    BitBandState *s = BITBAND(obj);
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);

    memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
                          "bitband", 0x02000000);
    sysbus_init_mmio(dev, &s->iomem);
}

static void bitband_realize(DeviceState *dev, Error **errp)
{
    BitBandState *s = BITBAND(dev);

    if (!s->source_memory) {
        error_setg(errp, "source-memory property not set");
        return;
    }

    address_space_init(&s->source_as, s->source_memory, "bitband-source");
}

/* Board init.  */

static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
    0x20000000, 0x40000000
};

static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
    0x22000000, 0x42000000
};

static void armv7m_instance_init(Object *obj)
{
    ARMv7MState *s = ARMV7M(obj);
    int i;

    /* Can't init the cpu here, we don't yet know which model to use */

    memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);

    object_initialize(&s->nvic, sizeof(s->nvic), TYPE_NVIC);
    qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());
    object_property_add_alias(obj, "num-irq",
                              OBJECT(&s->nvic), "num-irq", &error_abort);

    for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
        object_initialize(&s->bitband[i], sizeof(s->bitband[i]), TYPE_BITBAND);
        qdev_set_parent_bus(DEVICE(&s->bitband[i]), sysbus_get_default());
    }
}

static void armv7m_realize(DeviceState *dev, Error **errp)
{
    ARMv7MState *s = ARMV7M(dev);
    SysBusDevice *sbd;
    Error *err = NULL;
    int i;

    if (!s->board_memory) {
        error_setg(errp, "memory property was not set");
        return;
    }

    memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);

    s->cpu = ARM_CPU(object_new(s->cpu_type));

    object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
                             &error_abort);
    if (object_property_find(OBJECT(s->cpu), "idau", NULL)) {
        object_property_set_link(OBJECT(s->cpu), s->idau, "idau", &err);
        if (err != NULL) {
            error_propagate(errp, err);
            return;
        }
    }
    if (object_property_find(OBJECT(s->cpu), "init-svtor", NULL)) {
        object_property_set_uint(OBJECT(s->cpu), s->init_svtor,
                                 "init-svtor", &err);
        if (err != NULL) {
            error_propagate(errp, err);
            return;
        }
    }
    object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
    if (err != NULL) {
        error_propagate(errp, err);
        return;
    }

    /* Note that we must realize the NVIC after the CPU */
    object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
    if (err != NULL) {
        error_propagate(errp, err);
        return;
    }

    /* Alias the NVIC's input and output GPIOs as our own so the board
     * code can wire them up. (We do this in realize because the
     * NVIC doesn't create the input GPIO array until realize.)
     */
    qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
    qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");

    /* Wire the NVIC up to the CPU */
    sbd = SYS_BUS_DEVICE(&s->nvic);
    sysbus_connect_irq(sbd, 0,
                       qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
    s->cpu->env.nvic = &s->nvic;

    memory_region_add_subregion(&s->container, 0xe000e000,
                                sysbus_mmio_get_region(sbd, 0));

    for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
        Object *obj = OBJECT(&s->bitband[i]);
        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);

        object_property_set_int(obj, bitband_input_addr[i], "base", &err);
        if (err != NULL) {
            error_propagate(errp, err);
            return;
        }
        object_property_set_link(obj, OBJECT(s->board_memory),
                                 "source-memory", &error_abort);
        object_property_set_bool(obj, true, "realized", &err);
        if (err != NULL) {
            error_propagate(errp, err);
            return;
        }

        memory_region_add_subregion(&s->container, bitband_output_addr[i],
                                    sysbus_mmio_get_region(sbd, 0));
    }
}

static Property armv7m_properties[] = {
    DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type),
    DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,
                     MemoryRegion *),
    DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *),
    DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void armv7m_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = armv7m_realize;
    dc->props = armv7m_properties;
}

static const TypeInfo armv7m_info = {
    .name = TYPE_ARMV7M,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(ARMv7MState),
    .instance_init = armv7m_instance_init,
    .class_init = armv7m_class_init,
};

static void armv7m_reset(void *opaque)
{
    ARMCPU *cpu = opaque;

    cpu_reset(CPU(cpu));
}

/* Init CPU and memory for a v7-M based board.
   mem_size is in bytes.
   Returns the ARMv7M device.  */

DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
                         const char *kernel_filename, const char *cpu_type)
{
    DeviceState *armv7m;

    armv7m = qdev_create(NULL, TYPE_ARMV7M);
    qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
    qdev_prop_set_string(armv7m, "cpu-type", cpu_type);
    object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),
                                     "memory", &error_abort);
    /* This will exit with an error if the user passed us a bad cpu_type */
    qdev_init_nofail(armv7m);

    armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);
    return armv7m;
}

void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
{
    int image_size;
    uint64_t entry;
    uint64_t lowaddr;
    int big_endian;
    AddressSpace *as;
    int asidx;
    CPUState *cs = CPU(cpu);

#ifdef TARGET_WORDS_BIGENDIAN
    big_endian = 1;
#else
    big_endian = 0;
#endif

    if (!kernel_filename && !qtest_enabled()) {
        error_report("Guest image must be specified (using -kernel)");
        exit(1);
    }

    if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
        asidx = ARMASIdx_S;
    } else {
        asidx = ARMASIdx_NS;
    }
    as = cpu_get_address_space(cs, asidx);

    if (kernel_filename) {
        image_size = load_elf_as(kernel_filename, NULL, NULL, &entry, &lowaddr,
                                 NULL, big_endian, EM_ARM, 1, 0, as);
        if (image_size < 0) {
            image_size = load_image_targphys_as(kernel_filename, 0,
                                                mem_size, as);
            lowaddr = 0;
        }
        if (image_size < 0) {
            error_report("Could not load kernel '%s'", kernel_filename);
            exit(1);
        }
    }

    /* CPU objects (unlike devices) are not automatically reset on system
     * reset, so we must always register a handler to do so. Unlike
     * A-profile CPUs, we don't need to do anything special in the
     * handler to arrange that it starts correctly.
     * This is arguably the wrong place to do this, but it matches the
     * way A-profile does it. Note that this means that every M profile
     * board must call this function!
     */
    qemu_register_reset(armv7m_reset, cpu);
}

static Property bitband_properties[] = {
    DEFINE_PROP_UINT32("base", BitBandState, base, 0),
    DEFINE_PROP_LINK("source-memory", BitBandState, source_memory,
                     TYPE_MEMORY_REGION, MemoryRegion *),
    DEFINE_PROP_END_OF_LIST(),
};

static void bitband_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = bitband_realize;
    dc->props = bitband_properties;
}

static const TypeInfo bitband_info = {
    .name          = TYPE_BITBAND,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(BitBandState),
    .instance_init = bitband_init,
    .class_init    = bitband_class_init,
};

static void armv7m_register_types(void)
{
    type_register_static(&bitband_info);
    type_register_static(&armv7m_info);
}

type_init(armv7m_register_types)
Commit	Line	Data
9ee6e8bb PB	1	/*
	2	* ARMV7M System emulation.
	3	*
	4	* Copyright (c) 2006-2007 CodeSourcery.
	5	* Written by Paul Brook
	6	*
2167f7bc	7	* This code is licensed under the GPL.
9ee6e8bb PB	8	*/
9ee6e8bb PB	9
12b16722	10	#include "qemu/osdep.h"
56b7c66f	11	#include "hw/arm/armv7m.h"
da34e65c	12	#include "qapi/error.h"
4771d756 PB	13	#include "qemu-common.h"
4771d756 PB	14	#include "cpu.h"
83c9f4ca	15	#include "hw/sysbus.h"
bd2be150	16	#include "hw/arm/arm.h"
83c9f4ca	17	#include "hw/loader.h"
ca20cf32	18	#include "elf.h"
5633b90a AF	19	#include "sysemu/qtest.h"
5633b90a AF	20	#include "qemu/error-report.h"
618119c2	21	#include "exec/address-spaces.h"
c60c1b0d	22	#include "target/arm/idau.h"
9ee6e8bb PB	23
	24	/* Bitbanded IO. Each word corresponds to a single bit. */
	25
2167f7bc	26	/* Get the byte address of the real memory for a bitband access. */
f68d881c	27	static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
9ee6e8bb	28	{
f68d881c	29	return s->base \| (offset & 0x1ffffff) >> 5;
9ee6e8bb PB	30	}
9ee6e8bb PB	31
f68d881c PM	32	static MemTxResult bitband_read(void *opaque, hwaddr offset,
f68d881c PM	33	uint64_t *data, unsigned size, MemTxAttrs attrs)
9ee6e8bb	34	{
f68d881c PM	35	BitBandState *s = opaque;
	36	uint8_t buf[4];
	37	MemTxResult res;
	38	int bitpos, bit;
	39	hwaddr addr;
	40
	41	assert(size <= 4);
	42
	43	/* Find address in underlying memory and round down to multiple of size */
	44	addr = bitband_addr(s, offset) & (-size);
b516572f	45	res = address_space_read(&s->source_as, addr, attrs, buf, size);
f68d881c PM	46	if (res) {
	47	return res;
	48	}
	49	/* Bit position in the N bytes read... */
	50	bitpos = (offset >> 2) & ((size * 8) - 1);
	51	/* ...converted to byte in buffer and bit in byte */
	52	bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
	53	*data = bit;
	54	return MEMTX_OK;
9ee6e8bb PB	55	}
9ee6e8bb PB	56
f68d881c PM	57	static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
f68d881c PM	58	unsigned size, MemTxAttrs attrs)
9ee6e8bb	59	{
f68d881c PM	60	BitBandState *s = opaque;
	61	uint8_t buf[4];
	62	MemTxResult res;
	63	int bitpos, bit;
	64	hwaddr addr;
	65
	66	assert(size <= 4);
	67
	68	/* Find address in underlying memory and round down to multiple of size */
	69	addr = bitband_addr(s, offset) & (-size);
b516572f	70	res = address_space_read(&s->source_as, addr, attrs, buf, size);
f68d881c PM	71	if (res) {
	72	return res;
	73	}
	74	/* Bit position in the N bytes read... */
	75	bitpos = (offset >> 2) & ((size * 8) - 1);
	76	/* ...converted to byte in buffer and bit in byte */
	77	bit = 1 << (bitpos & 7);
	78	if (value & 1) {
	79	buf[bitpos >> 3] \|= bit;
	80	} else {
	81	buf[bitpos >> 3] &= ~bit;
	82	}
b516572f	83	return address_space_write(&s->source_as, addr, attrs, buf, size);
9ee6e8bb PB	84	}
9ee6e8bb PB	85
f69bf9d4	86	static const MemoryRegionOps bitband_ops = {
f68d881c PM	87	.read_with_attrs = bitband_read,
f68d881c PM	88	.write_with_attrs = bitband_write,
f69bf9d4	89	.endianness = DEVICE_NATIVE_ENDIAN,
f68d881c PM	90	.impl.min_access_size = 1,
	91	.impl.max_access_size = 4,
	92	.valid.min_access_size = 1,
	93	.valid.max_access_size = 4,
9ee6e8bb PB	94	};
9ee6e8bb PB	95
3f5ab254	96	static void bitband_init(Object *obj)
9ee6e8bb	97	{
3f5ab254 XZ	98	BitBandState *s = BITBAND(obj);
3f5ab254 XZ	99	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
9ee6e8bb	100
f68d881c	101	memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
64bde0f3	102	"bitband", 0x02000000);
750ecd44	103	sysbus_init_mmio(dev, &s->iomem);
40905a6a PB	104	}
40905a6a PB	105
f68d881c PM	106	static void bitband_realize(DeviceState dev, Error *errp)
	107	{
	108	BitBandState *s = BITBAND(dev);
	109
	110	if (!s->source_memory) {
	111	error_setg(errp, "source-memory property not set");
	112	return;
	113	}
	114
b516572f	115	address_space_init(&s->source_as, s->source_memory, "bitband-source");
f68d881c PM	116	}
f68d881c PM	117
9ee6e8bb	118	/* Board init. */
983fe826	119
56b7c66f PM	120	static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
	121	0x20000000, 0x40000000
	122	};
	123
	124	static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
	125	0x22000000, 0x42000000
	126	};
	127
	128	static void armv7m_instance_init(Object *obj)
	129	{
	130	ARMv7MState *s = ARMV7M(obj);
	131	int i;
	132
	133	/* Can't init the cpu here, we don't yet know which model to use */
	134
618119c2 PM	135	memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
618119c2 PM	136
c2de81e2	137	object_initialize(&s->nvic, sizeof(s->nvic), TYPE_NVIC);
56b7c66f PM	138	qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());
	139	object_property_add_alias(obj, "num-irq",
	140	OBJECT(&s->nvic), "num-irq", &error_abort);
	141
	142	for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
	143	object_initialize(&s->bitband[i], sizeof(s->bitband[i]), TYPE_BITBAND);
	144	qdev_set_parent_bus(DEVICE(&s->bitband[i]), sysbus_get_default());
	145	}
	146	}
	147
	148	static void armv7m_realize(DeviceState dev, Error *errp)
	149	{
	150	ARMv7MState *s = ARMV7M(dev);
98957a94	151	SysBusDevice *sbd;
56b7c66f PM	152	Error *err = NULL;
56b7c66f PM	153	int i;
56b7c66f	154
618119c2 PM	155	if (!s->board_memory) {
	156	error_setg(errp, "memory property was not set");
	157	return;
	158	}
	159
	160	memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
	161
ba1ba5cc	162	s->cpu = ARM_CPU(object_new(s->cpu_type));
56b7c66f	163
618119c2 PM	164	object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
618119c2 PM	165	&error_abort);
c60c1b0d PM	166	if (object_property_find(OBJECT(s->cpu), "idau", NULL)) {
	167	object_property_set_link(OBJECT(s->cpu), s->idau, "idau", &err);
	168	if (err != NULL) {
	169	error_propagate(errp, err);
	170	return;
	171	}
	172	}
60d75d81 PM	173	if (object_property_find(OBJECT(s->cpu), "init-svtor", NULL)) {
	174	object_property_set_uint(OBJECT(s->cpu), s->init_svtor,
	175	"init-svtor", &err);
	176	if (err != NULL) {
	177	error_propagate(errp, err);
	178	return;
	179	}
	180	}
56b7c66f PM	181	object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
	182	if (err != NULL) {
	183	error_propagate(errp, err);
	184	return;
	185	}
	186
	187	/* Note that we must realize the NVIC after the CPU */
	188	object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
	189	if (err != NULL) {
	190	error_propagate(errp, err);
	191	return;
	192	}
	193
	194	/* Alias the NVIC's input and output GPIOs as our own so the board
	195	* code can wire them up. (We do this in realize because the
	196	* NVIC doesn't create the input GPIO array until realize.)
	197	*/
	198	qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
	199	qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
	200
	201	/* Wire the NVIC up to the CPU */
98957a94 PM	202	sbd = SYS_BUS_DEVICE(&s->nvic);
98957a94 PM	203	sysbus_connect_irq(sbd, 0,
56b7c66f PM	204	qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
	205	s->cpu->env.nvic = &s->nvic;
	206
98957a94 PM	207	memory_region_add_subregion(&s->container, 0xe000e000,
	208	sysbus_mmio_get_region(sbd, 0));
	209
56b7c66f PM	210	for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
	211	Object *obj = OBJECT(&s->bitband[i]);
	212	SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
	213
	214	object_property_set_int(obj, bitband_input_addr[i], "base", &err);
	215	if (err != NULL) {
	216	error_propagate(errp, err);
	217	return;
	218	}
f68d881c PM	219	object_property_set_link(obj, OBJECT(s->board_memory),
f68d881c PM	220	"source-memory", &error_abort);
56b7c66f PM	221	object_property_set_bool(obj, true, "realized", &err);
	222	if (err != NULL) {
	223	error_propagate(errp, err);
	224	return;
	225	}
	226
618119c2 PM	227	memory_region_add_subregion(&s->container, bitband_output_addr[i],
618119c2 PM	228	sysbus_mmio_get_region(sbd, 0));
56b7c66f PM	229	}
	230	}
	231
	232	static Property armv7m_properties[] = {
ba1ba5cc	233	DEFINE_PROP_STRING("cpu-type", ARMv7MState, cpu_type),
e2ff1215 FZ	234	DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,
e2ff1215 FZ	235	MemoryRegion *),
c60c1b0d	236	DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *),
60d75d81	237	DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0),
56b7c66f PM	238	DEFINE_PROP_END_OF_LIST(),
	239	};
	240
	241	static void armv7m_class_init(ObjectClass klass, void data)
	242	{
	243	DeviceClass *dc = DEVICE_CLASS(klass);
	244
	245	dc->realize = armv7m_realize;
	246	dc->props = armv7m_properties;
	247	}
	248
	249	static const TypeInfo armv7m_info = {
	250	.name = TYPE_ARMV7M,
	251	.parent = TYPE_SYS_BUS_DEVICE,
	252	.instance_size = sizeof(ARMv7MState),
	253	.instance_init = armv7m_instance_init,
	254	.class_init = armv7m_class_init,
	255	};
	256
983fe826 PB	257	static void armv7m_reset(void *opaque)
983fe826 PB	258	{
31363f12 AF	259	ARMCPU *cpu = opaque;
	260
	261	cpu_reset(CPU(cpu));
983fe826 PB	262	}
983fe826 PB	263
9ee6e8bb	264	/* Init CPU and memory for a v7-M based board.
fe6ac447	265	mem_size is in bytes.
21e0c38f	266	Returns the ARMv7M device. */
9ee6e8bb	267
20c59c38	268	DeviceState armv7m_init(MemoryRegion system_memory, int mem_size, int num_irq,
ba1ba5cc	269	const char kernel_filename, const char cpu_type)
9ee6e8bb	270	{
21e0c38f	271	DeviceState *armv7m;
9ee6e8bb	272
c2de81e2	273	armv7m = qdev_create(NULL, TYPE_ARMV7M);
21e0c38f	274	qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
ba1ba5cc	275	qdev_prop_set_string(armv7m, "cpu-type", cpu_type);
618119c2 PM	276	object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),
618119c2 PM	277	"memory", &error_abort);
ba1ba5cc	278	/* This will exit with an error if the user passed us a bad cpu_type */
21e0c38f PM	279	qdev_init_nofail(armv7m);
	280
	281	armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);
	282	return armv7m;
3651c285 PM	283	}
	284
	285	void armv7m_load_kernel(ARMCPU cpu, const char kernel_filename, int mem_size)
	286	{
	287	int image_size;
	288	uint64_t entry;
	289	uint64_t lowaddr;
	290	int big_endian;
891f3bc3 PM	291	AddressSpace *as;
	292	int asidx;
	293	CPUState *cs = CPU(cpu);
9ee6e8bb	294
ca20cf32 BS	295	#ifdef TARGET_WORDS_BIGENDIAN
	296	big_endian = 1;
	297	#else
	298	big_endian = 0;
	299	#endif
	300
5633b90a	301	if (!kernel_filename && !qtest_enabled()) {
c0dbca36	302	error_report("Guest image must be specified (using -kernel)");
01fd41ab PC	303	exit(1);
	304	}
	305
891f3bc3 PM	306	if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
	307	asidx = ARMASIdx_S;
	308	} else {
	309	asidx = ARMASIdx_NS;
	310	}
	311	as = cpu_get_address_space(cs, asidx);
	312
5633b90a	313	if (kernel_filename) {
891f3bc3 PM	314	image_size = load_elf_as(kernel_filename, NULL, NULL, &entry, &lowaddr,
891f3bc3 PM	315	NULL, big_endian, EM_ARM, 1, 0, as);
5633b90a	316	if (image_size < 0) {
891f3bc3 PM	317	image_size = load_image_targphys_as(kernel_filename, 0,
891f3bc3 PM	318	mem_size, as);
5633b90a AF	319	lowaddr = 0;
	320	}
	321	if (image_size < 0) {
	322	error_report("Could not load kernel '%s'", kernel_filename);
	323	exit(1);
	324	}
9ee6e8bb PB	325	}
9ee6e8bb PB	326
3651c285 PM	327	/* CPU objects (unlike devices) are not automatically reset on system
	328	* reset, so we must always register a handler to do so. Unlike
	329	* A-profile CPUs, we don't need to do anything special in the
	330	* handler to arrange that it starts correctly.
	331	* This is arguably the wrong place to do this, but it matches the
	332	* way A-profile does it. Note that this means that every M profile
	333	* board must call this function!
	334	*/
31363f12	335	qemu_register_reset(armv7m_reset, cpu);
9ee6e8bb	336	}
40905a6a	337
999e12bb AL	338	static Property bitband_properties[] = {
999e12bb AL	339	DEFINE_PROP_UINT32("base", BitBandState, base, 0),
5f486f97 FZ	340	DEFINE_PROP_LINK("source-memory", BitBandState, source_memory,
5f486f97 FZ	341	TYPE_MEMORY_REGION, MemoryRegion *),
999e12bb AL	342	DEFINE_PROP_END_OF_LIST(),
	343	};
	344
	345	static void bitband_class_init(ObjectClass klass, void data)
	346	{
39bffca2	347	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	348
f68d881c	349	dc->realize = bitband_realize;
39bffca2	350	dc->props = bitband_properties;
999e12bb AL	351	}
999e12bb AL	352
8c43a6f0	353	static const TypeInfo bitband_info = {
936230a7	354	.name = TYPE_BITBAND,
39bffca2 AL	355	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	356	.instance_size = sizeof(BitBandState),
3f5ab254	357	.instance_init = bitband_init,
39bffca2	358	.class_init = bitband_class_init,
ee6847d1 GH	359	};
ee6847d1 GH	360
83f7d43a	361	static void armv7m_register_types(void)
40905a6a	362	{
39bffca2	363	type_register_static(&bitband_info);
56b7c66f	364	type_register_static(&armv7m_info);
40905a6a PB	365	}
40905a6a PB	366
83f7d43a	367	type_init(armv7m_register_types)