[qemu.git] / hw / etraxfs_eth.c

/*
 * QEMU ETRAX Ethernet Controller.
 *
 * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include <stdio.h>
#include "hw.h"
#include "net.h"

#include "etraxfs_dma.h"

#define D(x)

/* 
 * The MDIO extensions in the TDK PHY model were reversed engineered from the 
 * linux driver (PHYID and Diagnostics reg).
 * TODO: Add friendly names for the register nums.
 */
struct qemu_phy
{
	uint32_t regs[32];

	unsigned int (*read)(struct qemu_phy *phy, unsigned int req);
	void (*write)(struct qemu_phy *phy, unsigned int req, 
		      unsigned int data);
};

static unsigned int tdk_read(struct qemu_phy *phy, unsigned int req)
{
	int regnum;
	unsigned r = 0;

	regnum = req & 0x1f;

	switch (regnum) {
		case 1:
			/* MR1.	 */
			/* Speeds and modes.  */
			r |= (1 << 13) | (1 << 14);
			r |= (1 << 11) | (1 << 12);
			r |= (1 << 5); /* Autoneg complete.  */
			r |= (1 << 3); /* Autoneg able.	 */
			r |= (1 << 2); /* Link.	 */
			break;
		case 5:
			/* Link partner ability.
			   We are kind; always agree with whatever best mode
			   the guest advertises.  */
			r = 1 << 14; /* Success.  */
			/* Copy advertised modes.  */
			r |= phy->regs[4] & (15 << 5);
			/* Autoneg support.  */
			r |= 1;
			break;
		case 18:
		{
			/* Diagnostics reg.  */
			int duplex = 0;
			int speed_100 = 0;

			/* Are we advertising 100 half or 100 duplex ? */
			speed_100 = !!(phy->regs[4] & 0x180);
			/* Are we advertising 10 duplex or 100 duplex ? */
			duplex = !!(phy->regs[4] & 0x180);
			r = (speed_100 << 10) | (duplex << 11);
		}
		break;

		default:
			r = phy->regs[regnum];
			break;
	}
	D(printf("\n%s %x = reg[%d]\n", __func__, r, regnum));
	return r;
}

static void 
tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data)
{
	int regnum;

	regnum = req & 0x1f;
	D(printf("%s reg[%d] = %x\n", __func__, regnum, data));
	switch (regnum) {
		default:
			phy->regs[regnum] = data;
			break;
	}
}

static void 
tdk_init(struct qemu_phy *phy)
{
	phy->regs[0] = 0x3100;
	/* PHY Id.  */
	phy->regs[2] = 0x0300;
	phy->regs[3] = 0xe400;
	/* Autonegotiation advertisement reg.  */
	phy->regs[4] = 0x01E1;

	phy->read = tdk_read;
	phy->write = tdk_write;
}

struct qemu_mdio
{
	/* bus.	 */
	int mdc;
	int mdio;

	/* decoder.  */
	enum {
		PREAMBLE,
		SOF,
		OPC,
		ADDR,
		REQ,
		TURNAROUND,
		DATA
	} state;
	unsigned int drive;

	unsigned int cnt;
	unsigned int addr;
	unsigned int opc;
	unsigned int req;
	unsigned int data;

	struct qemu_phy *devs[32];
};

static void 
mdio_attach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr)
{
	bus->devs[addr & 0x1f] = phy;
}

static void 
mdio_detach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr)
{
	bus->devs[addr & 0x1f] = NULL;	
}

static void mdio_read_req(struct qemu_mdio *bus)
{
	struct qemu_phy *phy;

	phy = bus->devs[bus->addr];
	if (phy && phy->read)
		bus->data = phy->read(phy, bus->req);
	else 
		bus->data = 0xffff;
}

static void mdio_write_req(struct qemu_mdio *bus)
{
	struct qemu_phy *phy;

	phy = bus->devs[bus->addr];
	if (phy && phy->write)
		phy->write(phy, bus->req, bus->data);
}

static void mdio_cycle(struct qemu_mdio *bus)
{
	bus->cnt++;

	D(printf("mdc=%d mdio=%d state=%d cnt=%d drv=%d\n",
		bus->mdc, bus->mdio, bus->state, bus->cnt, bus->drive));
#if 0
	if (bus->mdc)
		printf("%d", bus->mdio);
#endif
	switch (bus->state)
	{
		case PREAMBLE:
			if (bus->mdc) {
				if (bus->cnt >= (32 * 2) && !bus->mdio) {
					bus->cnt = 0;
					bus->state = SOF;
					bus->data = 0;
				}
			}
			break;
		case SOF:
			if (bus->mdc) {
				if (bus->mdio != 1)
					printf("WARNING: no SOF\n");
				if (bus->cnt == 1*2) {
					bus->cnt = 0;
					bus->opc = 0;
					bus->state = OPC;
				}
			}
			break;
		case OPC:
			if (bus->mdc) {
				bus->opc <<= 1;
				bus->opc |= bus->mdio & 1;
				if (bus->cnt == 2*2) {
					bus->cnt = 0;
					bus->addr = 0;
					bus->state = ADDR;
				}
			}
			break;
		case ADDR:
			if (bus->mdc) {
				bus->addr <<= 1;
				bus->addr |= bus->mdio & 1;

				if (bus->cnt == 5*2) {
					bus->cnt = 0;
					bus->req = 0;
					bus->state = REQ;
				}
			}
			break;
		case REQ:
			if (bus->mdc) {
				bus->req <<= 1;
				bus->req |= bus->mdio & 1;
				if (bus->cnt == 5*2) {
					bus->cnt = 0;
					bus->state = TURNAROUND;
				}
			}
			break;
		case TURNAROUND:
			if (bus->mdc && bus->cnt == 2*2) {
				bus->mdio = 0;
				bus->cnt = 0;

				if (bus->opc == 2) {
					bus->drive = 1;
					mdio_read_req(bus);
					bus->mdio = bus->data & 1;
				}
				bus->state = DATA;
			}
			break;
		case DATA:			
			if (!bus->mdc) {
				if (bus->drive) {
					bus->mdio = !!(bus->data & (1 << 15));
					bus->data <<= 1;
				}
			} else {
				if (!bus->drive) {
					bus->data <<= 1;
					bus->data |= bus->mdio;
				}
				if (bus->cnt == 16 * 2) {
					bus->cnt = 0;
					bus->state = PREAMBLE;
					if (!bus->drive)
						mdio_write_req(bus);
					bus->drive = 0;
				}
			}
			break;
		default:
			break;
	}
}

/* ETRAX-FS Ethernet MAC block starts here.  */

#define RW_MA0_LO	  0x00
#define RW_MA0_HI	  0x04
#define RW_MA1_LO	  0x08
#define RW_MA1_HI	  0x0c
#define RW_GA_LO	  0x10
#define RW_GA_HI	  0x14
#define RW_GEN_CTRL	  0x18
#define RW_REC_CTRL	  0x1c
#define RW_TR_CTRL	  0x20
#define RW_CLR_ERR	  0x24
#define RW_MGM_CTRL	  0x28
#define R_STAT		  0x2c
#define FS_ETH_MAX_REGS	  0x5c

struct fs_eth
{
	CPUState *env;
	qemu_irq *irq;
	target_phys_addr_t base;
	VLANClientState *vc;
	int ethregs;

	/* Two addrs in the filter.  */
	uint8_t macaddr[2][6];
	uint32_t regs[FS_ETH_MAX_REGS];

	unsigned char rx_fifo[1536];
	int rx_fifo_len;
	int rx_fifo_pos;

	struct etraxfs_dma_client *dma_out;
	struct etraxfs_dma_client *dma_in;

	/* MDIO bus.  */
	struct qemu_mdio mdio_bus;
	/* PHY.	 */
	struct qemu_phy phy;
};

static uint32_t eth_rinvalid (void *opaque, target_phys_addr_t addr)
{
	struct fs_eth *eth = opaque;
	CPUState *env = eth->env;
	cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n", 
		  addr, env->pc);
	return 0;
}

static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
{
	struct fs_eth *eth = opaque;
	D(CPUState *env = eth->env);
	uint32_t r = 0;

	/* Make addr relative to this instances base.  */
	addr -= eth->base;
	switch (addr) {
		case R_STAT:
			/* Attach an MDIO/PHY abstraction.  */
			r = eth->mdio_bus.mdio & 1;
			break;
	default:
		r = eth->regs[addr];
		D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
		break;
	}
	return r;
}

static void
eth_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
{
	struct fs_eth *eth = opaque;
	CPUState *env = eth->env;
	cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n", 
		  addr, env->pc);
}

static void eth_update_ma(struct fs_eth *eth, int ma)
{
	int reg;
	int i = 0;

	ma &= 1;

	reg = RW_MA0_LO;
	if (ma)
		reg = RW_MA1_LO;

	eth->macaddr[ma][i++] = eth->regs[reg];
	eth->macaddr[ma][i++] = eth->regs[reg] >> 8;
	eth->macaddr[ma][i++] = eth->regs[reg] >> 16;
	eth->macaddr[ma][i++] = eth->regs[reg] >> 24;
	eth->macaddr[ma][i++] = eth->regs[reg + 4];
	eth->macaddr[ma][i++] = eth->regs[reg + 4] >> 8;

	D(printf("set mac%d=%x.%x.%x.%x.%x.%x\n", ma,
		 eth->macaddr[ma][0], eth->macaddr[ma][1],
		 eth->macaddr[ma][2], eth->macaddr[ma][3],
		 eth->macaddr[ma][4], eth->macaddr[ma][5]));
}

static void
eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
	struct fs_eth *eth = opaque;

	/* Make addr relative to this instances base.  */
	addr -= eth->base;
	switch (addr)
	{
		case RW_MA0_LO:
			eth->regs[addr] = value;
			eth_update_ma(eth, 0);
			break;
		case RW_MA0_HI:
			eth->regs[addr] = value;
			eth_update_ma(eth, 0);
			break;
		case RW_MA1_LO:
			eth->regs[addr] = value;
			eth_update_ma(eth, 1);
			break;
		case RW_MA1_HI:
			eth->regs[addr] = value;
			eth_update_ma(eth, 1);
			break;

		case RW_MGM_CTRL:
			/* Attach an MDIO/PHY abstraction.  */
			if (value & 2)
				eth->mdio_bus.mdio = value & 1;
			if (eth->mdio_bus.mdc != (value & 4))
				mdio_cycle(&eth->mdio_bus);
			eth->mdio_bus.mdc = !!(value & 4);
			break;

		default:
			eth->regs[addr] = value;
			D(printf ("%s %x %x\n",
				  __func__, addr, value));
			break;
	}
}

/* The ETRAX FS has a groupt address table (GAT) which works like a k=1 bloom
   filter dropping group addresses we have not joined.	The filter has 64
   bits (m). The has function is a simple nible xor of the group addr.	*/
static int eth_match_groupaddr(struct fs_eth *eth, const unsigned char *sa)
{
	unsigned int hsh;
	int m_individual = eth->regs[RW_REC_CTRL] & 4;
	int match;

	/* First bit on the wire of a MAC address signals multicast or
	   physical address.  */
	if (!m_individual && !sa[0] & 1)
		return 0;

	/* Calculate the hash index for the GA registers. */
	hsh = 0;
	hsh ^= (*sa) & 0x3f;
	hsh ^= ((*sa) >> 6) & 0x03;
	++sa;
	hsh ^= ((*sa) << 2) & 0x03c;
	hsh ^= ((*sa) >> 4) & 0xf;
	++sa;
	hsh ^= ((*sa) << 4) & 0x30;
	hsh ^= ((*sa) >> 2) & 0x3f;
	++sa;
	hsh ^= (*sa) & 0x3f;
	hsh ^= ((*sa) >> 6) & 0x03;
	++sa;
	hsh ^= ((*sa) << 2) & 0x03c;
	hsh ^= ((*sa) >> 4) & 0xf;
	++sa;
	hsh ^= ((*sa) << 4) & 0x30;
	hsh ^= ((*sa) >> 2) & 0x3f;

	hsh &= 63;
	if (hsh > 31)
		match = eth->regs[RW_GA_HI] & (1 << (hsh - 32));
	else
		match = eth->regs[RW_GA_LO] & (1 << hsh);
	D(printf("hsh=%x ga=%x.%x mtch=%d\n", hsh,
		 eth->regs[RW_GA_HI], eth->regs[RW_GA_LO], match));
	return match;
}

static int eth_can_receive(void *opaque)
{
	struct fs_eth *eth = opaque;
	int r;

	r = eth->rx_fifo_len == 0;
	if (!r) {
		/* TODO: signal fifo overrun.  */
		printf("PACKET LOSS!\n");
	}
	return r;
}

static void eth_receive(void *opaque, const uint8_t *buf, int size)
{
	unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
	struct fs_eth *eth = opaque;
	int use_ma0 = eth->regs[RW_REC_CTRL] & 1;
	int use_ma1 = eth->regs[RW_REC_CTRL] & 2;
	int r_bcast = eth->regs[RW_REC_CTRL] & 8;

	if (size < 12)
		return;

	D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n",
		 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
		 use_ma0, use_ma1, r_bcast));
	       
	/* Does the frame get through the address filters?  */
	if ((!use_ma0 || memcmp(buf, eth->macaddr[0], 6))
	    && (!use_ma1 || memcmp(buf, eth->macaddr[1], 6))
	    && (!r_bcast || memcmp(buf, sa_bcast, 6))
	    && !eth_match_groupaddr(eth, buf))
		return;

	if (size > sizeof(eth->rx_fifo)) {
		/* TODO: signal error.	*/
	} else if (eth->rx_fifo_len) {
		/* FIFO overrun.  */
	} else {
		memcpy(eth->rx_fifo, buf, size);
		/* +4, HW passes the CRC to sw.	 */
		eth->rx_fifo_len = size + 4;
		eth->rx_fifo_pos = 0;
	}
}

static void eth_rx_pull(void *opaque)
{
	struct fs_eth *eth = opaque;
	int len;
	if (eth->rx_fifo_len) {		
		D(printf("%s %d\n", __func__, eth->rx_fifo_len));
#if 0
		{
			int i;
			for (i = 0; i < 32; i++)
				printf("%2.2x", eth->rx_fifo[i]);
			printf("\n");
		}
#endif
		len = etraxfs_dmac_input(eth->dma_in,
					 eth->rx_fifo + eth->rx_fifo_pos, 
					 eth->rx_fifo_len, 1);
		eth->rx_fifo_len -= len;
		eth->rx_fifo_pos += len;
	}
}

static int eth_tx_push(void *opaque, unsigned char *buf, int len)
{
	struct fs_eth *eth = opaque;

	D(printf("%s buf=%p len=%d\n", __func__, buf, len));
	qemu_send_packet(eth->vc, buf, len);
	return len;
}

static CPUReadMemoryFunc *eth_read[] = {
	&eth_rinvalid,
	&eth_rinvalid,
	&eth_readl,
};

static CPUWriteMemoryFunc *eth_write[] = {
	&eth_winvalid,
	&eth_winvalid,
	&eth_writel,
};

void *etraxfs_eth_init(NICInfo *nd, CPUState *env, 
		       qemu_irq *irq, target_phys_addr_t base)
{
	struct etraxfs_dma_client *dma = NULL;	
	struct fs_eth *eth = NULL;

	dma = qemu_mallocz(sizeof *dma * 2);
	if (!dma)
		return NULL;

	eth = qemu_mallocz(sizeof *eth);
	if (!eth)
		goto err;

	dma[0].client.push = eth_tx_push;
	dma[0].client.opaque = eth;
	dma[1].client.opaque = eth;
	dma[1].client.pull = eth_rx_pull;

	eth->env = env;
	eth->base = base;
	eth->irq = irq;
	eth->dma_out = dma;
	eth->dma_in = dma + 1;

	/* Connect the phy.  */
	tdk_init(&eth->phy);
	mdio_attach(&eth->mdio_bus, &eth->phy, 0x1);

	eth->ethregs = cpu_register_io_memory(0, eth_read, eth_write, eth);
	cpu_register_physical_memory (base, 0x5c, eth->ethregs);

	eth->vc = qemu_new_vlan_client(nd->vlan, 
				       eth_receive, eth_can_receive, eth);

	return dma;
  err:
	qemu_free(eth);
	qemu_free(dma);
	return NULL;
}
Commit	Line	Data
a3ea5df5 EI	1	/*
	2	* QEMU ETRAX Ethernet Controller.
	3	*
	4	* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include <stdio.h>
	26	#include "hw.h"
	27	#include "net.h"
	28
	29	#include "etraxfs_dma.h"
	30
	31	#define D(x)
	32
2e56350e EI	33	/*
	34	* The MDIO extensions in the TDK PHY model were reversed engineered from the
	35	* linux driver (PHYID and Diagnostics reg).
	36	* TODO: Add friendly names for the register nums.
	37	*/
a3ea5df5 EI	38	struct qemu_phy
	39	{
	40	uint32_t regs[32];
	41
	42	unsigned int (read)(struct qemu_phy phy, unsigned int req);
2e56350e EI	43	void (write)(struct qemu_phy phy, unsigned int req,
2e56350e EI	44	unsigned int data);
a3ea5df5 EI	45	};
	46
	47	static unsigned int tdk_read(struct qemu_phy *phy, unsigned int req)
	48	{
	49	int regnum;
	50	unsigned r = 0;
	51
	52	regnum = req & 0x1f;
	53
	54	switch (regnum) {
	55	case 1:
f6953f13	56	/* MR1. */
a3ea5df5 EI	57	/* Speeds and modes. */
	58	r \|= (1 << 13) \| (1 << 14);
	59	r \|= (1 << 11) \| (1 << 12);
	60	r \|= (1 << 5); /* Autoneg complete. */
f6953f13 EI	61	r \|= (1 << 3); /* Autoneg able. */
f6953f13 EI	62	r \|= (1 << 2); /* Link. */
a3ea5df5	63	break;
2e56350e EI	64	case 5:
	65	/* Link partner ability.
	66	We are kind; always agree with whatever best mode
	67	the guest advertises. */
	68	r = 1 << 14; /* Success. */
	69	/* Copy advertised modes. */
	70	r \|= phy->regs[4] & (15 << 5);
	71	/* Autoneg support. */
	72	r \|= 1;
	73	break;
	74	case 18:
	75	{
	76	/* Diagnostics reg. */
	77	int duplex = 0;
	78	int speed_100 = 0;
	79
	80	/* Are we advertising 100 half or 100 duplex ? */
	81	speed_100 = !!(phy->regs[4] & 0x180);
	82	/* Are we advertising 10 duplex or 100 duplex ? */
	83	duplex = !!(phy->regs[4] & 0x180);
	84	r = (speed_100 << 10) \| (duplex << 11);
	85	}
	86	break;
	87
a3ea5df5 EI	88	default:
	89	r = phy->regs[regnum];
	90	break;
	91	}
2e56350e	92	D(printf("\n%s %x = reg[%d]\n", __func__, r, regnum));
a3ea5df5 EI	93	return r;
	94	}
	95
	96	static void
	97	tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data)
	98	{
	99	int regnum;
	100
	101	regnum = req & 0x1f;
	102	D(printf("%s reg[%d] = %x\n", __func__, regnum, data));
	103	switch (regnum) {
	104	default:
	105	phy->regs[regnum] = data;
	106	break;
	107	}
	108	}
	109
	110	static void
	111	tdk_init(struct qemu_phy *phy)
	112	{
2e56350e EI	113	phy->regs[0] = 0x3100;
	114	/* PHY Id. */
	115	phy->regs[2] = 0x0300;
	116	phy->regs[3] = 0xe400;
	117	/* Autonegotiation advertisement reg. */
	118	phy->regs[4] = 0x01E1;
	119
a3ea5df5 EI	120	phy->read = tdk_read;
	121	phy->write = tdk_write;
	122	}
	123
	124	struct qemu_mdio
	125	{
f6953f13	126	/* bus. */
a3ea5df5 EI	127	int mdc;
	128	int mdio;
	129
	130	/* decoder. */
	131	enum {
	132	PREAMBLE,
	133	SOF,
	134	OPC,
	135	ADDR,
	136	REQ,
	137	TURNAROUND,
	138	DATA
	139	} state;
	140	unsigned int drive;
	141
	142	unsigned int cnt;
	143	unsigned int addr;
	144	unsigned int opc;
	145	unsigned int req;
	146	unsigned int data;
	147
	148	struct qemu_phy *devs[32];
	149	};
	150
	151	static void
	152	mdio_attach(struct qemu_mdio bus, struct qemu_phy phy, unsigned int addr)
	153	{
	154	bus->devs[addr & 0x1f] = phy;
	155	}
	156
	157	static void
	158	mdio_detach(struct qemu_mdio bus, struct qemu_phy phy, unsigned int addr)
	159	{
	160	bus->devs[addr & 0x1f] = NULL;
	161	}
	162
	163	static void mdio_read_req(struct qemu_mdio *bus)
	164	{
	165	struct qemu_phy *phy;
	166
	167	phy = bus->devs[bus->addr];
	168	if (phy && phy->read)
	169	bus->data = phy->read(phy, bus->req);
	170	else
	171	bus->data = 0xffff;
	172	}
	173
	174	static void mdio_write_req(struct qemu_mdio *bus)
	175	{
	176	struct qemu_phy *phy;
	177
	178	phy = bus->devs[bus->addr];
	179	if (phy && phy->write)
	180	phy->write(phy, bus->req, bus->data);
	181	}
	182
	183	static void mdio_cycle(struct qemu_mdio *bus)
	184	{
	185	bus->cnt++;
	186
	187	D(printf("mdc=%d mdio=%d state=%d cnt=%d drv=%d\n",
	188	bus->mdc, bus->mdio, bus->state, bus->cnt, bus->drive));
	189	#if 0
	190	if (bus->mdc)
191	printf("%d", bus->mdio);
192	#endif
193	switch (bus->state)
194	{
195	case PREAMBLE:
196	if (bus->mdc) {
197	if (bus->cnt >= (32 * 2) && !bus->mdio) {
198	bus->cnt = 0;
199	bus->state = SOF;
200	bus->data = 0;
201	}
202	}
203	break;
204	case SOF:
205	if (bus->mdc) {
206	if (bus->mdio != 1)
207	printf("WARNING: no SOF\n");
208	if (bus->cnt == 1*2) {
209	bus->cnt = 0;
210	bus->opc = 0;
211	bus->state = OPC;
212	}
213	}
214	break;
215	case OPC:
216	if (bus->mdc) {
217	bus->opc <<= 1;
218	bus->opc \|= bus->mdio & 1;
219	if (bus->cnt == 2*2) {
220	bus->cnt = 0;
221	bus->addr = 0;
222	bus->state = ADDR;
223	}
224	}
225	break;
226	case ADDR:
227	if (bus->mdc) {
228	bus->addr <<= 1;
229	bus->addr \|= bus->mdio & 1;
230
231	if (bus->cnt == 5*2) {
232	bus->cnt = 0;
233	bus->req = 0;
234	bus->state = REQ;
235	}
236	}
237	break;
238	case REQ:
239	if (bus->mdc) {
240	bus->req <<= 1;
241	bus->req \|= bus->mdio & 1;
242	if (bus->cnt == 5*2) {
243	bus->cnt = 0;
244	bus->state = TURNAROUND;
245	}
246	}
247	break;
248	case TURNAROUND:
249	if (bus->mdc && bus->cnt == 2*2) {
250	bus->mdio = 0;
251	bus->cnt = 0;
252
253	if (bus->opc == 2) {
254	bus->drive = 1;
255	mdio_read_req(bus);
256	bus->mdio = bus->data & 1;
257	}
258	bus->state = DATA;
259	}
260	break;
261	case DATA:
262	if (!bus->mdc) {
263	if (bus->drive) {
2e56350e EI	264	bus->mdio = !!(bus->data & (1 << 15));
2e56350e EI	265	bus->data <<= 1;
a3ea5df5 EI	266	}
	267	} else {
	268	if (!bus->drive) {
	269	bus->data <<= 1;
	270	bus->data \|= bus->mdio;
	271	}
	272	if (bus->cnt == 16 * 2) {
	273	bus->cnt = 0;
	274	bus->state = PREAMBLE;
2e56350e EI	275	if (!bus->drive)
	276	mdio_write_req(bus);
	277	bus->drive = 0;
a3ea5df5 EI	278	}
	279	}
	280	break;
	281	default:
	282	break;
	283	}
	284	}
	285
2e56350e EI	286	/* ETRAX-FS Ethernet MAC block starts here. */
2e56350e EI	287
f6953f13 EI	288	#define RW_MA0_LO 0x00
	289	#define RW_MA0_HI 0x04
	290	#define RW_MA1_LO 0x08
	291	#define RW_MA1_HI 0x0c
	292	#define RW_GA_LO 0x10
	293	#define RW_GA_HI 0x14
	294	#define RW_GEN_CTRL 0x18
	295	#define RW_REC_CTRL 0x1c
	296	#define RW_TR_CTRL 0x20
	297	#define RW_CLR_ERR 0x24
	298	#define RW_MGM_CTRL 0x28
	299	#define R_STAT 0x2c
	300	#define FS_ETH_MAX_REGS 0x5c
a3ea5df5 EI	301
	302	struct fs_eth
	303	{
f6953f13	304	CPUState *env;
a3ea5df5	305	qemu_irq *irq;
f6953f13	306	target_phys_addr_t base;
a3ea5df5	307	VLANClientState *vc;
a3ea5df5 EI	308	int ethregs;
a3ea5df5 EI	309
f6953f13 EI	310	/* Two addrs in the filter. */
f6953f13 EI	311	uint8_t macaddr[2][6];
a3ea5df5 EI	312	uint32_t regs[FS_ETH_MAX_REGS];
	313
	314	unsigned char rx_fifo[1536];
	315	int rx_fifo_len;
	316	int rx_fifo_pos;
	317
	318	struct etraxfs_dma_client *dma_out;
	319	struct etraxfs_dma_client *dma_in;
	320
	321	/* MDIO bus. */
	322	struct qemu_mdio mdio_bus;
f6953f13	323	/* PHY. */
a3ea5df5 EI	324	struct qemu_phy phy;
	325	};
	326
	327	static uint32_t eth_rinvalid (void *opaque, target_phys_addr_t addr)
	328	{
f6953f13 EI	329	struct fs_eth *eth = opaque;
	330	CPUState *env = eth->env;
	331	cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
	332	addr, env->pc);
	333	return 0;
a3ea5df5 EI	334	}
	335
	336	static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
	337	{
f6953f13 EI	338	struct fs_eth *eth = opaque;
	339	D(CPUState *env = eth->env);
	340	uint32_t r = 0;
a3ea5df5	341
f6953f13 EI	342	/* Make addr relative to this instances base. */
	343	addr -= eth->base;
	344	switch (addr) {
a3ea5df5 EI	345	case R_STAT:
	346	/* Attach an MDIO/PHY abstraction. */
	347	r = eth->mdio_bus.mdio & 1;
	348	break;
f6953f13	349	default:
a3ea5df5	350	r = eth->regs[addr];
f6953f13 EI	351	D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
	352	break;
	353	}
	354	return r;
a3ea5df5 EI	355	}
	356
	357	static void
	358	eth_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
	359	{
f6953f13 EI	360	struct fs_eth *eth = opaque;
	361	CPUState *env = eth->env;
	362	cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
	363	addr, env->pc);
	364	}
	365
	366	static void eth_update_ma(struct fs_eth *eth, int ma)
	367	{
	368	int reg;
	369	int i = 0;
	370
	371	ma &= 1;
	372
	373	reg = RW_MA0_LO;
	374	if (ma)
	375	reg = RW_MA1_LO;
	376
	377	eth->macaddr[ma][i++] = eth->regs[reg];
	378	eth->macaddr[ma][i++] = eth->regs[reg] >> 8;
	379	eth->macaddr[ma][i++] = eth->regs[reg] >> 16;
	380	eth->macaddr[ma][i++] = eth->regs[reg] >> 24;
	381	eth->macaddr[ma][i++] = eth->regs[reg + 4];
	382	eth->macaddr[ma][i++] = eth->regs[reg + 4] >> 8;
	383
	384	D(printf("set mac%d=%x.%x.%x.%x.%x.%x\n", ma,
	385	eth->macaddr[ma][0], eth->macaddr[ma][1],
	386	eth->macaddr[ma][2], eth->macaddr[ma][3],
	387	eth->macaddr[ma][4], eth->macaddr[ma][5]));
a3ea5df5 EI	388	}
	389
	390	static void
	391	eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
	392	{
f6953f13	393	struct fs_eth *eth = opaque;
f6953f13 EI	394
	395	/* Make addr relative to this instances base. */
	396	addr -= eth->base;
	397	switch (addr)
	398	{
	399	case RW_MA0_LO:
	400	eth->regs[addr] = value;
	401	eth_update_ma(eth, 0);
	402	break;
	403	case RW_MA0_HI:
	404	eth->regs[addr] = value;
	405	eth_update_ma(eth, 0);
	406	break;
	407	case RW_MA1_LO:
	408	eth->regs[addr] = value;
	409	eth_update_ma(eth, 1);
	410	break;
	411	case RW_MA1_HI:
	412	eth->regs[addr] = value;
	413	eth_update_ma(eth, 1);
	414	break;
a3ea5df5	415
a3ea5df5 EI	416	case RW_MGM_CTRL:
	417	/* Attach an MDIO/PHY abstraction. */
	418	if (value & 2)
	419	eth->mdio_bus.mdio = value & 1;
	420	if (eth->mdio_bus.mdc != (value & 4))
	421	mdio_cycle(&eth->mdio_bus);
	422	eth->mdio_bus.mdc = !!(value & 4);
	423	break;
	424
f6953f13 EI	425	default:
f6953f13 EI	426	eth->regs[addr] = value;
9bcd77d6 EI	427	D(printf ("%s %x %x\n",
9bcd77d6 EI	428	__func__, addr, value));
f6953f13 EI	429	break;
	430	}
	431	}
	432
	433	/* The ETRAX FS has a groupt address table (GAT) which works like a k=1 bloom
	434	filter dropping group addresses we have not joined. The filter has 64
	435	bits (m). The has function is a simple nible xor of the group addr. */
	436	static int eth_match_groupaddr(struct fs_eth eth, const unsigned char sa)
	437	{
	438	unsigned int hsh;
	439	int m_individual = eth->regs[RW_REC_CTRL] & 4;
	440	int match;
	441
	442	/* First bit on the wire of a MAC address signals multicast or
	443	physical address. */
	444	if (!m_individual && !sa[0] & 1)
	445	return 0;
	446
	447	/* Calculate the hash index for the GA registers. */
	448	hsh = 0;
	449	hsh ^= (*sa) & 0x3f;
	450	hsh ^= ((*sa) >> 6) & 0x03;
	451	++sa;
	452	hsh ^= ((*sa) << 2) & 0x03c;
	453	hsh ^= ((*sa) >> 4) & 0xf;
	454	++sa;
	455	hsh ^= ((*sa) << 4) & 0x30;
	456	hsh ^= ((*sa) >> 2) & 0x3f;
	457	++sa;
	458	hsh ^= (*sa) & 0x3f;
	459	hsh ^= ((*sa) >> 6) & 0x03;
	460	++sa;
	461	hsh ^= ((*sa) << 2) & 0x03c;
	462	hsh ^= ((*sa) >> 4) & 0xf;
	463	++sa;
	464	hsh ^= ((*sa) << 4) & 0x30;
	465	hsh ^= ((*sa) >> 2) & 0x3f;
	466
	467	hsh &= 63;
	468	if (hsh > 31)
	469	match = eth->regs[RW_GA_HI] & (1 << (hsh - 32));
	470	else
	471	match = eth->regs[RW_GA_LO] & (1 << hsh);
	472	D(printf("hsh=%x ga=%x.%x mtch=%d\n", hsh,
	473	eth->regs[RW_GA_HI], eth->regs[RW_GA_LO], match));
	474	return match;
a3ea5df5 EI	475	}
	476
	477	static int eth_can_receive(void *opaque)
	478	{
	479	struct fs_eth *eth = opaque;
	480	int r;
	481
	482	r = eth->rx_fifo_len == 0;
	483	if (!r) {
	484	/* TODO: signal fifo overrun. */
	485	printf("PACKET LOSS!\n");
	486	}
	487	return r;
	488	}
	489
	490	static void eth_receive(void opaque, const uint8_t buf, int size)
	491	{
f6953f13	492	unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
a3ea5df5	493	struct fs_eth *eth = opaque;
f6953f13 EI	494	int use_ma0 = eth->regs[RW_REC_CTRL] & 1;
	495	int use_ma1 = eth->regs[RW_REC_CTRL] & 2;
	496	int r_bcast = eth->regs[RW_REC_CTRL] & 8;
	497
	498	if (size < 12)
	499	return;
	500
	501	D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n",
	502	buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
	503	use_ma0, use_ma1, r_bcast));
	504
	505	/* Does the frame get through the address filters? */
	506	if ((!use_ma0 \|\| memcmp(buf, eth->macaddr[0], 6))
	507	&& (!use_ma1 \|\| memcmp(buf, eth->macaddr[1], 6))
	508	&& (!r_bcast \|\| memcmp(buf, sa_bcast, 6))
	509	&& !eth_match_groupaddr(eth, buf))
	510	return;
	511
a3ea5df5	512	if (size > sizeof(eth->rx_fifo)) {
f6953f13 EI	513	/* TODO: signal error. */
	514	} else if (eth->rx_fifo_len) {
	515	/* FIFO overrun. */
a3ea5df5 EI	516	} else {
a3ea5df5 EI	517	memcpy(eth->rx_fifo, buf, size);
f6953f13	518	/* +4, HW passes the CRC to sw. */
a3ea5df5 EI	519	eth->rx_fifo_len = size + 4;
	520	eth->rx_fifo_pos = 0;
	521	}
	522	}
	523
	524	static void eth_rx_pull(void *opaque)
	525	{
	526	struct fs_eth *eth = opaque;
	527	int len;
	528	if (eth->rx_fifo_len) {
	529	D(printf("%s %d\n", __func__, eth->rx_fifo_len));
	530	#if 0
	531	{
	532	int i;
	533	for (i = 0; i < 32; i++)
	534	printf("%2.2x", eth->rx_fifo[i]);
	535	printf("\n");
	536	}
	537	#endif
	538	len = etraxfs_dmac_input(eth->dma_in,
	539	eth->rx_fifo + eth->rx_fifo_pos,
	540	eth->rx_fifo_len, 1);
	541	eth->rx_fifo_len -= len;
	542	eth->rx_fifo_pos += len;
	543	}
	544	}
	545
	546	static int eth_tx_push(void opaque, unsigned char buf, int len)
	547	{
	548	struct fs_eth *eth = opaque;
	549
	550	D(printf("%s buf=%p len=%d\n", __func__, buf, len));
	551	qemu_send_packet(eth->vc, buf, len);
	552	return len;
	553	}
	554
	555	static CPUReadMemoryFunc *eth_read[] = {
2e56350e EI	556	&eth_rinvalid,
	557	&eth_rinvalid,
	558	&eth_readl,
a3ea5df5 EI	559	};
	560
	561	static CPUWriteMemoryFunc *eth_write[] = {
2e56350e EI	562	&eth_winvalid,
	563	&eth_winvalid,
	564	&eth_writel,
a3ea5df5 EI	565	};
	566
	567	void etraxfs_eth_init(NICInfo nd, CPUState *env,
	568	qemu_irq *irq, target_phys_addr_t base)
	569	{
	570	struct etraxfs_dma_client *dma = NULL;
	571	struct fs_eth *eth = NULL;
	572
	573	dma = qemu_mallocz(sizeof dma 2);
	574	if (!dma)
	575	return NULL;
	576
	577	eth = qemu_mallocz(sizeof *eth);
	578	if (!eth)
	579	goto err;
	580
	581	dma[0].client.push = eth_tx_push;
	582	dma[0].client.opaque = eth;
	583	dma[1].client.opaque = eth;
	584	dma[1].client.pull = eth_rx_pull;
	585
	586	eth->env = env;
	587	eth->base = base;
	588	eth->irq = irq;
	589	eth->dma_out = dma;
	590	eth->dma_in = dma + 1;
a3ea5df5 EI	591
	592	/* Connect the phy. */
	593	tdk_init(&eth->phy);
	594	mdio_attach(&eth->mdio_bus, &eth->phy, 0x1);
	595
	596	eth->ethregs = cpu_register_io_memory(0, eth_read, eth_write, eth);
	597	cpu_register_physical_memory (base, 0x5c, eth->ethregs);
	598
	599	eth->vc = qemu_new_vlan_client(nd->vlan,
	600	eth_receive, eth_can_receive, eth);
	601
	602	return dma;
	603	err:
	604	qemu_free(eth);
	605	qemu_free(dma);
	606	return NULL;
	607	}