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migration: disable auto-converge during bulk block migration
[qemu.git] / hw / s390x / css.c
CommitLineData
df1fe5bb
CH		 1/*
2 * Channel subsystem base support.
3 *
4 * Copyright 2012 IBM Corp.
5 * Author(s): Cornelia Huck <[email protected]>
6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or (at
8 * your option) any later version. See the COPYING file in the top-level
9 * directory.
10 */
11
9615495a 12#include "qemu/osdep.h"
c1755b14 13#include "qapi/error.h"
06e686ea 14#include "qapi/visitor.h"
a9c94277 15#include "hw/qdev.h"
8f3cf012 16#include "qemu/error-report.h"
df1fe5bb 17#include "qemu/bitops.h"
8ed179c9 18#include "qemu/error-report.h"
fdfba1a2 19#include "exec/address-spaces.h"
df1fe5bb 20#include "cpu.h"
bd3f16ac
PB		 21#include "hw/s390x/ioinst.h"
22#include "hw/s390x/css.h"
df1fe5bb 23#include "trace.h"
03cf077a 24#include "hw/s390x/s390_flic.h"
517ff12c 25#include "hw/s390x/s390-virtio-ccw.h"
df1fe5bb
CH		 26
27typedef struct CrwContainer {
28 CRW crw;
29 QTAILQ_ENTRY(CrwContainer) sibling;
30} CrwContainer;
31
457af626
HP		 32static const VMStateDescription vmstate_crw = {
33 .name = "s390_crw",
34 .version_id = 1,
35 .minimum_version_id = 1,
36 .fields = (VMStateField[]) {
37 VMSTATE_UINT16(flags, CRW),
38 VMSTATE_UINT16(rsid, CRW),
39 VMSTATE_END_OF_LIST()
40 },
41};
42
43static const VMStateDescription vmstate_crw_container = {
44 .name = "s390_crw_container",
45 .version_id = 1,
46 .minimum_version_id = 1,
47 .fields = (VMStateField[]) {
48 VMSTATE_STRUCT(crw, CrwContainer, 0, vmstate_crw, CRW),
49 VMSTATE_END_OF_LIST()
50 },
51};
52
df1fe5bb
CH		 53typedef struct ChpInfo {
54 uint8_t in_use;
55 uint8_t type;
56 uint8_t is_virtual;
57} ChpInfo;
58
457af626
HP		 59static const VMStateDescription vmstate_chp_info = {
60 .name = "s390_chp_info",
61 .version_id = 1,
62 .minimum_version_id = 1,
63 .fields = (VMStateField[]) {
64 VMSTATE_UINT8(in_use, ChpInfo),
65 VMSTATE_UINT8(type, ChpInfo),
66 VMSTATE_UINT8(is_virtual, ChpInfo),
67 VMSTATE_END_OF_LIST()
68 }
69};
70
df1fe5bb
CH		 71typedef struct SubchSet {
72 SubchDev *sch[MAX_SCHID + 1];
73 unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)];
74 unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)];
75} SubchSet;
76
517ff12c
HP		 77static const VMStateDescription vmstate_scsw = {
78 .name = "s390_scsw",
79 .version_id = 1,
80 .minimum_version_id = 1,
81 .fields = (VMStateField[]) {
82 VMSTATE_UINT16(flags, SCSW),
83 VMSTATE_UINT16(ctrl, SCSW),
84 VMSTATE_UINT32(cpa, SCSW),
85 VMSTATE_UINT8(dstat, SCSW),
86 VMSTATE_UINT8(cstat, SCSW),
87 VMSTATE_UINT16(count, SCSW),
88 VMSTATE_END_OF_LIST()
89 }
90};
91
92static const VMStateDescription vmstate_pmcw = {
93 .name = "s390_pmcw",
94 .version_id = 1,
95 .minimum_version_id = 1,
96 .fields = (VMStateField[]) {
97 VMSTATE_UINT32(intparm, PMCW),
98 VMSTATE_UINT16(flags, PMCW),
99 VMSTATE_UINT16(devno, PMCW),
100 VMSTATE_UINT8(lpm, PMCW),
101 VMSTATE_UINT8(pnom, PMCW),
102 VMSTATE_UINT8(lpum, PMCW),
103 VMSTATE_UINT8(pim, PMCW),
104 VMSTATE_UINT16(mbi, PMCW),
105 VMSTATE_UINT8(pom, PMCW),
106 VMSTATE_UINT8(pam, PMCW),
107 VMSTATE_UINT8_ARRAY(chpid, PMCW, 8),
108 VMSTATE_UINT32(chars, PMCW),
109 VMSTATE_END_OF_LIST()
110 }
111};
112
113static const VMStateDescription vmstate_schib = {
114 .name = "s390_schib",
115 .version_id = 1,
116 .minimum_version_id = 1,
117 .fields = (VMStateField[]) {
118 VMSTATE_STRUCT(pmcw, SCHIB, 0, vmstate_pmcw, PMCW),
119 VMSTATE_STRUCT(scsw, SCHIB, 0, vmstate_scsw, SCSW),
120 VMSTATE_UINT64(mba, SCHIB),
121 VMSTATE_UINT8_ARRAY(mda, SCHIB, 4),
122 VMSTATE_END_OF_LIST()
123 }
124};
125
126
127static const VMStateDescription vmstate_ccw1 = {
128 .name = "s390_ccw1",
129 .version_id = 1,
130 .minimum_version_id = 1,
131 .fields = (VMStateField[]) {
132 VMSTATE_UINT8(cmd_code, CCW1),
133 VMSTATE_UINT8(flags, CCW1),
134 VMSTATE_UINT16(count, CCW1),
135 VMSTATE_UINT32(cda, CCW1),
136 VMSTATE_END_OF_LIST()
137 }
138};
139
140static const VMStateDescription vmstate_ciw = {
141 .name = "s390_ciw",
142 .version_id = 1,
143 .minimum_version_id = 1,
144 .fields = (VMStateField[]) {
145 VMSTATE_UINT8(type, CIW),
146 VMSTATE_UINT8(command, CIW),
147 VMSTATE_UINT16(count, CIW),
148 VMSTATE_END_OF_LIST()
149 }
150};
151
152static const VMStateDescription vmstate_sense_id = {
153 .name = "s390_sense_id",
154 .version_id = 1,
155 .minimum_version_id = 1,
156 .fields = (VMStateField[]) {
157 VMSTATE_UINT8(reserved, SenseId),
158 VMSTATE_UINT16(cu_type, SenseId),
159 VMSTATE_UINT8(cu_model, SenseId),
160 VMSTATE_UINT16(dev_type, SenseId),
161 VMSTATE_UINT8(dev_model, SenseId),
162 VMSTATE_UINT8(unused, SenseId),
163 VMSTATE_STRUCT_ARRAY(ciw, SenseId, MAX_CIWS, 0, vmstate_ciw, CIW),
164 VMSTATE_END_OF_LIST()
165 }
166};
167
ff443fe6
HP		 168static const VMStateDescription vmstate_orb = {
169 .name = "s390_orb",
170 .version_id = 1,
171 .minimum_version_id = 1,
172 .fields = (VMStateField[]) {
173 VMSTATE_UINT32(intparm, ORB),
174 VMSTATE_UINT16(ctrl0, ORB),
175 VMSTATE_UINT8(lpm, ORB),
176 VMSTATE_UINT8(ctrl1, ORB),
177 VMSTATE_UINT32(cpa, ORB),
178 VMSTATE_END_OF_LIST()
179 }
180};
181
182static bool vmstate_schdev_orb_needed(void *opaque)
183{
184 return css_migration_enabled();
185}
186
187static const VMStateDescription vmstate_schdev_orb = {
188 .name = "s390_subch_dev/orb",
189 .version_id = 1,
190 .minimum_version_id = 1,
191 .needed = vmstate_schdev_orb_needed,
192 .fields = (VMStateField[]) {
193 VMSTATE_STRUCT(orb, SubchDev, 1, vmstate_orb, ORB),
194 VMSTATE_END_OF_LIST()
195 }
196};
197
517ff12c
HP		 198static int subch_dev_post_load(void *opaque, int version_id);
199static void subch_dev_pre_save(void *opaque);
200
201const char err_hint_devno[] = "Devno mismatch, tried to load wrong section!"
202 " Likely reason: some sequences of plug and unplug can break"
203 " migration for machine versions prior to 2.7 (known design flaw).";
204
205const VMStateDescription vmstate_subch_dev = {
206 .name = "s390_subch_dev",
207 .version_id = 1,
208 .minimum_version_id = 1,
209 .post_load = subch_dev_post_load,
210 .pre_save = subch_dev_pre_save,
211 .fields = (VMStateField[]) {
212 VMSTATE_UINT8_EQUAL(cssid, SubchDev, "Bug!"),
213 VMSTATE_UINT8_EQUAL(ssid, SubchDev, "Bug!"),
214 VMSTATE_UINT16(migrated_schid, SubchDev),
215 VMSTATE_UINT16_EQUAL(devno, SubchDev, err_hint_devno),
216 VMSTATE_BOOL(thinint_active, SubchDev),
217 VMSTATE_STRUCT(curr_status, SubchDev, 0, vmstate_schib, SCHIB),
218 VMSTATE_UINT8_ARRAY(sense_data, SubchDev, 32),
219 VMSTATE_UINT64(channel_prog, SubchDev),
220 VMSTATE_STRUCT(last_cmd, SubchDev, 0, vmstate_ccw1, CCW1),
221 VMSTATE_BOOL(last_cmd_valid, SubchDev),
222 VMSTATE_STRUCT(id, SubchDev, 0, vmstate_sense_id, SenseId),
223 VMSTATE_BOOL(ccw_fmt_1, SubchDev),
224 VMSTATE_UINT8(ccw_no_data_cnt, SubchDev),
225 VMSTATE_END_OF_LIST()
ff443fe6
HP		 226 },
227 .subsections = (const VMStateDescription * []) {
228 &vmstate_schdev_orb,
229 NULL
517ff12c
HP		 230 }
231};
232
233typedef struct IndAddrPtrTmp {
234 IndAddr **parent;
235 uint64_t addr;
236 int32_t len;
237} IndAddrPtrTmp;
238
239static int post_load_ind_addr(void *opaque, int version_id)
240{
241 IndAddrPtrTmp *ptmp = opaque;
242 IndAddr **ind_addr = ptmp->parent;
243
244 if (ptmp->len != 0) {
245 *ind_addr = get_indicator(ptmp->addr, ptmp->len);
246 } else {
247 *ind_addr = NULL;
248 }
249 return 0;
250}
251
252static void pre_save_ind_addr(void *opaque)
253{
254 IndAddrPtrTmp *ptmp = opaque;
255 IndAddr *ind_addr = *(ptmp->parent);
256
257 if (ind_addr != NULL) {
258 ptmp->len = ind_addr->len;
259 ptmp->addr = ind_addr->addr;
260 } else {
261 ptmp->len = 0;
262 ptmp->addr = 0L;
263 }
264}
265
266const VMStateDescription vmstate_ind_addr_tmp = {
267 .name = "s390_ind_addr_tmp",
268 .pre_save = pre_save_ind_addr,
269 .post_load = post_load_ind_addr,
270
271 .fields = (VMStateField[]) {
272 VMSTATE_INT32(len, IndAddrPtrTmp),
273 VMSTATE_UINT64(addr, IndAddrPtrTmp),
274 VMSTATE_END_OF_LIST()
275 }
276};
277
278const VMStateDescription vmstate_ind_addr = {
279 .name = "s390_ind_addr_tmp",
280 .fields = (VMStateField[]) {
281 VMSTATE_WITH_TMP(IndAddr*, IndAddrPtrTmp, vmstate_ind_addr_tmp),
282 VMSTATE_END_OF_LIST()
283 }
284};
285
df1fe5bb
CH		 286typedef struct CssImage {
287 SubchSet *sch_set[MAX_SSID + 1];
288 ChpInfo chpids[MAX_CHPID + 1];
289} CssImage;
290
457af626
HP		 291static const VMStateDescription vmstate_css_img = {
292 .name = "s390_css_img",
293 .version_id = 1,
294 .minimum_version_id = 1,
295 .fields = (VMStateField[]) {
296 /* Subchannel sets have no relevant state. */
297 VMSTATE_STRUCT_ARRAY(chpids, CssImage, MAX_CHPID + 1, 0,
298 vmstate_chp_info, ChpInfo),
299 VMSTATE_END_OF_LIST()
300 }
301
302};
303
03cf077a
CH		 304typedef struct IoAdapter {
305 uint32_t id;
306 uint8_t type;
307 uint8_t isc;
1497c160 308 uint8_t flags;
03cf077a
CH		 309} IoAdapter;
310
df1fe5bb
CH		 311typedef struct ChannelSubSys {
312 QTAILQ_HEAD(, CrwContainer) pending_crws;
c81b4f89 313 bool sei_pending;
df1fe5bb
CH		 314 bool do_crw_mchk;
315 bool crws_lost;
316 uint8_t max_cssid;
317 uint8_t max_ssid;
318 bool chnmon_active;
319 uint64_t chnmon_area;
320 CssImage *css[MAX_CSSID + 1];
321 uint8_t default_cssid;
457af626 322 /* don't migrate, see css_register_io_adapters */
dde522bb 323 IoAdapter *io_adapters[CSS_IO_ADAPTER_TYPE_NUMS][MAX_ISC + 1];
457af626 324 /* don't migrate, see get_indicator and IndAddrPtrTmp */
a28d8391 325 QTAILQ_HEAD(, IndAddr) indicator_addresses;
df1fe5bb
CH		 326} ChannelSubSys;
327
457af626
HP		 328static const VMStateDescription vmstate_css = {
329 .name = "s390_css",
330 .version_id = 1,
331 .minimum_version_id = 1,
332 .fields = (VMStateField[]) {
333 VMSTATE_QTAILQ_V(pending_crws, ChannelSubSys, 1, vmstate_crw_container,
334 CrwContainer, sibling),
335 VMSTATE_BOOL(sei_pending, ChannelSubSys),
336 VMSTATE_BOOL(do_crw_mchk, ChannelSubSys),
337 VMSTATE_BOOL(crws_lost, ChannelSubSys),
338 /* These were kind of migrated by virtio */
339 VMSTATE_UINT8(max_cssid, ChannelSubSys),
340 VMSTATE_UINT8(max_ssid, ChannelSubSys),
341 VMSTATE_BOOL(chnmon_active, ChannelSubSys),
342 VMSTATE_UINT64(chnmon_area, ChannelSubSys),
343 VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(css, ChannelSubSys, MAX_CSSID + 1,
344 0, vmstate_css_img, CssImage),
345 VMSTATE_UINT8(default_cssid, ChannelSubSys),
346 VMSTATE_END_OF_LIST()
347 }
348};
349
bc994b74
EH		 350static ChannelSubSys channel_subsys = {
351 .pending_crws = QTAILQ_HEAD_INITIALIZER(channel_subsys.pending_crws),
352 .do_crw_mchk = true,
353 .sei_pending = false,
354 .do_crw_mchk = true,
355 .crws_lost = false,
356 .chnmon_active = false,
bc994b74
EH		 357 .indicator_addresses =
358 QTAILQ_HEAD_INITIALIZER(channel_subsys.indicator_addresses),
359};
df1fe5bb 360
517ff12c
HP		 361static void subch_dev_pre_save(void *opaque)
362{
363 SubchDev *s = opaque;
364
365 /* Prepare remote_schid for save */
366 s->migrated_schid = s->schid;
367}
368
369static int subch_dev_post_load(void *opaque, int version_id)
370{
371
372 SubchDev *s = opaque;
373
374 /* Re-assign the subchannel to remote_schid if necessary */
375 if (s->migrated_schid != s->schid) {
376 if (css_find_subch(true, s->cssid, s->ssid, s->schid) == s) {
377 /*
378 * Cleanup the slot before moving to s->migrated_schid provided
379 * it still belongs to us, i.e. it was not changed by previous
380 * invocation of this function.
381 */
382 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, NULL);
383 }
384 /* It's OK to re-assign without a prior de-assign. */
385 s->schid = s->migrated_schid;
386 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, s);
387 }
388
457af626
HP		 389 if (css_migration_enabled()) {
390 /* No compat voodoo to do ;) */
391 return 0;
392 }
517ff12c
HP		 393 /*
394 * Hack alert. If we don't migrate the channel subsystem status
395 * we still need to find out if the guest enabled mss/mcss-e.
396 * If the subchannel is enabled, it certainly was able to access it,
397 * so adjust the max_ssid/max_cssid values for relevant ssid/cssid
398 * values. This is not watertight, but better than nothing.
399 */
400 if (s->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA) {
401 if (s->ssid) {
402 channel_subsys.max_ssid = MAX_SSID;
403 }
404 if (s->cssid != channel_subsys.default_cssid) {
405 channel_subsys.max_cssid = MAX_CSSID;
406 }
407 }
408 return 0;
409}
410
e996583e
HP		 411void css_register_vmstate(void)
412{
413 vmstate_register(NULL, 0, &vmstate_css, &channel_subsys);
414}
415
a28d8391
YMZ		 416IndAddr *get_indicator(hwaddr ind_addr, int len)
417{
418 IndAddr *indicator;
419
562f5e0b 420 QTAILQ_FOREACH(indicator, &channel_subsys.indicator_addresses, sibling) {
a28d8391
YMZ		 421 if (indicator->addr == ind_addr) {
422 indicator->refcnt++;
423 return indicator;
424 }
425 }
426 indicator = g_new0(IndAddr, 1);
427 indicator->addr = ind_addr;
428 indicator->len = len;
429 indicator->refcnt = 1;
562f5e0b 430 QTAILQ_INSERT_TAIL(&channel_subsys.indicator_addresses,
a28d8391
YMZ		 431 indicator, sibling);
432 return indicator;
433}
434
435static int s390_io_adapter_map(AdapterInfo *adapter, uint64_t map_addr,
436 bool do_map)
437{
438 S390FLICState *fs = s390_get_flic();
439 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
440
441 return fsc->io_adapter_map(fs, adapter->adapter_id, map_addr, do_map);
442}
443
444void release_indicator(AdapterInfo *adapter, IndAddr *indicator)
445{
446 assert(indicator->refcnt > 0);
447 indicator->refcnt--;
448 if (indicator->refcnt > 0) {
449 return;
450 }
562f5e0b 451 QTAILQ_REMOVE(&channel_subsys.indicator_addresses, indicator, sibling);
a28d8391
YMZ		 452 if (indicator->map) {
453 s390_io_adapter_map(adapter, indicator->map, false);
454 }
455 g_free(indicator);
456}
457
458int map_indicator(AdapterInfo *adapter, IndAddr *indicator)
459{
460 int ret;
461
462 if (indicator->map) {
463 return 0; /* already mapped is not an error */
464 }
465 indicator->map = indicator->addr;
466 ret = s390_io_adapter_map(adapter, indicator->map, true);
467 if ((ret != 0) && (ret != -ENOSYS)) {
468 goto out_err;
469 }
470 return 0;
471
472out_err:
473 indicator->map = 0;
474 return ret;
475}
476
df1fe5bb
CH		 477int css_create_css_image(uint8_t cssid, bool default_image)
478{
479 trace_css_new_image(cssid, default_image ? "(default)" : "");
882b3b97
CH		 480 /* 255 is reserved */
481 if (cssid == 255) {
df1fe5bb
CH		 482 return -EINVAL;
483 }
562f5e0b 484 if (channel_subsys.css[cssid]) {
df1fe5bb
CH		 485 return -EBUSY;
486 }
562f5e0b 487 channel_subsys.css[cssid] = g_malloc0(sizeof(CssImage));
df1fe5bb 488 if (default_image) {
562f5e0b 489 channel_subsys.default_cssid = cssid;
df1fe5bb
CH		 490 }
491 return 0;
492}
493
dde522bb 494uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc)
03cf077a 495{
dde522bb
FL		 496 if (type >= CSS_IO_ADAPTER_TYPE_NUMS || isc > MAX_ISC ||
497 !channel_subsys.io_adapters[type][isc]) {
498 return -1;
499 }
500
501 return channel_subsys.io_adapters[type][isc]->id;
502}
503
504/**
505 * css_register_io_adapters: Register I/O adapters per ISC during init
506 *
507 * @swap: an indication if byte swap is needed.
508 * @maskable: an indication if the adapter is subject to the mask operation.
1497c160
FL		 509 * @flags: further characteristics of the adapter.
510 * e.g. suppressible, an indication if the adapter is subject to AIS.
dde522bb
FL		 511 * @errp: location to store error information.
512 */
513void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
1497c160 514 uint8_t flags, Error **errp)
dde522bb
FL		 515{
516 uint32_t id;
517 int ret, isc;
03cf077a 518 IoAdapter *adapter;
03cf077a
CH		 519 S390FLICState *fs = s390_get_flic();
520 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
521
dde522bb
FL		 522 /*
523 * Disallow multiple registrations for the same device type.
524 * Report an error if registering for an already registered type.
525 */
526 if (channel_subsys.io_adapters[type][0]) {
527 error_setg(errp, "Adapters for type %d already registered", type);
528 }
529
530 for (isc = 0; isc <= MAX_ISC; isc++) {
531 id = (type << 3) | isc;
1497c160 532 ret = fsc->register_io_adapter(fs, id, isc, swap, maskable, flags);
dde522bb
FL		 533 if (ret == 0) {
534 adapter = g_new0(IoAdapter, 1);
535 adapter->id = id;
536 adapter->isc = isc;
537 adapter->type = type;
1497c160 538 adapter->flags = flags;
dde522bb
FL		 539 channel_subsys.io_adapters[type][isc] = adapter;
540 } else {
541 error_setg_errno(errp, -ret, "Unexpected error %d when "
542 "registering adapter %d", ret, id);
03cf077a
CH		 543 break;
544 }
03cf077a 545 }
dde522bb
FL		 546
547 /*
548 * No need to free registered adapters in kvm: kvm will clean up
549 * when the machine goes away.
550 */
551 if (ret) {
552 for (isc--; isc >= 0; isc--) {
553 g_free(channel_subsys.io_adapters[type][isc]);
554 channel_subsys.io_adapters[type][isc] = NULL;
555 }
03cf077a 556 }
dde522bb 557
03cf077a
CH		 558}
559
c1755b14
HP		 560static void css_clear_io_interrupt(uint16_t subchannel_id,
561 uint16_t subchannel_nr)
562{
563 Error *err = NULL;
564 static bool no_clear_irq;
565 S390FLICState *fs = s390_get_flic();
566 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
567 int r;
568
569 if (unlikely(no_clear_irq)) {
570 return;
571 }
572 r = fsc->clear_io_irq(fs, subchannel_id, subchannel_nr);
573 switch (r) {
574 case 0:
575 break;
576 case -ENOSYS:
577 no_clear_irq = true;
578 /*
579 * Ignore unavailability, as the user can't do anything
580 * about it anyway.
581 */
582 break;
583 default:
584 error_setg_errno(&err, -r, "unexpected error condition");
585 error_propagate(&error_abort, err);
586 }
587}
588
589static inline uint16_t css_do_build_subchannel_id(uint8_t cssid, uint8_t ssid)
df1fe5bb 590{
562f5e0b 591 if (channel_subsys.max_cssid > 0) {
c1755b14 592 return (cssid << 8) | (1 << 3) | (ssid << 1) | 1;
df1fe5bb 593 }
c1755b14
HP		 594 return (ssid << 1) | 1;
595}
596
597uint16_t css_build_subchannel_id(SubchDev *sch)
598{
599 return css_do_build_subchannel_id(sch->cssid, sch->ssid);
df1fe5bb
CH		 600}
601
8ca2b376 602void css_inject_io_interrupt(SubchDev *sch)
df1fe5bb 603{
df1fe5bb
CH		 604 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
605
606 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
607 sch->curr_status.pmcw.intparm, isc, "");
de13d216 608 s390_io_interrupt(css_build_subchannel_id(sch),
df1fe5bb
CH		 609 sch->schid,
610 sch->curr_status.pmcw.intparm,
91b0a8f3 611 isc << 27);
df1fe5bb
CH		 612}
613
614void css_conditional_io_interrupt(SubchDev *sch)
615{
616 /*
617 * If the subchannel is not currently status pending, make it pending
618 * with alert status.
619 */
620 if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) {
df1fe5bb
CH		 621 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
622
623 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
624 sch->curr_status.pmcw.intparm, isc,
625 "(unsolicited)");
626 sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
627 sch->curr_status.scsw.ctrl |=
628 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
629 /* Inject an I/O interrupt. */
de13d216 630 s390_io_interrupt(css_build_subchannel_id(sch),
df1fe5bb
CH		 631 sch->schid,
632 sch->curr_status.pmcw.intparm,
91b0a8f3 633 isc << 27);
df1fe5bb
CH		 634 }
635}
636
2283f4d6
FL		 637int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode)
638{
639 S390FLICState *fs = s390_get_flic();
640 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
641 int r;
642
643 if (env->psw.mask & PSW_MASK_PSTATE) {
644 r = -PGM_PRIVILEGED;
645 goto out;
646 }
647
648 trace_css_do_sic(mode, isc);
649 switch (mode) {
650 case SIC_IRQ_MODE_ALL:
651 case SIC_IRQ_MODE_SINGLE:
652 break;
653 default:
654 r = -PGM_OPERAND;
655 goto out;
656 }
657
658 r = fsc->modify_ais_mode(fs, isc, mode) ? -PGM_OPERATION : 0;
659out:
660 return r;
661}
662
25a08b8d 663void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc)
7e749462 664{
25a08b8d
YMZ		 665 S390FLICState *fs = s390_get_flic();
666 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
7e749462 667 uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI;
25a08b8d
YMZ		 668 IoAdapter *adapter = channel_subsys.io_adapters[type][isc];
669
670 if (!adapter) {
671 return;
672 }
7e749462
CH		 673
674 trace_css_adapter_interrupt(isc);
25a08b8d
YMZ		 675 if (fs->ais_supported) {
676 if (fsc->inject_airq(fs, type, isc, adapter->flags)) {
677 error_report("Failed to inject airq with AIS supported");
678 exit(1);
679 }
680 } else {
681 s390_io_interrupt(0, 0, 0, io_int_word);
682 }
7e749462
CH		 683}
684
df1fe5bb
CH		 685static void sch_handle_clear_func(SubchDev *sch)
686{
687 PMCW *p = &sch->curr_status.pmcw;
688 SCSW *s = &sch->curr_status.scsw;
689 int path;
690
691 /* Path management: In our simple css, we always choose the only path. */
692 path = 0x80;
693
4c293dc6 694 /* Reset values prior to 'issuing the clear signal'. */
df1fe5bb
CH		 695 p->lpum = 0;
696 p->pom = 0xff;
697 s->flags &= ~SCSW_FLAGS_MASK_PNO;
698
699 /* We always 'attempt to issue the clear signal', and we always succeed. */
df1fe5bb
CH		 700 sch->channel_prog = 0x0;
701 sch->last_cmd_valid = false;
702 s->ctrl &= ~SCSW_ACTL_CLEAR_PEND;
703 s->ctrl |= SCSW_STCTL_STATUS_PEND;
704
705 s->dstat = 0;
706 s->cstat = 0;
707 p->lpum = path;
708
709}
710
711static void sch_handle_halt_func(SubchDev *sch)
712{
713
714 PMCW *p = &sch->curr_status.pmcw;
715 SCSW *s = &sch->curr_status.scsw;
2ed982b6 716 hwaddr curr_ccw = sch->channel_prog;
df1fe5bb
CH		 717 int path;
718
719 /* Path management: In our simple css, we always choose the only path. */
720 path = 0x80;
721
722 /* We always 'attempt to issue the halt signal', and we always succeed. */
df1fe5bb
CH		 723 sch->channel_prog = 0x0;
724 sch->last_cmd_valid = false;
725 s->ctrl &= ~SCSW_ACTL_HALT_PEND;
726 s->ctrl |= SCSW_STCTL_STATUS_PEND;
727
728 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) ||
729 !((s->ctrl & SCSW_ACTL_START_PEND) ||
730 (s->ctrl & SCSW_ACTL_SUSP))) {
731 s->dstat = SCSW_DSTAT_DEVICE_END;
732 }
2ed982b6
CH		 733 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) ||
734 (s->ctrl & SCSW_ACTL_SUSP)) {
735 s->cpa = curr_ccw + 8;
736 }
df1fe5bb
CH		 737 s->cstat = 0;
738 p->lpum = path;
739
740}
741
742static void copy_sense_id_to_guest(SenseId *dest, SenseId *src)
743{
744 int i;
745
746 dest->reserved = src->reserved;
747 dest->cu_type = cpu_to_be16(src->cu_type);
748 dest->cu_model = src->cu_model;
749 dest->dev_type = cpu_to_be16(src->dev_type);
750 dest->dev_model = src->dev_model;
751 dest->unused = src->unused;
752 for (i = 0; i < ARRAY_SIZE(dest->ciw); i++) {
753 dest->ciw[i].type = src->ciw[i].type;
754 dest->ciw[i].command = src->ciw[i].command;
755 dest->ciw[i].count = cpu_to_be16(src->ciw[i].count);
756 }
757}
758
a327c921 759static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1)
df1fe5bb 760{
a327c921
CH		 761 CCW0 tmp0;
762 CCW1 tmp1;
df1fe5bb
CH		 763 CCW1 ret;
764
a327c921
CH		 765 if (fmt1) {
766 cpu_physical_memory_read(addr, &tmp1, sizeof(tmp1));
767 ret.cmd_code = tmp1.cmd_code;
768 ret.flags = tmp1.flags;
769 ret.count = be16_to_cpu(tmp1.count);
770 ret.cda = be32_to_cpu(tmp1.cda);
771 } else {
772 cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0));
9f94f84c
DJS		 773 if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) {
774 ret.cmd_code = CCW_CMD_TIC;
775 ret.flags = 0;
776 ret.count = 0;
777 } else {
778 ret.cmd_code = tmp0.cmd_code;
779 ret.flags = tmp0.flags;
780 ret.count = be16_to_cpu(tmp0.count);
fde8206b 781 }
9f94f84c 782 ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16);
a327c921 783 }
df1fe5bb
CH		 784 return ret;
785}
786
ce350f32
CH		 787static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr,
788 bool suspend_allowed)
df1fe5bb
CH		 789{
790 int ret;
791 bool check_len;
792 int len;
793 CCW1 ccw;
794
795 if (!ccw_addr) {
cc6a9f8d 796 return -EINVAL; /* channel-program check */
df1fe5bb 797 }
198c0d1f
HP		 798 /* Check doubleword aligned and 31 or 24 (fmt 0) bit addressable. */
799 if (ccw_addr & (sch->ccw_fmt_1 ? 0x80000007 : 0xff000007)) {
800 return -EINVAL;
801 }
df1fe5bb 802
a327c921
CH		 803 /* Translate everything to format-1 ccws - the information is the same. */
804 ccw = copy_ccw_from_guest(ccw_addr, sch->ccw_fmt_1);
df1fe5bb
CH		 805
806 /* Check for invalid command codes. */
807 if ((ccw.cmd_code & 0x0f) == 0) {
808 return -EINVAL;
809 }
810 if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) &&
811 ((ccw.cmd_code & 0xf0) != 0)) {
812 return -EINVAL;
813 }
fa4463e0
CH		 814 if (!sch->ccw_fmt_1 && (ccw.count == 0) &&
815 (ccw.cmd_code != CCW_CMD_TIC)) {
816 return -EINVAL;
817 }
df1fe5bb 818
4e19b57b
CH		 819 /* We don't support MIDA. */
820 if (ccw.flags & CCW_FLAG_MIDA) {
821 return -EINVAL;
822 }
823
df1fe5bb 824 if (ccw.flags & CCW_FLAG_SUSPEND) {
ce350f32 825 return suspend_allowed ? -EINPROGRESS : -EINVAL;
df1fe5bb
CH		 826 }
827
828 check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC));
829
e8601dd5
CH		 830 if (!ccw.cda) {
831 if (sch->ccw_no_data_cnt == 255) {
832 return -EINVAL;
833 }
834 sch->ccw_no_data_cnt++;
835 }
836
df1fe5bb
CH		 837 /* Look at the command. */
838 switch (ccw.cmd_code) {
839 case CCW_CMD_NOOP:
840 /* Nothing to do. */
841 ret = 0;
842 break;
843 case CCW_CMD_BASIC_SENSE:
844 if (check_len) {
845 if (ccw.count != sizeof(sch->sense_data)) {
846 ret = -EINVAL;
847 break;
848 }
849 }
850 len = MIN(ccw.count, sizeof(sch->sense_data));
851 cpu_physical_memory_write(ccw.cda, sch->sense_data, len);
852 sch->curr_status.scsw.count = ccw.count - len;
853 memset(sch->sense_data, 0, sizeof(sch->sense_data));
854 ret = 0;
855 break;
856 case CCW_CMD_SENSE_ID:
857 {
858 SenseId sense_id;
859
860 copy_sense_id_to_guest(&sense_id, &sch->id);
861 /* Sense ID information is device specific. */
862 if (check_len) {
863 if (ccw.count != sizeof(sense_id)) {
864 ret = -EINVAL;
865 break;
866 }
867 }
868 len = MIN(ccw.count, sizeof(sense_id));
869 /*
870 * Only indicate 0xff in the first sense byte if we actually
871 * have enough place to store at least bytes 0-3.
872 */
873 if (len >= 4) {
874 sense_id.reserved = 0xff;
875 } else {
876 sense_id.reserved = 0;
877 }
878 cpu_physical_memory_write(ccw.cda, &sense_id, len);
879 sch->curr_status.scsw.count = ccw.count - len;
880 ret = 0;
881 break;
882 }
883 case CCW_CMD_TIC:
884 if (sch->last_cmd_valid && (sch->last_cmd.cmd_code == CCW_CMD_TIC)) {
885 ret = -EINVAL;
886 break;
887 }
4add0da6
HP		 888 if (ccw.flags || ccw.count) {
889 /* We have already sanitized these if converted from fmt 0. */
df1fe5bb
CH		 890 ret = -EINVAL;
891 break;
892 }
893 sch->channel_prog = ccw.cda;
894 ret = -EAGAIN;
895 break;
896 default:
897 if (sch->ccw_cb) {
898 /* Handle device specific commands. */
899 ret = sch->ccw_cb(sch, ccw);
900 } else {
8d034a6f 901 ret = -ENOSYS;
df1fe5bb
CH		 902 }
903 break;
904 }
905 sch->last_cmd = ccw;
906 sch->last_cmd_valid = true;
907 if (ret == 0) {
908 if (ccw.flags & CCW_FLAG_CC) {
909 sch->channel_prog += 8;
910 ret = -EAGAIN;
911 }
912 }
913
914 return ret;
915}
916
b5f5a3af 917static void sch_handle_start_func_virtual(SubchDev *sch)
df1fe5bb
CH		 918{
919
920 PMCW *p = &sch->curr_status.pmcw;
921 SCSW *s = &sch->curr_status.scsw;
df1fe5bb
CH		 922 int path;
923 int ret;
ce350f32 924 bool suspend_allowed;
df1fe5bb
CH		 925
926 /* Path management: In our simple css, we always choose the only path. */
927 path = 0x80;
928
929 if (!(s->ctrl & SCSW_ACTL_SUSP)) {
727a0424 930 /* Start Function triggered via ssch, i.e. we have an ORB */
b5f5a3af 931 ORB *orb = &sch->orb;
6b7741c2
CH		 932 s->cstat = 0;
933 s->dstat = 0;
df1fe5bb
CH		 934 /* Look at the orb and try to execute the channel program. */
935 p->intparm = orb->intparm;
936 if (!(orb->lpm & path)) {
937 /* Generate a deferred cc 3 condition. */
938 s->flags |= SCSW_FLAGS_MASK_CC;
939 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
940 s->ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND);
941 return;
942 }
a327c921 943 sch->ccw_fmt_1 = !!(orb->ctrl0 & ORB_CTRL0_MASK_FMT);
485dd690 944 s->flags |= (sch->ccw_fmt_1) ? SCSW_FLAGS_MASK_FMT : 0;
e8601dd5 945 sch->ccw_no_data_cnt = 0;
ce350f32 946 suspend_allowed = !!(orb->ctrl0 & ORB_CTRL0_MASK_SPND);
df1fe5bb 947 } else {
b5f5a3af 948 /* Start Function resumed via rsch */
df1fe5bb 949 s->ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND);
ce350f32
CH		 950 /* The channel program had been suspended before. */
951 suspend_allowed = true;
df1fe5bb
CH		 952 }
953 sch->last_cmd_valid = false;
954 do {
ce350f32 955 ret = css_interpret_ccw(sch, sch->channel_prog, suspend_allowed);
df1fe5bb
CH		 956 switch (ret) {
957 case -EAGAIN:
958 /* ccw chain, continue processing */
959 break;
960 case 0:
961 /* success */
962 s->ctrl &= ~SCSW_ACTL_START_PEND;
963 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
964 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
965 SCSW_STCTL_STATUS_PEND;
966 s->dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END;
2ed982b6 967 s->cpa = sch->channel_prog + 8;
df1fe5bb 968 break;
2dc95b4c
JL		 969 case -EIO:
970 /* I/O errors, status depends on specific devices */
971 break;
8d034a6f 972 case -ENOSYS:
df1fe5bb
CH		 973 /* unsupported command, generate unit check (command reject) */
974 s->ctrl &= ~SCSW_ACTL_START_PEND;
975 s->dstat = SCSW_DSTAT_UNIT_CHECK;
976 /* Set sense bit 0 in ecw0. */
977 sch->sense_data[0] = 0x80;
978 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
979 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
980 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
2ed982b6 981 s->cpa = sch->channel_prog + 8;
df1fe5bb 982 break;
8d034a6f 983 case -EINPROGRESS:
df1fe5bb
CH		 984 /* channel program has been suspended */
985 s->ctrl &= ~SCSW_ACTL_START_PEND;
986 s->ctrl |= SCSW_ACTL_SUSP;
987 break;
988 default:
989 /* error, generate channel program check */
990 s->ctrl &= ~SCSW_ACTL_START_PEND;
991 s->cstat = SCSW_CSTAT_PROG_CHECK;
992 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
993 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
994 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
2ed982b6 995 s->cpa = sch->channel_prog + 8;
df1fe5bb
CH		 996 break;
997 }
998 } while (ret == -EAGAIN);
999
1000}
1001
b5f5a3af 1002static int sch_handle_start_func_passthrough(SubchDev *sch)
bab482d7
XFR		 1003{
1004
1005 PMCW *p = &sch->curr_status.pmcw;
1006 SCSW *s = &sch->curr_status.scsw;
1007 int ret;
1008
b5f5a3af 1009 ORB *orb = &sch->orb;
bab482d7
XFR		 1010 if (!(s->ctrl & SCSW_ACTL_SUSP)) {
1011 assert(orb != NULL);
1012 p->intparm = orb->intparm;
1013 }
1014
1015 /*
1016 * Only support prefetch enable mode.
1017 * Only support 64bit addressing idal.
1018 */
1019 if (!(orb->ctrl0 & ORB_CTRL0_MASK_PFCH) ||
1020 !(orb->ctrl0 & ORB_CTRL0_MASK_C64)) {
1021 return -EINVAL;
1022 }
1023
1024 ret = s390_ccw_cmd_request(orb, s, sch->driver_data);
1025 switch (ret) {
1026 /* Currently we don't update control block and just return the cc code. */
1027 case 0:
1028 break;
1029 case -EBUSY:
1030 break;
1031 case -ENODEV:
1032 break;
1033 case -EACCES:
1034 /* Let's reflect an inaccessible host device by cc 3. */
1035 ret = -ENODEV;
1036 break;
1037 default:
1038 /*
1039 * All other return codes will trigger a program check,
1040 * or set cc to 1.
1041 */
1042 break;
1043 };
1044
1045 return ret;
1046}
1047
df1fe5bb
CH		 1048/*
1049 * On real machines, this would run asynchronously to the main vcpus.
1050 * We might want to make some parts of the ssch handling (interpreting
1051 * read/writes) asynchronous later on if we start supporting more than
1052 * our current very simple devices.
1053 */
b5f5a3af 1054int do_subchannel_work_virtual(SubchDev *sch)
df1fe5bb
CH		 1055{
1056
1057 SCSW *s = &sch->curr_status.scsw;
1058
1059 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) {
1060 sch_handle_clear_func(sch);
1061 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) {
1062 sch_handle_halt_func(sch);
1063 } else if (s->ctrl & SCSW_FCTL_START_FUNC) {
727a0424 1064 /* Triggered by both ssch and rsch. */
b5f5a3af 1065 sch_handle_start_func_virtual(sch);
df1fe5bb
CH		 1066 } else {
1067 /* Cannot happen. */
bab482d7 1068 return 0;
df1fe5bb
CH		 1069 }
1070 css_inject_io_interrupt(sch);
bab482d7
XFR		 1071 return 0;
1072}
1073
b5f5a3af 1074int do_subchannel_work_passthrough(SubchDev *sch)
bab482d7
XFR		 1075{
1076 int ret;
1077 SCSW *s = &sch->curr_status.scsw;
1078
1079 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) {
1080 /* TODO: Clear handling */
1081 sch_handle_clear_func(sch);
1082 ret = 0;
1083 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) {
1084 /* TODO: Halt handling */
1085 sch_handle_halt_func(sch);
1086 ret = 0;
1087 } else if (s->ctrl & SCSW_FCTL_START_FUNC) {
b5f5a3af 1088 ret = sch_handle_start_func_passthrough(sch);
bab482d7
XFR		 1089 } else {
1090 /* Cannot happen. */
1091 return -ENODEV;
1092 }
1093
1094 return ret;
1095}
1096
b5f5a3af 1097static int do_subchannel_work(SubchDev *sch)
bab482d7
XFR		 1098{
1099 if (sch->do_subchannel_work) {
b5f5a3af 1100 return sch->do_subchannel_work(sch);
bab482d7
XFR		 1101 } else {
1102 return -EINVAL;
1103 }
df1fe5bb
CH		 1104}
1105
1106static void copy_pmcw_to_guest(PMCW *dest, const PMCW *src)
1107{
1108 int i;
1109
1110 dest->intparm = cpu_to_be32(src->intparm);
1111 dest->flags = cpu_to_be16(src->flags);
1112 dest->devno = cpu_to_be16(src->devno);
1113 dest->lpm = src->lpm;
1114 dest->pnom = src->pnom;
1115 dest->lpum = src->lpum;
1116 dest->pim = src->pim;
1117 dest->mbi = cpu_to_be16(src->mbi);
1118 dest->pom = src->pom;
1119 dest->pam = src->pam;
1120 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) {
1121 dest->chpid[i] = src->chpid[i];
1122 }
1123 dest->chars = cpu_to_be32(src->chars);
1124}
1125
8ca2b376 1126void copy_scsw_to_guest(SCSW *dest, const SCSW *src)
df1fe5bb
CH		 1127{
1128 dest->flags = cpu_to_be16(src->flags);
1129 dest->ctrl = cpu_to_be16(src->ctrl);
1130 dest->cpa = cpu_to_be32(src->cpa);
1131 dest->dstat = src->dstat;
1132 dest->cstat = src->cstat;
1133 dest->count = cpu_to_be16(src->count);
1134}
1135
1136static void copy_schib_to_guest(SCHIB *dest, const SCHIB *src)
1137{
1138 int i;
1139
1140 copy_pmcw_to_guest(&dest->pmcw, &src->pmcw);
1141 copy_scsw_to_guest(&dest->scsw, &src->scsw);
1142 dest->mba = cpu_to_be64(src->mba);
1143 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) {
1144 dest->mda[i] = src->mda[i];
1145 }
1146}
1147
1148int css_do_stsch(SubchDev *sch, SCHIB *schib)
1149{
1150 /* Use current status. */
1151 copy_schib_to_guest(schib, &sch->curr_status);
1152 return 0;
1153}
1154
1155static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src)
1156{
1157 int i;
1158
1159 dest->intparm = be32_to_cpu(src->intparm);
1160 dest->flags = be16_to_cpu(src->flags);
1161 dest->devno = be16_to_cpu(src->devno);
1162 dest->lpm = src->lpm;
1163 dest->pnom = src->pnom;
1164 dest->lpum = src->lpum;
1165 dest->pim = src->pim;
1166 dest->mbi = be16_to_cpu(src->mbi);
1167 dest->pom = src->pom;
1168 dest->pam = src->pam;
1169 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) {
1170 dest->chpid[i] = src->chpid[i];
1171 }
1172 dest->chars = be32_to_cpu(src->chars);
1173}
1174
1175static void copy_scsw_from_guest(SCSW *dest, const SCSW *src)
1176{
1177 dest->flags = be16_to_cpu(src->flags);
1178 dest->ctrl = be16_to_cpu(src->ctrl);
1179 dest->cpa = be32_to_cpu(src->cpa);
1180 dest->dstat = src->dstat;
1181 dest->cstat = src->cstat;
1182 dest->count = be16_to_cpu(src->count);
1183}
1184
1185static void copy_schib_from_guest(SCHIB *dest, const SCHIB *src)
1186{
1187 int i;
1188
1189 copy_pmcw_from_guest(&dest->pmcw, &src->pmcw);
1190 copy_scsw_from_guest(&dest->scsw, &src->scsw);
1191 dest->mba = be64_to_cpu(src->mba);
1192 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) {
1193 dest->mda[i] = src->mda[i];
1194 }
1195}
1196
bffd09cd 1197int css_do_msch(SubchDev *sch, const SCHIB *orig_schib)
df1fe5bb
CH		 1198{
1199 SCSW *s = &sch->curr_status.scsw;
1200 PMCW *p = &sch->curr_status.pmcw;
62ac4a52 1201 uint16_t oldflags;
df1fe5bb
CH		 1202 int ret;
1203 SCHIB schib;
1204
1205 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_DNV)) {
1206 ret = 0;
1207 goto out;
1208 }
1209
1210 if (s->ctrl & SCSW_STCTL_STATUS_PEND) {
1211 ret = -EINPROGRESS;
1212 goto out;
1213 }
1214
1215 if (s->ctrl &
1216 (SCSW_FCTL_START_FUNC|SCSW_FCTL_HALT_FUNC|SCSW_FCTL_CLEAR_FUNC)) {
1217 ret = -EBUSY;
1218 goto out;
1219 }
1220
1221 copy_schib_from_guest(&schib, orig_schib);
1222 /* Only update the program-modifiable fields. */
1223 p->intparm = schib.pmcw.intparm;
62ac4a52 1224 oldflags = p->flags;
df1fe5bb
CH		 1225 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
1226 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
1227 PMCW_FLAGS_MASK_MP);
1228 p->flags |= schib.pmcw.flags &
1229 (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
1230 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
1231 PMCW_FLAGS_MASK_MP);
1232 p->lpm = schib.pmcw.lpm;
1233 p->mbi = schib.pmcw.mbi;
1234 p->pom = schib.pmcw.pom;
1235 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE);
1236 p->chars |= schib.pmcw.chars &
1237 (PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE);
1238 sch->curr_status.mba = schib.mba;
1239
62ac4a52
TH		 1240 /* Has the channel been disabled? */
1241 if (sch->disable_cb && (oldflags & PMCW_FLAGS_MASK_ENA) != 0
1242 && (p->flags & PMCW_FLAGS_MASK_ENA) == 0) {
1243 sch->disable_cb(sch);
1244 }
1245
df1fe5bb
CH		 1246 ret = 0;
1247
1248out:
1249 return ret;
1250}
1251
1252int css_do_xsch(SubchDev *sch)
1253{
1254 SCSW *s = &sch->curr_status.scsw;
1255 PMCW *p = &sch->curr_status.pmcw;
1256 int ret;
1257
c679e74d 1258 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
df1fe5bb
CH		 1259 ret = -ENODEV;
1260 goto out;
1261 }
1262
6c864622
HP		 1263 if (s->ctrl & SCSW_CTRL_MASK_STCTL) {
1264 ret = -EINPROGRESS;
1265 goto out;
1266 }
1267
df1fe5bb
CH		 1268 if (!(s->ctrl & SCSW_CTRL_MASK_FCTL) ||
1269 ((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) ||
1270 (!(s->ctrl &
1271 (SCSW_ACTL_RESUME_PEND | SCSW_ACTL_START_PEND | SCSW_ACTL_SUSP))) ||
1272 (s->ctrl & SCSW_ACTL_SUBCH_ACTIVE)) {
df1fe5bb
CH		 1273 ret = -EBUSY;
1274 goto out;
1275 }
1276
1277 /* Cancel the current operation. */
1278 s->ctrl &= ~(SCSW_FCTL_START_FUNC |
1279 SCSW_ACTL_RESUME_PEND |
1280 SCSW_ACTL_START_PEND |
1281 SCSW_ACTL_SUSP);
1282 sch->channel_prog = 0x0;
1283 sch->last_cmd_valid = false;
df1fe5bb
CH		 1284 s->dstat = 0;
1285 s->cstat = 0;
1286 ret = 0;
1287
1288out:
1289 return ret;
1290}
1291
1292int css_do_csch(SubchDev *sch)
1293{
1294 SCSW *s = &sch->curr_status.scsw;
1295 PMCW *p = &sch->curr_status.pmcw;
1296 int ret;
1297
c679e74d 1298 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
df1fe5bb
CH		 1299 ret = -ENODEV;
1300 goto out;
1301 }
1302
1303 /* Trigger the clear function. */
1304 s->ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL);
4c6bf79a 1305 s->ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_ACTL_CLEAR_PEND;
df1fe5bb 1306
b5f5a3af 1307 do_subchannel_work(sch);
df1fe5bb
CH		 1308 ret = 0;
1309
1310out:
1311 return ret;
1312}
1313
1314int css_do_hsch(SubchDev *sch)
1315{
1316 SCSW *s = &sch->curr_status.scsw;
1317 PMCW *p = &sch->curr_status.pmcw;
1318 int ret;
1319
c679e74d 1320 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
df1fe5bb
CH		 1321 ret = -ENODEV;
1322 goto out;
1323 }
1324
1325 if (((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_STATUS_PEND) ||
1326 (s->ctrl & (SCSW_STCTL_PRIMARY |
1327 SCSW_STCTL_SECONDARY |
1328 SCSW_STCTL_ALERT))) {
1329 ret = -EINPROGRESS;
1330 goto out;
1331 }
1332
1333 if (s->ctrl & (SCSW_FCTL_HALT_FUNC | SCSW_FCTL_CLEAR_FUNC)) {
1334 ret = -EBUSY;
1335 goto out;
1336 }
1337
1338 /* Trigger the halt function. */
1339 s->ctrl |= SCSW_FCTL_HALT_FUNC;
1340 s->ctrl &= ~SCSW_FCTL_START_FUNC;
1341 if (((s->ctrl & SCSW_CTRL_MASK_ACTL) ==
1342 (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) &&
1343 ((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_INTERMEDIATE)) {
1344 s->ctrl &= ~SCSW_STCTL_STATUS_PEND;
1345 }
1346 s->ctrl |= SCSW_ACTL_HALT_PEND;
1347
b5f5a3af 1348 do_subchannel_work(sch);
df1fe5bb
CH		 1349 ret = 0;
1350
1351out:
1352 return ret;
1353}
1354
1355static void css_update_chnmon(SubchDev *sch)
1356{
1357 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_MME)) {
1358 /* Not active. */
1359 return;
1360 }
1361 /* The counter is conveniently located at the beginning of the struct. */
1362 if (sch->curr_status.pmcw.chars & PMCW_CHARS_MASK_MBFC) {
1363 /* Format 1, per-subchannel area. */
1364 uint32_t count;
1365
42874d3a
PM		 1366 count = address_space_ldl(&address_space_memory,
1367 sch->curr_status.mba,
1368 MEMTXATTRS_UNSPECIFIED,
1369 NULL);
df1fe5bb 1370 count++;
42874d3a
PM		 1371 address_space_stl(&address_space_memory, sch->curr_status.mba, count,
1372 MEMTXATTRS_UNSPECIFIED, NULL);
df1fe5bb
CH		 1373 } else {
1374 /* Format 0, global area. */
1375 uint32_t offset;
1376 uint16_t count;
1377
1378 offset = sch->curr_status.pmcw.mbi << 5;
42874d3a 1379 count = address_space_lduw(&address_space_memory,
562f5e0b 1380 channel_subsys.chnmon_area + offset,
42874d3a
PM		 1381 MEMTXATTRS_UNSPECIFIED,
1382 NULL);
df1fe5bb 1383 count++;
42874d3a 1384 address_space_stw(&address_space_memory,
562f5e0b 1385 channel_subsys.chnmon_area + offset, count,
42874d3a 1386 MEMTXATTRS_UNSPECIFIED, NULL);
df1fe5bb
CH		 1387 }
1388}
1389
1390int css_do_ssch(SubchDev *sch, ORB *orb)
1391{
1392 SCSW *s = &sch->curr_status.scsw;
1393 PMCW *p = &sch->curr_status.pmcw;
1394 int ret;
1395
c679e74d 1396 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
df1fe5bb
CH		 1397 ret = -ENODEV;
1398 goto out;
1399 }
1400
1401 if (s->ctrl & SCSW_STCTL_STATUS_PEND) {
1402 ret = -EINPROGRESS;
1403 goto out;
1404 }
1405
1406 if (s->ctrl & (SCSW_FCTL_START_FUNC |
1407 SCSW_FCTL_HALT_FUNC |
1408 SCSW_FCTL_CLEAR_FUNC)) {
1409 ret = -EBUSY;
1410 goto out;
1411 }
1412
1413 /* If monitoring is active, update counter. */
562f5e0b 1414 if (channel_subsys.chnmon_active) {
df1fe5bb
CH		 1415 css_update_chnmon(sch);
1416 }
ff443fe6 1417 sch->orb = *orb;
df1fe5bb
CH		 1418 sch->channel_prog = orb->cpa;
1419 /* Trigger the start function. */
1420 s->ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND);
1421 s->flags &= ~SCSW_FLAGS_MASK_PNO;
1422
b5f5a3af 1423 ret = do_subchannel_work(sch);
df1fe5bb
CH		 1424
1425out:
1426 return ret;
1427}
1428
b7b6348a
TH		 1429static void copy_irb_to_guest(IRB *dest, const IRB *src, PMCW *pmcw,
1430 int *irb_len)
df1fe5bb
CH		 1431{
1432 int i;
f068d320
CH		 1433 uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL;
1434 uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL;
df1fe5bb
CH		 1435
1436 copy_scsw_to_guest(&dest->scsw, &src->scsw);
1437
1438 for (i = 0; i < ARRAY_SIZE(dest->esw); i++) {
1439 dest->esw[i] = cpu_to_be32(src->esw[i]);
1440 }
1441 for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) {
1442 dest->ecw[i] = cpu_to_be32(src->ecw[i]);
1443 }
b7b6348a
TH		 1444 *irb_len = sizeof(*dest) - sizeof(dest->emw);
1445
f068d320
CH		 1446 /* extended measurements enabled? */
1447 if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) ||
1448 !(pmcw->flags & PMCW_FLAGS_MASK_TF) ||
1449 !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) {
1450 return;
1451 }
1452 /* extended measurements pending? */
1453 if (!(stctl & SCSW_STCTL_STATUS_PEND)) {
1454 return;
1455 }
1456 if ((stctl & SCSW_STCTL_PRIMARY) ||
1457 (stctl == SCSW_STCTL_SECONDARY) ||
1458 ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) {
1459 for (i = 0; i < ARRAY_SIZE(dest->emw); i++) {
1460 dest->emw[i] = cpu_to_be32(src->emw[i]);
1461 }
df1fe5bb 1462 }
b7b6348a 1463 *irb_len = sizeof(*dest);
df1fe5bb
CH		 1464}
1465
b7b6348a 1466int css_do_tsch_get_irb(SubchDev *sch, IRB *target_irb, int *irb_len)
df1fe5bb
CH		 1467{
1468 SCSW *s = &sch->curr_status.scsw;
1469 PMCW *p = &sch->curr_status.pmcw;
1470 uint16_t stctl;
df1fe5bb 1471 IRB irb;
df1fe5bb 1472
c679e74d 1473 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
b7b6348a 1474 return 3;
df1fe5bb
CH		 1475 }
1476
1477 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL;
df1fe5bb
CH		 1478
1479 /* Prepare the irb for the guest. */
1480 memset(&irb, 0, sizeof(IRB));
1481
1482 /* Copy scsw from current status. */
1483 memcpy(&irb.scsw, s, sizeof(SCSW));
1484 if (stctl & SCSW_STCTL_STATUS_PEND) {
1485 if (s->cstat & (SCSW_CSTAT_DATA_CHECK |
1486 SCSW_CSTAT_CHN_CTRL_CHK |
1487 SCSW_CSTAT_INTF_CTRL_CHK)) {
1488 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF;
1489 irb.esw[0] = 0x04804000;
1490 } else {
1491 irb.esw[0] = 0x00800000;
1492 }
1493 /* If a unit check is pending, copy sense data. */
1494 if ((s->dstat & SCSW_DSTAT_UNIT_CHECK) &&
1495 (p->chars & PMCW_CHARS_MASK_CSENSE)) {
b498484e
CH		 1496 int i;
1497
df1fe5bb 1498 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL;
b498484e 1499 /* Attention: sense_data is already BE! */
df1fe5bb 1500 memcpy(irb.ecw, sch->sense_data, sizeof(sch->sense_data));
b498484e
CH		 1501 for (i = 0; i < ARRAY_SIZE(irb.ecw); i++) {
1502 irb.ecw[i] = be32_to_cpu(irb.ecw[i]);
1503 }
8312976e 1504 irb.esw[1] = 0x01000000 | (sizeof(sch->sense_data) << 8);
df1fe5bb
CH		 1505 }
1506 }
1507 /* Store the irb to the guest. */
b7b6348a
TH		 1508 copy_irb_to_guest(target_irb, &irb, p, irb_len);
1509
1510 return ((stctl & SCSW_STCTL_STATUS_PEND) == 0);
1511}
1512
1513void css_do_tsch_update_subch(SubchDev *sch)
1514{
1515 SCSW *s = &sch->curr_status.scsw;
1516 PMCW *p = &sch->curr_status.pmcw;
1517 uint16_t stctl;
1518 uint16_t fctl;
1519 uint16_t actl;
1520
1521 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL;
1522 fctl = s->ctrl & SCSW_CTRL_MASK_FCTL;
1523 actl = s->ctrl & SCSW_CTRL_MASK_ACTL;
df1fe5bb
CH		 1524
1525 /* Clear conditions on subchannel, if applicable. */
1526 if (stctl & SCSW_STCTL_STATUS_PEND) {
1527 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
1528 if ((stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) ||
1529 ((fctl & SCSW_FCTL_HALT_FUNC) &&
1530 (actl & SCSW_ACTL_SUSP))) {
1531 s->ctrl &= ~SCSW_CTRL_MASK_FCTL;
1532 }
1533 if (stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) {
1534 s->flags &= ~SCSW_FLAGS_MASK_PNO;
1535 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND |
1536 SCSW_ACTL_START_PEND |
1537 SCSW_ACTL_HALT_PEND |
1538 SCSW_ACTL_CLEAR_PEND |
1539 SCSW_ACTL_SUSP);
1540 } else {
1541 if ((actl & SCSW_ACTL_SUSP) &&
1542 (fctl & SCSW_FCTL_START_FUNC)) {
1543 s->flags &= ~SCSW_FLAGS_MASK_PNO;
1544 if (fctl & SCSW_FCTL_HALT_FUNC) {
1545 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND |
1546 SCSW_ACTL_START_PEND |
1547 SCSW_ACTL_HALT_PEND |
1548 SCSW_ACTL_CLEAR_PEND |
1549 SCSW_ACTL_SUSP);
1550 } else {
1551 s->ctrl &= ~SCSW_ACTL_RESUME_PEND;
1552 }
1553 }
1554 }
1555 /* Clear pending sense data. */
1556 if (p->chars & PMCW_CHARS_MASK_CSENSE) {
1557 memset(sch->sense_data, 0 , sizeof(sch->sense_data));
1558 }
1559 }
df1fe5bb
CH		 1560}
1561
1562static void copy_crw_to_guest(CRW *dest, const CRW *src)
1563{
1564 dest->flags = cpu_to_be16(src->flags);
1565 dest->rsid = cpu_to_be16(src->rsid);
1566}
1567
1568int css_do_stcrw(CRW *crw)
1569{
1570 CrwContainer *crw_cont;
1571 int ret;
1572
562f5e0b 1573 crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws);
df1fe5bb 1574 if (crw_cont) {
562f5e0b 1575 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling);
df1fe5bb
CH		 1576 copy_crw_to_guest(crw, &crw_cont->crw);
1577 g_free(crw_cont);
1578 ret = 0;
1579 } else {
1580 /* List was empty, turn crw machine checks on again. */
1581 memset(crw, 0, sizeof(*crw));
562f5e0b 1582 channel_subsys.do_crw_mchk = true;
df1fe5bb
CH		 1583 ret = 1;
1584 }
1585
1586 return ret;
1587}
1588
7f74f0aa
TH		 1589static void copy_crw_from_guest(CRW *dest, const CRW *src)
1590{
1591 dest->flags = be16_to_cpu(src->flags);
1592 dest->rsid = be16_to_cpu(src->rsid);
1593}
1594
1595void css_undo_stcrw(CRW *crw)
1596{
1597 CrwContainer *crw_cont;
1598
1599 crw_cont = g_try_malloc0(sizeof(CrwContainer));
1600 if (!crw_cont) {
562f5e0b 1601 channel_subsys.crws_lost = true;
7f74f0aa
TH		 1602 return;
1603 }
1604 copy_crw_from_guest(&crw_cont->crw, crw);
1605
562f5e0b 1606 QTAILQ_INSERT_HEAD(&channel_subsys.pending_crws, crw_cont, sibling);
7f74f0aa
TH		 1607}
1608
50c8d9bf 1609int css_do_tpi(IOIntCode *int_code, int lowcore)
df1fe5bb
CH		 1610{
1611 /* No pending interrupts for !KVM. */
1612 return 0;
1613 }
1614
1615int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
1616 int rfmt, void *buf)
1617{
1618 int i, desc_size;
1619 uint32_t words[8];
1620 uint32_t chpid_type_word;
1621 CssImage *css;
1622
1623 if (!m && !cssid) {
562f5e0b 1624 css = channel_subsys.css[channel_subsys.default_cssid];
df1fe5bb 1625 } else {
562f5e0b 1626 css = channel_subsys.css[cssid];
df1fe5bb
CH		 1627 }
1628 if (!css) {
1629 return 0;
1630 }
1631 desc_size = 0;
1632 for (i = f_chpid; i <= l_chpid; i++) {
1633 if (css->chpids[i].in_use) {
1634 chpid_type_word = 0x80000000 | (css->chpids[i].type << 8) | i;
1635 if (rfmt == 0) {
1636 words[0] = cpu_to_be32(chpid_type_word);
1637 words[1] = 0;
1638 memcpy(buf + desc_size, words, 8);
1639 desc_size += 8;
1640 } else if (rfmt == 1) {
1641 words[0] = cpu_to_be32(chpid_type_word);
1642 words[1] = 0;
1643 words[2] = 0;
1644 words[3] = 0;
1645 words[4] = 0;
1646 words[5] = 0;
1647 words[6] = 0;
1648 words[7] = 0;
1649 memcpy(buf + desc_size, words, 32);
1650 desc_size += 32;
1651 }
1652 }
1653 }
1654 return desc_size;
1655}
1656
1657void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
1658{
1659 /* dct is currently ignored (not really meaningful for our devices) */
1660 /* TODO: Don't ignore mbk. */
562f5e0b 1661 if (update && !channel_subsys.chnmon_active) {
df1fe5bb 1662 /* Enable measuring. */
562f5e0b
EH		 1663 channel_subsys.chnmon_area = mbo;
1664 channel_subsys.chnmon_active = true;
df1fe5bb 1665 }
562f5e0b 1666 if (!update && channel_subsys.chnmon_active) {
df1fe5bb 1667 /* Disable measuring. */
562f5e0b
EH		 1668 channel_subsys.chnmon_area = 0;
1669 channel_subsys.chnmon_active = false;
df1fe5bb
CH		 1670 }
1671}
1672
1673int css_do_rsch(SubchDev *sch)
1674{
1675 SCSW *s = &sch->curr_status.scsw;
1676 PMCW *p = &sch->curr_status.pmcw;
1677 int ret;
1678
c679e74d 1679 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
df1fe5bb
CH		 1680 ret = -ENODEV;
1681 goto out;
1682 }
1683
1684 if (s->ctrl & SCSW_STCTL_STATUS_PEND) {
1685 ret = -EINPROGRESS;
1686 goto out;
1687 }
1688
1689 if (((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) ||
1690 (s->ctrl & SCSW_ACTL_RESUME_PEND) ||
1691 (!(s->ctrl & SCSW_ACTL_SUSP))) {
1692 ret = -EINVAL;
1693 goto out;
1694 }
1695
1696 /* If monitoring is active, update counter. */
562f5e0b 1697 if (channel_subsys.chnmon_active) {
df1fe5bb
CH		 1698 css_update_chnmon(sch);
1699 }
1700
1701 s->ctrl |= SCSW_ACTL_RESUME_PEND;
b5f5a3af 1702 do_subchannel_work(sch);
df1fe5bb
CH		 1703 ret = 0;
1704
1705out:
1706 return ret;
1707}
1708
1709int css_do_rchp(uint8_t cssid, uint8_t chpid)
1710{
1711 uint8_t real_cssid;
1712
562f5e0b 1713 if (cssid > channel_subsys.max_cssid) {
df1fe5bb
CH		 1714 return -EINVAL;
1715 }
562f5e0b
EH		 1716 if (channel_subsys.max_cssid == 0) {
1717 real_cssid = channel_subsys.default_cssid;
df1fe5bb
CH		 1718 } else {
1719 real_cssid = cssid;
1720 }
562f5e0b 1721 if (!channel_subsys.css[real_cssid]) {
df1fe5bb
CH		 1722 return -EINVAL;
1723 }
1724
562f5e0b 1725 if (!channel_subsys.css[real_cssid]->chpids[chpid].in_use) {
df1fe5bb
CH		 1726 return -ENODEV;
1727 }
1728
562f5e0b 1729 if (!channel_subsys.css[real_cssid]->chpids[chpid].is_virtual) {
df1fe5bb
CH		 1730 fprintf(stderr,
1731 "rchp unsupported for non-virtual chpid %x.%02x!\n",
1732 real_cssid, chpid);
1733 return -ENODEV;
1734 }
1735
1736 /* We don't really use a channel path, so we're done here. */
5c8d6f00 1737 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1,
562f5e0b
EH		 1738 channel_subsys.max_cssid > 0 ? 1 : 0, chpid);
1739 if (channel_subsys.max_cssid > 0) {
5c8d6f00 1740 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1, 0, real_cssid << 8);
df1fe5bb
CH		 1741 }
1742 return 0;
1743}
1744
38dd7cc7 1745bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid)
df1fe5bb
CH		 1746{
1747 SubchSet *set;
38dd7cc7 1748 uint8_t real_cssid;
df1fe5bb 1749
562f5e0b 1750 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid;
882b3b97 1751 if (ssid > MAX_SSID ||
562f5e0b
EH		 1752 !channel_subsys.css[real_cssid] ||
1753 !channel_subsys.css[real_cssid]->sch_set[ssid]) {
df1fe5bb
CH		 1754 return true;
1755 }
562f5e0b 1756 set = channel_subsys.css[real_cssid]->sch_set[ssid];
df1fe5bb
CH		 1757 return schid > find_last_bit(set->schids_used,
1758 (MAX_SCHID + 1) / sizeof(unsigned long));
1759}
1760
6c15e9bf
JL		 1761unsigned int css_find_free_chpid(uint8_t cssid)
1762{
1763 CssImage *css = channel_subsys.css[cssid];
1764 unsigned int chpid;
1765
1766 if (!css) {
1767 return MAX_CHPID + 1;
1768 }
1769
1770 for (chpid = 0; chpid <= MAX_CHPID; chpid++) {
1771 /* skip reserved chpid */
1772 if (chpid == VIRTIO_CCW_CHPID) {
1773 continue;
1774 }
1775 if (!css->chpids[chpid].in_use) {
1776 return chpid;
1777 }
1778 }
1779 return MAX_CHPID + 1;
1780}
1781
8f3cf012
XFR		 1782static int css_add_chpid(uint8_t cssid, uint8_t chpid, uint8_t type,
1783 bool is_virt)
df1fe5bb
CH		 1784{
1785 CssImage *css;
1786
1787 trace_css_chpid_add(cssid, chpid, type);
562f5e0b 1788 css = channel_subsys.css[cssid];
df1fe5bb
CH		 1789 if (!css) {
1790 return -EINVAL;
1791 }
1792 if (css->chpids[chpid].in_use) {
1793 return -EEXIST;
1794 }
1795 css->chpids[chpid].in_use = 1;
1796 css->chpids[chpid].type = type;
8f3cf012 1797 css->chpids[chpid].is_virtual = is_virt;
df1fe5bb
CH		 1798
1799 css_generate_chp_crws(cssid, chpid);
1800
1801 return 0;
1802}
1803
1804void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type)
1805{
1806 PMCW *p = &sch->curr_status.pmcw;
1807 SCSW *s = &sch->curr_status.scsw;
1808 int i;
562f5e0b 1809 CssImage *css = channel_subsys.css[sch->cssid];
df1fe5bb
CH		 1810
1811 assert(css != NULL);
1812 memset(p, 0, sizeof(PMCW));
1813 p->flags |= PMCW_FLAGS_MASK_DNV;
1814 p->devno = sch->devno;
1815 /* single path */
1816 p->pim = 0x80;
1817 p->pom = 0xff;
1818 p->pam = 0x80;
1819 p->chpid[0] = chpid;
1820 if (!css->chpids[chpid].in_use) {
8f3cf012 1821 css_add_chpid(sch->cssid, chpid, type, true);
df1fe5bb
CH		 1822 }
1823
1824 memset(s, 0, sizeof(SCSW));
1825 sch->curr_status.mba = 0;
1826 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) {
1827 sch->curr_status.mda[i] = 0;
1828 }
1829}
1830
1831SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid)
1832{
1833 uint8_t real_cssid;
1834
562f5e0b 1835 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid;
df1fe5bb 1836
562f5e0b 1837 if (!channel_subsys.css[real_cssid]) {
df1fe5bb
CH		 1838 return NULL;
1839 }
1840
562f5e0b 1841 if (!channel_subsys.css[real_cssid]->sch_set[ssid]) {
df1fe5bb
CH		 1842 return NULL;
1843 }
1844
562f5e0b 1845 return channel_subsys.css[real_cssid]->sch_set[ssid]->sch[schid];
df1fe5bb
CH		 1846}
1847
cf249935
SS		 1848/**
1849 * Return free device number in subchannel set.
1850 *
1851 * Return index of the first free device number in the subchannel set
1852 * identified by @p cssid and @p ssid, beginning the search at @p
1853 * start and wrapping around at MAX_DEVNO. Return a value exceeding
1854 * MAX_SCHID if there are no free device numbers in the subchannel
1855 * set.
1856 */
1857static uint32_t css_find_free_devno(uint8_t cssid, uint8_t ssid,
1858 uint16_t start)
1859{
1860 uint32_t round;
1861
1862 for (round = 0; round <= MAX_DEVNO; round++) {
1863 uint16_t devno = (start + round) % MAX_DEVNO;
1864
1865 if (!css_devno_used(cssid, ssid, devno)) {
1866 return devno;
1867 }
1868 }
1869 return MAX_DEVNO + 1;
1870}
1871
1872/**
1873 * Return first free subchannel (id) in subchannel set.
1874 *
1875 * Return index of the first free subchannel in the subchannel set
1876 * identified by @p cssid and @p ssid, if there is any. Return a value
1877 * exceeding MAX_SCHID if there are no free subchannels in the
1878 * subchannel set.
1879 */
1880static uint32_t css_find_free_subch(uint8_t cssid, uint8_t ssid)
1881{
1882 uint32_t schid;
1883
1884 for (schid = 0; schid <= MAX_SCHID; schid++) {
1885 if (!css_find_subch(1, cssid, ssid, schid)) {
1886 return schid;
1887 }
1888 }
1889 return MAX_SCHID + 1;
1890}
1891
1892/**
1893 * Return first free subchannel (id) in subchannel set for a device number
1894 *
1895 * Verify the device number @p devno is not used yet in the subchannel
1896 * set identified by @p cssid and @p ssid. Set @p schid to the index
1897 * of the first free subchannel in the subchannel set, if there is
1898 * any. Return true if everything succeeded and false otherwise.
1899 */
1900static bool css_find_free_subch_for_devno(uint8_t cssid, uint8_t ssid,
1901 uint16_t devno, uint16_t *schid,
1902 Error **errp)
1903{
1904 uint32_t free_schid;
1905
1906 assert(schid);
1907 if (css_devno_used(cssid, ssid, devno)) {
1908 error_setg(errp, "Device %x.%x.%04x already exists",
1909 cssid, ssid, devno);
1910 return false;
1911 }
1912 free_schid = css_find_free_subch(cssid, ssid);
1913 if (free_schid > MAX_SCHID) {
1914 error_setg(errp, "No free subchannel found for %x.%x.%04x",
1915 cssid, ssid, devno);
1916 return false;
1917 }
1918 *schid = free_schid;
1919 return true;
1920}
1921
1922/**
1923 * Return first free subchannel (id) and device number
1924 *
1925 * Locate the first free subchannel and first free device number in
1926 * any of the subchannel sets of the channel subsystem identified by
1927 * @p cssid. Return false if no free subchannel / device number could
1928 * be found. Otherwise set @p ssid, @p devno and @p schid to identify
1929 * the available subchannel and device number and return true.
1930 *
1931 * May modify @p ssid, @p devno and / or @p schid even if no free
1932 * subchannel / device number could be found.
1933 */
1934static bool css_find_free_subch_and_devno(uint8_t cssid, uint8_t *ssid,
1935 uint16_t *devno, uint16_t *schid,
1936 Error **errp)
1937{
1938 uint32_t free_schid, free_devno;
1939
1940 assert(ssid && devno && schid);
1941 for (*ssid = 0; *ssid <= MAX_SSID; (*ssid)++) {
1942 free_schid = css_find_free_subch(cssid, *ssid);
1943 if (free_schid > MAX_SCHID) {
1944 continue;
1945 }
1946 free_devno = css_find_free_devno(cssid, *ssid, free_schid);
1947 if (free_devno > MAX_DEVNO) {
1948 continue;
1949 }
1950 *schid = free_schid;
1951 *devno = free_devno;
1952 return true;
1953 }
1954 error_setg(errp, "Virtual channel subsystem is full!");
1955 return false;
1956}
1957
df1fe5bb
CH		 1958bool css_subch_visible(SubchDev *sch)
1959{
562f5e0b 1960 if (sch->ssid > channel_subsys.max_ssid) {
df1fe5bb
CH		 1961 return false;
1962 }
1963
562f5e0b
EH		 1964 if (sch->cssid != channel_subsys.default_cssid) {
1965 return (channel_subsys.max_cssid > 0);
df1fe5bb
CH		 1966 }
1967
1968 return true;
1969}
1970
1971bool css_present(uint8_t cssid)
1972{
562f5e0b 1973 return (channel_subsys.css[cssid] != NULL);
df1fe5bb
CH		 1974}
1975
1976bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno)
1977{
562f5e0b 1978 if (!channel_subsys.css[cssid]) {
df1fe5bb
CH		 1979 return false;
1980 }
562f5e0b 1981 if (!channel_subsys.css[cssid]->sch_set[ssid]) {
df1fe5bb
CH		 1982 return false;
1983 }
1984
1985 return !!test_bit(devno,
562f5e0b 1986 channel_subsys.css[cssid]->sch_set[ssid]->devnos_used);
df1fe5bb
CH		 1987}
1988
1989void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid,
1990 uint16_t devno, SubchDev *sch)
1991{
1992 CssImage *css;
1993 SubchSet *s_set;
1994
1995 trace_css_assign_subch(sch ? "assign" : "deassign", cssid, ssid, schid,
1996 devno);
562f5e0b 1997 if (!channel_subsys.css[cssid]) {
df1fe5bb
CH		 1998 fprintf(stderr,
1999 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n",
2000 __func__, cssid, ssid, schid);
2001 return;
2002 }
562f5e0b 2003 css = channel_subsys.css[cssid];
df1fe5bb
CH		 2004
2005 if (!css->sch_set[ssid]) {
2006 css->sch_set[ssid] = g_malloc0(sizeof(SubchSet));
2007 }
2008 s_set = css->sch_set[ssid];
2009
2010 s_set->sch[schid] = sch;
2011 if (sch) {
2012 set_bit(schid, s_set->schids_used);
2013 set_bit(devno, s_set->devnos_used);
2014 } else {
2015 clear_bit(schid, s_set->schids_used);
2016 clear_bit(devno, s_set->devnos_used);
2017 }
2018}
2019
5c8d6f00
DJS		 2020void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited,
2021 int chain, uint16_t rsid)
df1fe5bb
CH		 2022{
2023 CrwContainer *crw_cont;
2024
2025 trace_css_crw(rsc, erc, rsid, chain ? "(chained)" : "");
2026 /* TODO: Maybe use a static crw pool? */
2027 crw_cont = g_try_malloc0(sizeof(CrwContainer));
2028 if (!crw_cont) {
562f5e0b 2029 channel_subsys.crws_lost = true;
df1fe5bb
CH		 2030 return;
2031 }
2032 crw_cont->crw.flags = (rsc << 8) | erc;
5c8d6f00
DJS		 2033 if (solicited) {
2034 crw_cont->crw.flags |= CRW_FLAGS_MASK_S;
2035 }
df1fe5bb
CH		 2036 if (chain) {
2037 crw_cont->crw.flags |= CRW_FLAGS_MASK_C;
2038 }
2039 crw_cont->crw.rsid = rsid;
562f5e0b 2040 if (channel_subsys.crws_lost) {
df1fe5bb 2041 crw_cont->crw.flags |= CRW_FLAGS_MASK_R;
562f5e0b 2042 channel_subsys.crws_lost = false;
df1fe5bb
CH		 2043 }
2044
562f5e0b 2045 QTAILQ_INSERT_TAIL(&channel_subsys.pending_crws, crw_cont, sibling);
df1fe5bb 2046
562f5e0b
EH		 2047 if (channel_subsys.do_crw_mchk) {
2048 channel_subsys.do_crw_mchk = false;
df1fe5bb 2049 /* Inject crw pending machine check. */
de13d216 2050 s390_crw_mchk();
df1fe5bb
CH		 2051 }
2052}
2053
2054void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid,
2055 int hotplugged, int add)
2056{
2057 uint8_t guest_cssid;
2058 bool chain_crw;
2059
2060 if (add && !hotplugged) {
2061 return;
2062 }
562f5e0b 2063 if (channel_subsys.max_cssid == 0) {
df1fe5bb 2064 /* Default cssid shows up as 0. */
562f5e0b 2065 guest_cssid = (cssid == channel_subsys.default_cssid) ? 0 : cssid;
df1fe5bb
CH		 2066 } else {
2067 /* Show real cssid to the guest. */
2068 guest_cssid = cssid;
2069 }
2070 /*
2071 * Only notify for higher subchannel sets/channel subsystems if the
2072 * guest has enabled it.
2073 */
562f5e0b
EH		 2074 if ((ssid > channel_subsys.max_ssid) ||
2075 (guest_cssid > channel_subsys.max_cssid) ||
2076 ((channel_subsys.max_cssid == 0) &&
2077 (cssid != channel_subsys.default_cssid))) {
df1fe5bb
CH		 2078 return;
2079 }
562f5e0b
EH		 2080 chain_crw = (channel_subsys.max_ssid > 0) ||
2081 (channel_subsys.max_cssid > 0);
5c8d6f00 2082 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, chain_crw ? 1 : 0, schid);
df1fe5bb 2083 if (chain_crw) {
5c8d6f00 2084 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, 0,
df1fe5bb
CH		 2085 (guest_cssid << 8) | (ssid << 4));
2086 }
c1755b14
HP		 2087 /* RW_ERC_IPI --> clear pending interrupts */
2088 css_clear_io_interrupt(css_do_build_subchannel_id(cssid, ssid), schid);
df1fe5bb
CH		 2089}
2090
2091void css_generate_chp_crws(uint8_t cssid, uint8_t chpid)
2092{
2093 /* TODO */
2094}
2095
8cba80c3
FB		 2096void css_generate_css_crws(uint8_t cssid)
2097{
562f5e0b 2098 if (!channel_subsys.sei_pending) {
5c8d6f00 2099 css_queue_crw(CRW_RSC_CSS, CRW_ERC_EVENT, 0, 0, cssid);
c81b4f89 2100 }
562f5e0b 2101 channel_subsys.sei_pending = true;
c81b4f89
SSG		 2102}
2103
2104void css_clear_sei_pending(void)
2105{
562f5e0b 2106 channel_subsys.sei_pending = false;
8cba80c3
FB		 2107}
2108
df1fe5bb
CH		 2109int css_enable_mcsse(void)
2110{
2111 trace_css_enable_facility("mcsse");
562f5e0b 2112 channel_subsys.max_cssid = MAX_CSSID;
df1fe5bb
CH		 2113 return 0;
2114}
2115
2116int css_enable_mss(void)
2117{
2118 trace_css_enable_facility("mss");
562f5e0b 2119 channel_subsys.max_ssid = MAX_SSID;
df1fe5bb
CH		 2120 return 0;
2121}
2122
df1fe5bb
CH		 2123void css_reset_sch(SubchDev *sch)
2124{
2125 PMCW *p = &sch->curr_status.pmcw;
2126
62ac4a52
TH		 2127 if ((p->flags & PMCW_FLAGS_MASK_ENA) != 0 && sch->disable_cb) {
2128 sch->disable_cb(sch);
2129 }
2130
df1fe5bb
CH		 2131 p->intparm = 0;
2132 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
2133 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
2134 PMCW_FLAGS_MASK_MP | PMCW_FLAGS_MASK_TF);
2135 p->flags |= PMCW_FLAGS_MASK_DNV;
2136 p->devno = sch->devno;
2137 p->pim = 0x80;
2138 p->lpm = p->pim;
2139 p->pnom = 0;
2140 p->lpum = 0;
2141 p->mbi = 0;
2142 p->pom = 0xff;
2143 p->pam = 0x80;
2144 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_XMWME |
2145 PMCW_CHARS_MASK_CSENSE);
2146
2147 memset(&sch->curr_status.scsw, 0, sizeof(sch->curr_status.scsw));
2148 sch->curr_status.mba = 0;
2149
2150 sch->channel_prog = 0x0;
2151 sch->last_cmd_valid = false;
7e749462 2152 sch->thinint_active = false;
df1fe5bb
CH		 2153}
2154
2155void css_reset(void)
2156{
2157 CrwContainer *crw_cont;
2158
2159 /* Clean up monitoring. */
562f5e0b
EH		 2160 channel_subsys.chnmon_active = false;
2161 channel_subsys.chnmon_area = 0;
df1fe5bb
CH		 2162
2163 /* Clear pending CRWs. */
562f5e0b
EH		 2164 while ((crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws))) {
2165 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling);
df1fe5bb
CH		 2166 g_free(crw_cont);
2167 }
562f5e0b
EH		 2168 channel_subsys.sei_pending = false;
2169 channel_subsys.do_crw_mchk = true;
2170 channel_subsys.crws_lost = false;
df1fe5bb
CH		 2171
2172 /* Reset maximum ids. */
562f5e0b
EH		 2173 channel_subsys.max_cssid = 0;
2174 channel_subsys.max_ssid = 0;
df1fe5bb 2175}
06e686ea
CH		 2176
2177static void get_css_devid(Object *obj, Visitor *v, const char *name,
2178 void *opaque, Error **errp)
2179{
2180 DeviceState *dev = DEVICE(obj);
2181 Property *prop = opaque;
2182 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop);
2183 char buffer[] = "xx.x.xxxx";
2184 char *p = buffer;
2185 int r;
2186
2187 if (dev_id->valid) {
2188
2189 r = snprintf(buffer, sizeof(buffer), "%02x.%1x.%04x", dev_id->cssid,
2190 dev_id->ssid, dev_id->devid);
2191 assert(r == sizeof(buffer) - 1);
2192
2193 /* drop leading zero */
2194 if (dev_id->cssid <= 0xf) {
2195 p++;
2196 }
2197 } else {
2198 snprintf(buffer, sizeof(buffer), "<unset>");
2199 }
2200
2201 visit_type_str(v, name, &p, errp);
2202}
2203
2204/*
2205 * parse <cssid>.<ssid>.<devid> and assert valid range for cssid/ssid
2206 */
2207static void set_css_devid(Object *obj, Visitor *v, const char *name,
2208 void *opaque, Error **errp)
2209{
2210 DeviceState *dev = DEVICE(obj);
2211 Property *prop = opaque;
2212 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop);
2213 Error *local_err = NULL;
2214 char *str;
2215 int num, n1, n2;
2216 unsigned int cssid, ssid, devid;
2217
2218 if (dev->realized) {
2219 qdev_prop_set_after_realize(dev, name, errp);
2220 return;
2221 }
2222
2223 visit_type_str(v, name, &str, &local_err);
2224 if (local_err) {
2225 error_propagate(errp, local_err);
2226 return;
2227 }
2228
2229 num = sscanf(str, "%2x.%1x%n.%4x%n", &cssid, &ssid, &n1, &devid, &n2);
2230 if (num != 3 || (n2 - n1) != 5 || strlen(str) != n2) {
2231 error_set_from_qdev_prop_error(errp, EINVAL, dev, prop, str);
2232 goto out;
2233 }
2234 if ((cssid > MAX_CSSID) || (ssid > MAX_SSID)) {
2235 error_setg(errp, "Invalid cssid or ssid: cssid %x, ssid %x",
2236 cssid, ssid);
2237 goto out;
2238 }
2239
2240 dev_id->cssid = cssid;
2241 dev_id->ssid = ssid;
2242 dev_id->devid = devid;
2243 dev_id->valid = true;
2244
2245out:
2246 g_free(str);
2247}
2248
1b6b7d10 2249const PropertyInfo css_devid_propinfo = {
06e686ea
CH		 2250 .name = "str",
2251 .description = "Identifier of an I/O device in the channel "
2252 "subsystem, example: fe.1.23ab",
2253 .get = get_css_devid,
2254 .set = set_css_devid,
2255};
cf249935 2256
1b6b7d10 2257const PropertyInfo css_devid_ro_propinfo = {
c35fc6aa
DJS		 2258 .name = "str",
2259 .description = "Read-only identifier of an I/O device in the channel "
2260 "subsystem, example: fe.1.23ab",
2261 .get = get_css_devid,
2262};
2263
817d4a6b
DJS		 2264SubchDev *css_create_sch(CssDevId bus_id, bool is_virtual, bool squash_mcss,
2265 Error **errp)
cf249935
SS		 2266{
2267 uint16_t schid = 0;
2268 SubchDev *sch;
2269
2270 if (bus_id.valid) {
817d4a6b
DJS		 2271 if (is_virtual != (bus_id.cssid == VIRTUAL_CSSID)) {
2272 error_setg(errp, "cssid %hhx not valid for %s devices",
2273 bus_id.cssid,
2274 (is_virtual ? "virtual" : "non-virtual"));
cf249935
SS		 2275 return NULL;
2276 }
817d4a6b
DJS		 2277 }
2278
2279 if (bus_id.valid) {
2280 if (squash_mcss) {
2281 bus_id.cssid = channel_subsys.default_cssid;
2282 } else if (!channel_subsys.css[bus_id.cssid]) {
2283 css_create_css_image(bus_id.cssid, false);
2284 }
2285
cf249935
SS		 2286 if (!css_find_free_subch_for_devno(bus_id.cssid, bus_id.ssid,
2287 bus_id.devid, &schid, errp)) {
2288 return NULL;
2289 }
817d4a6b
DJS		 2290 } else if (squash_mcss || is_virtual) {
2291 bus_id.cssid = channel_subsys.default_cssid;
2292
cf249935
SS		 2293 if (!css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid,
2294 &bus_id.devid, &schid, errp)) {
2295 return NULL;
2296 }
817d4a6b
DJS		 2297 } else {
2298 for (bus_id.cssid = 0; bus_id.cssid < MAX_CSSID; ++bus_id.cssid) {
2299 if (bus_id.cssid == VIRTUAL_CSSID) {
2300 continue;
2301 }
2302
2303 if (!channel_subsys.css[bus_id.cssid]) {
2304 css_create_css_image(bus_id.cssid, false);
2305 }
2306
2307 if (css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid,
2308 &bus_id.devid, &schid,
2309 NULL)) {
2310 break;
2311 }
2312 if (bus_id.cssid == MAX_CSSID) {
2313 error_setg(errp, "Virtual channel subsystem is full!");
2314 return NULL;
2315 }
2316 }
cf249935
SS		 2317 }
2318
2319 sch = g_malloc0(sizeof(*sch));
2320 sch->cssid = bus_id.cssid;
2321 sch->ssid = bus_id.ssid;
2322 sch->devno = bus_id.devid;
2323 sch->schid = schid;
2324 css_subch_assign(sch->cssid, sch->ssid, schid, sch->devno, sch);
2325 return sch;
2326}
8f3cf012
XFR		 2327
2328static int css_sch_get_chpids(SubchDev *sch, CssDevId *dev_id)
2329{
2330 char *fid_path;
2331 FILE *fd;
2332 uint32_t chpid[8];
2333 int i;
2334 PMCW *p = &sch->curr_status.pmcw;
2335
2336 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/chpids",
2337 dev_id->cssid, dev_id->ssid, dev_id->devid);
2338 fd = fopen(fid_path, "r");
2339 if (fd == NULL) {
2340 error_report("%s: open %s failed", __func__, fid_path);
2341 g_free(fid_path);
2342 return -EINVAL;
2343 }
2344
2345 if (fscanf(fd, "%x %x %x %x %x %x %x %x",
2346 &chpid[0], &chpid[1], &chpid[2], &chpid[3],
2347 &chpid[4], &chpid[5], &chpid[6], &chpid[7]) != 8) {
2348 fclose(fd);
2349 g_free(fid_path);
2350 return -EINVAL;
2351 }
2352
2353 for (i = 0; i < ARRAY_SIZE(p->chpid); i++) {
2354 p->chpid[i] = chpid[i];
2355 }
2356
2357 fclose(fd);
2358 g_free(fid_path);
2359
2360 return 0;
2361}
2362
2363static int css_sch_get_path_masks(SubchDev *sch, CssDevId *dev_id)
2364{
2365 char *fid_path;
2366 FILE *fd;
2367 uint32_t pim, pam, pom;
2368 PMCW *p = &sch->curr_status.pmcw;
2369
2370 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/pimpampom",
2371 dev_id->cssid, dev_id->ssid, dev_id->devid);
2372 fd = fopen(fid_path, "r");
2373 if (fd == NULL) {
2374 error_report("%s: open %s failed", __func__, fid_path);
2375 g_free(fid_path);
2376 return -EINVAL;
2377 }
2378
2379 if (fscanf(fd, "%x %x %x", &pim, &pam, &pom) != 3) {
2380 fclose(fd);
2381 g_free(fid_path);
2382 return -EINVAL;
2383 }
2384
2385 p->pim = pim;
2386 p->pam = pam;
2387 p->pom = pom;
2388 fclose(fd);
2389 g_free(fid_path);
2390
2391 return 0;
2392}
2393
2394static int css_sch_get_chpid_type(uint8_t chpid, uint32_t *type,
2395 CssDevId *dev_id)
2396{
2397 char *fid_path;
2398 FILE *fd;
2399
2400 fid_path = g_strdup_printf("/sys/devices/css%x/chp0.%02x/type",
2401 dev_id->cssid, chpid);
2402 fd = fopen(fid_path, "r");
2403 if (fd == NULL) {
2404 error_report("%s: open %s failed", __func__, fid_path);
2405 g_free(fid_path);
2406 return -EINVAL;
2407 }
2408
2409 if (fscanf(fd, "%x", type) != 1) {
2410 fclose(fd);
2411 g_free(fid_path);
2412 return -EINVAL;
2413 }
2414
2415 fclose(fd);
2416 g_free(fid_path);
2417
2418 return 0;
2419}
2420
2421/*
2422 * We currently retrieve the real device information from sysfs to build the
2423 * guest subchannel information block without considering the migration feature.
2424 * We need to revisit this problem when we want to add migration support.
2425 */
2426int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id)
2427{
2428 CssImage *css = channel_subsys.css[sch->cssid];
2429 PMCW *p = &sch->curr_status.pmcw;
2430 SCSW *s = &sch->curr_status.scsw;
2431 uint32_t type;
2432 int i, ret;
2433
2434 assert(css != NULL);
2435 memset(p, 0, sizeof(PMCW));
2436 p->flags |= PMCW_FLAGS_MASK_DNV;
2437 /* We are dealing with I/O subchannels only. */
2438 p->devno = sch->devno;
2439
2440 /* Grab path mask from sysfs. */
2441 ret = css_sch_get_path_masks(sch, dev_id);
2442 if (ret) {
2443 return ret;
2444 }
2445
2446 /* Grab chpids from sysfs. */
2447 ret = css_sch_get_chpids(sch, dev_id);
2448 if (ret) {
2449 return ret;
2450 }
2451
2452 /* Build chpid type. */
2453 for (i = 0; i < ARRAY_SIZE(p->chpid); i++) {
2454 if (p->chpid[i] && !css->chpids[p->chpid[i]].in_use) {
2455 ret = css_sch_get_chpid_type(p->chpid[i], &type, dev_id);
2456 if (ret) {
2457 return ret;
2458 }
2459 css_add_chpid(sch->cssid, p->chpid[i], type, false);
2460 }
2461 }
2462
2463 memset(s, 0, sizeof(SCSW));
2464 sch->curr_status.mba = 0;
2465 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) {
2466 sch->curr_status.mda[i] = 0;
2467 }
2468
2469 return 0;
2470}
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