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s390x/css: add missing css state conditionally
[qemu.git] / hw / s390x / css.c
CommitLineData
df1fe5bb
CH		 1/*
2 * Channel subsystem base support.
3 *
4 * Copyright 2012 IBM Corp.
5 * Author(s): Cornelia Huck <[email protected]>
6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or (at
8 * your option) any later version. See the COPYING file in the top-level
9 * directory.
10 */
11
9615495a 12#include "qemu/osdep.h"
c1755b14 13#include "qapi/error.h"
06e686ea 14#include "qapi/visitor.h"
a9c94277 15#include "hw/qdev.h"
8f3cf012 16#include "qemu/error-report.h"
df1fe5bb 17#include "qemu/bitops.h"
8ed179c9 18#include "qemu/error-report.h"
fdfba1a2 19#include "exec/address-spaces.h"
df1fe5bb 20#include "cpu.h"
bd3f16ac
PB		 21#include "hw/s390x/ioinst.h"
22#include "hw/s390x/css.h"
df1fe5bb 23#include "trace.h"
03cf077a 24#include "hw/s390x/s390_flic.h"
517ff12c 25#include "hw/s390x/s390-virtio-ccw.h"
df1fe5bb
CH		 26
27typedef struct CrwContainer {
28 CRW crw;
29 QTAILQ_ENTRY(CrwContainer) sibling;
30} CrwContainer;
31
457af626
HP		 32static const VMStateDescription vmstate_crw = {
33 .name = "s390_crw",
34 .version_id = 1,
35 .minimum_version_id = 1,
36 .fields = (VMStateField[]) {
37 VMSTATE_UINT16(flags, CRW),
38 VMSTATE_UINT16(rsid, CRW),
39 VMSTATE_END_OF_LIST()
40 },
41};
42
43static const VMStateDescription vmstate_crw_container = {
44 .name = "s390_crw_container",
45 .version_id = 1,
46 .minimum_version_id = 1,
47 .fields = (VMStateField[]) {
48 VMSTATE_STRUCT(crw, CrwContainer, 0, vmstate_crw, CRW),
49 VMSTATE_END_OF_LIST()
50 },
51};
52
df1fe5bb
CH		 53typedef struct ChpInfo {
54 uint8_t in_use;
55 uint8_t type;
56 uint8_t is_virtual;
57} ChpInfo;
58
457af626
HP		 59static const VMStateDescription vmstate_chp_info = {
60 .name = "s390_chp_info",
61 .version_id = 1,
62 .minimum_version_id = 1,
63 .fields = (VMStateField[]) {
64 VMSTATE_UINT8(in_use, ChpInfo),
65 VMSTATE_UINT8(type, ChpInfo),
66 VMSTATE_UINT8(is_virtual, ChpInfo),
67 VMSTATE_END_OF_LIST()
68 }
69};
70
df1fe5bb
CH		 71typedef struct SubchSet {
72 SubchDev *sch[MAX_SCHID + 1];
73 unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)];
74 unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)];
75} SubchSet;
76
517ff12c
HP		 77static const VMStateDescription vmstate_scsw = {
78 .name = "s390_scsw",
79 .version_id = 1,
80 .minimum_version_id = 1,
81 .fields = (VMStateField[]) {
82 VMSTATE_UINT16(flags, SCSW),
83 VMSTATE_UINT16(ctrl, SCSW),
84 VMSTATE_UINT32(cpa, SCSW),
85 VMSTATE_UINT8(dstat, SCSW),
86 VMSTATE_UINT8(cstat, SCSW),
87 VMSTATE_UINT16(count, SCSW),
88 VMSTATE_END_OF_LIST()
89 }
90};
91
92static const VMStateDescription vmstate_pmcw = {
93 .name = "s390_pmcw",
94 .version_id = 1,
95 .minimum_version_id = 1,
96 .fields = (VMStateField[]) {
97 VMSTATE_UINT32(intparm, PMCW),
98 VMSTATE_UINT16(flags, PMCW),
99 VMSTATE_UINT16(devno, PMCW),
100 VMSTATE_UINT8(lpm, PMCW),
101 VMSTATE_UINT8(pnom, PMCW),
102 VMSTATE_UINT8(lpum, PMCW),
103 VMSTATE_UINT8(pim, PMCW),
104 VMSTATE_UINT16(mbi, PMCW),
105 VMSTATE_UINT8(pom, PMCW),
106 VMSTATE_UINT8(pam, PMCW),
107 VMSTATE_UINT8_ARRAY(chpid, PMCW, 8),
108 VMSTATE_UINT32(chars, PMCW),
109 VMSTATE_END_OF_LIST()
110 }
111};
112
113static const VMStateDescription vmstate_schib = {
114 .name = "s390_schib",
115 .version_id = 1,
116 .minimum_version_id = 1,
117 .fields = (VMStateField[]) {
118 VMSTATE_STRUCT(pmcw, SCHIB, 0, vmstate_pmcw, PMCW),
119 VMSTATE_STRUCT(scsw, SCHIB, 0, vmstate_scsw, SCSW),
120 VMSTATE_UINT64(mba, SCHIB),
121 VMSTATE_UINT8_ARRAY(mda, SCHIB, 4),
122 VMSTATE_END_OF_LIST()
123 }
124};
125
126
127static const VMStateDescription vmstate_ccw1 = {
128 .name = "s390_ccw1",
129 .version_id = 1,
130 .minimum_version_id = 1,
131 .fields = (VMStateField[]) {
132 VMSTATE_UINT8(cmd_code, CCW1),
133 VMSTATE_UINT8(flags, CCW1),
134 VMSTATE_UINT16(count, CCW1),
135 VMSTATE_UINT32(cda, CCW1),
136 VMSTATE_END_OF_LIST()
137 }
138};
139
140static const VMStateDescription vmstate_ciw = {
141 .name = "s390_ciw",
142 .version_id = 1,
143 .minimum_version_id = 1,
144 .fields = (VMStateField[]) {
145 VMSTATE_UINT8(type, CIW),
146 VMSTATE_UINT8(command, CIW),
147 VMSTATE_UINT16(count, CIW),
148 VMSTATE_END_OF_LIST()
149 }
150};
151
152static const VMStateDescription vmstate_sense_id = {
153 .name = "s390_sense_id",
154 .version_id = 1,
155 .minimum_version_id = 1,
156 .fields = (VMStateField[]) {
157 VMSTATE_UINT8(reserved, SenseId),
158 VMSTATE_UINT16(cu_type, SenseId),
159 VMSTATE_UINT8(cu_model, SenseId),
160 VMSTATE_UINT16(dev_type, SenseId),
161 VMSTATE_UINT8(dev_model, SenseId),
162 VMSTATE_UINT8(unused, SenseId),
163 VMSTATE_STRUCT_ARRAY(ciw, SenseId, MAX_CIWS, 0, vmstate_ciw, CIW),
164 VMSTATE_END_OF_LIST()
165 }
166};
167
168static int subch_dev_post_load(void *opaque, int version_id);
169static void subch_dev_pre_save(void *opaque);
170
171const char err_hint_devno[] = "Devno mismatch, tried to load wrong section!"
172 " Likely reason: some sequences of plug and unplug can break"
173 " migration for machine versions prior to 2.7 (known design flaw).";
174
175const VMStateDescription vmstate_subch_dev = {
176 .name = "s390_subch_dev",
177 .version_id = 1,
178 .minimum_version_id = 1,
179 .post_load = subch_dev_post_load,
180 .pre_save = subch_dev_pre_save,
181 .fields = (VMStateField[]) {
182 VMSTATE_UINT8_EQUAL(cssid, SubchDev, "Bug!"),
183 VMSTATE_UINT8_EQUAL(ssid, SubchDev, "Bug!"),
184 VMSTATE_UINT16(migrated_schid, SubchDev),
185 VMSTATE_UINT16_EQUAL(devno, SubchDev, err_hint_devno),
186 VMSTATE_BOOL(thinint_active, SubchDev),
187 VMSTATE_STRUCT(curr_status, SubchDev, 0, vmstate_schib, SCHIB),
188 VMSTATE_UINT8_ARRAY(sense_data, SubchDev, 32),
189 VMSTATE_UINT64(channel_prog, SubchDev),
190 VMSTATE_STRUCT(last_cmd, SubchDev, 0, vmstate_ccw1, CCW1),
191 VMSTATE_BOOL(last_cmd_valid, SubchDev),
192 VMSTATE_STRUCT(id, SubchDev, 0, vmstate_sense_id, SenseId),
193 VMSTATE_BOOL(ccw_fmt_1, SubchDev),
194 VMSTATE_UINT8(ccw_no_data_cnt, SubchDev),
195 VMSTATE_END_OF_LIST()
196 }
197};
198
199typedef struct IndAddrPtrTmp {
200 IndAddr **parent;
201 uint64_t addr;
202 int32_t len;
203} IndAddrPtrTmp;
204
205static int post_load_ind_addr(void *opaque, int version_id)
206{
207 IndAddrPtrTmp *ptmp = opaque;
208 IndAddr **ind_addr = ptmp->parent;
209
210 if (ptmp->len != 0) {
211 *ind_addr = get_indicator(ptmp->addr, ptmp->len);
212 } else {
213 *ind_addr = NULL;
214 }
215 return 0;
216}
217
218static void pre_save_ind_addr(void *opaque)
219{
220 IndAddrPtrTmp *ptmp = opaque;
221 IndAddr *ind_addr = *(ptmp->parent);
222
223 if (ind_addr != NULL) {
224 ptmp->len = ind_addr->len;
225 ptmp->addr = ind_addr->addr;
226 } else {
227 ptmp->len = 0;
228 ptmp->addr = 0L;
229 }
230}
231
232const VMStateDescription vmstate_ind_addr_tmp = {
233 .name = "s390_ind_addr_tmp",
234 .pre_save = pre_save_ind_addr,
235 .post_load = post_load_ind_addr,
236
237 .fields = (VMStateField[]) {
238 VMSTATE_INT32(len, IndAddrPtrTmp),
239 VMSTATE_UINT64(addr, IndAddrPtrTmp),
240 VMSTATE_END_OF_LIST()
241 }
242};
243
244const VMStateDescription vmstate_ind_addr = {
245 .name = "s390_ind_addr_tmp",
246 .fields = (VMStateField[]) {
247 VMSTATE_WITH_TMP(IndAddr*, IndAddrPtrTmp, vmstate_ind_addr_tmp),
248 VMSTATE_END_OF_LIST()
249 }
250};
251
df1fe5bb
CH		 252typedef struct CssImage {
253 SubchSet *sch_set[MAX_SSID + 1];
254 ChpInfo chpids[MAX_CHPID + 1];
255} CssImage;
256
457af626
HP		 257static const VMStateDescription vmstate_css_img = {
258 .name = "s390_css_img",
259 .version_id = 1,
260 .minimum_version_id = 1,
261 .fields = (VMStateField[]) {
262 /* Subchannel sets have no relevant state. */
263 VMSTATE_STRUCT_ARRAY(chpids, CssImage, MAX_CHPID + 1, 0,
264 vmstate_chp_info, ChpInfo),
265 VMSTATE_END_OF_LIST()
266 }
267
268};
269
03cf077a
CH		 270typedef struct IoAdapter {
271 uint32_t id;
272 uint8_t type;
273 uint8_t isc;
1497c160 274 uint8_t flags;
03cf077a
CH		 275} IoAdapter;
276
df1fe5bb
CH		 277typedef struct ChannelSubSys {
278 QTAILQ_HEAD(, CrwContainer) pending_crws;
c81b4f89 279 bool sei_pending;
df1fe5bb
CH		 280 bool do_crw_mchk;
281 bool crws_lost;
282 uint8_t max_cssid;
283 uint8_t max_ssid;
284 bool chnmon_active;
285 uint64_t chnmon_area;
286 CssImage *css[MAX_CSSID + 1];
287 uint8_t default_cssid;
457af626 288 /* don't migrate, see css_register_io_adapters */
dde522bb 289 IoAdapter *io_adapters[CSS_IO_ADAPTER_TYPE_NUMS][MAX_ISC + 1];
457af626 290 /* don't migrate, see get_indicator and IndAddrPtrTmp */
a28d8391 291 QTAILQ_HEAD(, IndAddr) indicator_addresses;
df1fe5bb
CH		 292} ChannelSubSys;
293
457af626
HP		 294static const VMStateDescription vmstate_css = {
295 .name = "s390_css",
296 .version_id = 1,
297 .minimum_version_id = 1,
298 .fields = (VMStateField[]) {
299 VMSTATE_QTAILQ_V(pending_crws, ChannelSubSys, 1, vmstate_crw_container,
300 CrwContainer, sibling),
301 VMSTATE_BOOL(sei_pending, ChannelSubSys),
302 VMSTATE_BOOL(do_crw_mchk, ChannelSubSys),
303 VMSTATE_BOOL(crws_lost, ChannelSubSys),
304 /* These were kind of migrated by virtio */
305 VMSTATE_UINT8(max_cssid, ChannelSubSys),
306 VMSTATE_UINT8(max_ssid, ChannelSubSys),
307 VMSTATE_BOOL(chnmon_active, ChannelSubSys),
308 VMSTATE_UINT64(chnmon_area, ChannelSubSys),
309 VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(css, ChannelSubSys, MAX_CSSID + 1,
310 0, vmstate_css_img, CssImage),
311 VMSTATE_UINT8(default_cssid, ChannelSubSys),
312 VMSTATE_END_OF_LIST()
313 }
314};
315
bc994b74
EH		 316static ChannelSubSys channel_subsys = {
317 .pending_crws = QTAILQ_HEAD_INITIALIZER(channel_subsys.pending_crws),
318 .do_crw_mchk = true,
319 .sei_pending = false,
320 .do_crw_mchk = true,
321 .crws_lost = false,
322 .chnmon_active = false,
bc994b74
EH		 323 .indicator_addresses =
324 QTAILQ_HEAD_INITIALIZER(channel_subsys.indicator_addresses),
325};
df1fe5bb 326
517ff12c
HP		 327static void subch_dev_pre_save(void *opaque)
328{
329 SubchDev *s = opaque;
330
331 /* Prepare remote_schid for save */
332 s->migrated_schid = s->schid;
333}
334
335static int subch_dev_post_load(void *opaque, int version_id)
336{
337
338 SubchDev *s = opaque;
339
340 /* Re-assign the subchannel to remote_schid if necessary */
341 if (s->migrated_schid != s->schid) {
342 if (css_find_subch(true, s->cssid, s->ssid, s->schid) == s) {
343 /*
344 * Cleanup the slot before moving to s->migrated_schid provided
345 * it still belongs to us, i.e. it was not changed by previous
346 * invocation of this function.
347 */
348 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, NULL);
349 }
350 /* It's OK to re-assign without a prior de-assign. */
351 s->schid = s->migrated_schid;
352 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, s);
353 }
354
457af626
HP		 355 if (css_migration_enabled()) {
356 /* No compat voodoo to do ;) */
357 return 0;
358 }
517ff12c
HP		 359 /*
360 * Hack alert. If we don't migrate the channel subsystem status
361 * we still need to find out if the guest enabled mss/mcss-e.
362 * If the subchannel is enabled, it certainly was able to access it,
363 * so adjust the max_ssid/max_cssid values for relevant ssid/cssid
364 * values. This is not watertight, but better than nothing.
365 */
366 if (s->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA) {
367 if (s->ssid) {
368 channel_subsys.max_ssid = MAX_SSID;
369 }
370 if (s->cssid != channel_subsys.default_cssid) {
371 channel_subsys.max_cssid = MAX_CSSID;
372 }
373 }
374 return 0;
375}
376
a28d8391
YMZ		 377IndAddr *get_indicator(hwaddr ind_addr, int len)
378{
379 IndAddr *indicator;
380
562f5e0b 381 QTAILQ_FOREACH(indicator, &channel_subsys.indicator_addresses, sibling) {
a28d8391
YMZ		 382 if (indicator->addr == ind_addr) {
383 indicator->refcnt++;
384 return indicator;
385 }
386 }
387 indicator = g_new0(IndAddr, 1);
388 indicator->addr = ind_addr;
389 indicator->len = len;
390 indicator->refcnt = 1;
562f5e0b 391 QTAILQ_INSERT_TAIL(&channel_subsys.indicator_addresses,
a28d8391
YMZ		 392 indicator, sibling);
393 return indicator;
394}
395
396static int s390_io_adapter_map(AdapterInfo *adapter, uint64_t map_addr,
397 bool do_map)
398{
399 S390FLICState *fs = s390_get_flic();
400 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
401
402 return fsc->io_adapter_map(fs, adapter->adapter_id, map_addr, do_map);
403}
404
405void release_indicator(AdapterInfo *adapter, IndAddr *indicator)
406{
407 assert(indicator->refcnt > 0);
408 indicator->refcnt--;
409 if (indicator->refcnt > 0) {
410 return;
411 }
562f5e0b 412 QTAILQ_REMOVE(&channel_subsys.indicator_addresses, indicator, sibling);
a28d8391
YMZ		 413 if (indicator->map) {
414 s390_io_adapter_map(adapter, indicator->map, false);
415 }
416 g_free(indicator);
417}
418
419int map_indicator(AdapterInfo *adapter, IndAddr *indicator)
420{
421 int ret;
422
423 if (indicator->map) {
424 return 0; /* already mapped is not an error */
425 }
426 indicator->map = indicator->addr;
427 ret = s390_io_adapter_map(adapter, indicator->map, true);
428 if ((ret != 0) && (ret != -ENOSYS)) {
429 goto out_err;
430 }
431 return 0;
432
433out_err:
434 indicator->map = 0;
435 return ret;
436}
437
df1fe5bb
CH		 438int css_create_css_image(uint8_t cssid, bool default_image)
439{
440 trace_css_new_image(cssid, default_image ? "(default)" : "");
882b3b97
CH		 441 /* 255 is reserved */
442 if (cssid == 255) {
df1fe5bb
CH		 443 return -EINVAL;
444 }
562f5e0b 445 if (channel_subsys.css[cssid]) {
df1fe5bb
CH		 446 return -EBUSY;
447 }
562f5e0b 448 channel_subsys.css[cssid] = g_malloc0(sizeof(CssImage));
df1fe5bb 449 if (default_image) {
562f5e0b 450 channel_subsys.default_cssid = cssid;
df1fe5bb
CH		 451 }
452 return 0;
453}
454
dde522bb 455uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc)
03cf077a 456{
dde522bb
FL		 457 if (type >= CSS_IO_ADAPTER_TYPE_NUMS || isc > MAX_ISC ||
458 !channel_subsys.io_adapters[type][isc]) {
459 return -1;
460 }
461
462 return channel_subsys.io_adapters[type][isc]->id;
463}
464
465/**
466 * css_register_io_adapters: Register I/O adapters per ISC during init
467 *
468 * @swap: an indication if byte swap is needed.
469 * @maskable: an indication if the adapter is subject to the mask operation.
1497c160
FL		 470 * @flags: further characteristics of the adapter.
471 * e.g. suppressible, an indication if the adapter is subject to AIS.
dde522bb
FL		 472 * @errp: location to store error information.
473 */
474void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
1497c160 475 uint8_t flags, Error **errp)
dde522bb
FL		 476{
477 uint32_t id;
478 int ret, isc;
03cf077a 479 IoAdapter *adapter;
03cf077a
CH		 480 S390FLICState *fs = s390_get_flic();
481 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
482
dde522bb
FL		 483 /*
484 * Disallow multiple registrations for the same device type.
485 * Report an error if registering for an already registered type.
486 */
487 if (channel_subsys.io_adapters[type][0]) {
488 error_setg(errp, "Adapters for type %d already registered", type);
489 }
490
491 for (isc = 0; isc <= MAX_ISC; isc++) {
492 id = (type << 3) | isc;
1497c160 493 ret = fsc->register_io_adapter(fs, id, isc, swap, maskable, flags);
dde522bb
FL		 494 if (ret == 0) {
495 adapter = g_new0(IoAdapter, 1);
496 adapter->id = id;
497 adapter->isc = isc;
498 adapter->type = type;
1497c160 499 adapter->flags = flags;
dde522bb
FL		 500 channel_subsys.io_adapters[type][isc] = adapter;
501 } else {
502 error_setg_errno(errp, -ret, "Unexpected error %d when "
503 "registering adapter %d", ret, id);
03cf077a
CH		 504 break;
505 }
03cf077a 506 }
dde522bb
FL		 507
508 /*
509 * No need to free registered adapters in kvm: kvm will clean up
510 * when the machine goes away.
511 */
512 if (ret) {
513 for (isc--; isc >= 0; isc--) {
514 g_free(channel_subsys.io_adapters[type][isc]);
515 channel_subsys.io_adapters[type][isc] = NULL;
516 }
03cf077a 517 }
dde522bb 518
03cf077a
CH		 519}
520
c1755b14
HP		 521static void css_clear_io_interrupt(uint16_t subchannel_id,
522 uint16_t subchannel_nr)
523{
524 Error *err = NULL;
525 static bool no_clear_irq;
526 S390FLICState *fs = s390_get_flic();
527 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
528 int r;
529
530 if (unlikely(no_clear_irq)) {
531 return;
532 }
533 r = fsc->clear_io_irq(fs, subchannel_id, subchannel_nr);
534 switch (r) {
535 case 0:
536 break;
537 case -ENOSYS:
538 no_clear_irq = true;
539 /*
540 * Ignore unavailability, as the user can't do anything
541 * about it anyway.
542 */
543 break;
544 default:
545 error_setg_errno(&err, -r, "unexpected error condition");
546 error_propagate(&error_abort, err);
547 }
548}
549
550static inline uint16_t css_do_build_subchannel_id(uint8_t cssid, uint8_t ssid)
df1fe5bb 551{
562f5e0b 552 if (channel_subsys.max_cssid > 0) {
c1755b14 553 return (cssid << 8) | (1 << 3) | (ssid << 1) | 1;
df1fe5bb 554 }
c1755b14
HP		 555 return (ssid << 1) | 1;
556}
557
558uint16_t css_build_subchannel_id(SubchDev *sch)
559{
560 return css_do_build_subchannel_id(sch->cssid, sch->ssid);
df1fe5bb
CH		 561}
562
8ca2b376 563void css_inject_io_interrupt(SubchDev *sch)
df1fe5bb 564{
df1fe5bb
CH		 565 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
566
567 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
568 sch->curr_status.pmcw.intparm, isc, "");
de13d216 569 s390_io_interrupt(css_build_subchannel_id(sch),
df1fe5bb
CH		 570 sch->schid,
571 sch->curr_status.pmcw.intparm,
91b0a8f3 572 isc << 27);
df1fe5bb
CH		 573}
574
575void css_conditional_io_interrupt(SubchDev *sch)
576{
577 /*
578 * If the subchannel is not currently status pending, make it pending
579 * with alert status.
580 */
581 if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) {
df1fe5bb
CH		 582 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
583
584 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
585 sch->curr_status.pmcw.intparm, isc,
586 "(unsolicited)");
587 sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
588 sch->curr_status.scsw.ctrl |=
589 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
590 /* Inject an I/O interrupt. */
de13d216 591 s390_io_interrupt(css_build_subchannel_id(sch),
df1fe5bb
CH		 592 sch->schid,
593 sch->curr_status.pmcw.intparm,
91b0a8f3 594 isc << 27);
df1fe5bb
CH		 595 }
596}
597
2283f4d6
FL		 598int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode)
599{
600 S390FLICState *fs = s390_get_flic();
601 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
602 int r;
603
604 if (env->psw.mask & PSW_MASK_PSTATE) {
605 r = -PGM_PRIVILEGED;
606 goto out;
607 }
608
609 trace_css_do_sic(mode, isc);
610 switch (mode) {
611 case SIC_IRQ_MODE_ALL:
612 case SIC_IRQ_MODE_SINGLE:
613 break;
614 default:
615 r = -PGM_OPERAND;
616 goto out;
617 }
618
619 r = fsc->modify_ais_mode(fs, isc, mode) ? -PGM_OPERATION : 0;
620out:
621 return r;
622}
623
25a08b8d 624void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc)
7e749462 625{
25a08b8d
YMZ		 626 S390FLICState *fs = s390_get_flic();
627 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
7e749462 628 uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI;
25a08b8d
YMZ		 629 IoAdapter *adapter = channel_subsys.io_adapters[type][isc];
630
631 if (!adapter) {
632 return;
633 }
7e749462
CH		 634
635 trace_css_adapter_interrupt(isc);
25a08b8d
YMZ		 636 if (fs->ais_supported) {
637 if (fsc->inject_airq(fs, type, isc, adapter->flags)) {
638 error_report("Failed to inject airq with AIS supported");
639 exit(1);
640 }
641 } else {
642 s390_io_interrupt(0, 0, 0, io_int_word);
643 }
7e749462
CH		 644}
645
df1fe5bb
CH		 646static void sch_handle_clear_func(SubchDev *sch)
647{
648 PMCW *p = &sch->curr_status.pmcw;
649 SCSW *s = &sch->curr_status.scsw;
650 int path;
651
652 /* Path management: In our simple css, we always choose the only path. */
653 path = 0x80;
654
4c293dc6 655 /* Reset values prior to 'issuing the clear signal'. */
df1fe5bb
CH		 656 p->lpum = 0;
657 p->pom = 0xff;
658 s->flags &= ~SCSW_FLAGS_MASK_PNO;
659
660 /* We always 'attempt to issue the clear signal', and we always succeed. */
df1fe5bb
CH		 661 sch->channel_prog = 0x0;
662 sch->last_cmd_valid = false;
663 s->ctrl &= ~SCSW_ACTL_CLEAR_PEND;
664 s->ctrl |= SCSW_STCTL_STATUS_PEND;
665
666 s->dstat = 0;
667 s->cstat = 0;
668 p->lpum = path;
669
670}
671
672static void sch_handle_halt_func(SubchDev *sch)
673{
674
675 PMCW *p = &sch->curr_status.pmcw;
676 SCSW *s = &sch->curr_status.scsw;
2ed982b6 677 hwaddr curr_ccw = sch->channel_prog;
df1fe5bb
CH		 678 int path;
679
680 /* Path management: In our simple css, we always choose the only path. */
681 path = 0x80;
682
683 /* We always 'attempt to issue the halt signal', and we always succeed. */
df1fe5bb
CH		 684 sch->channel_prog = 0x0;
685 sch->last_cmd_valid = false;
686 s->ctrl &= ~SCSW_ACTL_HALT_PEND;
687 s->ctrl |= SCSW_STCTL_STATUS_PEND;
688
689 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) ||
690 !((s->ctrl & SCSW_ACTL_START_PEND) ||
691 (s->ctrl & SCSW_ACTL_SUSP))) {
692 s->dstat = SCSW_DSTAT_DEVICE_END;
693 }
2ed982b6
CH		 694 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) ||
695 (s->ctrl & SCSW_ACTL_SUSP)) {
696 s->cpa = curr_ccw + 8;
697 }
df1fe5bb
CH		 698 s->cstat = 0;
699 p->lpum = path;
700
701}
702
703static void copy_sense_id_to_guest(SenseId *dest, SenseId *src)
704{
705 int i;
706
707 dest->reserved = src->reserved;
708 dest->cu_type = cpu_to_be16(src->cu_type);
709 dest->cu_model = src->cu_model;
710 dest->dev_type = cpu_to_be16(src->dev_type);
711 dest->dev_model = src->dev_model;
712 dest->unused = src->unused;
713 for (i = 0; i < ARRAY_SIZE(dest->ciw); i++) {
714 dest->ciw[i].type = src->ciw[i].type;
715 dest->ciw[i].command = src->ciw[i].command;
716 dest->ciw[i].count = cpu_to_be16(src->ciw[i].count);
717 }
718}
719
a327c921 720static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1)
df1fe5bb 721{
a327c921
CH		 722 CCW0 tmp0;
723 CCW1 tmp1;
df1fe5bb
CH		 724 CCW1 ret;
725
a327c921
CH		 726 if (fmt1) {
727 cpu_physical_memory_read(addr, &tmp1, sizeof(tmp1));
728 ret.cmd_code = tmp1.cmd_code;
729 ret.flags = tmp1.flags;
730 ret.count = be16_to_cpu(tmp1.count);
731 ret.cda = be32_to_cpu(tmp1.cda);
732 } else {
733 cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0));
9f94f84c
DJS		 734 if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) {
735 ret.cmd_code = CCW_CMD_TIC;
736 ret.flags = 0;
737 ret.count = 0;
738 } else {
739 ret.cmd_code = tmp0.cmd_code;
740 ret.flags = tmp0.flags;
741 ret.count = be16_to_cpu(tmp0.count);
fde8206b 742 }
9f94f84c 743 ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16);
a327c921 744 }
df1fe5bb
CH		 745 return ret;
746}
747
ce350f32
CH		 748static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr,
749 bool suspend_allowed)
df1fe5bb
CH		 750{
751 int ret;
752 bool check_len;
753 int len;
754 CCW1 ccw;
755
756 if (!ccw_addr) {
757 return -EIO;
758 }
759
a327c921
CH		 760 /* Translate everything to format-1 ccws - the information is the same. */
761 ccw = copy_ccw_from_guest(ccw_addr, sch->ccw_fmt_1);
df1fe5bb
CH		 762
763 /* Check for invalid command codes. */
764 if ((ccw.cmd_code & 0x0f) == 0) {
765 return -EINVAL;
766 }
767 if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) &&
768 ((ccw.cmd_code & 0xf0) != 0)) {
769 return -EINVAL;
770 }
fa4463e0
CH		 771 if (!sch->ccw_fmt_1 && (ccw.count == 0) &&
772 (ccw.cmd_code != CCW_CMD_TIC)) {
773 return -EINVAL;
774 }
df1fe5bb 775
4e19b57b
CH		 776 /* We don't support MIDA. */
777 if (ccw.flags & CCW_FLAG_MIDA) {
778 return -EINVAL;
779 }
780
df1fe5bb 781 if (ccw.flags & CCW_FLAG_SUSPEND) {
ce350f32 782 return suspend_allowed ? -EINPROGRESS : -EINVAL;
df1fe5bb
CH		 783 }
784
785 check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC));
786
e8601dd5
CH		 787 if (!ccw.cda) {
788 if (sch->ccw_no_data_cnt == 255) {
789 return -EINVAL;
790 }
791 sch->ccw_no_data_cnt++;
792 }
793
df1fe5bb
CH		 794 /* Look at the command. */
795 switch (ccw.cmd_code) {
796 case CCW_CMD_NOOP:
797 /* Nothing to do. */
798 ret = 0;
799 break;
800 case CCW_CMD_BASIC_SENSE:
801 if (check_len) {
802 if (ccw.count != sizeof(sch->sense_data)) {
803 ret = -EINVAL;
804 break;
805 }
806 }
807 len = MIN(ccw.count, sizeof(sch->sense_data));
808 cpu_physical_memory_write(ccw.cda, sch->sense_data, len);
809 sch->curr_status.scsw.count = ccw.count - len;
810 memset(sch->sense_data, 0, sizeof(sch->sense_data));
811 ret = 0;
812 break;
813 case CCW_CMD_SENSE_ID:
814 {
815 SenseId sense_id;
816
817 copy_sense_id_to_guest(&sense_id, &sch->id);
818 /* Sense ID information is device specific. */
819 if (check_len) {
820 if (ccw.count != sizeof(sense_id)) {
821 ret = -EINVAL;
822 break;
823 }
824 }
825 len = MIN(ccw.count, sizeof(sense_id));
826 /*
827 * Only indicate 0xff in the first sense byte if we actually
828 * have enough place to store at least bytes 0-3.
829 */
830 if (len >= 4) {
831 sense_id.reserved = 0xff;
832 } else {
833 sense_id.reserved = 0;
834 }
835 cpu_physical_memory_write(ccw.cda, &sense_id, len);
836 sch->curr_status.scsw.count = ccw.count - len;
837 ret = 0;
838 break;
839 }
840 case CCW_CMD_TIC:
841 if (sch->last_cmd_valid && (sch->last_cmd.cmd_code == CCW_CMD_TIC)) {
842 ret = -EINVAL;
843 break;
844 }
845 if (ccw.flags & (CCW_FLAG_CC | CCW_FLAG_DC)) {
846 ret = -EINVAL;
847 break;
848 }
849 sch->channel_prog = ccw.cda;
850 ret = -EAGAIN;
851 break;
852 default:
853 if (sch->ccw_cb) {
854 /* Handle device specific commands. */
855 ret = sch->ccw_cb(sch, ccw);
856 } else {
8d034a6f 857 ret = -ENOSYS;
df1fe5bb
CH		 858 }
859 break;
860 }
861 sch->last_cmd = ccw;
862 sch->last_cmd_valid = true;
863 if (ret == 0) {
864 if (ccw.flags & CCW_FLAG_CC) {
865 sch->channel_prog += 8;
866 ret = -EAGAIN;
867 }
868 }
869
870 return ret;
871}
872
bab482d7 873static void sch_handle_start_func_virtual(SubchDev *sch, ORB *orb)
df1fe5bb
CH		 874{
875
876 PMCW *p = &sch->curr_status.pmcw;
877 SCSW *s = &sch->curr_status.scsw;
df1fe5bb
CH		 878 int path;
879 int ret;
ce350f32 880 bool suspend_allowed;
df1fe5bb
CH		 881
882 /* Path management: In our simple css, we always choose the only path. */
883 path = 0x80;
884
885 if (!(s->ctrl & SCSW_ACTL_SUSP)) {
727a0424 886 /* Start Function triggered via ssch, i.e. we have an ORB */
6b7741c2
CH		 887 s->cstat = 0;
888 s->dstat = 0;
df1fe5bb 889 /* Look at the orb and try to execute the channel program. */
56bf1a8e 890 assert(orb != NULL); /* resume does not pass an orb */
df1fe5bb
CH		 891 p->intparm = orb->intparm;
892 if (!(orb->lpm & path)) {
893 /* Generate a deferred cc 3 condition. */
894 s->flags |= SCSW_FLAGS_MASK_CC;
895 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
896 s->ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND);
897 return;
898 }
a327c921 899 sch->ccw_fmt_1 = !!(orb->ctrl0 & ORB_CTRL0_MASK_FMT);
485dd690 900 s->flags |= (sch->ccw_fmt_1) ? SCSW_FLAGS_MASK_FMT : 0;
e8601dd5 901 sch->ccw_no_data_cnt = 0;
ce350f32 902 suspend_allowed = !!(orb->ctrl0 & ORB_CTRL0_MASK_SPND);
df1fe5bb 903 } else {
727a0424
SS		 904 /* Start Function resumed via rsch, i.e. we don't have an
905 * ORB */
df1fe5bb 906 s->ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND);
ce350f32
CH		 907 /* The channel program had been suspended before. */
908 suspend_allowed = true;
df1fe5bb
CH		 909 }
910 sch->last_cmd_valid = false;
911 do {
ce350f32 912 ret = css_interpret_ccw(sch, sch->channel_prog, suspend_allowed);
df1fe5bb
CH		 913 switch (ret) {
914 case -EAGAIN:
915 /* ccw chain, continue processing */
916 break;
917 case 0:
918 /* success */
919 s->ctrl &= ~SCSW_ACTL_START_PEND;
920 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
921 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
922 SCSW_STCTL_STATUS_PEND;
923 s->dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END;
2ed982b6 924 s->cpa = sch->channel_prog + 8;
df1fe5bb 925 break;
2dc95b4c
JL		 926 case -EIO:
927 /* I/O errors, status depends on specific devices */
928 break;
8d034a6f 929 case -ENOSYS:
df1fe5bb
CH		 930 /* unsupported command, generate unit check (command reject) */
931 s->ctrl &= ~SCSW_ACTL_START_PEND;
932 s->dstat = SCSW_DSTAT_UNIT_CHECK;
933 /* Set sense bit 0 in ecw0. */
934 sch->sense_data[0] = 0x80;
935 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
936 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
937 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
2ed982b6 938 s->cpa = sch->channel_prog + 8;
df1fe5bb
CH		 939 break;
940 case -EFAULT:
941 /* memory problem, generate channel data check */
942 s->ctrl &= ~SCSW_ACTL_START_PEND;
943 s->cstat = SCSW_CSTAT_DATA_CHECK;
944 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
945 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
946 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
2ed982b6 947 s->cpa = sch->channel_prog + 8;
df1fe5bb
CH		 948 break;
949 case -EBUSY:
950 /* subchannel busy, generate deferred cc 1 */
951 s->flags &= ~SCSW_FLAGS_MASK_CC;
952 s->flags |= (1 << 8);
953 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
954 s->ctrl |= SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
955 break;
8d034a6f 956 case -EINPROGRESS:
df1fe5bb
CH		 957 /* channel program has been suspended */
958 s->ctrl &= ~SCSW_ACTL_START_PEND;
959 s->ctrl |= SCSW_ACTL_SUSP;
960 break;
961 default:
962 /* error, generate channel program check */
963 s->ctrl &= ~SCSW_ACTL_START_PEND;
964 s->cstat = SCSW_CSTAT_PROG_CHECK;
965 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
966 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
967 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
2ed982b6 968 s->cpa = sch->channel_prog + 8;
df1fe5bb
CH		 969 break;
970 }
971 } while (ret == -EAGAIN);
972
973}
974
bab482d7
XFR		 975static int sch_handle_start_func_passthrough(SubchDev *sch, ORB *orb)
976{
977
978 PMCW *p = &sch->curr_status.pmcw;
979 SCSW *s = &sch->curr_status.scsw;
980 int ret;
981
982 if (!(s->ctrl & SCSW_ACTL_SUSP)) {
983 assert(orb != NULL);
984 p->intparm = orb->intparm;
985 }
986
987 /*
988 * Only support prefetch enable mode.
989 * Only support 64bit addressing idal.
990 */
991 if (!(orb->ctrl0 & ORB_CTRL0_MASK_PFCH) ||
992 !(orb->ctrl0 & ORB_CTRL0_MASK_C64)) {
993 return -EINVAL;
994 }
995
996 ret = s390_ccw_cmd_request(orb, s, sch->driver_data);
997 switch (ret) {
998 /* Currently we don't update control block and just return the cc code. */
999 case 0:
1000 break;
1001 case -EBUSY:
1002 break;
1003 case -ENODEV:
1004 break;
1005 case -EACCES:
1006 /* Let's reflect an inaccessible host device by cc 3. */
1007 ret = -ENODEV;
1008 break;
1009 default:
1010 /*
1011 * All other return codes will trigger a program check,
1012 * or set cc to 1.
1013 */
1014 break;
1015 };
1016
1017 return ret;
1018}
1019
df1fe5bb
CH		 1020/*
1021 * On real machines, this would run asynchronously to the main vcpus.
1022 * We might want to make some parts of the ssch handling (interpreting
1023 * read/writes) asynchronous later on if we start supporting more than
1024 * our current very simple devices.
1025 */
bab482d7 1026int do_subchannel_work_virtual(SubchDev *sch, ORB *orb)
df1fe5bb
CH		 1027{
1028
1029 SCSW *s = &sch->curr_status.scsw;
1030
1031 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) {
1032 sch_handle_clear_func(sch);
1033 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) {
1034 sch_handle_halt_func(sch);
1035 } else if (s->ctrl & SCSW_FCTL_START_FUNC) {
727a0424 1036 /* Triggered by both ssch and rsch. */
bab482d7 1037 sch_handle_start_func_virtual(sch, orb);
df1fe5bb
CH		 1038 } else {
1039 /* Cannot happen. */
bab482d7 1040 return 0;
df1fe5bb
CH		 1041 }
1042 css_inject_io_interrupt(sch);
bab482d7
XFR		 1043 return 0;
1044}
1045
1046int do_subchannel_work_passthrough(SubchDev *sch, ORB *orb)
1047{
1048 int ret;
1049 SCSW *s = &sch->curr_status.scsw;
1050
1051 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) {
1052 /* TODO: Clear handling */
1053 sch_handle_clear_func(sch);
1054 ret = 0;
1055 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) {
1056 /* TODO: Halt handling */
1057 sch_handle_halt_func(sch);
1058 ret = 0;
1059 } else if (s->ctrl & SCSW_FCTL_START_FUNC) {
1060 ret = sch_handle_start_func_passthrough(sch, orb);
1061 } else {
1062 /* Cannot happen. */
1063 return -ENODEV;
1064 }
1065
1066 return ret;
1067}
1068
1069static int do_subchannel_work(SubchDev *sch, ORB *orb)
1070{
1071 if (sch->do_subchannel_work) {
1072 return sch->do_subchannel_work(sch, orb);
1073 } else {
1074 return -EINVAL;
1075 }
df1fe5bb
CH		 1076}
1077
1078static void copy_pmcw_to_guest(PMCW *dest, const PMCW *src)
1079{
1080 int i;
1081
1082 dest->intparm = cpu_to_be32(src->intparm);
1083 dest->flags = cpu_to_be16(src->flags);
1084 dest->devno = cpu_to_be16(src->devno);
1085 dest->lpm = src->lpm;
1086 dest->pnom = src->pnom;
1087 dest->lpum = src->lpum;
1088 dest->pim = src->pim;
1089 dest->mbi = cpu_to_be16(src->mbi);
1090 dest->pom = src->pom;
1091 dest->pam = src->pam;
1092 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) {
1093 dest->chpid[i] = src->chpid[i];
1094 }
1095 dest->chars = cpu_to_be32(src->chars);
1096}
1097
8ca2b376 1098void copy_scsw_to_guest(SCSW *dest, const SCSW *src)
df1fe5bb
CH		 1099{
1100 dest->flags = cpu_to_be16(src->flags);
1101 dest->ctrl = cpu_to_be16(src->ctrl);
1102 dest->cpa = cpu_to_be32(src->cpa);
1103 dest->dstat = src->dstat;
1104 dest->cstat = src->cstat;
1105 dest->count = cpu_to_be16(src->count);
1106}
1107
1108static void copy_schib_to_guest(SCHIB *dest, const SCHIB *src)
1109{
1110 int i;
1111
1112 copy_pmcw_to_guest(&dest->pmcw, &src->pmcw);
1113 copy_scsw_to_guest(&dest->scsw, &src->scsw);
1114 dest->mba = cpu_to_be64(src->mba);
1115 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) {
1116 dest->mda[i] = src->mda[i];
1117 }
1118}
1119
1120int css_do_stsch(SubchDev *sch, SCHIB *schib)
1121{
1122 /* Use current status. */
1123 copy_schib_to_guest(schib, &sch->curr_status);
1124 return 0;
1125}
1126
1127static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src)
1128{
1129 int i;
1130
1131 dest->intparm = be32_to_cpu(src->intparm);
1132 dest->flags = be16_to_cpu(src->flags);
1133 dest->devno = be16_to_cpu(src->devno);
1134 dest->lpm = src->lpm;
1135 dest->pnom = src->pnom;
1136 dest->lpum = src->lpum;
1137 dest->pim = src->pim;
1138 dest->mbi = be16_to_cpu(src->mbi);
1139 dest->pom = src->pom;
1140 dest->pam = src->pam;
1141 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) {
1142 dest->chpid[i] = src->chpid[i];
1143 }
1144 dest->chars = be32_to_cpu(src->chars);
1145}
1146
1147static void copy_scsw_from_guest(SCSW *dest, const SCSW *src)
1148{
1149 dest->flags = be16_to_cpu(src->flags);
1150 dest->ctrl = be16_to_cpu(src->ctrl);
1151 dest->cpa = be32_to_cpu(src->cpa);
1152 dest->dstat = src->dstat;
1153 dest->cstat = src->cstat;
1154 dest->count = be16_to_cpu(src->count);
1155}
1156
1157static void copy_schib_from_guest(SCHIB *dest, const SCHIB *src)
1158{
1159 int i;
1160
1161 copy_pmcw_from_guest(&dest->pmcw, &src->pmcw);
1162 copy_scsw_from_guest(&dest->scsw, &src->scsw);
1163 dest->mba = be64_to_cpu(src->mba);
1164 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) {
1165 dest->mda[i] = src->mda[i];
1166 }
1167}
1168
bffd09cd 1169int css_do_msch(SubchDev *sch, const SCHIB *orig_schib)
df1fe5bb
CH		 1170{
1171 SCSW *s = &sch->curr_status.scsw;
1172 PMCW *p = &sch->curr_status.pmcw;
62ac4a52 1173 uint16_t oldflags;
df1fe5bb
CH		 1174 int ret;
1175 SCHIB schib;
1176
1177 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_DNV)) {
1178 ret = 0;
1179 goto out;
1180 }
1181
1182 if (s->ctrl & SCSW_STCTL_STATUS_PEND) {
1183 ret = -EINPROGRESS;
1184 goto out;
1185 }
1186
1187 if (s->ctrl &
1188 (SCSW_FCTL_START_FUNC|SCSW_FCTL_HALT_FUNC|SCSW_FCTL_CLEAR_FUNC)) {
1189 ret = -EBUSY;
1190 goto out;
1191 }
1192
1193 copy_schib_from_guest(&schib, orig_schib);
1194 /* Only update the program-modifiable fields. */
1195 p->intparm = schib.pmcw.intparm;
62ac4a52 1196 oldflags = p->flags;
df1fe5bb
CH		 1197 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
1198 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
1199 PMCW_FLAGS_MASK_MP);
1200 p->flags |= schib.pmcw.flags &
1201 (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
1202 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
1203 PMCW_FLAGS_MASK_MP);
1204 p->lpm = schib.pmcw.lpm;
1205 p->mbi = schib.pmcw.mbi;
1206 p->pom = schib.pmcw.pom;
1207 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE);
1208 p->chars |= schib.pmcw.chars &
1209 (PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE);
1210 sch->curr_status.mba = schib.mba;
1211
62ac4a52
TH		 1212 /* Has the channel been disabled? */
1213 if (sch->disable_cb && (oldflags & PMCW_FLAGS_MASK_ENA) != 0
1214 && (p->flags & PMCW_FLAGS_MASK_ENA) == 0) {
1215 sch->disable_cb(sch);
1216 }
1217
df1fe5bb
CH		 1218 ret = 0;
1219
1220out:
1221 return ret;
1222}
1223
1224int css_do_xsch(SubchDev *sch)
1225{
1226 SCSW *s = &sch->curr_status.scsw;
1227 PMCW *p = &sch->curr_status.pmcw;
1228 int ret;
1229
c679e74d 1230 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
df1fe5bb
CH		 1231 ret = -ENODEV;
1232 goto out;
1233 }
1234
1235 if (!(s->ctrl & SCSW_CTRL_MASK_FCTL) ||
1236 ((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) ||
1237 (!(s->ctrl &
1238 (SCSW_ACTL_RESUME_PEND | SCSW_ACTL_START_PEND | SCSW_ACTL_SUSP))) ||
1239 (s->ctrl & SCSW_ACTL_SUBCH_ACTIVE)) {
1240 ret = -EINPROGRESS;
1241 goto out;
1242 }
1243
1244 if (s->ctrl & SCSW_CTRL_MASK_STCTL) {
1245 ret = -EBUSY;
1246 goto out;
1247 }
1248
1249 /* Cancel the current operation. */
1250 s->ctrl &= ~(SCSW_FCTL_START_FUNC |
1251 SCSW_ACTL_RESUME_PEND |
1252 SCSW_ACTL_START_PEND |
1253 SCSW_ACTL_SUSP);
1254 sch->channel_prog = 0x0;
1255 sch->last_cmd_valid = false;
df1fe5bb
CH		 1256 s->dstat = 0;
1257 s->cstat = 0;
1258 ret = 0;
1259
1260out:
1261 return ret;
1262}
1263
1264int css_do_csch(SubchDev *sch)
1265{
1266 SCSW *s = &sch->curr_status.scsw;
1267 PMCW *p = &sch->curr_status.pmcw;
1268 int ret;
1269
c679e74d 1270 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
df1fe5bb
CH		 1271 ret = -ENODEV;
1272 goto out;
1273 }
1274
1275 /* Trigger the clear function. */
1276 s->ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL);
4c6bf79a 1277 s->ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_ACTL_CLEAR_PEND;
df1fe5bb 1278
56bf1a8e 1279 do_subchannel_work(sch, NULL);
df1fe5bb
CH		 1280 ret = 0;
1281
1282out:
1283 return ret;
1284}
1285
1286int css_do_hsch(SubchDev *sch)
1287{
1288 SCSW *s = &sch->curr_status.scsw;
1289 PMCW *p = &sch->curr_status.pmcw;
1290 int ret;
1291
c679e74d 1292 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
df1fe5bb
CH		 1293 ret = -ENODEV;
1294 goto out;
1295 }
1296
1297 if (((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_STATUS_PEND) ||
1298 (s->ctrl & (SCSW_STCTL_PRIMARY |
1299 SCSW_STCTL_SECONDARY |
1300 SCSW_STCTL_ALERT))) {
1301 ret = -EINPROGRESS;
1302 goto out;
1303 }
1304
1305 if (s->ctrl & (SCSW_FCTL_HALT_FUNC | SCSW_FCTL_CLEAR_FUNC)) {
1306 ret = -EBUSY;
1307 goto out;
1308 }
1309
1310 /* Trigger the halt function. */
1311 s->ctrl |= SCSW_FCTL_HALT_FUNC;
1312 s->ctrl &= ~SCSW_FCTL_START_FUNC;
1313 if (((s->ctrl & SCSW_CTRL_MASK_ACTL) ==
1314 (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) &&
1315 ((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_INTERMEDIATE)) {
1316 s->ctrl &= ~SCSW_STCTL_STATUS_PEND;
1317 }
1318 s->ctrl |= SCSW_ACTL_HALT_PEND;
1319
56bf1a8e 1320 do_subchannel_work(sch, NULL);
df1fe5bb
CH		 1321 ret = 0;
1322
1323out:
1324 return ret;
1325}
1326
1327static void css_update_chnmon(SubchDev *sch)
1328{
1329 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_MME)) {
1330 /* Not active. */
1331 return;
1332 }
1333 /* The counter is conveniently located at the beginning of the struct. */
1334 if (sch->curr_status.pmcw.chars & PMCW_CHARS_MASK_MBFC) {
1335 /* Format 1, per-subchannel area. */
1336 uint32_t count;
1337
42874d3a
PM		 1338 count = address_space_ldl(&address_space_memory,
1339 sch->curr_status.mba,
1340 MEMTXATTRS_UNSPECIFIED,
1341 NULL);
df1fe5bb 1342 count++;
42874d3a
PM		 1343 address_space_stl(&address_space_memory, sch->curr_status.mba, count,
1344 MEMTXATTRS_UNSPECIFIED, NULL);
df1fe5bb
CH		 1345 } else {
1346 /* Format 0, global area. */
1347 uint32_t offset;
1348 uint16_t count;
1349
1350 offset = sch->curr_status.pmcw.mbi << 5;
42874d3a 1351 count = address_space_lduw(&address_space_memory,
562f5e0b 1352 channel_subsys.chnmon_area + offset,
42874d3a
PM		 1353 MEMTXATTRS_UNSPECIFIED,
1354 NULL);
df1fe5bb 1355 count++;
42874d3a 1356 address_space_stw(&address_space_memory,
562f5e0b 1357 channel_subsys.chnmon_area + offset, count,
42874d3a 1358 MEMTXATTRS_UNSPECIFIED, NULL);
df1fe5bb
CH		 1359 }
1360}
1361
1362int css_do_ssch(SubchDev *sch, ORB *orb)
1363{
1364 SCSW *s = &sch->curr_status.scsw;
1365 PMCW *p = &sch->curr_status.pmcw;
1366 int ret;
1367
c679e74d 1368 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
df1fe5bb
CH		 1369 ret = -ENODEV;
1370 goto out;
1371 }
1372
1373 if (s->ctrl & SCSW_STCTL_STATUS_PEND) {
1374 ret = -EINPROGRESS;
1375 goto out;
1376 }
1377
1378 if (s->ctrl & (SCSW_FCTL_START_FUNC |
1379 SCSW_FCTL_HALT_FUNC |
1380 SCSW_FCTL_CLEAR_FUNC)) {
1381 ret = -EBUSY;
1382 goto out;
1383 }
1384
1385 /* If monitoring is active, update counter. */
562f5e0b 1386 if (channel_subsys.chnmon_active) {
df1fe5bb
CH		 1387 css_update_chnmon(sch);
1388 }
df1fe5bb
CH		 1389 sch->channel_prog = orb->cpa;
1390 /* Trigger the start function. */
1391 s->ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND);
1392 s->flags &= ~SCSW_FLAGS_MASK_PNO;
1393
bab482d7 1394 ret = do_subchannel_work(sch, orb);
df1fe5bb
CH		 1395
1396out:
1397 return ret;
1398}
1399
b7b6348a
TH		 1400static void copy_irb_to_guest(IRB *dest, const IRB *src, PMCW *pmcw,
1401 int *irb_len)
df1fe5bb
CH		 1402{
1403 int i;
f068d320
CH		 1404 uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL;
1405 uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL;
df1fe5bb
CH		 1406
1407 copy_scsw_to_guest(&dest->scsw, &src->scsw);
1408
1409 for (i = 0; i < ARRAY_SIZE(dest->esw); i++) {
1410 dest->esw[i] = cpu_to_be32(src->esw[i]);
1411 }
1412 for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) {
1413 dest->ecw[i] = cpu_to_be32(src->ecw[i]);
1414 }
b7b6348a
TH		 1415 *irb_len = sizeof(*dest) - sizeof(dest->emw);
1416
f068d320
CH		 1417 /* extended measurements enabled? */
1418 if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) ||
1419 !(pmcw->flags & PMCW_FLAGS_MASK_TF) ||
1420 !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) {
1421 return;
1422 }
1423 /* extended measurements pending? */
1424 if (!(stctl & SCSW_STCTL_STATUS_PEND)) {
1425 return;
1426 }
1427 if ((stctl & SCSW_STCTL_PRIMARY) ||
1428 (stctl == SCSW_STCTL_SECONDARY) ||
1429 ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) {
1430 for (i = 0; i < ARRAY_SIZE(dest->emw); i++) {
1431 dest->emw[i] = cpu_to_be32(src->emw[i]);
1432 }
df1fe5bb 1433 }
b7b6348a 1434 *irb_len = sizeof(*dest);
df1fe5bb
CH		 1435}
1436
b7b6348a 1437int css_do_tsch_get_irb(SubchDev *sch, IRB *target_irb, int *irb_len)
df1fe5bb
CH		 1438{
1439 SCSW *s = &sch->curr_status.scsw;
1440 PMCW *p = &sch->curr_status.pmcw;
1441 uint16_t stctl;
df1fe5bb 1442 IRB irb;
df1fe5bb 1443
c679e74d 1444 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
b7b6348a 1445 return 3;
df1fe5bb
CH		 1446 }
1447
1448 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL;
df1fe5bb
CH		 1449
1450 /* Prepare the irb for the guest. */
1451 memset(&irb, 0, sizeof(IRB));
1452
1453 /* Copy scsw from current status. */
1454 memcpy(&irb.scsw, s, sizeof(SCSW));
1455 if (stctl & SCSW_STCTL_STATUS_PEND) {
1456 if (s->cstat & (SCSW_CSTAT_DATA_CHECK |
1457 SCSW_CSTAT_CHN_CTRL_CHK |
1458 SCSW_CSTAT_INTF_CTRL_CHK)) {
1459 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF;
1460 irb.esw[0] = 0x04804000;
1461 } else {
1462 irb.esw[0] = 0x00800000;
1463 }
1464 /* If a unit check is pending, copy sense data. */
1465 if ((s->dstat & SCSW_DSTAT_UNIT_CHECK) &&
1466 (p->chars & PMCW_CHARS_MASK_CSENSE)) {
b498484e
CH		 1467 int i;
1468
df1fe5bb 1469 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL;
b498484e 1470 /* Attention: sense_data is already BE! */
df1fe5bb 1471 memcpy(irb.ecw, sch->sense_data, sizeof(sch->sense_data));
b498484e
CH		 1472 for (i = 0; i < ARRAY_SIZE(irb.ecw); i++) {
1473 irb.ecw[i] = be32_to_cpu(irb.ecw[i]);
1474 }
8312976e 1475 irb.esw[1] = 0x01000000 | (sizeof(sch->sense_data) << 8);
df1fe5bb
CH		 1476 }
1477 }
1478 /* Store the irb to the guest. */
b7b6348a
TH		 1479 copy_irb_to_guest(target_irb, &irb, p, irb_len);
1480
1481 return ((stctl & SCSW_STCTL_STATUS_PEND) == 0);
1482}
1483
1484void css_do_tsch_update_subch(SubchDev *sch)
1485{
1486 SCSW *s = &sch->curr_status.scsw;
1487 PMCW *p = &sch->curr_status.pmcw;
1488 uint16_t stctl;
1489 uint16_t fctl;
1490 uint16_t actl;
1491
1492 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL;
1493 fctl = s->ctrl & SCSW_CTRL_MASK_FCTL;
1494 actl = s->ctrl & SCSW_CTRL_MASK_ACTL;
df1fe5bb
CH		 1495
1496 /* Clear conditions on subchannel, if applicable. */
1497 if (stctl & SCSW_STCTL_STATUS_PEND) {
1498 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
1499 if ((stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) ||
1500 ((fctl & SCSW_FCTL_HALT_FUNC) &&
1501 (actl & SCSW_ACTL_SUSP))) {
1502 s->ctrl &= ~SCSW_CTRL_MASK_FCTL;
1503 }
1504 if (stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) {
1505 s->flags &= ~SCSW_FLAGS_MASK_PNO;
1506 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND |
1507 SCSW_ACTL_START_PEND |
1508 SCSW_ACTL_HALT_PEND |
1509 SCSW_ACTL_CLEAR_PEND |
1510 SCSW_ACTL_SUSP);
1511 } else {
1512 if ((actl & SCSW_ACTL_SUSP) &&
1513 (fctl & SCSW_FCTL_START_FUNC)) {
1514 s->flags &= ~SCSW_FLAGS_MASK_PNO;
1515 if (fctl & SCSW_FCTL_HALT_FUNC) {
1516 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND |
1517 SCSW_ACTL_START_PEND |
1518 SCSW_ACTL_HALT_PEND |
1519 SCSW_ACTL_CLEAR_PEND |
1520 SCSW_ACTL_SUSP);
1521 } else {
1522 s->ctrl &= ~SCSW_ACTL_RESUME_PEND;
1523 }
1524 }
1525 }
1526 /* Clear pending sense data. */
1527 if (p->chars & PMCW_CHARS_MASK_CSENSE) {
1528 memset(sch->sense_data, 0 , sizeof(sch->sense_data));
1529 }
1530 }
df1fe5bb
CH		 1531}
1532
1533static void copy_crw_to_guest(CRW *dest, const CRW *src)
1534{
1535 dest->flags = cpu_to_be16(src->flags);
1536 dest->rsid = cpu_to_be16(src->rsid);
1537}
1538
1539int css_do_stcrw(CRW *crw)
1540{
1541 CrwContainer *crw_cont;
1542 int ret;
1543
562f5e0b 1544 crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws);
df1fe5bb 1545 if (crw_cont) {
562f5e0b 1546 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling);
df1fe5bb
CH		 1547 copy_crw_to_guest(crw, &crw_cont->crw);
1548 g_free(crw_cont);
1549 ret = 0;
1550 } else {
1551 /* List was empty, turn crw machine checks on again. */
1552 memset(crw, 0, sizeof(*crw));
562f5e0b 1553 channel_subsys.do_crw_mchk = true;
df1fe5bb
CH		 1554 ret = 1;
1555 }
1556
1557 return ret;
1558}
1559
7f74f0aa
TH		 1560static void copy_crw_from_guest(CRW *dest, const CRW *src)
1561{
1562 dest->flags = be16_to_cpu(src->flags);
1563 dest->rsid = be16_to_cpu(src->rsid);
1564}
1565
1566void css_undo_stcrw(CRW *crw)
1567{
1568 CrwContainer *crw_cont;
1569
1570 crw_cont = g_try_malloc0(sizeof(CrwContainer));
1571 if (!crw_cont) {
562f5e0b 1572 channel_subsys.crws_lost = true;
7f74f0aa
TH		 1573 return;
1574 }
1575 copy_crw_from_guest(&crw_cont->crw, crw);
1576
562f5e0b 1577 QTAILQ_INSERT_HEAD(&channel_subsys.pending_crws, crw_cont, sibling);
7f74f0aa
TH		 1578}
1579
50c8d9bf 1580int css_do_tpi(IOIntCode *int_code, int lowcore)
df1fe5bb
CH		 1581{
1582 /* No pending interrupts for !KVM. */
1583 return 0;
1584 }
1585
1586int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
1587 int rfmt, void *buf)
1588{
1589 int i, desc_size;
1590 uint32_t words[8];
1591 uint32_t chpid_type_word;
1592 CssImage *css;
1593
1594 if (!m && !cssid) {
562f5e0b 1595 css = channel_subsys.css[channel_subsys.default_cssid];
df1fe5bb 1596 } else {
562f5e0b 1597 css = channel_subsys.css[cssid];
df1fe5bb
CH		 1598 }
1599 if (!css) {
1600 return 0;
1601 }
1602 desc_size = 0;
1603 for (i = f_chpid; i <= l_chpid; i++) {
1604 if (css->chpids[i].in_use) {
1605 chpid_type_word = 0x80000000 | (css->chpids[i].type << 8) | i;
1606 if (rfmt == 0) {
1607 words[0] = cpu_to_be32(chpid_type_word);
1608 words[1] = 0;
1609 memcpy(buf + desc_size, words, 8);
1610 desc_size += 8;
1611 } else if (rfmt == 1) {
1612 words[0] = cpu_to_be32(chpid_type_word);
1613 words[1] = 0;
1614 words[2] = 0;
1615 words[3] = 0;
1616 words[4] = 0;
1617 words[5] = 0;
1618 words[6] = 0;
1619 words[7] = 0;
1620 memcpy(buf + desc_size, words, 32);
1621 desc_size += 32;
1622 }
1623 }
1624 }
1625 return desc_size;
1626}
1627
1628void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
1629{
1630 /* dct is currently ignored (not really meaningful for our devices) */
1631 /* TODO: Don't ignore mbk. */
562f5e0b 1632 if (update && !channel_subsys.chnmon_active) {
df1fe5bb 1633 /* Enable measuring. */
562f5e0b
EH		 1634 channel_subsys.chnmon_area = mbo;
1635 channel_subsys.chnmon_active = true;
df1fe5bb 1636 }
562f5e0b 1637 if (!update && channel_subsys.chnmon_active) {
df1fe5bb 1638 /* Disable measuring. */
562f5e0b
EH		 1639 channel_subsys.chnmon_area = 0;
1640 channel_subsys.chnmon_active = false;
df1fe5bb
CH		 1641 }
1642}
1643
1644int css_do_rsch(SubchDev *sch)
1645{
1646 SCSW *s = &sch->curr_status.scsw;
1647 PMCW *p = &sch->curr_status.pmcw;
1648 int ret;
1649
c679e74d 1650 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
df1fe5bb
CH		 1651 ret = -ENODEV;
1652 goto out;
1653 }
1654
1655 if (s->ctrl & SCSW_STCTL_STATUS_PEND) {
1656 ret = -EINPROGRESS;
1657 goto out;
1658 }
1659
1660 if (((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) ||
1661 (s->ctrl & SCSW_ACTL_RESUME_PEND) ||
1662 (!(s->ctrl & SCSW_ACTL_SUSP))) {
1663 ret = -EINVAL;
1664 goto out;
1665 }
1666
1667 /* If monitoring is active, update counter. */
562f5e0b 1668 if (channel_subsys.chnmon_active) {
df1fe5bb
CH		 1669 css_update_chnmon(sch);
1670 }
1671
1672 s->ctrl |= SCSW_ACTL_RESUME_PEND;
56bf1a8e 1673 do_subchannel_work(sch, NULL);
df1fe5bb
CH		 1674 ret = 0;
1675
1676out:
1677 return ret;
1678}
1679
1680int css_do_rchp(uint8_t cssid, uint8_t chpid)
1681{
1682 uint8_t real_cssid;
1683
562f5e0b 1684 if (cssid > channel_subsys.max_cssid) {
df1fe5bb
CH		 1685 return -EINVAL;
1686 }
562f5e0b
EH		 1687 if (channel_subsys.max_cssid == 0) {
1688 real_cssid = channel_subsys.default_cssid;
df1fe5bb
CH		 1689 } else {
1690 real_cssid = cssid;
1691 }
562f5e0b 1692 if (!channel_subsys.css[real_cssid]) {
df1fe5bb
CH		 1693 return -EINVAL;
1694 }
1695
562f5e0b 1696 if (!channel_subsys.css[real_cssid]->chpids[chpid].in_use) {
df1fe5bb
CH		 1697 return -ENODEV;
1698 }
1699
562f5e0b 1700 if (!channel_subsys.css[real_cssid]->chpids[chpid].is_virtual) {
df1fe5bb
CH		 1701 fprintf(stderr,
1702 "rchp unsupported for non-virtual chpid %x.%02x!\n",
1703 real_cssid, chpid);
1704 return -ENODEV;
1705 }
1706
1707 /* We don't really use a channel path, so we're done here. */
1708 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT,
562f5e0b
EH		 1709 channel_subsys.max_cssid > 0 ? 1 : 0, chpid);
1710 if (channel_subsys.max_cssid > 0) {
df1fe5bb
CH		 1711 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 0, real_cssid << 8);
1712 }
1713 return 0;
1714}
1715
38dd7cc7 1716bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid)
df1fe5bb
CH		 1717{
1718 SubchSet *set;
38dd7cc7 1719 uint8_t real_cssid;
df1fe5bb 1720
562f5e0b 1721 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid;
882b3b97 1722 if (ssid > MAX_SSID ||
562f5e0b
EH		 1723 !channel_subsys.css[real_cssid] ||
1724 !channel_subsys.css[real_cssid]->sch_set[ssid]) {
df1fe5bb
CH		 1725 return true;
1726 }
562f5e0b 1727 set = channel_subsys.css[real_cssid]->sch_set[ssid];
df1fe5bb
CH		 1728 return schid > find_last_bit(set->schids_used,
1729 (MAX_SCHID + 1) / sizeof(unsigned long));
1730}
1731
6c15e9bf
JL		 1732unsigned int css_find_free_chpid(uint8_t cssid)
1733{
1734 CssImage *css = channel_subsys.css[cssid];
1735 unsigned int chpid;
1736
1737 if (!css) {
1738 return MAX_CHPID + 1;
1739 }
1740
1741 for (chpid = 0; chpid <= MAX_CHPID; chpid++) {
1742 /* skip reserved chpid */
1743 if (chpid == VIRTIO_CCW_CHPID) {
1744 continue;
1745 }
1746 if (!css->chpids[chpid].in_use) {
1747 return chpid;
1748 }
1749 }
1750 return MAX_CHPID + 1;
1751}
1752
8f3cf012
XFR		 1753static int css_add_chpid(uint8_t cssid, uint8_t chpid, uint8_t type,
1754 bool is_virt)
df1fe5bb
CH		 1755{
1756 CssImage *css;
1757
1758 trace_css_chpid_add(cssid, chpid, type);
562f5e0b 1759 css = channel_subsys.css[cssid];
df1fe5bb
CH		 1760 if (!css) {
1761 return -EINVAL;
1762 }
1763 if (css->chpids[chpid].in_use) {
1764 return -EEXIST;
1765 }
1766 css->chpids[chpid].in_use = 1;
1767 css->chpids[chpid].type = type;
8f3cf012 1768 css->chpids[chpid].is_virtual = is_virt;
df1fe5bb
CH		 1769
1770 css_generate_chp_crws(cssid, chpid);
1771
1772 return 0;
1773}
1774
1775void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type)
1776{
1777 PMCW *p = &sch->curr_status.pmcw;
1778 SCSW *s = &sch->curr_status.scsw;
1779 int i;
562f5e0b 1780 CssImage *css = channel_subsys.css[sch->cssid];
df1fe5bb
CH		 1781
1782 assert(css != NULL);
1783 memset(p, 0, sizeof(PMCW));
1784 p->flags |= PMCW_FLAGS_MASK_DNV;
1785 p->devno = sch->devno;
1786 /* single path */
1787 p->pim = 0x80;
1788 p->pom = 0xff;
1789 p->pam = 0x80;
1790 p->chpid[0] = chpid;
1791 if (!css->chpids[chpid].in_use) {
8f3cf012 1792 css_add_chpid(sch->cssid, chpid, type, true);
df1fe5bb
CH		 1793 }
1794
1795 memset(s, 0, sizeof(SCSW));
1796 sch->curr_status.mba = 0;
1797 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) {
1798 sch->curr_status.mda[i] = 0;
1799 }
1800}
1801
1802SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid)
1803{
1804 uint8_t real_cssid;
1805
562f5e0b 1806 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid;
df1fe5bb 1807
562f5e0b 1808 if (!channel_subsys.css[real_cssid]) {
df1fe5bb
CH		 1809 return NULL;
1810 }
1811
562f5e0b 1812 if (!channel_subsys.css[real_cssid]->sch_set[ssid]) {
df1fe5bb
CH		 1813 return NULL;
1814 }
1815
562f5e0b 1816 return channel_subsys.css[real_cssid]->sch_set[ssid]->sch[schid];
df1fe5bb
CH		 1817}
1818
cf249935
SS		 1819/**
1820 * Return free device number in subchannel set.
1821 *
1822 * Return index of the first free device number in the subchannel set
1823 * identified by @p cssid and @p ssid, beginning the search at @p
1824 * start and wrapping around at MAX_DEVNO. Return a value exceeding
1825 * MAX_SCHID if there are no free device numbers in the subchannel
1826 * set.
1827 */
1828static uint32_t css_find_free_devno(uint8_t cssid, uint8_t ssid,
1829 uint16_t start)
1830{
1831 uint32_t round;
1832
1833 for (round = 0; round <= MAX_DEVNO; round++) {
1834 uint16_t devno = (start + round) % MAX_DEVNO;
1835
1836 if (!css_devno_used(cssid, ssid, devno)) {
1837 return devno;
1838 }
1839 }
1840 return MAX_DEVNO + 1;
1841}
1842
1843/**
1844 * Return first free subchannel (id) in subchannel set.
1845 *
1846 * Return index of the first free subchannel in the subchannel set
1847 * identified by @p cssid and @p ssid, if there is any. Return a value
1848 * exceeding MAX_SCHID if there are no free subchannels in the
1849 * subchannel set.
1850 */
1851static uint32_t css_find_free_subch(uint8_t cssid, uint8_t ssid)
1852{
1853 uint32_t schid;
1854
1855 for (schid = 0; schid <= MAX_SCHID; schid++) {
1856 if (!css_find_subch(1, cssid, ssid, schid)) {
1857 return schid;
1858 }
1859 }
1860 return MAX_SCHID + 1;
1861}
1862
1863/**
1864 * Return first free subchannel (id) in subchannel set for a device number
1865 *
1866 * Verify the device number @p devno is not used yet in the subchannel
1867 * set identified by @p cssid and @p ssid. Set @p schid to the index
1868 * of the first free subchannel in the subchannel set, if there is
1869 * any. Return true if everything succeeded and false otherwise.
1870 */
1871static bool css_find_free_subch_for_devno(uint8_t cssid, uint8_t ssid,
1872 uint16_t devno, uint16_t *schid,
1873 Error **errp)
1874{
1875 uint32_t free_schid;
1876
1877 assert(schid);
1878 if (css_devno_used(cssid, ssid, devno)) {
1879 error_setg(errp, "Device %x.%x.%04x already exists",
1880 cssid, ssid, devno);
1881 return false;
1882 }
1883 free_schid = css_find_free_subch(cssid, ssid);
1884 if (free_schid > MAX_SCHID) {
1885 error_setg(errp, "No free subchannel found for %x.%x.%04x",
1886 cssid, ssid, devno);
1887 return false;
1888 }
1889 *schid = free_schid;
1890 return true;
1891}
1892
1893/**
1894 * Return first free subchannel (id) and device number
1895 *
1896 * Locate the first free subchannel and first free device number in
1897 * any of the subchannel sets of the channel subsystem identified by
1898 * @p cssid. Return false if no free subchannel / device number could
1899 * be found. Otherwise set @p ssid, @p devno and @p schid to identify
1900 * the available subchannel and device number and return true.
1901 *
1902 * May modify @p ssid, @p devno and / or @p schid even if no free
1903 * subchannel / device number could be found.
1904 */
1905static bool css_find_free_subch_and_devno(uint8_t cssid, uint8_t *ssid,
1906 uint16_t *devno, uint16_t *schid,
1907 Error **errp)
1908{
1909 uint32_t free_schid, free_devno;
1910
1911 assert(ssid && devno && schid);
1912 for (*ssid = 0; *ssid <= MAX_SSID; (*ssid)++) {
1913 free_schid = css_find_free_subch(cssid, *ssid);
1914 if (free_schid > MAX_SCHID) {
1915 continue;
1916 }
1917 free_devno = css_find_free_devno(cssid, *ssid, free_schid);
1918 if (free_devno > MAX_DEVNO) {
1919 continue;
1920 }
1921 *schid = free_schid;
1922 *devno = free_devno;
1923 return true;
1924 }
1925 error_setg(errp, "Virtual channel subsystem is full!");
1926 return false;
1927}
1928
df1fe5bb
CH		 1929bool css_subch_visible(SubchDev *sch)
1930{
562f5e0b 1931 if (sch->ssid > channel_subsys.max_ssid) {
df1fe5bb
CH		 1932 return false;
1933 }
1934
562f5e0b
EH		 1935 if (sch->cssid != channel_subsys.default_cssid) {
1936 return (channel_subsys.max_cssid > 0);
df1fe5bb
CH		 1937 }
1938
1939 return true;
1940}
1941
1942bool css_present(uint8_t cssid)
1943{
562f5e0b 1944 return (channel_subsys.css[cssid] != NULL);
df1fe5bb
CH		 1945}
1946
1947bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno)
1948{
562f5e0b 1949 if (!channel_subsys.css[cssid]) {
df1fe5bb
CH		 1950 return false;
1951 }
562f5e0b 1952 if (!channel_subsys.css[cssid]->sch_set[ssid]) {
df1fe5bb
CH		 1953 return false;
1954 }
1955
1956 return !!test_bit(devno,
562f5e0b 1957 channel_subsys.css[cssid]->sch_set[ssid]->devnos_used);
df1fe5bb
CH		 1958}
1959
1960void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid,
1961 uint16_t devno, SubchDev *sch)
1962{
1963 CssImage *css;
1964 SubchSet *s_set;
1965
1966 trace_css_assign_subch(sch ? "assign" : "deassign", cssid, ssid, schid,
1967 devno);
562f5e0b 1968 if (!channel_subsys.css[cssid]) {
df1fe5bb
CH		 1969 fprintf(stderr,
1970 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n",
1971 __func__, cssid, ssid, schid);
1972 return;
1973 }
562f5e0b 1974 css = channel_subsys.css[cssid];
df1fe5bb
CH		 1975
1976 if (!css->sch_set[ssid]) {
1977 css->sch_set[ssid] = g_malloc0(sizeof(SubchSet));
1978 }
1979 s_set = css->sch_set[ssid];
1980
1981 s_set->sch[schid] = sch;
1982 if (sch) {
1983 set_bit(schid, s_set->schids_used);
1984 set_bit(devno, s_set->devnos_used);
1985 } else {
1986 clear_bit(schid, s_set->schids_used);
1987 clear_bit(devno, s_set->devnos_used);
1988 }
1989}
1990
1991void css_queue_crw(uint8_t rsc, uint8_t erc, int chain, uint16_t rsid)
1992{
1993 CrwContainer *crw_cont;
1994
1995 trace_css_crw(rsc, erc, rsid, chain ? "(chained)" : "");
1996 /* TODO: Maybe use a static crw pool? */
1997 crw_cont = g_try_malloc0(sizeof(CrwContainer));
1998 if (!crw_cont) {
562f5e0b 1999 channel_subsys.crws_lost = true;
df1fe5bb
CH		 2000 return;
2001 }
2002 crw_cont->crw.flags = (rsc << 8) | erc;
2003 if (chain) {
2004 crw_cont->crw.flags |= CRW_FLAGS_MASK_C;
2005 }
2006 crw_cont->crw.rsid = rsid;
562f5e0b 2007 if (channel_subsys.crws_lost) {
df1fe5bb 2008 crw_cont->crw.flags |= CRW_FLAGS_MASK_R;
562f5e0b 2009 channel_subsys.crws_lost = false;
df1fe5bb
CH		 2010 }
2011
562f5e0b 2012 QTAILQ_INSERT_TAIL(&channel_subsys.pending_crws, crw_cont, sibling);
df1fe5bb 2013
562f5e0b
EH		 2014 if (channel_subsys.do_crw_mchk) {
2015 channel_subsys.do_crw_mchk = false;
df1fe5bb 2016 /* Inject crw pending machine check. */
de13d216 2017 s390_crw_mchk();
df1fe5bb
CH		 2018 }
2019}
2020
2021void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid,
2022 int hotplugged, int add)
2023{
2024 uint8_t guest_cssid;
2025 bool chain_crw;
2026
2027 if (add && !hotplugged) {
2028 return;
2029 }
562f5e0b 2030 if (channel_subsys.max_cssid == 0) {
df1fe5bb 2031 /* Default cssid shows up as 0. */
562f5e0b 2032 guest_cssid = (cssid == channel_subsys.default_cssid) ? 0 : cssid;
df1fe5bb
CH		 2033 } else {
2034 /* Show real cssid to the guest. */
2035 guest_cssid = cssid;
2036 }
2037 /*
2038 * Only notify for higher subchannel sets/channel subsystems if the
2039 * guest has enabled it.
2040 */
562f5e0b
EH		 2041 if ((ssid > channel_subsys.max_ssid) ||
2042 (guest_cssid > channel_subsys.max_cssid) ||
2043 ((channel_subsys.max_cssid == 0) &&
2044 (cssid != channel_subsys.default_cssid))) {
df1fe5bb
CH		 2045 return;
2046 }
562f5e0b
EH		 2047 chain_crw = (channel_subsys.max_ssid > 0) ||
2048 (channel_subsys.max_cssid > 0);
df1fe5bb
CH		 2049 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, chain_crw ? 1 : 0, schid);
2050 if (chain_crw) {
2051 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0,
2052 (guest_cssid << 8) | (ssid << 4));
2053 }
c1755b14
HP		 2054 /* RW_ERC_IPI --> clear pending interrupts */
2055 css_clear_io_interrupt(css_do_build_subchannel_id(cssid, ssid), schid);
df1fe5bb
CH		 2056}
2057
2058void css_generate_chp_crws(uint8_t cssid, uint8_t chpid)
2059{
2060 /* TODO */
2061}
2062
8cba80c3
FB		 2063void css_generate_css_crws(uint8_t cssid)
2064{
562f5e0b 2065 if (!channel_subsys.sei_pending) {
c81b4f89
SSG		 2066 css_queue_crw(CRW_RSC_CSS, 0, 0, cssid);
2067 }
562f5e0b 2068 channel_subsys.sei_pending = true;
c81b4f89
SSG		 2069}
2070
2071void css_clear_sei_pending(void)
2072{
562f5e0b 2073 channel_subsys.sei_pending = false;
8cba80c3
FB		 2074}
2075
df1fe5bb
CH		 2076int css_enable_mcsse(void)
2077{
2078 trace_css_enable_facility("mcsse");
562f5e0b 2079 channel_subsys.max_cssid = MAX_CSSID;
df1fe5bb
CH		 2080 return 0;
2081}
2082
2083int css_enable_mss(void)
2084{
2085 trace_css_enable_facility("mss");
562f5e0b 2086 channel_subsys.max_ssid = MAX_SSID;
df1fe5bb
CH		 2087 return 0;
2088}
2089
df1fe5bb
CH		 2090void css_reset_sch(SubchDev *sch)
2091{
2092 PMCW *p = &sch->curr_status.pmcw;
2093
62ac4a52
TH		 2094 if ((p->flags & PMCW_FLAGS_MASK_ENA) != 0 && sch->disable_cb) {
2095 sch->disable_cb(sch);
2096 }
2097
df1fe5bb
CH		 2098 p->intparm = 0;
2099 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
2100 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
2101 PMCW_FLAGS_MASK_MP | PMCW_FLAGS_MASK_TF);
2102 p->flags |= PMCW_FLAGS_MASK_DNV;
2103 p->devno = sch->devno;
2104 p->pim = 0x80;
2105 p->lpm = p->pim;
2106 p->pnom = 0;
2107 p->lpum = 0;
2108 p->mbi = 0;
2109 p->pom = 0xff;
2110 p->pam = 0x80;
2111 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_XMWME |
2112 PMCW_CHARS_MASK_CSENSE);
2113
2114 memset(&sch->curr_status.scsw, 0, sizeof(sch->curr_status.scsw));
2115 sch->curr_status.mba = 0;
2116
2117 sch->channel_prog = 0x0;
2118 sch->last_cmd_valid = false;
7e749462 2119 sch->thinint_active = false;
df1fe5bb
CH		 2120}
2121
2122void css_reset(void)
2123{
2124 CrwContainer *crw_cont;
2125
2126 /* Clean up monitoring. */
562f5e0b
EH		 2127 channel_subsys.chnmon_active = false;
2128 channel_subsys.chnmon_area = 0;
df1fe5bb
CH		 2129
2130 /* Clear pending CRWs. */
562f5e0b
EH		 2131 while ((crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws))) {
2132 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling);
df1fe5bb
CH		 2133 g_free(crw_cont);
2134 }
562f5e0b
EH		 2135 channel_subsys.sei_pending = false;
2136 channel_subsys.do_crw_mchk = true;
2137 channel_subsys.crws_lost = false;
df1fe5bb
CH		 2138
2139 /* Reset maximum ids. */
562f5e0b
EH		 2140 channel_subsys.max_cssid = 0;
2141 channel_subsys.max_ssid = 0;
df1fe5bb 2142}
06e686ea
CH		 2143
2144static void get_css_devid(Object *obj, Visitor *v, const char *name,
2145 void *opaque, Error **errp)
2146{
2147 DeviceState *dev = DEVICE(obj);
2148 Property *prop = opaque;
2149 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop);
2150 char buffer[] = "xx.x.xxxx";
2151 char *p = buffer;
2152 int r;
2153
2154 if (dev_id->valid) {
2155
2156 r = snprintf(buffer, sizeof(buffer), "%02x.%1x.%04x", dev_id->cssid,
2157 dev_id->ssid, dev_id->devid);
2158 assert(r == sizeof(buffer) - 1);
2159
2160 /* drop leading zero */
2161 if (dev_id->cssid <= 0xf) {
2162 p++;
2163 }
2164 } else {
2165 snprintf(buffer, sizeof(buffer), "<unset>");
2166 }
2167
2168 visit_type_str(v, name, &p, errp);
2169}
2170
2171/*
2172 * parse <cssid>.<ssid>.<devid> and assert valid range for cssid/ssid
2173 */
2174static void set_css_devid(Object *obj, Visitor *v, const char *name,
2175 void *opaque, Error **errp)
2176{
2177 DeviceState *dev = DEVICE(obj);
2178 Property *prop = opaque;
2179 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop);
2180 Error *local_err = NULL;
2181 char *str;
2182 int num, n1, n2;
2183 unsigned int cssid, ssid, devid;
2184
2185 if (dev->realized) {
2186 qdev_prop_set_after_realize(dev, name, errp);
2187 return;
2188 }
2189
2190 visit_type_str(v, name, &str, &local_err);
2191 if (local_err) {
2192 error_propagate(errp, local_err);
2193 return;
2194 }
2195
2196 num = sscanf(str, "%2x.%1x%n.%4x%n", &cssid, &ssid, &n1, &devid, &n2);
2197 if (num != 3 || (n2 - n1) != 5 || strlen(str) != n2) {
2198 error_set_from_qdev_prop_error(errp, EINVAL, dev, prop, str);
2199 goto out;
2200 }
2201 if ((cssid > MAX_CSSID) || (ssid > MAX_SSID)) {
2202 error_setg(errp, "Invalid cssid or ssid: cssid %x, ssid %x",
2203 cssid, ssid);
2204 goto out;
2205 }
2206
2207 dev_id->cssid = cssid;
2208 dev_id->ssid = ssid;
2209 dev_id->devid = devid;
2210 dev_id->valid = true;
2211
2212out:
2213 g_free(str);
2214}
2215
2216PropertyInfo css_devid_propinfo = {
2217 .name = "str",
2218 .description = "Identifier of an I/O device in the channel "
2219 "subsystem, example: fe.1.23ab",
2220 .get = get_css_devid,
2221 .set = set_css_devid,
2222};
cf249935 2223
c35fc6aa
DJS		 2224PropertyInfo css_devid_ro_propinfo = {
2225 .name = "str",
2226 .description = "Read-only identifier of an I/O device in the channel "
2227 "subsystem, example: fe.1.23ab",
2228 .get = get_css_devid,
2229};
2230
817d4a6b
DJS		 2231SubchDev *css_create_sch(CssDevId bus_id, bool is_virtual, bool squash_mcss,
2232 Error **errp)
cf249935
SS		 2233{
2234 uint16_t schid = 0;
2235 SubchDev *sch;
2236
2237 if (bus_id.valid) {
817d4a6b
DJS		 2238 if (is_virtual != (bus_id.cssid == VIRTUAL_CSSID)) {
2239 error_setg(errp, "cssid %hhx not valid for %s devices",
2240 bus_id.cssid,
2241 (is_virtual ? "virtual" : "non-virtual"));
cf249935
SS		 2242 return NULL;
2243 }
817d4a6b
DJS		 2244 }
2245
2246 if (bus_id.valid) {
2247 if (squash_mcss) {
2248 bus_id.cssid = channel_subsys.default_cssid;
2249 } else if (!channel_subsys.css[bus_id.cssid]) {
2250 css_create_css_image(bus_id.cssid, false);
2251 }
2252
cf249935
SS		 2253 if (!css_find_free_subch_for_devno(bus_id.cssid, bus_id.ssid,
2254 bus_id.devid, &schid, errp)) {
2255 return NULL;
2256 }
817d4a6b
DJS		 2257 } else if (squash_mcss || is_virtual) {
2258 bus_id.cssid = channel_subsys.default_cssid;
2259
cf249935
SS		 2260 if (!css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid,
2261 &bus_id.devid, &schid, errp)) {
2262 return NULL;
2263 }
817d4a6b
DJS		 2264 } else {
2265 for (bus_id.cssid = 0; bus_id.cssid < MAX_CSSID; ++bus_id.cssid) {
2266 if (bus_id.cssid == VIRTUAL_CSSID) {
2267 continue;
2268 }
2269
2270 if (!channel_subsys.css[bus_id.cssid]) {
2271 css_create_css_image(bus_id.cssid, false);
2272 }
2273
2274 if (css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid,
2275 &bus_id.devid, &schid,
2276 NULL)) {
2277 break;
2278 }
2279 if (bus_id.cssid == MAX_CSSID) {
2280 error_setg(errp, "Virtual channel subsystem is full!");
2281 return NULL;
2282 }
2283 }
cf249935
SS		 2284 }
2285
2286 sch = g_malloc0(sizeof(*sch));
2287 sch->cssid = bus_id.cssid;
2288 sch->ssid = bus_id.ssid;
2289 sch->devno = bus_id.devid;
2290 sch->schid = schid;
2291 css_subch_assign(sch->cssid, sch->ssid, schid, sch->devno, sch);
2292 return sch;
2293}
8f3cf012
XFR		 2294
2295static int css_sch_get_chpids(SubchDev *sch, CssDevId *dev_id)
2296{
2297 char *fid_path;
2298 FILE *fd;
2299 uint32_t chpid[8];
2300 int i;
2301 PMCW *p = &sch->curr_status.pmcw;
2302
2303 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/chpids",
2304 dev_id->cssid, dev_id->ssid, dev_id->devid);
2305 fd = fopen(fid_path, "r");
2306 if (fd == NULL) {
2307 error_report("%s: open %s failed", __func__, fid_path);
2308 g_free(fid_path);
2309 return -EINVAL;
2310 }
2311
2312 if (fscanf(fd, "%x %x %x %x %x %x %x %x",
2313 &chpid[0], &chpid[1], &chpid[2], &chpid[3],
2314 &chpid[4], &chpid[5], &chpid[6], &chpid[7]) != 8) {
2315 fclose(fd);
2316 g_free(fid_path);
2317 return -EINVAL;
2318 }
2319
2320 for (i = 0; i < ARRAY_SIZE(p->chpid); i++) {
2321 p->chpid[i] = chpid[i];
2322 }
2323
2324 fclose(fd);
2325 g_free(fid_path);
2326
2327 return 0;
2328}
2329
2330static int css_sch_get_path_masks(SubchDev *sch, CssDevId *dev_id)
2331{
2332 char *fid_path;
2333 FILE *fd;
2334 uint32_t pim, pam, pom;
2335 PMCW *p = &sch->curr_status.pmcw;
2336
2337 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/pimpampom",
2338 dev_id->cssid, dev_id->ssid, dev_id->devid);
2339 fd = fopen(fid_path, "r");
2340 if (fd == NULL) {
2341 error_report("%s: open %s failed", __func__, fid_path);
2342 g_free(fid_path);
2343 return -EINVAL;
2344 }
2345
2346 if (fscanf(fd, "%x %x %x", &pim, &pam, &pom) != 3) {
2347 fclose(fd);
2348 g_free(fid_path);
2349 return -EINVAL;
2350 }
2351
2352 p->pim = pim;
2353 p->pam = pam;
2354 p->pom = pom;
2355 fclose(fd);
2356 g_free(fid_path);
2357
2358 return 0;
2359}
2360
2361static int css_sch_get_chpid_type(uint8_t chpid, uint32_t *type,
2362 CssDevId *dev_id)
2363{
2364 char *fid_path;
2365 FILE *fd;
2366
2367 fid_path = g_strdup_printf("/sys/devices/css%x/chp0.%02x/type",
2368 dev_id->cssid, chpid);
2369 fd = fopen(fid_path, "r");
2370 if (fd == NULL) {
2371 error_report("%s: open %s failed", __func__, fid_path);
2372 g_free(fid_path);
2373 return -EINVAL;
2374 }
2375
2376 if (fscanf(fd, "%x", type) != 1) {
2377 fclose(fd);
2378 g_free(fid_path);
2379 return -EINVAL;
2380 }
2381
2382 fclose(fd);
2383 g_free(fid_path);
2384
2385 return 0;
2386}
2387
2388/*
2389 * We currently retrieve the real device information from sysfs to build the
2390 * guest subchannel information block without considering the migration feature.
2391 * We need to revisit this problem when we want to add migration support.
2392 */
2393int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id)
2394{
2395 CssImage *css = channel_subsys.css[sch->cssid];
2396 PMCW *p = &sch->curr_status.pmcw;
2397 SCSW *s = &sch->curr_status.scsw;
2398 uint32_t type;
2399 int i, ret;
2400
2401 assert(css != NULL);
2402 memset(p, 0, sizeof(PMCW));
2403 p->flags |= PMCW_FLAGS_MASK_DNV;
2404 /* We are dealing with I/O subchannels only. */
2405 p->devno = sch->devno;
2406
2407 /* Grab path mask from sysfs. */
2408 ret = css_sch_get_path_masks(sch, dev_id);
2409 if (ret) {
2410 return ret;
2411 }
2412
2413 /* Grab chpids from sysfs. */
2414 ret = css_sch_get_chpids(sch, dev_id);
2415 if (ret) {
2416 return ret;
2417 }
2418
2419 /* Build chpid type. */
2420 for (i = 0; i < ARRAY_SIZE(p->chpid); i++) {
2421 if (p->chpid[i] && !css->chpids[p->chpid[i]].in_use) {
2422 ret = css_sch_get_chpid_type(p->chpid[i], &type, dev_id);
2423 if (ret) {
2424 return ret;
2425 }
2426 css_add_chpid(sch->cssid, p->chpid[i], type, false);
2427 }
2428 }
2429
2430 memset(s, 0, sizeof(SCSW));
2431 sch->curr_status.mba = 0;
2432 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) {
2433 sch->curr_status.mda[i] = 0;
2434 }
2435
2436 return 0;
2437}
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