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Merge remote-tracking branch 'mst/tags/for_anthony' into staging
[qemu.git] / tcg / tcg-op.h
CommitLineData
c896fe29
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#include "tcg.h"
25
c896fe29
FB		 26int gen_new_label(void);
27
212c328d
RH		 28static inline void tcg_gen_op0(TCGOpcode opc)
29{
efd7f486 30 *tcg_ctx.gen_opc_ptr++ = opc;
212c328d
RH		 31}
32
a9751609 33static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1)
c896fe29 34{
efd7f486 35 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4 36 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
a7812ae4
PB		 37}
38
a9751609 39static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1)
a7812ae4 40{
efd7f486 41 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4 42 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
c896fe29
FB		 43}
44
a9751609 45static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1)
c896fe29 46{
efd7f486 47 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4 48 *tcg_ctx.gen_opparam_ptr++ = arg1;
c896fe29
FB		 49}
50
a9751609 51static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2)
a7812ae4 52{
efd7f486 53 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 54 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
55 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
a7812ae4
PB		 56}
57
a9751609 58static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2)
a7812ae4 59{
efd7f486 60 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 61 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
62 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
a7812ae4
PB		 63}
64
a9751609 65static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2)
c896fe29 66{
efd7f486 67 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 68 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
69 *tcg_ctx.gen_opparam_ptr++ = arg2;
c896fe29
FB		 70}
71
a9751609 72static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2)
c896fe29 73{
efd7f486 74 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 75 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
76 *tcg_ctx.gen_opparam_ptr++ = arg2;
ac56dd48
PB		 77}
78
a9751609 79static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2)
bcb0126f 80{
efd7f486 81 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 82 *tcg_ctx.gen_opparam_ptr++ = arg1;
83 *tcg_ctx.gen_opparam_ptr++ = arg2;
bcb0126f
PB		 84}
85
a9751609 86static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
a7812ae4
PB		 87 TCGv_i32 arg3)
88{
efd7f486 89 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 90 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
91 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
92 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
a7812ae4
PB		 93}
94
a9751609 95static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
a7812ae4
PB		 96 TCGv_i64 arg3)
97{
efd7f486 98 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 99 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
100 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
101 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
a7812ae4
PB		 102}
103
a9751609
RH		 104static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1,
105 TCGv_i32 arg2, TCGArg arg3)
ac56dd48 106{
efd7f486 107 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 108 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
109 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
110 *tcg_ctx.gen_opparam_ptr++ = arg3;
ac56dd48
PB		 111}
112
a9751609
RH		 113static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1,
114 TCGv_i64 arg2, TCGArg arg3)
ac56dd48 115{
efd7f486 116 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 117 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
118 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
119 *tcg_ctx.gen_opparam_ptr++ = arg3;
ac56dd48
PB		 120}
121
a9751609
RH		 122static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
123 TCGv_ptr base, TCGArg offset)
a7812ae4 124{
efd7f486 125 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 126 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(val);
127 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_PTR(base);
128 *tcg_ctx.gen_opparam_ptr++ = offset;
a7812ae4
PB		 129}
130
a9751609
RH		 131static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
132 TCGv_ptr base, TCGArg offset)
a7812ae4 133{
efd7f486 134 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 135 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(val);
136 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_PTR(base);
137 *tcg_ctx.gen_opparam_ptr++ = offset;
a7812ae4
PB		 138}
139
a9751609
RH		 140static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val,
141 TCGv_i32 addr, TCGArg mem_index)
a7812ae4 142{
efd7f486 143 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 144 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(val);
145 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(addr);
146 *tcg_ctx.gen_opparam_ptr++ = mem_index;
a7812ae4
PB		 147}
148
a9751609
RH		 149static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val,
150 TCGv_i64 addr, TCGArg mem_index)
a7812ae4 151{
efd7f486 152 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 153 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(val);
154 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(addr);
155 *tcg_ctx.gen_opparam_ptr++ = mem_index;
a7812ae4
PB		 156}
157
a9751609 158static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
a7812ae4
PB		 159 TCGv_i32 arg3, TCGv_i32 arg4)
160{
efd7f486 161 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 162 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
163 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
164 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
165 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
a7812ae4
PB		 166}
167
a9751609 168static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
a810a2de 169 TCGv_i64 arg3, TCGv_i64 arg4)
a7812ae4 170{
efd7f486 171 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 172 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
173 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
174 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
175 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
a7812ae4
PB		 176}
177
a9751609 178static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
a7812ae4
PB		 179 TCGv_i32 arg3, TCGArg arg4)
180{
efd7f486 181 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 182 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
183 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
184 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
185 *tcg_ctx.gen_opparam_ptr++ = arg4;
a7812ae4
PB		 186}
187
a9751609 188static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
a7812ae4 189 TCGv_i64 arg3, TCGArg arg4)
ac56dd48 190{
efd7f486 191 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 192 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
193 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
194 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
195 *tcg_ctx.gen_opparam_ptr++ = arg4;
ac56dd48
PB		 196}
197
a9751609 198static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
a7812ae4 199 TCGArg arg3, TCGArg arg4)
ac56dd48 200{
efd7f486 201 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 202 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
203 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
204 *tcg_ctx.gen_opparam_ptr++ = arg3;
205 *tcg_ctx.gen_opparam_ptr++ = arg4;
c896fe29
FB		 206}
207
a9751609 208static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
a7812ae4 209 TCGArg arg3, TCGArg arg4)
c896fe29 210{
efd7f486 211 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 212 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
213 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
214 *tcg_ctx.gen_opparam_ptr++ = arg3;
215 *tcg_ctx.gen_opparam_ptr++ = arg4;
ac56dd48
PB		 216}
217
a9751609 218static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
a7812ae4
PB		 219 TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
220{
efd7f486 221 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 222 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
223 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
224 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
225 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
226 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg5);
a7812ae4
PB		 227}
228
a9751609 229static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
a7812ae4
PB		 230 TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
231{
efd7f486 232 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 233 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
234 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
235 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
236 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
237 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg5);
a7812ae4
PB		 238}
239
a9751609 240static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
a7812ae4 241 TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
ac56dd48 242{
efd7f486 243 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 244 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
245 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
246 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
247 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
248 *tcg_ctx.gen_opparam_ptr++ = arg5;
ac56dd48
PB		 249}
250
a9751609 251static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
a7812ae4 252 TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
ac56dd48 253{
efd7f486 254 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 255 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
256 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
257 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
258 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
259 *tcg_ctx.gen_opparam_ptr++ = arg5;
c896fe29
FB		 260}
261
b7767f0f
RH		 262static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1,
263 TCGv_i32 arg2, TCGv_i32 arg3,
264 TCGArg arg4, TCGArg arg5)
265{
efd7f486 266 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 267 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
268 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
269 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
270 *tcg_ctx.gen_opparam_ptr++ = arg4;
271 *tcg_ctx.gen_opparam_ptr++ = arg5;
b7767f0f
RH		 272}
273
274static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1,
275 TCGv_i64 arg2, TCGv_i64 arg3,
276 TCGArg arg4, TCGArg arg5)
277{
efd7f486 278 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 279 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
280 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
281 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
282 *tcg_ctx.gen_opparam_ptr++ = arg4;
283 *tcg_ctx.gen_opparam_ptr++ = arg5;
b7767f0f
RH		 284}
285
a9751609 286static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
a7812ae4
PB		 287 TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
288 TCGv_i32 arg6)
289{
efd7f486 290 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 291 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
292 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
293 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
294 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
295 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg5);
296 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg6);
a7812ae4
PB		 297}
298
a9751609 299static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
a7812ae4
PB		 300 TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
301 TCGv_i64 arg6)
c896fe29 302{
efd7f486 303 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 304 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
305 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
306 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
307 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
308 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg5);
309 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg6);
ac56dd48
PB		 310}
311
a9751609 312static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
be210acb
RH		 313 TCGv_i32 arg3, TCGv_i32 arg4,
314 TCGv_i32 arg5, TCGArg arg6)
315{
efd7f486 316 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 317 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
318 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
319 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
320 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
321 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg5);
322 *tcg_ctx.gen_opparam_ptr++ = arg6;
be210acb
RH		 323}
324
a9751609 325static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
be210acb
RH		 326 TCGv_i64 arg3, TCGv_i64 arg4,
327 TCGv_i64 arg5, TCGArg arg6)
328{
efd7f486 329 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 330 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
331 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
332 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
333 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
334 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg5);
335 *tcg_ctx.gen_opparam_ptr++ = arg6;
be210acb
RH		 336}
337
a9751609
RH		 338static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1,
339 TCGv_i32 arg2, TCGv_i32 arg3,
340 TCGv_i32 arg4, TCGArg arg5, TCGArg arg6)
ac56dd48 341{
efd7f486 342 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 343 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
344 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
345 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
346 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
347 *tcg_ctx.gen_opparam_ptr++ = arg5;
348 *tcg_ctx.gen_opparam_ptr++ = arg6;
a7812ae4
PB		 349}
350
a9751609
RH		 351static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1,
352 TCGv_i64 arg2, TCGv_i64 arg3,
353 TCGv_i64 arg4, TCGArg arg5, TCGArg arg6)
a7812ae4 354{
efd7f486 355 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 356 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
357 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
358 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
359 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
360 *tcg_ctx.gen_opparam_ptr++ = arg5;
361 *tcg_ctx.gen_opparam_ptr++ = arg6;
c896fe29
FB		 362}
363
364static inline void gen_set_label(int n)
365{
ac56dd48 366 tcg_gen_op1i(INDEX_op_set_label, n);
c896fe29
FB		 367}
368
fb50d413
BS		 369static inline void tcg_gen_br(int label)
370{
371 tcg_gen_op1i(INDEX_op_br, label);
372}
373
a7812ae4 374static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 375{
fe75bcf7 376 if (!TCGV_EQUAL_I32(ret, arg))
a7812ae4 377 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
c896fe29
FB		 378}
379
a7812ae4 380static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
c896fe29 381{
a7812ae4 382 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
c896fe29
FB		 383}
384
2bece2c8
RH		 385/* A version of dh_sizemask from def-helper.h that doesn't rely on
386 preprocessor magic. */
387static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed)
388{
389 return (is_64bit << n*2) | (is_signed << (n*2 + 1));
390}
391
c896fe29 392/* helper calls */
a7812ae4
PB		 393static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
394 TCGArg ret, int nargs, TCGArg *args)
395{
396 TCGv_ptr fn;
73f5e313 397 fn = tcg_const_ptr(func);
a7812ae4
PB		 398 tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
399 nargs, args);
400 tcg_temp_free_ptr(fn);
401}
c896fe29 402
dbfff4de 403/* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
78505279
AJ		 404 reserved for helpers in tcg-runtime.c. These helpers all do not read
405 globals and do not have side effects, hence the call to tcg_gen_callN()
406 with TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_SIDE_EFFECTS. This may need
407 to be adjusted if these functions start to be used with other helpers. */
2bece2c8 408static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret,
31d66551
AJ		 409 TCGv_i32 a, TCGv_i32 b)
410{
411 TCGv_ptr fn;
412 TCGArg args[2];
73f5e313 413 fn = tcg_const_ptr(func);
31d66551
AJ		 414 args[0] = GET_TCGV_I32(a);
415 args[1] = GET_TCGV_I32(b);
78505279
AJ		 416 tcg_gen_callN(&tcg_ctx, fn,
417 TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_SIDE_EFFECTS,
418 sizemask, GET_TCGV_I32(ret), 2, args);
31d66551
AJ		 419 tcg_temp_free_ptr(fn);
420}
421
2bece2c8 422static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret,
a7812ae4 423 TCGv_i64 a, TCGv_i64 b)
c896fe29 424{
a7812ae4
PB		 425 TCGv_ptr fn;
426 TCGArg args[2];
73f5e313 427 fn = tcg_const_ptr(func);
a7812ae4
PB		 428 args[0] = GET_TCGV_I64(a);
429 args[1] = GET_TCGV_I64(b);
78505279
AJ		 430 tcg_gen_callN(&tcg_ctx, fn,
431 TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_SIDE_EFFECTS,
432 sizemask, GET_TCGV_I64(ret), 2, args);
a7812ae4 433 tcg_temp_free_ptr(fn);
f8422f52
BS		 434}
435
c896fe29
FB		 436/* 32 bit ops */
437
a7812ae4 438static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 439{
a7812ae4 440 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
c896fe29
FB		 441}
442
a7812ae4 443static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 444{
a7812ae4 445 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
c896fe29
FB		 446}
447
a7812ae4 448static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 449{
a7812ae4 450 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
c896fe29
FB		 451}
452
a7812ae4 453static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 454{
a7812ae4 455 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
c896fe29
FB		 456}
457
a7812ae4 458static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 459{
a7812ae4 460 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
c896fe29
FB		 461}
462
a7812ae4 463static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 464{
a7812ae4 465 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
c896fe29
FB		 466}
467
a7812ae4 468static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 469{
a7812ae4 470 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
c896fe29
FB		 471}
472
a7812ae4 473static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 474{
a7812ae4 475 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
c896fe29
FB		 476}
477
a7812ae4 478static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 479{
a7812ae4 480 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
c896fe29
FB		 481}
482
a7812ae4 483static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
c896fe29 484{
7089442c
BS		 485 /* some cases can be optimized here */
486 if (arg2 == 0) {
487 tcg_gen_mov_i32(ret, arg1);
488 } else {
a7812ae4 489 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 490 tcg_gen_add_i32(ret, arg1, t0);
a7812ae4 491 tcg_temp_free_i32(t0);
7089442c 492 }
c896fe29
FB		 493}
494
a7812ae4 495static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 496{
a7812ae4 497 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
c896fe29
FB		 498}
499
a7812ae4 500static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
0045734a 501{
a7812ae4 502 TCGv_i32 t0 = tcg_const_i32(arg1);
0045734a 503 tcg_gen_sub_i32(ret, t0, arg2);
a7812ae4 504 tcg_temp_free_i32(t0);
0045734a
AJ		 505}
506
a7812ae4 507static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
c896fe29 508{
7089442c
BS		 509 /* some cases can be optimized here */
510 if (arg2 == 0) {
511 tcg_gen_mov_i32(ret, arg1);
512 } else {
a7812ae4 513 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 514 tcg_gen_sub_i32(ret, arg1, t0);
a7812ae4 515 tcg_temp_free_i32(t0);
7089442c 516 }
c896fe29
FB		 517}
518
a7812ae4 519static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 520{
7fc81051
AJ		 521 if (TCGV_EQUAL_I32(arg1, arg2)) {
522 tcg_gen_mov_i32(ret, arg1);
523 } else {
524 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
525 }
c896fe29
FB		 526}
527
42ce3e20 528static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
c896fe29 529{
42ce3e20
RH		 530 TCGv_i32 t0;
531 /* Some cases can be optimized here. */
532 switch (arg2) {
533 case 0:
c896fe29 534 tcg_gen_movi_i32(ret, 0);
42ce3e20
RH		 535 return;
536 case 0xffffffffu:
c896fe29 537 tcg_gen_mov_i32(ret, arg1);
42ce3e20
RH		 538 return;
539 case 0xffu:
540 /* Don't recurse with tcg_gen_ext8u_i32. */
541 if (TCG_TARGET_HAS_ext8u_i32) {
542 tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1);
543 return;
544 }
545 break;
546 case 0xffffu:
547 if (TCG_TARGET_HAS_ext16u_i32) {
548 tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1);
549 return;
550 }
551 break;
c896fe29 552 }
42ce3e20
RH		 553 t0 = tcg_const_i32(arg2);
554 tcg_gen_and_i32(ret, arg1, t0);
555 tcg_temp_free_i32(t0);
c896fe29
FB		 556}
557
a7812ae4 558static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 559{
7fc81051
AJ		 560 if (TCGV_EQUAL_I32(arg1, arg2)) {
561 tcg_gen_mov_i32(ret, arg1);
562 } else {
563 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
564 }
c896fe29
FB		 565}
566
a7812ae4 567static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
c896fe29 568{
d81ada7f
RH		 569 /* Some cases can be optimized here. */
570 if (arg2 == -1) {
571 tcg_gen_movi_i32(ret, -1);
c896fe29
FB		 572 } else if (arg2 == 0) {
573 tcg_gen_mov_i32(ret, arg1);
574 } else {
a7812ae4 575 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 576 tcg_gen_or_i32(ret, arg1, t0);
a7812ae4 577 tcg_temp_free_i32(t0);
c896fe29
FB		 578 }
579}
580
a7812ae4 581static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 582{
7fc81051
AJ		 583 if (TCGV_EQUAL_I32(arg1, arg2)) {
584 tcg_gen_movi_i32(ret, 0);
585 } else {
586 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
587 }
c896fe29
FB		 588}
589
a7812ae4 590static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
c896fe29 591{
6f3bb33e 592 /* Some cases can be optimized here. */
c896fe29
FB		 593 if (arg2 == 0) {
594 tcg_gen_mov_i32(ret, arg1);
6f3bb33e
RH		 595 } else if (arg2 == -1 && TCG_TARGET_HAS_not_i32) {
596 /* Don't recurse with tcg_gen_not_i32. */
597 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1);
c896fe29 598 } else {
a7812ae4 599 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 600 tcg_gen_xor_i32(ret, arg1, t0);
a7812ae4 601 tcg_temp_free_i32(t0);
c896fe29
FB		 602 }
603}
604
a7812ae4 605static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 606{
a7812ae4 607 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
c896fe29
FB		 608}
609
a7812ae4 610static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
c896fe29 611{
34151a20
FB		 612 if (arg2 == 0) {
613 tcg_gen_mov_i32(ret, arg1);
614 } else {
a7812ae4 615 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 616 tcg_gen_shl_i32(ret, arg1, t0);
a7812ae4 617 tcg_temp_free_i32(t0);
34151a20 618 }
c896fe29
FB		 619}
620
a7812ae4 621static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 622{
a7812ae4 623 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
c896fe29
FB		 624}
625
a7812ae4 626static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
c896fe29 627{
34151a20
FB		 628 if (arg2 == 0) {
629 tcg_gen_mov_i32(ret, arg1);
630 } else {
a7812ae4 631 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 632 tcg_gen_shr_i32(ret, arg1, t0);
a7812ae4 633 tcg_temp_free_i32(t0);
34151a20 634 }
c896fe29
FB		 635}
636
a7812ae4 637static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 638{
a7812ae4 639 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
c896fe29
FB		 640}
641
a7812ae4 642static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
c896fe29 643{
34151a20
FB		 644 if (arg2 == 0) {
645 tcg_gen_mov_i32(ret, arg1);
646 } else {
a7812ae4 647 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 648 tcg_gen_sar_i32(ret, arg1, t0);
a7812ae4 649 tcg_temp_free_i32(t0);
34151a20 650 }
c896fe29
FB		 651}
652
8a56e840
RH		 653static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1,
654 TCGv_i32 arg2, int label_index)
c896fe29 655{
0aed257f
RH		 656 if (cond == TCG_COND_ALWAYS) {
657 tcg_gen_br(label_index);
658 } else if (cond != TCG_COND_NEVER) {
659 tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
660 }
c896fe29
FB		 661}
662
8a56e840
RH		 663static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1,
664 int32_t arg2, int label_index)
cb63669a 665{
0aed257f
RH		 666 if (cond == TCG_COND_ALWAYS) {
667 tcg_gen_br(label_index);
668 } else if (cond != TCG_COND_NEVER) {
669 TCGv_i32 t0 = tcg_const_i32(arg2);
670 tcg_gen_brcond_i32(cond, arg1, t0, label_index);
671 tcg_temp_free_i32(t0);
672 }
cb63669a
PB		 673}
674
8a56e840 675static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
5105c556
AJ		 676 TCGv_i32 arg1, TCGv_i32 arg2)
677{
0aed257f
RH		 678 if (cond == TCG_COND_ALWAYS) {
679 tcg_gen_movi_i32(ret, 1);
680 } else if (cond == TCG_COND_NEVER) {
681 tcg_gen_movi_i32(ret, 0);
682 } else {
683 tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
684 }
5105c556
AJ		 685}
686
8a56e840
RH		 687static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
688 TCGv_i32 arg1, int32_t arg2)
5105c556 689{
0aed257f
RH		 690 if (cond == TCG_COND_ALWAYS) {
691 tcg_gen_movi_i32(ret, 1);
692 } else if (cond == TCG_COND_NEVER) {
693 tcg_gen_movi_i32(ret, 0);
694 } else {
695 TCGv_i32 t0 = tcg_const_i32(arg2);
696 tcg_gen_setcond_i32(cond, ret, arg1, t0);
697 tcg_temp_free_i32(t0);
698 }
5105c556
AJ		 699}
700
a7812ae4 701static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 702{
a7812ae4 703 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
c896fe29
FB		 704}
705
a7812ae4 706static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
f730fd27 707{
a7812ae4 708 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 709 tcg_gen_mul_i32(ret, arg1, t0);
a7812ae4 710 tcg_temp_free_i32(t0);
f730fd27
TS		 711}
712
a7812ae4 713static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 714{
25c4d9cc
RH		 715 if (TCG_TARGET_HAS_div_i32) {
716 tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
717 } else if (TCG_TARGET_HAS_div2_i32) {
718 TCGv_i32 t0 = tcg_temp_new_i32();
719 tcg_gen_sari_i32(t0, arg1, 31);
720 tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
721 tcg_temp_free_i32(t0);
722 } else {
723 int sizemask = 0;
724 /* Return value and both arguments are 32-bit and signed. */
725 sizemask |= tcg_gen_sizemask(0, 0, 1);
726 sizemask |= tcg_gen_sizemask(1, 0, 1);
727 sizemask |= tcg_gen_sizemask(2, 0, 1);
728 tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2);
729 }
31d66551
AJ		 730}
731
732static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
733{
ca675f46 734 if (TCG_TARGET_HAS_rem_i32) {
25c4d9cc 735 tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
ca675f46
RH		 736 } else if (TCG_TARGET_HAS_div_i32) {
737 TCGv_i32 t0 = tcg_temp_new_i32();
738 tcg_gen_op3_i32(INDEX_op_div_i32, t0, arg1, arg2);
739 tcg_gen_mul_i32(t0, t0, arg2);
740 tcg_gen_sub_i32(ret, arg1, t0);
741 tcg_temp_free_i32(t0);
25c4d9cc
RH		 742 } else if (TCG_TARGET_HAS_div2_i32) {
743 TCGv_i32 t0 = tcg_temp_new_i32();
744 tcg_gen_sari_i32(t0, arg1, 31);
745 tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
746 tcg_temp_free_i32(t0);
747 } else {
748 int sizemask = 0;
749 /* Return value and both arguments are 32-bit and signed. */
750 sizemask |= tcg_gen_sizemask(0, 0, 1);
751 sizemask |= tcg_gen_sizemask(1, 0, 1);
752 sizemask |= tcg_gen_sizemask(2, 0, 1);
753 tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2);
754 }
31d66551
AJ		 755}
756
757static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
758{
25c4d9cc
RH		 759 if (TCG_TARGET_HAS_div_i32) {
760 tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
761 } else if (TCG_TARGET_HAS_div2_i32) {
762 TCGv_i32 t0 = tcg_temp_new_i32();
763 tcg_gen_movi_i32(t0, 0);
764 tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
765 tcg_temp_free_i32(t0);
766 } else {
767 int sizemask = 0;
768 /* Return value and both arguments are 32-bit and unsigned. */
769 sizemask |= tcg_gen_sizemask(0, 0, 0);
770 sizemask |= tcg_gen_sizemask(1, 0, 0);
771 sizemask |= tcg_gen_sizemask(2, 0, 0);
772 tcg_gen_helper32(tcg_helper_divu_i32, sizemask, ret, arg1, arg2);
773 }
31d66551
AJ		 774}
775
776static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
777{
ca675f46 778 if (TCG_TARGET_HAS_rem_i32) {
25c4d9cc 779 tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
ca675f46
RH		 780 } else if (TCG_TARGET_HAS_div_i32) {
781 TCGv_i32 t0 = tcg_temp_new_i32();
782 tcg_gen_op3_i32(INDEX_op_divu_i32, t0, arg1, arg2);
783 tcg_gen_mul_i32(t0, t0, arg2);
784 tcg_gen_sub_i32(ret, arg1, t0);
785 tcg_temp_free_i32(t0);
25c4d9cc
RH		 786 } else if (TCG_TARGET_HAS_div2_i32) {
787 TCGv_i32 t0 = tcg_temp_new_i32();
788 tcg_gen_movi_i32(t0, 0);
789 tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
790 tcg_temp_free_i32(t0);
791 } else {
792 int sizemask = 0;
793 /* Return value and both arguments are 32-bit and unsigned. */
794 sizemask |= tcg_gen_sizemask(0, 0, 0);
795 sizemask |= tcg_gen_sizemask(1, 0, 0);
796 sizemask |= tcg_gen_sizemask(2, 0, 0);
797 tcg_gen_helper32(tcg_helper_remu_i32, sizemask, ret, arg1, arg2);
798 }
31d66551 799}
c896fe29
FB		 800
801#if TCG_TARGET_REG_BITS == 32
802
a7812ae4 803static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 804{
fe75bcf7 805 if (!TCGV_EQUAL_I64(ret, arg)) {
a7812ae4 806 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
4d07272d
BS		 807 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
808 }
c896fe29
FB		 809}
810
a7812ae4 811static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
c896fe29 812{
a7812ae4 813 tcg_gen_movi_i32(TCGV_LOW(ret), arg);
ac56dd48 814 tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
c896fe29
FB		 815}
816
a7812ae4
PB		 817static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
818 tcg_target_long offset)
c896fe29 819{
a7812ae4 820 tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
ac56dd48 821 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
c896fe29
FB		 822}
823
a7812ae4
PB		 824static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
825 tcg_target_long offset)
c896fe29 826{
a7812ae4
PB		 827 tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
828 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
c896fe29
FB		 829}
830
a7812ae4
PB		 831static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
832 tcg_target_long offset)
c896fe29 833{
a747723b 834 tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
ac56dd48 835 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
c896fe29
FB		 836}
837
a7812ae4
PB		 838static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
839 tcg_target_long offset)
c896fe29 840{
a7812ae4
PB		 841 tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
842 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
c896fe29
FB		 843}
844
a7812ae4
PB		 845static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
846 tcg_target_long offset)
c896fe29 847{
a7812ae4 848 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
ac56dd48 849 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
c896fe29
FB		 850}
851
a7812ae4
PB		 852static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
853 tcg_target_long offset)
c896fe29 854{
a7812ae4
PB		 855 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
856 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
c896fe29
FB		 857}
858
a7812ae4
PB		 859static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
860 tcg_target_long offset)
c896fe29
FB		 861{
862 /* since arg2 and ret have different types, they cannot be the
863 same temporary */
864#ifdef TCG_TARGET_WORDS_BIGENDIAN
ac56dd48 865 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
a7812ae4 866 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
c896fe29 867#else
a7812ae4 868 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
ac56dd48 869 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
c896fe29
FB		 870#endif
871}
872
a7812ae4
PB		 873static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
874 tcg_target_long offset)
c896fe29 875{
a7812ae4 876 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 877}
878
a7812ae4
PB		 879static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
880 tcg_target_long offset)
c896fe29 881{
a7812ae4 882 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 883}
884
a7812ae4
PB		 885static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
886 tcg_target_long offset)
c896fe29 887{
a7812ae4 888 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 889}
890
a7812ae4
PB		 891static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
892 tcg_target_long offset)
c896fe29
FB		 893{
894#ifdef TCG_TARGET_WORDS_BIGENDIAN
ac56dd48 895 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
a7812ae4 896 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
c896fe29 897#else
a7812ae4 898 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
ac56dd48 899 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
c896fe29
FB		 900#endif
901}
902
a7812ae4 903static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 904{
a7812ae4
PB		 905 tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
906 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
907 TCGV_HIGH(arg2));
212c328d
RH		 908 /* Allow the optimizer room to replace add2 with two moves. */
909 tcg_gen_op0(INDEX_op_nop);
c896fe29
FB		 910}
911
a7812ae4 912static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 913{
a7812ae4
PB		 914 tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
915 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
916 TCGV_HIGH(arg2));
212c328d
RH		 917 /* Allow the optimizer room to replace sub2 with two moves. */
918 tcg_gen_op0(INDEX_op_nop);
c896fe29
FB		 919}
920
a7812ae4 921static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 922{
a7812ae4 923 tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
ac56dd48 924 tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
c896fe29
FB		 925}
926
a7812ae4 927static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 928{
e5105083
AJ		 929 tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
930 tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
c896fe29
FB		 931}
932
a7812ae4 933static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 934{
e5105083
AJ		 935 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
936 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
c896fe29
FB		 937}
938
a7812ae4 939static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 940{
a7812ae4 941 tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
ac56dd48 942 tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
c896fe29
FB		 943}
944
a7812ae4 945static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 946{
e5105083
AJ		 947 tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
948 tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
c896fe29
FB		 949}
950
a7812ae4 951static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 952{
a7812ae4 953 tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
ac56dd48 954 tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
c896fe29
FB		 955}
956
957/* XXX: use generic code when basic block handling is OK or CPU
958 specific code (x86) */
a7812ae4 959static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 960{
2bece2c8
RH		 961 int sizemask = 0;
962 /* Return value and both arguments are 64-bit and signed. */
963 sizemask |= tcg_gen_sizemask(0, 1, 1);
964 sizemask |= tcg_gen_sizemask(1, 1, 1);
965 sizemask |= tcg_gen_sizemask(2, 1, 1);
966
967 tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2);
c896fe29
FB		 968}
969
a7812ae4 970static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29
FB		 971{
972 tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
973}
974
a7812ae4 975static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 976{
2bece2c8
RH		 977 int sizemask = 0;
978 /* Return value and both arguments are 64-bit and signed. */
979 sizemask |= tcg_gen_sizemask(0, 1, 1);
980 sizemask |= tcg_gen_sizemask(1, 1, 1);
981 sizemask |= tcg_gen_sizemask(2, 1, 1);
982
983 tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2);
c896fe29
FB		 984}
985
a7812ae4 986static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29
FB		 987{
988 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
989}
990
a7812ae4 991static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 992{
2bece2c8
RH		 993 int sizemask = 0;
994 /* Return value and both arguments are 64-bit and signed. */
995 sizemask |= tcg_gen_sizemask(0, 1, 1);
996 sizemask |= tcg_gen_sizemask(1, 1, 1);
997 sizemask |= tcg_gen_sizemask(2, 1, 1);
998
999 tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2);
c896fe29
FB		 1000}
1001
a7812ae4 1002static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29
FB		 1003{
1004 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
1005}
1006
8a56e840
RH		 1007static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
1008 TCGv_i64 arg2, int label_index)
c896fe29 1009{
0aed257f
RH		 1010 if (cond == TCG_COND_ALWAYS) {
1011 tcg_gen_br(label_index);
1012 } else if (cond != TCG_COND_NEVER) {
1013 tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
1014 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
1015 TCGV_HIGH(arg2), cond, label_index);
1016 }
c896fe29
FB		 1017}
1018
8a56e840 1019static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
5105c556
AJ		 1020 TCGv_i64 arg1, TCGv_i64 arg2)
1021{
0aed257f
RH		 1022 if (cond == TCG_COND_ALWAYS) {
1023 tcg_gen_movi_i32(TCGV_LOW(ret), 1);
1024 } else if (cond == TCG_COND_NEVER) {
1025 tcg_gen_movi_i32(TCGV_LOW(ret), 0);
1026 } else {
1027 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
1028 TCGV_LOW(arg1), TCGV_HIGH(arg1),
1029 TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
1030 }
5105c556
AJ		 1031 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1032}
1033
a7812ae4 1034static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1035{
a7812ae4
PB		 1036 TCGv_i64 t0;
1037 TCGv_i32 t1;
c896fe29 1038
a7812ae4
PB		 1039 t0 = tcg_temp_new_i64();
1040 t1 = tcg_temp_new_i32();
1041
03271524
RH		 1042 if (TCG_TARGET_HAS_mulu2_i32) {
1043 tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
1044 TCGV_LOW(arg1), TCGV_LOW(arg2));
1045 /* Allow the optimizer room to replace mulu2 with two moves. */
1046 tcg_gen_op0(INDEX_op_nop);
1047 } else {
1048 tcg_debug_assert(TCG_TARGET_HAS_muluh_i32);
1049 tcg_gen_op3_i32(INDEX_op_mul_i32, TCGV_LOW(t0),
1050 TCGV_LOW(arg1), TCGV_LOW(arg2));
1051 tcg_gen_op3_i32(INDEX_op_muluh_i32, TCGV_HIGH(t0),
1052 TCGV_LOW(arg1), TCGV_LOW(arg2));
1053 }
a7812ae4
PB		 1054
1055 tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
ac56dd48 1056 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
a7812ae4 1057 tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
ac56dd48 1058 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
a7812ae4 1059
c896fe29 1060 tcg_gen_mov_i64(ret, t0);
a7812ae4
PB		 1061 tcg_temp_free_i64(t0);
1062 tcg_temp_free_i32(t1);
c896fe29
FB		 1063}
1064
a7812ae4 1065static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1066{
2bece2c8
RH		 1067 int sizemask = 0;
1068 /* Return value and both arguments are 64-bit and signed. */
1069 sizemask |= tcg_gen_sizemask(0, 1, 1);
1070 sizemask |= tcg_gen_sizemask(1, 1, 1);
1071 sizemask |= tcg_gen_sizemask(2, 1, 1);
1072
1073 tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
c896fe29
FB		 1074}
1075
a7812ae4 1076static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1077{
2bece2c8
RH		 1078 int sizemask = 0;
1079 /* Return value and both arguments are 64-bit and signed. */
1080 sizemask |= tcg_gen_sizemask(0, 1, 1);
1081 sizemask |= tcg_gen_sizemask(1, 1, 1);
1082 sizemask |= tcg_gen_sizemask(2, 1, 1);
1083
1084 tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
c896fe29
FB		 1085}
1086
a7812ae4 1087static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1088{
2bece2c8
RH		 1089 int sizemask = 0;
1090 /* Return value and both arguments are 64-bit and unsigned. */
1091 sizemask |= tcg_gen_sizemask(0, 1, 0);
1092 sizemask |= tcg_gen_sizemask(1, 1, 0);
1093 sizemask |= tcg_gen_sizemask(2, 1, 0);
1094
1095 tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
c896fe29
FB		 1096}
1097
a7812ae4 1098static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1099{
2bece2c8
RH		 1100 int sizemask = 0;
1101 /* Return value and both arguments are 64-bit and unsigned. */
1102 sizemask |= tcg_gen_sizemask(0, 1, 0);
1103 sizemask |= tcg_gen_sizemask(1, 1, 0);
1104 sizemask |= tcg_gen_sizemask(2, 1, 0);
1105
1106 tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
c896fe29
FB		 1107}
1108
1109#else
1110
a7812ae4 1111static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1112{
fe75bcf7 1113 if (!TCGV_EQUAL_I64(ret, arg))
a7812ae4 1114 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
c896fe29
FB		 1115}
1116
a7812ae4 1117static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
c896fe29 1118{
a7812ae4 1119 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
c896fe29
FB		 1120}
1121
6bd4b08a 1122static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
ac56dd48 1123 tcg_target_long offset)
c896fe29 1124{
a7812ae4 1125 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
c896fe29
FB		 1126}
1127
6bd4b08a 1128static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
ac56dd48 1129 tcg_target_long offset)
c896fe29 1130{
a7812ae4 1131 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
c896fe29
FB		 1132}
1133
6bd4b08a 1134static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
ac56dd48 1135 tcg_target_long offset)
c896fe29 1136{
a7812ae4 1137 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
c896fe29
FB		 1138}
1139
6bd4b08a 1140static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
ac56dd48 1141 tcg_target_long offset)
c896fe29 1142{
a7812ae4 1143 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
c896fe29
FB		 1144}
1145
6bd4b08a 1146static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
ac56dd48 1147 tcg_target_long offset)
c896fe29 1148{
a7812ae4 1149 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
c896fe29
FB		 1150}
1151
6bd4b08a 1152static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
ac56dd48 1153 tcg_target_long offset)
c896fe29 1154{
a7812ae4 1155 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
c896fe29
FB		 1156}
1157
6bd4b08a 1158static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 1159{
a7812ae4 1160 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
c896fe29
FB		 1161}
1162
6bd4b08a 1163static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
ac56dd48 1164 tcg_target_long offset)
c896fe29 1165{
a7812ae4 1166 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
c896fe29
FB		 1167}
1168
6bd4b08a 1169static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
ac56dd48 1170 tcg_target_long offset)
c896fe29 1171{
a7812ae4 1172 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
c896fe29
FB		 1173}
1174
6bd4b08a 1175static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
ac56dd48 1176 tcg_target_long offset)
c896fe29 1177{
a7812ae4 1178 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
c896fe29
FB		 1179}
1180
6bd4b08a 1181static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 1182{
a7812ae4 1183 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
c896fe29
FB		 1184}
1185
a7812ae4 1186static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1187{
a7812ae4 1188 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
c896fe29
FB		 1189}
1190
a7812ae4 1191static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1192{
a7812ae4 1193 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
c896fe29
FB		 1194}
1195
a7812ae4 1196static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1197{
7fc81051
AJ		 1198 if (TCGV_EQUAL_I64(arg1, arg2)) {
1199 tcg_gen_mov_i64(ret, arg1);
1200 } else {
1201 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
1202 }
c896fe29
FB		 1203}
1204
42ce3e20 1205static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
c896fe29 1206{
42ce3e20
RH		 1207 TCGv_i64 t0;
1208 /* Some cases can be optimized here. */
1209 switch (arg2) {
1210 case 0:
1211 tcg_gen_movi_i64(ret, 0);
1212 return;
1213 case 0xffffffffffffffffull:
1214 tcg_gen_mov_i64(ret, arg1);
1215 return;
1216 case 0xffull:
1217 /* Don't recurse with tcg_gen_ext8u_i32. */
1218 if (TCG_TARGET_HAS_ext8u_i64) {
1219 tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1);
1220 return;
1221 }
1222 break;
1223 case 0xffffu:
1224 if (TCG_TARGET_HAS_ext16u_i64) {
1225 tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1);
1226 return;
1227 }
1228 break;
1229 case 0xffffffffull:
1230 if (TCG_TARGET_HAS_ext32u_i64) {
1231 tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1);
1232 return;
1233 }
1234 break;
1235 }
1236 t0 = tcg_const_i64(arg2);
e8996ee0 1237 tcg_gen_and_i64(ret, arg1, t0);
a7812ae4 1238 tcg_temp_free_i64(t0);
c896fe29
FB		 1239}
1240
a7812ae4 1241static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1242{
7fc81051
AJ		 1243 if (TCGV_EQUAL_I64(arg1, arg2)) {
1244 tcg_gen_mov_i64(ret, arg1);
1245 } else {
1246 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
1247 }
c896fe29
FB		 1248}
1249
a7812ae4 1250static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 1251{
d81ada7f
RH		 1252 /* Some cases can be optimized here. */
1253 if (arg2 == -1) {
1254 tcg_gen_movi_i64(ret, -1);
1255 } else if (arg2 == 0) {
1256 tcg_gen_mov_i64(ret, arg1);
1257 } else {
1258 TCGv_i64 t0 = tcg_const_i64(arg2);
1259 tcg_gen_or_i64(ret, arg1, t0);
1260 tcg_temp_free_i64(t0);
1261 }
c896fe29
FB		 1262}
1263
a7812ae4 1264static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1265{
7fc81051
AJ		 1266 if (TCGV_EQUAL_I64(arg1, arg2)) {
1267 tcg_gen_movi_i64(ret, 0);
1268 } else {
1269 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
1270 }
c896fe29
FB		 1271}
1272
a7812ae4 1273static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 1274{
6f3bb33e
RH		 1275 /* Some cases can be optimized here. */
1276 if (arg2 == 0) {
1277 tcg_gen_mov_i64(ret, arg1);
1278 } else if (arg2 == -1 && TCG_TARGET_HAS_not_i64) {
1279 /* Don't recurse with tcg_gen_not_i64. */
1280 tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1);
1281 } else {
1282 TCGv_i64 t0 = tcg_const_i64(arg2);
1283 tcg_gen_xor_i64(ret, arg1, t0);
1284 tcg_temp_free_i64(t0);
1285 }
c896fe29
FB		 1286}
1287
a7812ae4 1288static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1289{
a7812ae4 1290 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
c896fe29
FB		 1291}
1292
a7812ae4 1293static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 1294{
34151a20
FB		 1295 if (arg2 == 0) {
1296 tcg_gen_mov_i64(ret, arg1);
1297 } else {
a7812ae4 1298 TCGv_i64 t0 = tcg_const_i64(arg2);
e8996ee0 1299 tcg_gen_shl_i64(ret, arg1, t0);
a7812ae4 1300 tcg_temp_free_i64(t0);
34151a20 1301 }
c896fe29
FB		 1302}
1303
a7812ae4 1304static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1305{
a7812ae4 1306 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
c896fe29
FB		 1307}
1308
a7812ae4 1309static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 1310{
34151a20
FB		 1311 if (arg2 == 0) {
1312 tcg_gen_mov_i64(ret, arg1);
1313 } else {
a7812ae4 1314 TCGv_i64 t0 = tcg_const_i64(arg2);
e8996ee0 1315 tcg_gen_shr_i64(ret, arg1, t0);
a7812ae4 1316 tcg_temp_free_i64(t0);
34151a20 1317 }
c896fe29
FB		 1318}
1319
a7812ae4 1320static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1321{
a7812ae4 1322 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
c896fe29
FB		 1323}
1324
a7812ae4 1325static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 1326{
34151a20
FB		 1327 if (arg2 == 0) {
1328 tcg_gen_mov_i64(ret, arg1);
1329 } else {
a7812ae4 1330 TCGv_i64 t0 = tcg_const_i64(arg2);
e8996ee0 1331 tcg_gen_sar_i64(ret, arg1, t0);
a7812ae4 1332 tcg_temp_free_i64(t0);
34151a20 1333 }
c896fe29
FB		 1334}
1335
8a56e840
RH		 1336static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
1337 TCGv_i64 arg2, int label_index)
c896fe29 1338{
0aed257f
RH		 1339 if (cond == TCG_COND_ALWAYS) {
1340 tcg_gen_br(label_index);
1341 } else if (cond != TCG_COND_NEVER) {
1342 tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1343 }
c896fe29
FB		 1344}
1345
8a56e840 1346static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
5105c556
AJ		 1347 TCGv_i64 arg1, TCGv_i64 arg2)
1348{
0aed257f
RH		 1349 if (cond == TCG_COND_ALWAYS) {
1350 tcg_gen_movi_i64(ret, 1);
1351 } else if (cond == TCG_COND_NEVER) {
1352 tcg_gen_movi_i64(ret, 0);
1353 } else {
1354 tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
1355 }
5105c556
AJ		 1356}
1357
a7812ae4 1358static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1359{
a7812ae4 1360 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
c896fe29
FB		 1361}
1362
31d66551
AJ		 1363static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1364{
25c4d9cc
RH		 1365 if (TCG_TARGET_HAS_div_i64) {
1366 tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1367 } else if (TCG_TARGET_HAS_div2_i64) {
1368 TCGv_i64 t0 = tcg_temp_new_i64();
1369 tcg_gen_sari_i64(t0, arg1, 63);
1370 tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1371 tcg_temp_free_i64(t0);
1372 } else {
1373 int sizemask = 0;
1374 /* Return value and both arguments are 64-bit and signed. */
1375 sizemask |= tcg_gen_sizemask(0, 1, 1);
1376 sizemask |= tcg_gen_sizemask(1, 1, 1);
1377 sizemask |= tcg_gen_sizemask(2, 1, 1);
1378 tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
1379 }
31d66551
AJ		 1380}
1381
1382static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1383{
ca675f46 1384 if (TCG_TARGET_HAS_rem_i64) {
25c4d9cc 1385 tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
ca675f46
RH		 1386 } else if (TCG_TARGET_HAS_div_i64) {
1387 TCGv_i64 t0 = tcg_temp_new_i64();
1388 tcg_gen_op3_i64(INDEX_op_div_i64, t0, arg1, arg2);
1389 tcg_gen_mul_i64(t0, t0, arg2);
1390 tcg_gen_sub_i64(ret, arg1, t0);
1391 tcg_temp_free_i64(t0);
25c4d9cc
RH		 1392 } else if (TCG_TARGET_HAS_div2_i64) {
1393 TCGv_i64 t0 = tcg_temp_new_i64();
1394 tcg_gen_sari_i64(t0, arg1, 63);
1395 tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1396 tcg_temp_free_i64(t0);
1397 } else {
1398 int sizemask = 0;
1399 /* Return value and both arguments are 64-bit and signed. */
1400 sizemask |= tcg_gen_sizemask(0, 1, 1);
1401 sizemask |= tcg_gen_sizemask(1, 1, 1);
1402 sizemask |= tcg_gen_sizemask(2, 1, 1);
1403 tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1404 }
31d66551
AJ		 1405}
1406
1407static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1408{
25c4d9cc
RH		 1409 if (TCG_TARGET_HAS_div_i64) {
1410 tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1411 } else if (TCG_TARGET_HAS_div2_i64) {
1412 TCGv_i64 t0 = tcg_temp_new_i64();
1413 tcg_gen_movi_i64(t0, 0);
1414 tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1415 tcg_temp_free_i64(t0);
1416 } else {
1417 int sizemask = 0;
1418 /* Return value and both arguments are 64-bit and unsigned. */
1419 sizemask |= tcg_gen_sizemask(0, 1, 0);
1420 sizemask |= tcg_gen_sizemask(1, 1, 0);
1421 sizemask |= tcg_gen_sizemask(2, 1, 0);
1422 tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1423 }
31d66551
AJ		 1424}
1425
1426static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1427{
ca675f46 1428 if (TCG_TARGET_HAS_rem_i64) {
25c4d9cc 1429 tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
ca675f46
RH		 1430 } else if (TCG_TARGET_HAS_div_i64) {
1431 TCGv_i64 t0 = tcg_temp_new_i64();
1432 tcg_gen_op3_i64(INDEX_op_divu_i64, t0, arg1, arg2);
1433 tcg_gen_mul_i64(t0, t0, arg2);
1434 tcg_gen_sub_i64(ret, arg1, t0);
1435 tcg_temp_free_i64(t0);
25c4d9cc
RH		 1436 } else if (TCG_TARGET_HAS_div2_i64) {
1437 TCGv_i64 t0 = tcg_temp_new_i64();
1438 tcg_gen_movi_i64(t0, 0);
1439 tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1440 tcg_temp_free_i64(t0);
1441 } else {
1442 int sizemask = 0;
1443 /* Return value and both arguments are 64-bit and unsigned. */
1444 sizemask |= tcg_gen_sizemask(0, 1, 0);
1445 sizemask |= tcg_gen_sizemask(1, 1, 0);
1446 sizemask |= tcg_gen_sizemask(2, 1, 0);
1447 tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1448 }
31d66551 1449}
25c4d9cc 1450#endif /* TCG_TARGET_REG_BITS == 32 */
c896fe29 1451
a7812ae4 1452static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
6359706f
AJ		 1453{
1454 /* some cases can be optimized here */
1455 if (arg2 == 0) {
1456 tcg_gen_mov_i64(ret, arg1);
1457 } else {
a7812ae4 1458 TCGv_i64 t0 = tcg_const_i64(arg2);
6359706f 1459 tcg_gen_add_i64(ret, arg1, t0);
a7812ae4 1460 tcg_temp_free_i64(t0);
6359706f
AJ		 1461 }
1462}
1463
a7812ae4 1464static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
0045734a 1465{
a7812ae4 1466 TCGv_i64 t0 = tcg_const_i64(arg1);
0045734a 1467 tcg_gen_sub_i64(ret, t0, arg2);
a7812ae4 1468 tcg_temp_free_i64(t0);
0045734a
AJ		 1469}
1470
a7812ae4 1471static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
6359706f
AJ		 1472{
1473 /* some cases can be optimized here */
1474 if (arg2 == 0) {
1475 tcg_gen_mov_i64(ret, arg1);
1476 } else {
a7812ae4 1477 TCGv_i64 t0 = tcg_const_i64(arg2);
6359706f 1478 tcg_gen_sub_i64(ret, arg1, t0);
a7812ae4 1479 tcg_temp_free_i64(t0);
6359706f
AJ		 1480 }
1481}
8a56e840
RH		 1482static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1,
1483 int64_t arg2, int label_index)
f02bb954 1484{
0aed257f
RH		 1485 if (cond == TCG_COND_ALWAYS) {
1486 tcg_gen_br(label_index);
1487 } else if (cond != TCG_COND_NEVER) {
1488 TCGv_i64 t0 = tcg_const_i64(arg2);
1489 tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1490 tcg_temp_free_i64(t0);
1491 }
f02bb954
AJ		 1492}
1493
8a56e840
RH		 1494static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1495 TCGv_i64 arg1, int64_t arg2)
5105c556
AJ		 1496{
1497 TCGv_i64 t0 = tcg_const_i64(arg2);
1498 tcg_gen_setcond_i64(cond, ret, arg1, t0);
1499 tcg_temp_free_i64(t0);
1500}
1501
a7812ae4 1502static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
f02bb954 1503{
a7812ae4 1504 TCGv_i64 t0 = tcg_const_i64(arg2);
f02bb954 1505 tcg_gen_mul_i64(ret, arg1, t0);
a7812ae4 1506 tcg_temp_free_i64(t0);
f02bb954
AJ		 1507}
1508
6359706f 1509
c896fe29
FB		 1510/***************************************/
1511/* optional operations */
1512
a7812ae4 1513static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 1514{
25c4d9cc
RH		 1515 if (TCG_TARGET_HAS_ext8s_i32) {
1516 tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1517 } else {
1518 tcg_gen_shli_i32(ret, arg, 24);
1519 tcg_gen_sari_i32(ret, ret, 24);
1520 }
c896fe29
FB		 1521}
1522
a7812ae4 1523static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 1524{
25c4d9cc
RH		 1525 if (TCG_TARGET_HAS_ext16s_i32) {
1526 tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1527 } else {
1528 tcg_gen_shli_i32(ret, arg, 16);
1529 tcg_gen_sari_i32(ret, ret, 16);
1530 }
c896fe29
FB		 1531}
1532
a7812ae4 1533static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
86831435 1534{
25c4d9cc
RH		 1535 if (TCG_TARGET_HAS_ext8u_i32) {
1536 tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg);
1537 } else {
1538 tcg_gen_andi_i32(ret, arg, 0xffu);
1539 }
86831435
PB		 1540}
1541
a7812ae4 1542static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
86831435 1543{
25c4d9cc
RH		 1544 if (TCG_TARGET_HAS_ext16u_i32) {
1545 tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg);
1546 } else {
1547 tcg_gen_andi_i32(ret, arg, 0xffffu);
1548 }
86831435
PB		 1549}
1550
c896fe29 1551/* Note: we assume the two high bytes are set to zero */
a7812ae4 1552static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 1553{
25c4d9cc
RH		 1554 if (TCG_TARGET_HAS_bswap16_i32) {
1555 tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1556 } else {
1557 TCGv_i32 t0 = tcg_temp_new_i32();
c896fe29 1558
25c4d9cc
RH		 1559 tcg_gen_ext8u_i32(t0, arg);
1560 tcg_gen_shli_i32(t0, t0, 8);
1561 tcg_gen_shri_i32(ret, arg, 8);
1562 tcg_gen_or_i32(ret, ret, t0);
1563 tcg_temp_free_i32(t0);
1564 }
c896fe29
FB		 1565}
1566
66896cb8 1567static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 1568{
25c4d9cc
RH		 1569 if (TCG_TARGET_HAS_bswap32_i32) {
1570 tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1571 } else {
1572 TCGv_i32 t0, t1;
1573 t0 = tcg_temp_new_i32();
1574 t1 = tcg_temp_new_i32();
c896fe29 1575
25c4d9cc 1576 tcg_gen_shli_i32(t0, arg, 24);
c896fe29 1577
25c4d9cc
RH		 1578 tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1579 tcg_gen_shli_i32(t1, t1, 8);
1580 tcg_gen_or_i32(t0, t0, t1);
c896fe29 1581
25c4d9cc
RH		 1582 tcg_gen_shri_i32(t1, arg, 8);
1583 tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1584 tcg_gen_or_i32(t0, t0, t1);
c896fe29 1585
25c4d9cc
RH		 1586 tcg_gen_shri_i32(t1, arg, 24);
1587 tcg_gen_or_i32(ret, t0, t1);
1588 tcg_temp_free_i32(t0);
1589 tcg_temp_free_i32(t1);
1590 }
c896fe29
FB		 1591}
1592
1593#if TCG_TARGET_REG_BITS == 32
a7812ae4 1594static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1595{
a7812ae4
PB		 1596 tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1597 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
c896fe29
FB		 1598}
1599
a7812ae4 1600static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1601{
a7812ae4
PB		 1602 tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1603 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
c896fe29
FB		 1604}
1605
a7812ae4 1606static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1607{
a7812ae4
PB		 1608 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1609 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
c896fe29
FB		 1610}
1611
a7812ae4 1612static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
86831435 1613{
a7812ae4 1614 tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
86831435
PB		 1615 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1616}
1617
a7812ae4 1618static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
86831435 1619{
a7812ae4 1620 tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
86831435
PB		 1621 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1622}
1623
a7812ae4 1624static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
86831435 1625{
a7812ae4 1626 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
86831435
PB		 1627 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1628}
1629
a7812ae4 1630static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
c896fe29 1631{
a7812ae4 1632 tcg_gen_mov_i32(ret, TCGV_LOW(arg));
c896fe29
FB		 1633}
1634
a7812ae4 1635static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
c896fe29 1636{
a7812ae4 1637 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
ac56dd48 1638 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
c896fe29
FB		 1639}
1640
a7812ae4 1641static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
c896fe29 1642{
a7812ae4
PB		 1643 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1644 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
c896fe29
FB		 1645}
1646
9a5c57fd
AJ		 1647/* Note: we assume the six high bytes are set to zero */
1648static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1649{
1650 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1651 tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1652}
1653
1654/* Note: we assume the four high bytes are set to zero */
1655static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1656{
1657 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1658 tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1659}
1660
66896cb8 1661static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1662{
a7812ae4
PB		 1663 TCGv_i32 t0, t1;
1664 t0 = tcg_temp_new_i32();
1665 t1 = tcg_temp_new_i32();
c896fe29 1666
66896cb8
AJ		 1667 tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1668 tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
a7812ae4 1669 tcg_gen_mov_i32(TCGV_LOW(ret), t1);
ac56dd48 1670 tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
a7812ae4
PB		 1671 tcg_temp_free_i32(t0);
1672 tcg_temp_free_i32(t1);
c896fe29
FB		 1673}
1674#else
1675
a7812ae4 1676static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1677{
25c4d9cc
RH		 1678 if (TCG_TARGET_HAS_ext8s_i64) {
1679 tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1680 } else {
1681 tcg_gen_shli_i64(ret, arg, 56);
1682 tcg_gen_sari_i64(ret, ret, 56);
1683 }
c896fe29
FB		 1684}
1685
a7812ae4 1686static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1687{
25c4d9cc
RH		 1688 if (TCG_TARGET_HAS_ext16s_i64) {
1689 tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1690 } else {
1691 tcg_gen_shli_i64(ret, arg, 48);
1692 tcg_gen_sari_i64(ret, ret, 48);
1693 }
c896fe29
FB		 1694}
1695
a7812ae4 1696static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1697{
25c4d9cc
RH		 1698 if (TCG_TARGET_HAS_ext32s_i64) {
1699 tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1700 } else {
1701 tcg_gen_shli_i64(ret, arg, 32);
1702 tcg_gen_sari_i64(ret, ret, 32);
1703 }
c896fe29
FB		 1704}
1705
a7812ae4 1706static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
86831435 1707{
25c4d9cc
RH		 1708 if (TCG_TARGET_HAS_ext8u_i64) {
1709 tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg);
1710 } else {
1711 tcg_gen_andi_i64(ret, arg, 0xffu);
1712 }
86831435
PB		 1713}
1714
a7812ae4 1715static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
86831435 1716{
25c4d9cc
RH		 1717 if (TCG_TARGET_HAS_ext16u_i64) {
1718 tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg);
1719 } else {
1720 tcg_gen_andi_i64(ret, arg, 0xffffu);
1721 }
86831435
PB		 1722}
1723
a7812ae4 1724static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
86831435 1725{
25c4d9cc
RH		 1726 if (TCG_TARGET_HAS_ext32u_i64) {
1727 tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg);
1728 } else {
1729 tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1730 }
86831435
PB		 1731}
1732
c896fe29 1733/* Note: we assume the target supports move between 32 and 64 bit
ac56dd48 1734 registers. This will probably break MIPS64 targets. */
a7812ae4 1735static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
c896fe29 1736{
a7812ae4 1737 tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
c896fe29
FB		 1738}
1739
1740/* Note: we assume the target supports move between 32 and 64 bit
1741 registers */
a7812ae4 1742static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
c896fe29 1743{
cfc86988 1744 tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
c896fe29
FB		 1745}
1746
1747/* Note: we assume the target supports move between 32 and 64 bit
1748 registers */
a7812ae4 1749static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
c896fe29 1750{
a7812ae4 1751 tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
c896fe29
FB		 1752}
1753
9a5c57fd
AJ		 1754/* Note: we assume the six high bytes are set to zero */
1755static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1756{
25c4d9cc
RH		 1757 if (TCG_TARGET_HAS_bswap16_i64) {
1758 tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
1759 } else {
1760 TCGv_i64 t0 = tcg_temp_new_i64();
9a5c57fd 1761
25c4d9cc
RH		 1762 tcg_gen_ext8u_i64(t0, arg);
1763 tcg_gen_shli_i64(t0, t0, 8);
1764 tcg_gen_shri_i64(ret, arg, 8);
1765 tcg_gen_or_i64(ret, ret, t0);
1766 tcg_temp_free_i64(t0);
1767 }
9a5c57fd
AJ		 1768}
1769
1770/* Note: we assume the four high bytes are set to zero */
1771static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1772{
25c4d9cc
RH		 1773 if (TCG_TARGET_HAS_bswap32_i64) {
1774 tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
1775 } else {
1776 TCGv_i64 t0, t1;
1777 t0 = tcg_temp_new_i64();
1778 t1 = tcg_temp_new_i64();
9a5c57fd 1779
25c4d9cc
RH		 1780 tcg_gen_shli_i64(t0, arg, 24);
1781 tcg_gen_ext32u_i64(t0, t0);
9a5c57fd 1782
25c4d9cc
RH		 1783 tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1784 tcg_gen_shli_i64(t1, t1, 8);
1785 tcg_gen_or_i64(t0, t0, t1);
9a5c57fd 1786
25c4d9cc
RH		 1787 tcg_gen_shri_i64(t1, arg, 8);
1788 tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1789 tcg_gen_or_i64(t0, t0, t1);
9a5c57fd 1790
25c4d9cc
RH		 1791 tcg_gen_shri_i64(t1, arg, 24);
1792 tcg_gen_or_i64(ret, t0, t1);
1793 tcg_temp_free_i64(t0);
1794 tcg_temp_free_i64(t1);
1795 }
9a5c57fd
AJ		 1796}
1797
66896cb8 1798static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1799{
25c4d9cc
RH		 1800 if (TCG_TARGET_HAS_bswap64_i64) {
1801 tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1802 } else {
1803 TCGv_i64 t0 = tcg_temp_new_i64();
1804 TCGv_i64 t1 = tcg_temp_new_i64();
c896fe29 1805
25c4d9cc 1806 tcg_gen_shli_i64(t0, arg, 56);
c896fe29 1807
25c4d9cc
RH		 1808 tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1809 tcg_gen_shli_i64(t1, t1, 40);
1810 tcg_gen_or_i64(t0, t0, t1);
c896fe29 1811
25c4d9cc
RH		 1812 tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1813 tcg_gen_shli_i64(t1, t1, 24);
1814 tcg_gen_or_i64(t0, t0, t1);
c896fe29 1815
25c4d9cc
RH		 1816 tcg_gen_andi_i64(t1, arg, 0xff000000);
1817 tcg_gen_shli_i64(t1, t1, 8);
1818 tcg_gen_or_i64(t0, t0, t1);
c896fe29 1819
25c4d9cc
RH		 1820 tcg_gen_shri_i64(t1, arg, 8);
1821 tcg_gen_andi_i64(t1, t1, 0xff000000);
1822 tcg_gen_or_i64(t0, t0, t1);
c896fe29 1823
25c4d9cc
RH		 1824 tcg_gen_shri_i64(t1, arg, 24);
1825 tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1826 tcg_gen_or_i64(t0, t0, t1);
c896fe29 1827
25c4d9cc
RH		 1828 tcg_gen_shri_i64(t1, arg, 40);
1829 tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1830 tcg_gen_or_i64(t0, t0, t1);
c896fe29 1831
25c4d9cc
RH		 1832 tcg_gen_shri_i64(t1, arg, 56);
1833 tcg_gen_or_i64(ret, t0, t1);
1834 tcg_temp_free_i64(t0);
1835 tcg_temp_free_i64(t1);
1836 }
c896fe29
FB		 1837}
1838
1839#endif
1840
a7812ae4 1841static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
390efc54 1842{
25c4d9cc
RH		 1843 if (TCG_TARGET_HAS_neg_i32) {
1844 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1845 } else {
1846 TCGv_i32 t0 = tcg_const_i32(0);
1847 tcg_gen_sub_i32(ret, t0, arg);
1848 tcg_temp_free_i32(t0);
1849 }
390efc54
PB		 1850}
1851
a7812ae4 1852static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
390efc54 1853{
25c4d9cc
RH		 1854 if (TCG_TARGET_HAS_neg_i64) {
1855 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1856 } else {
1857 TCGv_i64 t0 = tcg_const_i64(0);
1858 tcg_gen_sub_i64(ret, t0, arg);
1859 tcg_temp_free_i64(t0);
1860 }
390efc54
PB		 1861}
1862
a7812ae4 1863static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
0b6ce4cf 1864{
25c4d9cc
RH		 1865 if (TCG_TARGET_HAS_not_i32) {
1866 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1867 } else {
1868 tcg_gen_xori_i32(ret, arg, -1);
1869 }
0b6ce4cf
FB		 1870}
1871
a7812ae4 1872static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
0b6ce4cf 1873{
25c4d9cc
RH		 1874#if TCG_TARGET_REG_BITS == 64
1875 if (TCG_TARGET_HAS_not_i64) {
1876 tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1877 } else {
1878 tcg_gen_xori_i64(ret, arg, -1);
1879 }
1880#else
a10f9f4f
RH		 1881 tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1882 tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
d2604285 1883#endif
0b6ce4cf 1884}
5ff9d6a4 1885
a7812ae4 1886static inline void tcg_gen_discard_i32(TCGv_i32 arg)
5ff9d6a4 1887{
a7812ae4 1888 tcg_gen_op1_i32(INDEX_op_discard, arg);
5ff9d6a4
FB		 1889}
1890
a7812ae4 1891static inline void tcg_gen_discard_i64(TCGv_i64 arg)
5ff9d6a4 1892{
25c4d9cc 1893#if TCG_TARGET_REG_BITS == 32
a7812ae4 1894 tcg_gen_discard_i32(TCGV_LOW(arg));
5ff9d6a4 1895 tcg_gen_discard_i32(TCGV_HIGH(arg));
5ff9d6a4 1896#else
a7812ae4 1897 tcg_gen_op1_i64(INDEX_op_discard, arg);
5ff9d6a4 1898#endif
25c4d9cc 1899}
5ff9d6a4 1900
a7812ae4 1901static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
f24cb33e 1902{
25c4d9cc
RH		 1903 if (TCG_TARGET_HAS_andc_i32) {
1904 tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
1905 } else {
1906 TCGv_i32 t0 = tcg_temp_new_i32();
1907 tcg_gen_not_i32(t0, arg2);
1908 tcg_gen_and_i32(ret, arg1, t0);
1909 tcg_temp_free_i32(t0);
1910 }
f24cb33e
AJ		 1911}
1912
a7812ae4 1913static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
f24cb33e 1914{
25c4d9cc
RH		 1915#if TCG_TARGET_REG_BITS == 64
1916 if (TCG_TARGET_HAS_andc_i64) {
1917 tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
1918 } else {
1919 TCGv_i64 t0 = tcg_temp_new_i64();
1920 tcg_gen_not_i64(t0, arg2);
1921 tcg_gen_and_i64(ret, arg1, t0);
1922 tcg_temp_free_i64(t0);
1923 }
1924#else
241cbed4
RH		 1925 tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1926 tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
241cbed4 1927#endif
f24cb33e
AJ		 1928}
1929
a7812ae4 1930static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
f24cb33e 1931{
25c4d9cc
RH		 1932 if (TCG_TARGET_HAS_eqv_i32) {
1933 tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2);
1934 } else {
1935 tcg_gen_xor_i32(ret, arg1, arg2);
1936 tcg_gen_not_i32(ret, ret);
1937 }
f24cb33e
AJ		 1938}
1939
a7812ae4 1940static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
f24cb33e 1941{
25c4d9cc
RH		 1942#if TCG_TARGET_REG_BITS == 64
1943 if (TCG_TARGET_HAS_eqv_i64) {
1944 tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2);
1945 } else {
1946 tcg_gen_xor_i64(ret, arg1, arg2);
1947 tcg_gen_not_i64(ret, ret);
1948 }
1949#else
8d625cf1
RH		 1950 tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1951 tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
8d625cf1 1952#endif
f24cb33e
AJ		 1953}
1954
a7812ae4 1955static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
f24cb33e 1956{
25c4d9cc
RH		 1957 if (TCG_TARGET_HAS_nand_i32) {
1958 tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
1959 } else {
1960 tcg_gen_and_i32(ret, arg1, arg2);
1961 tcg_gen_not_i32(ret, ret);
1962 }
f24cb33e
AJ		 1963}
1964
a7812ae4 1965static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
f24cb33e 1966{
25c4d9cc
RH		 1967#if TCG_TARGET_REG_BITS == 64
1968 if (TCG_TARGET_HAS_nand_i64) {
1969 tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
1970 } else {
1971 tcg_gen_and_i64(ret, arg1, arg2);
1972 tcg_gen_not_i64(ret, ret);
1973 }
1974#else
9940a96b
RH		 1975 tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1976 tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
9940a96b 1977#endif
f24cb33e
AJ		 1978}
1979
a7812ae4 1980static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
f24cb33e 1981{
25c4d9cc
RH		 1982 if (TCG_TARGET_HAS_nor_i32) {
1983 tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2);
1984 } else {
1985 tcg_gen_or_i32(ret, arg1, arg2);
1986 tcg_gen_not_i32(ret, ret);
1987 }
f24cb33e
AJ		 1988}
1989
a7812ae4 1990static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
f24cb33e 1991{
25c4d9cc
RH		 1992#if TCG_TARGET_REG_BITS == 64
1993 if (TCG_TARGET_HAS_nor_i64) {
1994 tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2);
1995 } else {
1996 tcg_gen_or_i64(ret, arg1, arg2);
1997 tcg_gen_not_i64(ret, ret);
1998 }
1999#else
32d98fbd
RH		 2000 tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
2001 tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
32d98fbd 2002#endif
f24cb33e
AJ		 2003}
2004
a7812ae4 2005static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
f24cb33e 2006{
25c4d9cc
RH		 2007 if (TCG_TARGET_HAS_orc_i32) {
2008 tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
2009 } else {
2010 TCGv_i32 t0 = tcg_temp_new_i32();
2011 tcg_gen_not_i32(t0, arg2);
2012 tcg_gen_or_i32(ret, arg1, t0);
2013 tcg_temp_free_i32(t0);
2014 }
f24cb33e
AJ		 2015}
2016
a7812ae4 2017static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
f24cb33e 2018{
25c4d9cc
RH		 2019#if TCG_TARGET_REG_BITS == 64
2020 if (TCG_TARGET_HAS_orc_i64) {
2021 tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
2022 } else {
2023 TCGv_i64 t0 = tcg_temp_new_i64();
2024 tcg_gen_not_i64(t0, arg2);
2025 tcg_gen_or_i64(ret, arg1, t0);
2026 tcg_temp_free_i64(t0);
2027 }
2028#else
791d1262
RH		 2029 tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
2030 tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
791d1262 2031#endif
f24cb33e
AJ		 2032}
2033
a7812ae4 2034static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
15824571 2035{
25c4d9cc
RH		 2036 if (TCG_TARGET_HAS_rot_i32) {
2037 tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
2038 } else {
2039 TCGv_i32 t0, t1;
15824571 2040
25c4d9cc
RH		 2041 t0 = tcg_temp_new_i32();
2042 t1 = tcg_temp_new_i32();
2043 tcg_gen_shl_i32(t0, arg1, arg2);
2044 tcg_gen_subfi_i32(t1, 32, arg2);
2045 tcg_gen_shr_i32(t1, arg1, t1);
2046 tcg_gen_or_i32(ret, t0, t1);
2047 tcg_temp_free_i32(t0);
2048 tcg_temp_free_i32(t1);
2049 }
15824571
AJ		 2050}
2051
a7812ae4 2052static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
15824571 2053{
25c4d9cc
RH		 2054 if (TCG_TARGET_HAS_rot_i64) {
2055 tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
2056 } else {
2057 TCGv_i64 t0, t1;
2058 t0 = tcg_temp_new_i64();
2059 t1 = tcg_temp_new_i64();
2060 tcg_gen_shl_i64(t0, arg1, arg2);
2061 tcg_gen_subfi_i64(t1, 64, arg2);
2062 tcg_gen_shr_i64(t1, arg1, t1);
2063 tcg_gen_or_i64(ret, t0, t1);
2064 tcg_temp_free_i64(t0);
2065 tcg_temp_free_i64(t1);
2066 }
15824571
AJ		 2067}
2068
a7812ae4 2069static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
15824571
AJ		 2070{
2071 /* some cases can be optimized here */
2072 if (arg2 == 0) {
2073 tcg_gen_mov_i32(ret, arg1);
25c4d9cc 2074 } else if (TCG_TARGET_HAS_rot_i32) {
d42f183c
AJ		 2075 TCGv_i32 t0 = tcg_const_i32(arg2);
2076 tcg_gen_rotl_i32(ret, arg1, t0);
2077 tcg_temp_free_i32(t0);
25c4d9cc 2078 } else {
a7812ae4
PB		 2079 TCGv_i32 t0, t1;
2080 t0 = tcg_temp_new_i32();
2081 t1 = tcg_temp_new_i32();
15824571
AJ		 2082 tcg_gen_shli_i32(t0, arg1, arg2);
2083 tcg_gen_shri_i32(t1, arg1, 32 - arg2);
2084 tcg_gen_or_i32(ret, t0, t1);
a7812ae4
PB		 2085 tcg_temp_free_i32(t0);
2086 tcg_temp_free_i32(t1);
15824571
AJ		 2087 }
2088}
2089
a7812ae4 2090static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
15824571
AJ		 2091{
2092 /* some cases can be optimized here */
2093 if (arg2 == 0) {
2094 tcg_gen_mov_i64(ret, arg1);
25c4d9cc 2095 } else if (TCG_TARGET_HAS_rot_i64) {
d42f183c
AJ		 2096 TCGv_i64 t0 = tcg_const_i64(arg2);
2097 tcg_gen_rotl_i64(ret, arg1, t0);
2098 tcg_temp_free_i64(t0);
25c4d9cc 2099 } else {
a7812ae4
PB		 2100 TCGv_i64 t0, t1;
2101 t0 = tcg_temp_new_i64();
2102 t1 = tcg_temp_new_i64();
15824571
AJ		 2103 tcg_gen_shli_i64(t0, arg1, arg2);
2104 tcg_gen_shri_i64(t1, arg1, 64 - arg2);
2105 tcg_gen_or_i64(ret, t0, t1);
a7812ae4
PB		 2106 tcg_temp_free_i64(t0);
2107 tcg_temp_free_i64(t1);
15824571
AJ		 2108 }
2109}
2110
a7812ae4 2111static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
15824571 2112{
25c4d9cc
RH		 2113 if (TCG_TARGET_HAS_rot_i32) {
2114 tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
2115 } else {
2116 TCGv_i32 t0, t1;
15824571 2117
25c4d9cc
RH		 2118 t0 = tcg_temp_new_i32();
2119 t1 = tcg_temp_new_i32();
2120 tcg_gen_shr_i32(t0, arg1, arg2);
2121 tcg_gen_subfi_i32(t1, 32, arg2);
2122 tcg_gen_shl_i32(t1, arg1, t1);
2123 tcg_gen_or_i32(ret, t0, t1);
2124 tcg_temp_free_i32(t0);
2125 tcg_temp_free_i32(t1);
2126 }
15824571
AJ		 2127}
2128
a7812ae4 2129static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
15824571 2130{
25c4d9cc
RH		 2131 if (TCG_TARGET_HAS_rot_i64) {
2132 tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
2133 } else {
2134 TCGv_i64 t0, t1;
2135 t0 = tcg_temp_new_i64();
2136 t1 = tcg_temp_new_i64();
2137 tcg_gen_shr_i64(t0, arg1, arg2);
2138 tcg_gen_subfi_i64(t1, 64, arg2);
2139 tcg_gen_shl_i64(t1, arg1, t1);
2140 tcg_gen_or_i64(ret, t0, t1);
2141 tcg_temp_free_i64(t0);
2142 tcg_temp_free_i64(t1);
2143 }
15824571
AJ		 2144}
2145
a7812ae4 2146static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
15824571
AJ		 2147{
2148 /* some cases can be optimized here */
2149 if (arg2 == 0) {
2150 tcg_gen_mov_i32(ret, arg1);
2151 } else {
2152 tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
2153 }
2154}
2155
a7812ae4 2156static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
15824571
AJ		 2157{
2158 /* some cases can be optimized here */
2159 if (arg2 == 0) {
de3526b2 2160 tcg_gen_mov_i64(ret, arg1);
15824571
AJ		 2161 } else {
2162 tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
2163 }
2164}
2165
b7767f0f 2166static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
0756e71c
RH		 2167 TCGv_i32 arg2, unsigned int ofs,
2168 unsigned int len)
b7767f0f 2169{
df072774
RH		 2170 uint32_t mask;
2171 TCGv_i32 t1;
2172
717e7036
RH		 2173 tcg_debug_assert(ofs < 32);
2174 tcg_debug_assert(len <= 32);
2175 tcg_debug_assert(ofs + len <= 32);
2176
df072774
RH		 2177 if (ofs == 0 && len == 32) {
2178 tcg_gen_mov_i32(ret, arg2);
2179 return;
2180 }
a4773324 2181 if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) {
25c4d9cc 2182 tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
df072774
RH		 2183 return;
2184 }
2185
2186 mask = (1u << len) - 1;
2187 t1 = tcg_temp_new_i32();
b7767f0f 2188
df072774 2189 if (ofs + len < 32) {
25c4d9cc
RH		 2190 tcg_gen_andi_i32(t1, arg2, mask);
2191 tcg_gen_shli_i32(t1, t1, ofs);
df072774
RH		 2192 } else {
2193 tcg_gen_shli_i32(t1, arg2, ofs);
25c4d9cc 2194 }
df072774
RH		 2195 tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
2196 tcg_gen_or_i32(ret, ret, t1);
2197
2198 tcg_temp_free_i32(t1);
b7767f0f
RH		 2199}
2200
2201static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
0756e71c
RH		 2202 TCGv_i64 arg2, unsigned int ofs,
2203 unsigned int len)
b7767f0f 2204{
df072774
RH		 2205 uint64_t mask;
2206 TCGv_i64 t1;
2207
717e7036
RH		 2208 tcg_debug_assert(ofs < 64);
2209 tcg_debug_assert(len <= 64);
2210 tcg_debug_assert(ofs + len <= 64);
2211
df072774
RH		 2212 if (ofs == 0 && len == 64) {
2213 tcg_gen_mov_i64(ret, arg2);
2214 return;
2215 }
a4773324 2216 if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) {
25c4d9cc 2217 tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
df072774
RH		 2218 return;
2219 }
b7767f0f 2220
df072774
RH		 2221#if TCG_TARGET_REG_BITS == 32
2222 if (ofs >= 32) {
2223 tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1),
2224 TCGV_LOW(arg2), ofs - 32, len);
ed605126 2225 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
df072774
RH		 2226 return;
2227 }
2228 if (ofs + len <= 32) {
2229 tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1),
2230 TCGV_LOW(arg2), ofs, len);
2f98c9db 2231 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
df072774
RH		 2232 return;
2233 }
2234#endif
2235
2236 mask = (1ull << len) - 1;
2237 t1 = tcg_temp_new_i64();
2238
2239 if (ofs + len < 64) {
25c4d9cc
RH		 2240 tcg_gen_andi_i64(t1, arg2, mask);
2241 tcg_gen_shli_i64(t1, t1, ofs);
df072774
RH		 2242 } else {
2243 tcg_gen_shli_i64(t1, arg2, ofs);
25c4d9cc 2244 }
df072774
RH		 2245 tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
2246 tcg_gen_or_i64(ret, ret, t1);
2247
2248 tcg_temp_free_i64(t1);
b7767f0f
RH		 2249}
2250
77276f65
RH		 2251static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low,
2252 TCGv_i32 high)
2253{
2254#if TCG_TARGET_REG_BITS == 32
2255 tcg_gen_mov_i32(TCGV_LOW(dest), low);
2256 tcg_gen_mov_i32(TCGV_HIGH(dest), high);
2257#else
2258 TCGv_i64 tmp = tcg_temp_new_i64();
2259 /* These extensions are only needed for type correctness.
2260 We may be able to do better given target specific information. */
2261 tcg_gen_extu_i32_i64(tmp, high);
2262 tcg_gen_extu_i32_i64(dest, low);
2263 /* If deposit is available, use it. Otherwise use the extra
2264 knowledge that we have of the zero-extensions above. */
2265 if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(32, 32)) {
2266 tcg_gen_deposit_i64(dest, dest, tmp, 32, 32);
2267 } else {
2268 tcg_gen_shli_i64(tmp, tmp, 32);
2269 tcg_gen_or_i64(dest, dest, tmp);
2270 }
2271 tcg_temp_free_i64(tmp);
2272#endif
2273}
2274
2275static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low,
2276 TCGv_i64 high)
2277{
2278 tcg_gen_deposit_i64(dest, low, high, 32, 32);
2279}
2280
3c51a985
RH		 2281static inline void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg)
2282{
2283#if TCG_TARGET_REG_BITS == 32
2284 tcg_gen_mov_i32(lo, TCGV_LOW(arg));
2285 tcg_gen_mov_i32(hi, TCGV_HIGH(arg));
2286#else
2287 TCGv_i64 t0 = tcg_temp_new_i64();
2288 tcg_gen_trunc_i64_i32(lo, arg);
2289 tcg_gen_shri_i64(t0, arg, 32);
2290 tcg_gen_trunc_i64_i32(hi, t0);
2291 tcg_temp_free_i64(t0);
2292#endif
2293}
2294
2295static inline void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg)
2296{
2297 tcg_gen_ext32u_i64(lo, arg);
2298 tcg_gen_shri_i64(hi, arg, 32);
2299}
2300
ffc5ea09
RH		 2301static inline void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret,
2302 TCGv_i32 c1, TCGv_i32 c2,
2303 TCGv_i32 v1, TCGv_i32 v2)
2304{
2305 if (TCG_TARGET_HAS_movcond_i32) {
2306 tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond);
2307 } else {
2308 TCGv_i32 t0 = tcg_temp_new_i32();
2309 TCGv_i32 t1 = tcg_temp_new_i32();
2310 tcg_gen_setcond_i32(cond, t0, c1, c2);
2311 tcg_gen_neg_i32(t0, t0);
2312 tcg_gen_and_i32(t1, v1, t0);
2313 tcg_gen_andc_i32(ret, v2, t0);
2314 tcg_gen_or_i32(ret, ret, t1);
2315 tcg_temp_free_i32(t0);
2316 tcg_temp_free_i32(t1);
2317 }
2318}
2319
2320static inline void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret,
2321 TCGv_i64 c1, TCGv_i64 c2,
2322 TCGv_i64 v1, TCGv_i64 v2)
2323{
a463133e
RH		 2324#if TCG_TARGET_REG_BITS == 32
2325 TCGv_i32 t0 = tcg_temp_new_i32();
2326 TCGv_i32 t1 = tcg_temp_new_i32();
2327 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0,
2328 TCGV_LOW(c1), TCGV_HIGH(c1),
2329 TCGV_LOW(c2), TCGV_HIGH(c2), cond);
a463133e 2330
a80a6b63
RH		 2331 if (TCG_TARGET_HAS_movcond_i32) {
2332 tcg_gen_movi_i32(t1, 0);
2333 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, t1,
2334 TCGV_LOW(v1), TCGV_LOW(v2));
2335 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, t1,
2336 TCGV_HIGH(v1), TCGV_HIGH(v2));
2337 } else {
2338 tcg_gen_neg_i32(t0, t0);
a463133e 2339
a80a6b63
RH		 2340 tcg_gen_and_i32(t1, TCGV_LOW(v1), t0);
2341 tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0);
2342 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1);
a463133e 2343
a80a6b63
RH		 2344 tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0);
2345 tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0);
2346 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1);
2347 }
a463133e
RH		 2348 tcg_temp_free_i32(t0);
2349 tcg_temp_free_i32(t1);
2350#else
ffc5ea09
RH		 2351 if (TCG_TARGET_HAS_movcond_i64) {
2352 tcg_gen_op6i_i64(INDEX_op_movcond_i64, ret, c1, c2, v1, v2, cond);
2353 } else {
2354 TCGv_i64 t0 = tcg_temp_new_i64();
2355 TCGv_i64 t1 = tcg_temp_new_i64();
2356 tcg_gen_setcond_i64(cond, t0, c1, c2);
2357 tcg_gen_neg_i64(t0, t0);
2358 tcg_gen_and_i64(t1, v1, t0);
2359 tcg_gen_andc_i64(ret, v2, t0);
2360 tcg_gen_or_i64(ret, ret, t1);
2361 tcg_temp_free_i64(t0);
2362 tcg_temp_free_i64(t1);
2363 }
a463133e 2364#endif
ffc5ea09
RH		 2365}
2366
f6953a73
RH		 2367static inline void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
2368 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh)
2369{
2370 if (TCG_TARGET_HAS_add2_i32) {
2371 tcg_gen_op6_i32(INDEX_op_add2_i32, rl, rh, al, ah, bl, bh);
2372 /* Allow the optimizer room to replace add2 with two moves. */
2373 tcg_gen_op0(INDEX_op_nop);
2374 } else {
2375 TCGv_i64 t0 = tcg_temp_new_i64();
2376 TCGv_i64 t1 = tcg_temp_new_i64();
2377 tcg_gen_concat_i32_i64(t0, al, ah);
2378 tcg_gen_concat_i32_i64(t1, bl, bh);
2379 tcg_gen_add_i64(t0, t0, t1);
2380 tcg_gen_extr_i64_i32(rl, rh, t0);
2381 tcg_temp_free_i64(t0);
2382 tcg_temp_free_i64(t1);
2383 }
2384}
2385
2386static inline void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
2387 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh)
2388{
2389 if (TCG_TARGET_HAS_sub2_i32) {
2390 tcg_gen_op6_i32(INDEX_op_sub2_i32, rl, rh, al, ah, bl, bh);
2391 /* Allow the optimizer room to replace sub2 with two moves. */
2392 tcg_gen_op0(INDEX_op_nop);
2393 } else {
2394 TCGv_i64 t0 = tcg_temp_new_i64();
2395 TCGv_i64 t1 = tcg_temp_new_i64();
2396 tcg_gen_concat_i32_i64(t0, al, ah);
2397 tcg_gen_concat_i32_i64(t1, bl, bh);
2398 tcg_gen_sub_i64(t0, t0, t1);
2399 tcg_gen_extr_i64_i32(rl, rh, t0);
2400 tcg_temp_free_i64(t0);
2401 tcg_temp_free_i64(t1);
2402 }
2403}
2404
696a8be6
RH		 2405static inline void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh,
2406 TCGv_i32 arg1, TCGv_i32 arg2)
2407{
2408 if (TCG_TARGET_HAS_mulu2_i32) {
2409 tcg_gen_op4_i32(INDEX_op_mulu2_i32, rl, rh, arg1, arg2);
2410 /* Allow the optimizer room to replace mulu2 with two moves. */
2411 tcg_gen_op0(INDEX_op_nop);
03271524
RH		 2412 } else if (TCG_TARGET_HAS_muluh_i32) {
2413 TCGv_i32 t = tcg_temp_new_i32();
2414 tcg_gen_op3_i32(INDEX_op_mul_i32, t, arg1, arg2);
2415 tcg_gen_op3_i32(INDEX_op_muluh_i32, rh, arg1, arg2);
2416 tcg_gen_mov_i32(rl, t);
2417 tcg_temp_free_i32(t);
696a8be6
RH		 2418 } else {
2419 TCGv_i64 t0 = tcg_temp_new_i64();
2420 TCGv_i64 t1 = tcg_temp_new_i64();
2421 tcg_gen_extu_i32_i64(t0, arg1);
2422 tcg_gen_extu_i32_i64(t1, arg2);
2423 tcg_gen_mul_i64(t0, t0, t1);
2424 tcg_gen_extr_i64_i32(rl, rh, t0);
2425 tcg_temp_free_i64(t0);
2426 tcg_temp_free_i64(t1);
2427 }
2428}
2429
2430static inline void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh,
2431 TCGv_i32 arg1, TCGv_i32 arg2)
2432{
2433 if (TCG_TARGET_HAS_muls2_i32) {
2434 tcg_gen_op4_i32(INDEX_op_muls2_i32, rl, rh, arg1, arg2);
2435 /* Allow the optimizer room to replace muls2 with two moves. */
2436 tcg_gen_op0(INDEX_op_nop);
03271524
RH		 2437 } else if (TCG_TARGET_HAS_mulsh_i32) {
2438 TCGv_i32 t = tcg_temp_new_i32();
2439 tcg_gen_op3_i32(INDEX_op_mul_i32, t, arg1, arg2);
2440 tcg_gen_op3_i32(INDEX_op_mulsh_i32, rh, arg1, arg2);
2441 tcg_gen_mov_i32(rl, t);
2442 tcg_temp_free_i32(t);
f402f38f
RH		 2443 } else if (TCG_TARGET_REG_BITS == 32 && TCG_TARGET_HAS_mulu2_i32) {
2444 TCGv_i32 t0 = tcg_temp_new_i32();
2445 TCGv_i32 t1 = tcg_temp_new_i32();
2446 TCGv_i32 t2 = tcg_temp_new_i32();
2447 TCGv_i32 t3 = tcg_temp_new_i32();
2448 tcg_gen_op4_i32(INDEX_op_mulu2_i32, t0, t1, arg1, arg2);
2449 /* Allow the optimizer room to replace mulu2 with two moves. */
2450 tcg_gen_op0(INDEX_op_nop);
2451 /* Adjust for negative inputs. */
2452 tcg_gen_sari_i32(t2, arg1, 31);
2453 tcg_gen_sari_i32(t3, arg2, 31);
2454 tcg_gen_and_i32(t2, t2, arg2);
2455 tcg_gen_and_i32(t3, t3, arg1);
2456 tcg_gen_sub_i32(rh, t1, t2);
2457 tcg_gen_sub_i32(rh, rh, t3);
2458 tcg_gen_mov_i32(rl, t0);
2459 tcg_temp_free_i32(t0);
2460 tcg_temp_free_i32(t1);
2461 tcg_temp_free_i32(t2);
2462 tcg_temp_free_i32(t3);
696a8be6
RH		 2463 } else {
2464 TCGv_i64 t0 = tcg_temp_new_i64();
2465 TCGv_i64 t1 = tcg_temp_new_i64();
2466 tcg_gen_ext_i32_i64(t0, arg1);
2467 tcg_gen_ext_i32_i64(t1, arg2);
2468 tcg_gen_mul_i64(t0, t0, t1);
2469 tcg_gen_extr_i64_i32(rl, rh, t0);
2470 tcg_temp_free_i64(t0);
2471 tcg_temp_free_i64(t1);
2472 }
2473}
2474
f6953a73
RH		 2475static inline void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
2476 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
2477{
2478 if (TCG_TARGET_HAS_add2_i64) {
2479 tcg_gen_op6_i64(INDEX_op_add2_i64, rl, rh, al, ah, bl, bh);
2480 /* Allow the optimizer room to replace add2 with two moves. */
2481 tcg_gen_op0(INDEX_op_nop);
2482 } else {
2483 TCGv_i64 t0 = tcg_temp_new_i64();
2484 TCGv_i64 t1 = tcg_temp_new_i64();
2485 tcg_gen_add_i64(t0, al, bl);
2486 tcg_gen_setcond_i64(TCG_COND_LTU, t1, t0, al);
2487 tcg_gen_add_i64(rh, ah, bh);
2488 tcg_gen_add_i64(rh, rh, t1);
2489 tcg_gen_mov_i64(rl, t0);
2490 tcg_temp_free_i64(t0);
2491 tcg_temp_free_i64(t1);
2492 }
2493}
2494
2495static inline void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
2496 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
2497{
2498 if (TCG_TARGET_HAS_sub2_i64) {
2499 tcg_gen_op6_i64(INDEX_op_sub2_i64, rl, rh, al, ah, bl, bh);
2500 /* Allow the optimizer room to replace sub2 with two moves. */
2501 tcg_gen_op0(INDEX_op_nop);
2502 } else {
2503 TCGv_i64 t0 = tcg_temp_new_i64();
2504 TCGv_i64 t1 = tcg_temp_new_i64();
2505 tcg_gen_sub_i64(t0, al, bl);
2506 tcg_gen_setcond_i64(TCG_COND_LTU, t1, al, bl);
2507 tcg_gen_sub_i64(rh, ah, bh);
2508 tcg_gen_sub_i64(rh, rh, t1);
2509 tcg_gen_mov_i64(rl, t0);
2510 tcg_temp_free_i64(t0);
2511 tcg_temp_free_i64(t1);
2512 }
2513}
2514
696a8be6
RH		 2515static inline void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh,
2516 TCGv_i64 arg1, TCGv_i64 arg2)
2517{
2518 if (TCG_TARGET_HAS_mulu2_i64) {
2519 tcg_gen_op4_i64(INDEX_op_mulu2_i64, rl, rh, arg1, arg2);
2520 /* Allow the optimizer room to replace mulu2 with two moves. */
2521 tcg_gen_op0(INDEX_op_nop);
03271524
RH		 2522 } else if (TCG_TARGET_HAS_muluh_i64) {
2523 TCGv_i64 t = tcg_temp_new_i64();
2524 tcg_gen_op3_i64(INDEX_op_mul_i64, t, arg1, arg2);
2525 tcg_gen_op3_i64(INDEX_op_muluh_i64, rh, arg1, arg2);
2526 tcg_gen_mov_i64(rl, t);
2527 tcg_temp_free_i64(t);
f402f38f
RH		 2528 } else if (TCG_TARGET_HAS_mulu2_i64) {
2529 TCGv_i64 t0 = tcg_temp_new_i64();
2530 TCGv_i64 t1 = tcg_temp_new_i64();
2531 TCGv_i64 t2 = tcg_temp_new_i64();
2532 TCGv_i64 t3 = tcg_temp_new_i64();
2533 tcg_gen_op4_i64(INDEX_op_mulu2_i64, t0, t1, arg1, arg2);
2534 /* Allow the optimizer room to replace mulu2 with two moves. */
2535 tcg_gen_op0(INDEX_op_nop);
2536 /* Adjust for negative inputs. */
2537 tcg_gen_sari_i64(t2, arg1, 63);
2538 tcg_gen_sari_i64(t3, arg2, 63);
2539 tcg_gen_and_i64(t2, t2, arg2);
2540 tcg_gen_and_i64(t3, t3, arg1);
2541 tcg_gen_sub_i64(rh, t1, t2);
2542 tcg_gen_sub_i64(rh, rh, t3);
2543 tcg_gen_mov_i64(rl, t0);
2544 tcg_temp_free_i64(t0);
2545 tcg_temp_free_i64(t1);
2546 tcg_temp_free_i64(t2);
2547 tcg_temp_free_i64(t3);
696a8be6
RH		 2548 } else {
2549 TCGv_i64 t0 = tcg_temp_new_i64();
2550 int sizemask = 0;
2551 /* Return value and both arguments are 64-bit and unsigned. */
2552 sizemask |= tcg_gen_sizemask(0, 1, 0);
2553 sizemask |= tcg_gen_sizemask(1, 1, 0);
2554 sizemask |= tcg_gen_sizemask(2, 1, 0);
2555 tcg_gen_mul_i64(t0, arg1, arg2);
2556 tcg_gen_helper64(tcg_helper_muluh_i64, sizemask, rh, arg1, arg2);
2557 tcg_gen_mov_i64(rl, t0);
2558 tcg_temp_free_i64(t0);
2559 }
2560}
2561
2562static inline void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh,
2563 TCGv_i64 arg1, TCGv_i64 arg2)
2564{
2565 if (TCG_TARGET_HAS_muls2_i64) {
2566 tcg_gen_op4_i64(INDEX_op_muls2_i64, rl, rh, arg1, arg2);
2567 /* Allow the optimizer room to replace muls2 with two moves. */
2568 tcg_gen_op0(INDEX_op_nop);
03271524
RH		 2569 } else if (TCG_TARGET_HAS_mulsh_i64) {
2570 TCGv_i64 t = tcg_temp_new_i64();
2571 tcg_gen_op3_i64(INDEX_op_mul_i64, t, arg1, arg2);
2572 tcg_gen_op3_i64(INDEX_op_mulsh_i64, rh, arg1, arg2);
2573 tcg_gen_mov_i64(rl, t);
2574 tcg_temp_free_i64(t);
696a8be6
RH		 2575 } else {
2576 TCGv_i64 t0 = tcg_temp_new_i64();
2577 int sizemask = 0;
2578 /* Return value and both arguments are 64-bit and signed. */
2579 sizemask |= tcg_gen_sizemask(0, 1, 1);
2580 sizemask |= tcg_gen_sizemask(1, 1, 1);
2581 sizemask |= tcg_gen_sizemask(2, 1, 1);
2582 tcg_gen_mul_i64(t0, arg1, arg2);
2583 tcg_gen_helper64(tcg_helper_mulsh_i64, sizemask, rh, arg1, arg2);
2584 tcg_gen_mov_i64(rl, t0);
2585 tcg_temp_free_i64(t0);
2586 }
2587}
2588
c896fe29
FB		 2589/***************************************/
2590/* QEMU specific operations. Their type depend on the QEMU CPU
2591 type. */
2592#ifndef TARGET_LONG_BITS
2593#error must include QEMU headers
2594#endif
2595
a7812ae4
PB		 2596#if TARGET_LONG_BITS == 32
2597#define TCGv TCGv_i32
2598#define tcg_temp_new() tcg_temp_new_i32()
2599#define tcg_global_reg_new tcg_global_reg_new_i32
2600#define tcg_global_mem_new tcg_global_mem_new_i32
df9247b2 2601#define tcg_temp_local_new() tcg_temp_local_new_i32()
a7812ae4
PB		 2602#define tcg_temp_free tcg_temp_free_i32
2603#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
2604#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
2605#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
afcb92be 2606#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x)
fe75bcf7 2607#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
a7812ae4
PB		 2608#else
2609#define TCGv TCGv_i64
2610#define tcg_temp_new() tcg_temp_new_i64()
2611#define tcg_global_reg_new tcg_global_reg_new_i64
2612#define tcg_global_mem_new tcg_global_mem_new_i64
df9247b2 2613#define tcg_temp_local_new() tcg_temp_local_new_i64()
a7812ae4
PB		 2614#define tcg_temp_free tcg_temp_free_i64
2615#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
2616#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
2617#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
afcb92be 2618#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x)
fe75bcf7 2619#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
a7812ae4
PB		 2620#endif
2621
7e4597d7
FB		 2622/* debug info: write the PC of the corresponding QEMU CPU instruction */
2623static inline void tcg_gen_debug_insn_start(uint64_t pc)
2624{
2625 /* XXX: must really use a 32 bit size for TCGArg in all cases */
2626#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
bcb0126f
PB		 2627 tcg_gen_op2ii(INDEX_op_debug_insn_start,
2628 (uint32_t)(pc), (uint32_t)(pc >> 32));
7e4597d7
FB		 2629#else
2630 tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
2631#endif
2632}
2633
8cfd0495 2634static inline void tcg_gen_exit_tb(uintptr_t val)
c896fe29 2635{
ac56dd48 2636 tcg_gen_op1i(INDEX_op_exit_tb, val);
c896fe29
FB		 2637}
2638
0a209d4b
RH		 2639static inline void tcg_gen_goto_tb(unsigned idx)
2640{
2641 /* We only support two chained exits. */
2642 tcg_debug_assert(idx <= 1);
2643#ifdef CONFIG_DEBUG_TCG
2644 /* Verify that we havn't seen this numbered exit before. */
2645 tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) == 0);
2646 tcg_ctx.goto_tb_issue_mask |= 1 << idx;
2647#endif
ac56dd48 2648 tcg_gen_op1i(INDEX_op_goto_tb, idx);
c896fe29
FB		 2649}
2650
2651#if TCG_TARGET_REG_BITS == 32
ac56dd48 2652static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
c896fe29
FB		 2653{
2654#if TARGET_LONG_BITS == 32
a7812ae4 2655 tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
c896fe29 2656#else
a7812ae4
PB		 2657 tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
2658 TCGV_HIGH(addr), mem_index);
ac56dd48 2659 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
c896fe29
FB		 2660#endif
2661}
2662
ac56dd48 2663static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
c896fe29
FB		 2664{
2665#if TARGET_LONG_BITS == 32
a7812ae4 2666 tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
c896fe29 2667#else
a7812ae4
PB		 2668 tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
2669 TCGV_HIGH(addr), mem_index);
2670 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
c896fe29
FB		 2671#endif
2672}
2673
ac56dd48 2674static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
c896fe29
FB		 2675{
2676#if TARGET_LONG_BITS == 32
a7812ae4 2677 tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
c896fe29 2678#else
a7812ae4
PB		 2679 tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
2680 TCGV_HIGH(addr), mem_index);
ac56dd48 2681 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
c896fe29
FB		 2682#endif
2683}
2684
ac56dd48 2685static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
c896fe29
FB		 2686{
2687#if TARGET_LONG_BITS == 32
a7812ae4 2688 tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
c896fe29 2689#else
a7812ae4
PB		 2690 tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
2691 TCGV_HIGH(addr), mem_index);
2692 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
c896fe29
FB		 2693#endif
2694}
2695
ac56dd48 2696static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
c896fe29
FB		 2697{
2698#if TARGET_LONG_BITS == 32
86feb1c8 2699 tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
c896fe29 2700#else
86feb1c8 2701 tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
a7812ae4 2702 TCGV_HIGH(addr), mem_index);
ac56dd48 2703 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
c896fe29
FB		 2704#endif
2705}
2706
ac56dd48 2707static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
c896fe29
FB		 2708{
2709#if TARGET_LONG_BITS == 32
86feb1c8 2710 tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
c896fe29 2711#else
86feb1c8 2712 tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
a7812ae4
PB		 2713 TCGV_HIGH(addr), mem_index);
2714 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
c896fe29
FB		 2715#endif
2716}
2717
a7812ae4 2718static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
c896fe29
FB		 2719{
2720#if TARGET_LONG_BITS == 32
a7812ae4 2721 tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
c896fe29 2722#else
a7812ae4
PB		 2723 tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
2724 TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
c896fe29
FB		 2725#endif
2726}
2727
ac56dd48 2728static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
c896fe29
FB		 2729{
2730#if TARGET_LONG_BITS == 32
a7812ae4 2731 tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
c896fe29 2732#else
a7812ae4
PB		 2733 tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
2734 TCGV_HIGH(addr), mem_index);
c896fe29
FB		 2735#endif
2736}
2737
ac56dd48 2738static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
c896fe29
FB		 2739{
2740#if TARGET_LONG_BITS == 32
a7812ae4 2741 tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
c896fe29 2742#else
a7812ae4
PB		 2743 tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
2744 TCGV_HIGH(addr), mem_index);
c896fe29
FB		 2745#endif
2746}
2747
ac56dd48 2748static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
c896fe29
FB		 2749{
2750#if TARGET_LONG_BITS == 32
a7812ae4 2751 tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
c896fe29 2752#else
a7812ae4
PB		 2753 tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
2754 TCGV_HIGH(addr), mem_index);
c896fe29
FB		 2755#endif
2756}
2757
a7812ae4 2758static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
c896fe29
FB		 2759{
2760#if TARGET_LONG_BITS == 32
a7812ae4
PB		 2761 tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
2762 mem_index);
c896fe29 2763#else
a7812ae4
PB		 2764 tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
2765 TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
c896fe29
FB		 2766#endif
2767}
2768
ebecf363
PM		 2769#define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O))
2770#define tcg_gen_discard_ptr(A) tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A))
f8422f52 2771
c896fe29
FB		 2772#else /* TCG_TARGET_REG_BITS == 32 */
2773
ac56dd48 2774static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
c896fe29 2775{
a7812ae4 2776 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
c896fe29
FB		 2777}
2778
ac56dd48 2779static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
c896fe29 2780{
a7812ae4 2781 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
c896fe29
FB		 2782}
2783
ac56dd48 2784static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
c896fe29 2785{
a7812ae4 2786 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
c896fe29
FB		 2787}
2788
ac56dd48 2789static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
c896fe29 2790{
a7812ae4 2791 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
c896fe29
FB		 2792}
2793
ac56dd48 2794static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
c896fe29 2795{
3e1dbadd
RH		 2796#if TARGET_LONG_BITS == 32
2797 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2798#else
a7812ae4 2799 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
3e1dbadd 2800#endif
c896fe29
FB		 2801}
2802
ac56dd48 2803static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
c896fe29 2804{
3e1dbadd
RH		 2805#if TARGET_LONG_BITS == 32
2806 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2807#else
a7812ae4 2808 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
3e1dbadd 2809#endif
c896fe29
FB		 2810}
2811
a7812ae4 2812static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
c896fe29 2813{
a7812ae4 2814 tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
c896fe29
FB		 2815}
2816
ac56dd48 2817static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
c896fe29 2818{
a7812ae4 2819 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
c896fe29
FB		 2820}
2821
ac56dd48 2822static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
c896fe29 2823{
a7812ae4 2824 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
c896fe29
FB		 2825}
2826
ac56dd48 2827static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
c896fe29 2828{
a7812ae4 2829 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
c896fe29
FB		 2830}
2831
a7812ae4 2832static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
c896fe29 2833{
a7812ae4 2834 tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
c896fe29
FB		 2835}
2836
ebecf363
PM		 2837#define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O))
2838#define tcg_gen_discard_ptr(A) tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A))
f8422f52 2839
c896fe29 2840#endif /* TCG_TARGET_REG_BITS != 32 */
f8422f52
BS		 2841
2842#if TARGET_LONG_BITS == 64
f8422f52
BS		 2843#define tcg_gen_movi_tl tcg_gen_movi_i64
2844#define tcg_gen_mov_tl tcg_gen_mov_i64
2845#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2846#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2847#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2848#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2849#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2850#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2851#define tcg_gen_ld_tl tcg_gen_ld_i64
2852#define tcg_gen_st8_tl tcg_gen_st8_i64
2853#define tcg_gen_st16_tl tcg_gen_st16_i64
2854#define tcg_gen_st32_tl tcg_gen_st32_i64
2855#define tcg_gen_st_tl tcg_gen_st_i64
2856#define tcg_gen_add_tl tcg_gen_add_i64
2857#define tcg_gen_addi_tl tcg_gen_addi_i64
2858#define tcg_gen_sub_tl tcg_gen_sub_i64
390efc54 2859#define tcg_gen_neg_tl tcg_gen_neg_i64
10460c8a 2860#define tcg_gen_subfi_tl tcg_gen_subfi_i64
f8422f52
BS		 2861#define tcg_gen_subi_tl tcg_gen_subi_i64
2862#define tcg_gen_and_tl tcg_gen_and_i64
2863#define tcg_gen_andi_tl tcg_gen_andi_i64
2864#define tcg_gen_or_tl tcg_gen_or_i64
2865#define tcg_gen_ori_tl tcg_gen_ori_i64
2866#define tcg_gen_xor_tl tcg_gen_xor_i64
2867#define tcg_gen_xori_tl tcg_gen_xori_i64
0b6ce4cf 2868#define tcg_gen_not_tl tcg_gen_not_i64
f8422f52
BS		 2869#define tcg_gen_shl_tl tcg_gen_shl_i64
2870#define tcg_gen_shli_tl tcg_gen_shli_i64
2871#define tcg_gen_shr_tl tcg_gen_shr_i64
2872#define tcg_gen_shri_tl tcg_gen_shri_i64
2873#define tcg_gen_sar_tl tcg_gen_sar_i64
2874#define tcg_gen_sari_tl tcg_gen_sari_i64
0cf767d6 2875#define tcg_gen_brcond_tl tcg_gen_brcond_i64
cb63669a 2876#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
be210acb 2877#define tcg_gen_setcond_tl tcg_gen_setcond_i64
add1e7ea 2878#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
f730fd27
TS		 2879#define tcg_gen_mul_tl tcg_gen_mul_i64
2880#define tcg_gen_muli_tl tcg_gen_muli_i64
ab36421e
AJ		 2881#define tcg_gen_div_tl tcg_gen_div_i64
2882#define tcg_gen_rem_tl tcg_gen_rem_i64
864951af
AJ		 2883#define tcg_gen_divu_tl tcg_gen_divu_i64
2884#define tcg_gen_remu_tl tcg_gen_remu_i64
a768e4b2 2885#define tcg_gen_discard_tl tcg_gen_discard_i64
e429073d
BS		 2886#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2887#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2888#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2889#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2890#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2891#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
0b6ce4cf
FB		 2892#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2893#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2894#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2895#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2896#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2897#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
911d79ba
AJ		 2898#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2899#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2900#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
945ca823 2901#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
3c51a985 2902#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
f24cb33e
AJ		 2903#define tcg_gen_andc_tl tcg_gen_andc_i64
2904#define tcg_gen_eqv_tl tcg_gen_eqv_i64
2905#define tcg_gen_nand_tl tcg_gen_nand_i64
2906#define tcg_gen_nor_tl tcg_gen_nor_i64
2907#define tcg_gen_orc_tl tcg_gen_orc_i64
15824571
AJ		 2908#define tcg_gen_rotl_tl tcg_gen_rotl_i64
2909#define tcg_gen_rotli_tl tcg_gen_rotli_i64
2910#define tcg_gen_rotr_tl tcg_gen_rotr_i64
2911#define tcg_gen_rotri_tl tcg_gen_rotri_i64
b7767f0f 2912#define tcg_gen_deposit_tl tcg_gen_deposit_i64
a98824ac 2913#define tcg_const_tl tcg_const_i64
bdffd4a9 2914#define tcg_const_local_tl tcg_const_local_i64
ffc5ea09 2915#define tcg_gen_movcond_tl tcg_gen_movcond_i64
f6953a73
RH		 2916#define tcg_gen_add2_tl tcg_gen_add2_i64
2917#define tcg_gen_sub2_tl tcg_gen_sub2_i64
696a8be6
RH		 2918#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
2919#define tcg_gen_muls2_tl tcg_gen_muls2_i64
f8422f52 2920#else
f8422f52
BS		 2921#define tcg_gen_movi_tl tcg_gen_movi_i32
2922#define tcg_gen_mov_tl tcg_gen_mov_i32
2923#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2924#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2925#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2926#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2927#define tcg_gen_ld32u_tl tcg_gen_ld_i32
2928#define tcg_gen_ld32s_tl tcg_gen_ld_i32
2929#define tcg_gen_ld_tl tcg_gen_ld_i32
2930#define tcg_gen_st8_tl tcg_gen_st8_i32
2931#define tcg_gen_st16_tl tcg_gen_st16_i32
2932#define tcg_gen_st32_tl tcg_gen_st_i32
2933#define tcg_gen_st_tl tcg_gen_st_i32
2934#define tcg_gen_add_tl tcg_gen_add_i32
2935#define tcg_gen_addi_tl tcg_gen_addi_i32
2936#define tcg_gen_sub_tl tcg_gen_sub_i32
390efc54 2937#define tcg_gen_neg_tl tcg_gen_neg_i32
0045734a 2938#define tcg_gen_subfi_tl tcg_gen_subfi_i32
f8422f52
BS		 2939#define tcg_gen_subi_tl tcg_gen_subi_i32
2940#define tcg_gen_and_tl tcg_gen_and_i32
2941#define tcg_gen_andi_tl tcg_gen_andi_i32
2942#define tcg_gen_or_tl tcg_gen_or_i32
2943#define tcg_gen_ori_tl tcg_gen_ori_i32
2944#define tcg_gen_xor_tl tcg_gen_xor_i32
2945#define tcg_gen_xori_tl tcg_gen_xori_i32
0b6ce4cf 2946#define tcg_gen_not_tl tcg_gen_not_i32
f8422f52
BS		 2947#define tcg_gen_shl_tl tcg_gen_shl_i32
2948#define tcg_gen_shli_tl tcg_gen_shli_i32
2949#define tcg_gen_shr_tl tcg_gen_shr_i32
2950#define tcg_gen_shri_tl tcg_gen_shri_i32
2951#define tcg_gen_sar_tl tcg_gen_sar_i32
2952#define tcg_gen_sari_tl tcg_gen_sari_i32
0cf767d6 2953#define tcg_gen_brcond_tl tcg_gen_brcond_i32
cb63669a 2954#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
be210acb 2955#define tcg_gen_setcond_tl tcg_gen_setcond_i32
add1e7ea 2956#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
f730fd27
TS		 2957#define tcg_gen_mul_tl tcg_gen_mul_i32
2958#define tcg_gen_muli_tl tcg_gen_muli_i32
ab36421e
AJ		 2959#define tcg_gen_div_tl tcg_gen_div_i32
2960#define tcg_gen_rem_tl tcg_gen_rem_i32
864951af
AJ		 2961#define tcg_gen_divu_tl tcg_gen_divu_i32
2962#define tcg_gen_remu_tl tcg_gen_remu_i32
a768e4b2 2963#define tcg_gen_discard_tl tcg_gen_discard_i32
e429073d
BS		 2964#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2965#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2966#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2967#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2968#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2969#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
0b6ce4cf
FB		 2970#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2971#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2972#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2973#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2974#define tcg_gen_ext32u_tl tcg_gen_mov_i32
2975#define tcg_gen_ext32s_tl tcg_gen_mov_i32
911d79ba
AJ		 2976#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2977#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
945ca823 2978#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
3c51a985 2979#define tcg_gen_extr_tl_i64 tcg_gen_extr_i32_i64
f24cb33e
AJ		 2980#define tcg_gen_andc_tl tcg_gen_andc_i32
2981#define tcg_gen_eqv_tl tcg_gen_eqv_i32
2982#define tcg_gen_nand_tl tcg_gen_nand_i32
2983#define tcg_gen_nor_tl tcg_gen_nor_i32
2984#define tcg_gen_orc_tl tcg_gen_orc_i32
15824571
AJ		 2985#define tcg_gen_rotl_tl tcg_gen_rotl_i32
2986#define tcg_gen_rotli_tl tcg_gen_rotli_i32
2987#define tcg_gen_rotr_tl tcg_gen_rotr_i32
2988#define tcg_gen_rotri_tl tcg_gen_rotri_i32
b7767f0f 2989#define tcg_gen_deposit_tl tcg_gen_deposit_i32
a98824ac 2990#define tcg_const_tl tcg_const_i32
bdffd4a9 2991#define tcg_const_local_tl tcg_const_local_i32
ffc5ea09 2992#define tcg_gen_movcond_tl tcg_gen_movcond_i32
f6953a73
RH		 2993#define tcg_gen_add2_tl tcg_gen_add2_i32
2994#define tcg_gen_sub2_tl tcg_gen_sub2_i32
696a8be6
RH		 2995#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
2996#define tcg_gen_muls2_tl tcg_gen_muls2_i32
f8422f52 2997#endif
6ddbc6e4
PB		 2998
2999#if TCG_TARGET_REG_BITS == 32
ebecf363
PM		 3000#define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), \
3001 TCGV_PTR_TO_NAT(A), \
3002 TCGV_PTR_TO_NAT(B))
3003#define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), \
3004 TCGV_PTR_TO_NAT(A), (B))
3005#define tcg_gen_ext_i32_ptr(R, A) tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A))
6ddbc6e4 3006#else /* TCG_TARGET_REG_BITS == 32 */
ebecf363
PM		 3007#define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), \
3008 TCGV_PTR_TO_NAT(A), \
3009 TCGV_PTR_TO_NAT(B))
3010#define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), \
3011 TCGV_PTR_TO_NAT(A), (B))
3012#define tcg_gen_ext_i32_ptr(R, A) tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
6ddbc6e4 3013#endif /* TCG_TARGET_REG_BITS != 32 */
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