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Merge remote-tracking branch 'remotes/kraxel/tags/pull-usb-7' into staging
[qemu.git] / tcg / tcg-op.h
CommitLineData
c896fe29
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#include "tcg.h"
25
c896fe29
FB		 26int gen_new_label(void);
27
212c328d
RH		 28static inline void tcg_gen_op0(TCGOpcode opc)
29{
efd7f486 30 *tcg_ctx.gen_opc_ptr++ = opc;
212c328d
RH		 31}
32
a9751609 33static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1)
c896fe29 34{
efd7f486 35 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4 36 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
a7812ae4
PB		 37}
38
a9751609 39static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1)
a7812ae4 40{
efd7f486 41 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4 42 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
c896fe29
FB		 43}
44
a9751609 45static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1)
c896fe29 46{
efd7f486 47 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4 48 *tcg_ctx.gen_opparam_ptr++ = arg1;
c896fe29
FB		 49}
50
a9751609 51static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2)
a7812ae4 52{
efd7f486 53 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 54 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
55 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
a7812ae4
PB		 56}
57
a9751609 58static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2)
a7812ae4 59{
efd7f486 60 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 61 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
62 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
a7812ae4
PB		 63}
64
a9751609 65static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2)
c896fe29 66{
efd7f486 67 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 68 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
69 *tcg_ctx.gen_opparam_ptr++ = arg2;
c896fe29
FB		 70}
71
a9751609 72static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2)
c896fe29 73{
efd7f486 74 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 75 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
76 *tcg_ctx.gen_opparam_ptr++ = arg2;
ac56dd48
PB		 77}
78
a9751609 79static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2)
bcb0126f 80{
efd7f486 81 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 82 *tcg_ctx.gen_opparam_ptr++ = arg1;
83 *tcg_ctx.gen_opparam_ptr++ = arg2;
bcb0126f
PB		 84}
85
a9751609 86static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
a7812ae4
PB		 87 TCGv_i32 arg3)
88{
efd7f486 89 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 90 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
91 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
92 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
a7812ae4
PB		 93}
94
a9751609 95static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
a7812ae4
PB		 96 TCGv_i64 arg3)
97{
efd7f486 98 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 99 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
100 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
101 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
a7812ae4
PB		 102}
103
a9751609
RH		 104static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1,
105 TCGv_i32 arg2, TCGArg arg3)
ac56dd48 106{
efd7f486 107 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 108 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
109 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
110 *tcg_ctx.gen_opparam_ptr++ = arg3;
ac56dd48
PB		 111}
112
a9751609
RH		 113static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1,
114 TCGv_i64 arg2, TCGArg arg3)
ac56dd48 115{
efd7f486 116 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 117 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
118 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
119 *tcg_ctx.gen_opparam_ptr++ = arg3;
ac56dd48
PB		 120}
121
a9751609
RH		 122static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
123 TCGv_ptr base, TCGArg offset)
a7812ae4 124{
efd7f486 125 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 126 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(val);
127 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_PTR(base);
128 *tcg_ctx.gen_opparam_ptr++ = offset;
a7812ae4
PB		 129}
130
a9751609
RH		 131static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
132 TCGv_ptr base, TCGArg offset)
a7812ae4 133{
efd7f486 134 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 135 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(val);
136 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_PTR(base);
137 *tcg_ctx.gen_opparam_ptr++ = offset;
a7812ae4
PB		 138}
139
a9751609 140static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
a7812ae4
PB		 141 TCGv_i32 arg3, TCGv_i32 arg4)
142{
efd7f486 143 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 144 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
145 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
146 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
147 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
a7812ae4
PB		 148}
149
a9751609 150static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
a810a2de 151 TCGv_i64 arg3, TCGv_i64 arg4)
a7812ae4 152{
efd7f486 153 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 154 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
155 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
156 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
157 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
a7812ae4
PB		 158}
159
a9751609 160static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
a7812ae4
PB		 161 TCGv_i32 arg3, TCGArg arg4)
162{
efd7f486 163 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 164 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
165 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
166 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
167 *tcg_ctx.gen_opparam_ptr++ = arg4;
a7812ae4
PB		 168}
169
a9751609 170static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
a7812ae4 171 TCGv_i64 arg3, TCGArg arg4)
ac56dd48 172{
efd7f486 173 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 174 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
175 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
176 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
177 *tcg_ctx.gen_opparam_ptr++ = arg4;
ac56dd48
PB		 178}
179
a9751609 180static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
a7812ae4 181 TCGArg arg3, TCGArg arg4)
ac56dd48 182{
efd7f486 183 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 184 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
185 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
186 *tcg_ctx.gen_opparam_ptr++ = arg3;
187 *tcg_ctx.gen_opparam_ptr++ = arg4;
c896fe29
FB		 188}
189
a9751609 190static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
a7812ae4 191 TCGArg arg3, TCGArg arg4)
c896fe29 192{
efd7f486 193 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 194 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
195 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
196 *tcg_ctx.gen_opparam_ptr++ = arg3;
197 *tcg_ctx.gen_opparam_ptr++ = arg4;
ac56dd48
PB		 198}
199
a9751609 200static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
a7812ae4
PB		 201 TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
202{
efd7f486 203 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 204 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
205 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
206 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
207 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
208 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg5);
a7812ae4
PB		 209}
210
a9751609 211static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
a7812ae4
PB		 212 TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
213{
efd7f486 214 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 215 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
216 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
217 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
218 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
219 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg5);
a7812ae4
PB		 220}
221
a9751609 222static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
a7812ae4 223 TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
ac56dd48 224{
efd7f486 225 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 226 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
227 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
228 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
229 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
230 *tcg_ctx.gen_opparam_ptr++ = arg5;
ac56dd48
PB		 231}
232
a9751609 233static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
a7812ae4 234 TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
ac56dd48 235{
efd7f486 236 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 237 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
238 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
239 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
240 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
241 *tcg_ctx.gen_opparam_ptr++ = arg5;
c896fe29
FB		 242}
243
b7767f0f
RH		 244static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1,
245 TCGv_i32 arg2, TCGv_i32 arg3,
246 TCGArg arg4, TCGArg arg5)
247{
efd7f486 248 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 249 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
250 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
251 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
252 *tcg_ctx.gen_opparam_ptr++ = arg4;
253 *tcg_ctx.gen_opparam_ptr++ = arg5;
b7767f0f
RH		 254}
255
256static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1,
257 TCGv_i64 arg2, TCGv_i64 arg3,
258 TCGArg arg4, TCGArg arg5)
259{
efd7f486 260 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 261 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
262 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
263 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
264 *tcg_ctx.gen_opparam_ptr++ = arg4;
265 *tcg_ctx.gen_opparam_ptr++ = arg5;
b7767f0f
RH		 266}
267
a9751609 268static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
a7812ae4
PB		 269 TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
270 TCGv_i32 arg6)
271{
efd7f486 272 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 273 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
274 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
275 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
276 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
277 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg5);
278 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg6);
a7812ae4
PB		 279}
280
a9751609 281static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
a7812ae4
PB		 282 TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
283 TCGv_i64 arg6)
c896fe29 284{
efd7f486 285 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 286 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
287 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
288 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
289 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
290 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg5);
291 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg6);
ac56dd48
PB		 292}
293
a9751609 294static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
be210acb
RH		 295 TCGv_i32 arg3, TCGv_i32 arg4,
296 TCGv_i32 arg5, TCGArg arg6)
297{
efd7f486 298 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 299 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
300 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
301 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
302 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
303 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg5);
304 *tcg_ctx.gen_opparam_ptr++ = arg6;
be210acb
RH		 305}
306
a9751609 307static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
be210acb
RH		 308 TCGv_i64 arg3, TCGv_i64 arg4,
309 TCGv_i64 arg5, TCGArg arg6)
310{
efd7f486 311 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 312 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
313 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
314 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
315 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
316 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg5);
317 *tcg_ctx.gen_opparam_ptr++ = arg6;
be210acb
RH		 318}
319
a9751609
RH		 320static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1,
321 TCGv_i32 arg2, TCGv_i32 arg3,
322 TCGv_i32 arg4, TCGArg arg5, TCGArg arg6)
ac56dd48 323{
efd7f486 324 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 325 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
326 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
327 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
328 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
329 *tcg_ctx.gen_opparam_ptr++ = arg5;
330 *tcg_ctx.gen_opparam_ptr++ = arg6;
a7812ae4
PB		 331}
332
a9751609
RH		 333static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1,
334 TCGv_i64 arg2, TCGv_i64 arg3,
335 TCGv_i64 arg4, TCGArg arg5, TCGArg arg6)
a7812ae4 336{
efd7f486 337 *tcg_ctx.gen_opc_ptr++ = opc;
c4afe5c4
EV		 338 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
339 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
340 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
341 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
342 *tcg_ctx.gen_opparam_ptr++ = arg5;
343 *tcg_ctx.gen_opparam_ptr++ = arg6;
c896fe29
FB		 344}
345
f713d6ad
RH		 346static inline void tcg_add_param_i32(TCGv_i32 val)
347{
348 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(val);
349}
350
351static inline void tcg_add_param_i64(TCGv_i64 val)
352{
353#if TCG_TARGET_REG_BITS == 32
354 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(TCGV_LOW(val));
355 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(TCGV_HIGH(val));
356#else
357 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(val);
358#endif
359}
360
c896fe29
FB		 361static inline void gen_set_label(int n)
362{
ac56dd48 363 tcg_gen_op1i(INDEX_op_set_label, n);
c896fe29
FB		 364}
365
fb50d413
BS		 366static inline void tcg_gen_br(int label)
367{
368 tcg_gen_op1i(INDEX_op_br, label);
369}
370
a7812ae4 371static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 372{
fe75bcf7 373 if (!TCGV_EQUAL_I32(ret, arg))
a7812ae4 374 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
c896fe29
FB		 375}
376
a7812ae4 377static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
c896fe29 378{
a7812ae4 379 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
c896fe29
FB		 380}
381
2bece2c8
RH		 382/* A version of dh_sizemask from def-helper.h that doesn't rely on
383 preprocessor magic. */
384static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed)
385{
386 return (is_64bit << n*2) | (is_signed << (n*2 + 1));
387}
388
c896fe29 389/* helper calls */
a7812ae4
PB		 390static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
391 TCGArg ret, int nargs, TCGArg *args)
392{
cf066674 393 tcg_gen_callN(&tcg_ctx, func, flags, sizemask, ret, nargs, args);
a7812ae4 394}
c896fe29 395
dbfff4de 396/* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
78505279
AJ		 397 reserved for helpers in tcg-runtime.c. These helpers all do not read
398 globals and do not have side effects, hence the call to tcg_gen_callN()
399 with TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_SIDE_EFFECTS. This may need
400 to be adjusted if these functions start to be used with other helpers. */
2bece2c8 401static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret,
31d66551
AJ		 402 TCGv_i32 a, TCGv_i32 b)
403{
31d66551 404 TCGArg args[2];
31d66551
AJ		 405 args[0] = GET_TCGV_I32(a);
406 args[1] = GET_TCGV_I32(b);
cf066674 407 tcg_gen_callN(&tcg_ctx, func,
78505279
AJ		 408 TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_SIDE_EFFECTS,
409 sizemask, GET_TCGV_I32(ret), 2, args);
31d66551
AJ		 410}
411
2bece2c8 412static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret,
a7812ae4 413 TCGv_i64 a, TCGv_i64 b)
c896fe29 414{
a7812ae4 415 TCGArg args[2];
a7812ae4
PB		 416 args[0] = GET_TCGV_I64(a);
417 args[1] = GET_TCGV_I64(b);
cf066674 418 tcg_gen_callN(&tcg_ctx, func,
78505279
AJ		 419 TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_SIDE_EFFECTS,
420 sizemask, GET_TCGV_I64(ret), 2, args);
f8422f52
BS		 421}
422
c896fe29
FB		 423/* 32 bit ops */
424
a7812ae4 425static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 426{
a7812ae4 427 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
c896fe29
FB		 428}
429
a7812ae4 430static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 431{
a7812ae4 432 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
c896fe29
FB		 433}
434
a7812ae4 435static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 436{
a7812ae4 437 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
c896fe29
FB		 438}
439
a7812ae4 440static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 441{
a7812ae4 442 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
c896fe29
FB		 443}
444
a7812ae4 445static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 446{
a7812ae4 447 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
c896fe29
FB		 448}
449
a7812ae4 450static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 451{
a7812ae4 452 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
c896fe29
FB		 453}
454
a7812ae4 455static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 456{
a7812ae4 457 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
c896fe29
FB		 458}
459
a7812ae4 460static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 461{
a7812ae4 462 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
c896fe29
FB		 463}
464
a7812ae4 465static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 466{
a7812ae4 467 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
c896fe29
FB		 468}
469
a7812ae4 470static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
c896fe29 471{
7089442c
BS		 472 /* some cases can be optimized here */
473 if (arg2 == 0) {
474 tcg_gen_mov_i32(ret, arg1);
475 } else {
a7812ae4 476 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 477 tcg_gen_add_i32(ret, arg1, t0);
a7812ae4 478 tcg_temp_free_i32(t0);
7089442c 479 }
c896fe29
FB		 480}
481
a7812ae4 482static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 483{
a7812ae4 484 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
c896fe29
FB		 485}
486
a7812ae4 487static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
0045734a 488{
a7812ae4 489 TCGv_i32 t0 = tcg_const_i32(arg1);
0045734a 490 tcg_gen_sub_i32(ret, t0, arg2);
a7812ae4 491 tcg_temp_free_i32(t0);
0045734a
AJ		 492}
493
a7812ae4 494static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
c896fe29 495{
7089442c
BS		 496 /* some cases can be optimized here */
497 if (arg2 == 0) {
498 tcg_gen_mov_i32(ret, arg1);
499 } else {
a7812ae4 500 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 501 tcg_gen_sub_i32(ret, arg1, t0);
a7812ae4 502 tcg_temp_free_i32(t0);
7089442c 503 }
c896fe29
FB		 504}
505
a7812ae4 506static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 507{
7fc81051
AJ		 508 if (TCGV_EQUAL_I32(arg1, arg2)) {
509 tcg_gen_mov_i32(ret, arg1);
510 } else {
511 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
512 }
c896fe29
FB		 513}
514
42ce3e20 515static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
c896fe29 516{
42ce3e20
RH		 517 TCGv_i32 t0;
518 /* Some cases can be optimized here. */
519 switch (arg2) {
520 case 0:
c896fe29 521 tcg_gen_movi_i32(ret, 0);
42ce3e20
RH		 522 return;
523 case 0xffffffffu:
c896fe29 524 tcg_gen_mov_i32(ret, arg1);
42ce3e20
RH		 525 return;
526 case 0xffu:
527 /* Don't recurse with tcg_gen_ext8u_i32. */
528 if (TCG_TARGET_HAS_ext8u_i32) {
529 tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1);
530 return;
531 }
532 break;
533 case 0xffffu:
534 if (TCG_TARGET_HAS_ext16u_i32) {
535 tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1);
536 return;
537 }
538 break;
c896fe29 539 }
42ce3e20
RH		 540 t0 = tcg_const_i32(arg2);
541 tcg_gen_and_i32(ret, arg1, t0);
542 tcg_temp_free_i32(t0);
c896fe29
FB		 543}
544
a7812ae4 545static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 546{
7fc81051
AJ		 547 if (TCGV_EQUAL_I32(arg1, arg2)) {
548 tcg_gen_mov_i32(ret, arg1);
549 } else {
550 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
551 }
c896fe29
FB		 552}
553
a7812ae4 554static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
c896fe29 555{
d81ada7f
RH		 556 /* Some cases can be optimized here. */
557 if (arg2 == -1) {
558 tcg_gen_movi_i32(ret, -1);
c896fe29
FB		 559 } else if (arg2 == 0) {
560 tcg_gen_mov_i32(ret, arg1);
561 } else {
a7812ae4 562 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 563 tcg_gen_or_i32(ret, arg1, t0);
a7812ae4 564 tcg_temp_free_i32(t0);
c896fe29
FB		 565 }
566}
567
a7812ae4 568static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 569{
7fc81051
AJ		 570 if (TCGV_EQUAL_I32(arg1, arg2)) {
571 tcg_gen_movi_i32(ret, 0);
572 } else {
573 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
574 }
c896fe29
FB		 575}
576
a7812ae4 577static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
c896fe29 578{
6f3bb33e 579 /* Some cases can be optimized here. */
c896fe29
FB		 580 if (arg2 == 0) {
581 tcg_gen_mov_i32(ret, arg1);
6f3bb33e
RH		 582 } else if (arg2 == -1 && TCG_TARGET_HAS_not_i32) {
583 /* Don't recurse with tcg_gen_not_i32. */
584 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1);
c896fe29 585 } else {
a7812ae4 586 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 587 tcg_gen_xor_i32(ret, arg1, t0);
a7812ae4 588 tcg_temp_free_i32(t0);
c896fe29
FB		 589 }
590}
591
a7812ae4 592static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 593{
a7812ae4 594 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
c896fe29
FB		 595}
596
a7812ae4 597static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
c896fe29 598{
34151a20
FB		 599 if (arg2 == 0) {
600 tcg_gen_mov_i32(ret, arg1);
601 } else {
a7812ae4 602 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 603 tcg_gen_shl_i32(ret, arg1, t0);
a7812ae4 604 tcg_temp_free_i32(t0);
34151a20 605 }
c896fe29
FB		 606}
607
a7812ae4 608static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 609{
a7812ae4 610 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
c896fe29
FB		 611}
612
a7812ae4 613static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
c896fe29 614{
34151a20
FB		 615 if (arg2 == 0) {
616 tcg_gen_mov_i32(ret, arg1);
617 } else {
a7812ae4 618 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 619 tcg_gen_shr_i32(ret, arg1, t0);
a7812ae4 620 tcg_temp_free_i32(t0);
34151a20 621 }
c896fe29
FB		 622}
623
a7812ae4 624static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 625{
a7812ae4 626 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
c896fe29
FB		 627}
628
a7812ae4 629static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
c896fe29 630{
34151a20
FB		 631 if (arg2 == 0) {
632 tcg_gen_mov_i32(ret, arg1);
633 } else {
a7812ae4 634 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 635 tcg_gen_sar_i32(ret, arg1, t0);
a7812ae4 636 tcg_temp_free_i32(t0);
34151a20 637 }
c896fe29
FB		 638}
639
8a56e840
RH		 640static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1,
641 TCGv_i32 arg2, int label_index)
c896fe29 642{
0aed257f
RH		 643 if (cond == TCG_COND_ALWAYS) {
644 tcg_gen_br(label_index);
645 } else if (cond != TCG_COND_NEVER) {
646 tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
647 }
c896fe29
FB		 648}
649
8a56e840
RH		 650static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1,
651 int32_t arg2, int label_index)
cb63669a 652{
0aed257f
RH		 653 if (cond == TCG_COND_ALWAYS) {
654 tcg_gen_br(label_index);
655 } else if (cond != TCG_COND_NEVER) {
656 TCGv_i32 t0 = tcg_const_i32(arg2);
657 tcg_gen_brcond_i32(cond, arg1, t0, label_index);
658 tcg_temp_free_i32(t0);
659 }
cb63669a
PB		 660}
661
8a56e840 662static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
5105c556
AJ		 663 TCGv_i32 arg1, TCGv_i32 arg2)
664{
0aed257f
RH		 665 if (cond == TCG_COND_ALWAYS) {
666 tcg_gen_movi_i32(ret, 1);
667 } else if (cond == TCG_COND_NEVER) {
668 tcg_gen_movi_i32(ret, 0);
669 } else {
670 tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
671 }
5105c556
AJ		 672}
673
8a56e840
RH		 674static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
675 TCGv_i32 arg1, int32_t arg2)
5105c556 676{
0aed257f
RH		 677 if (cond == TCG_COND_ALWAYS) {
678 tcg_gen_movi_i32(ret, 1);
679 } else if (cond == TCG_COND_NEVER) {
680 tcg_gen_movi_i32(ret, 0);
681 } else {
682 TCGv_i32 t0 = tcg_const_i32(arg2);
683 tcg_gen_setcond_i32(cond, ret, arg1, t0);
684 tcg_temp_free_i32(t0);
685 }
5105c556
AJ		 686}
687
a7812ae4 688static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 689{
a7812ae4 690 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
c896fe29
FB		 691}
692
a7812ae4 693static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
f730fd27 694{
a7812ae4 695 TCGv_i32 t0 = tcg_const_i32(arg2);
e8996ee0 696 tcg_gen_mul_i32(ret, arg1, t0);
a7812ae4 697 tcg_temp_free_i32(t0);
f730fd27
TS		 698}
699
a7812ae4 700static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 701{
25c4d9cc
RH		 702 if (TCG_TARGET_HAS_div_i32) {
703 tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
704 } else if (TCG_TARGET_HAS_div2_i32) {
705 TCGv_i32 t0 = tcg_temp_new_i32();
706 tcg_gen_sari_i32(t0, arg1, 31);
707 tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
708 tcg_temp_free_i32(t0);
709 } else {
710 int sizemask = 0;
711 /* Return value and both arguments are 32-bit and signed. */
712 sizemask |= tcg_gen_sizemask(0, 0, 1);
713 sizemask |= tcg_gen_sizemask(1, 0, 1);
714 sizemask |= tcg_gen_sizemask(2, 0, 1);
715 tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2);
716 }
31d66551
AJ		 717}
718
719static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
720{
ca675f46 721 if (TCG_TARGET_HAS_rem_i32) {
25c4d9cc 722 tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
ca675f46
RH		 723 } else if (TCG_TARGET_HAS_div_i32) {
724 TCGv_i32 t0 = tcg_temp_new_i32();
725 tcg_gen_op3_i32(INDEX_op_div_i32, t0, arg1, arg2);
726 tcg_gen_mul_i32(t0, t0, arg2);
727 tcg_gen_sub_i32(ret, arg1, t0);
728 tcg_temp_free_i32(t0);
25c4d9cc
RH		 729 } else if (TCG_TARGET_HAS_div2_i32) {
730 TCGv_i32 t0 = tcg_temp_new_i32();
731 tcg_gen_sari_i32(t0, arg1, 31);
732 tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
733 tcg_temp_free_i32(t0);
734 } else {
735 int sizemask = 0;
736 /* Return value and both arguments are 32-bit and signed. */
737 sizemask |= tcg_gen_sizemask(0, 0, 1);
738 sizemask |= tcg_gen_sizemask(1, 0, 1);
739 sizemask |= tcg_gen_sizemask(2, 0, 1);
740 tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2);
741 }
31d66551
AJ		 742}
743
744static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
745{
25c4d9cc
RH		 746 if (TCG_TARGET_HAS_div_i32) {
747 tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
748 } else if (TCG_TARGET_HAS_div2_i32) {
749 TCGv_i32 t0 = tcg_temp_new_i32();
750 tcg_gen_movi_i32(t0, 0);
751 tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
752 tcg_temp_free_i32(t0);
753 } else {
754 int sizemask = 0;
755 /* Return value and both arguments are 32-bit and unsigned. */
756 sizemask |= tcg_gen_sizemask(0, 0, 0);
757 sizemask |= tcg_gen_sizemask(1, 0, 0);
758 sizemask |= tcg_gen_sizemask(2, 0, 0);
759 tcg_gen_helper32(tcg_helper_divu_i32, sizemask, ret, arg1, arg2);
760 }
31d66551
AJ		 761}
762
763static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
764{
ca675f46 765 if (TCG_TARGET_HAS_rem_i32) {
25c4d9cc 766 tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
ca675f46
RH		 767 } else if (TCG_TARGET_HAS_div_i32) {
768 TCGv_i32 t0 = tcg_temp_new_i32();
769 tcg_gen_op3_i32(INDEX_op_divu_i32, t0, arg1, arg2);
770 tcg_gen_mul_i32(t0, t0, arg2);
771 tcg_gen_sub_i32(ret, arg1, t0);
772 tcg_temp_free_i32(t0);
25c4d9cc
RH		 773 } else if (TCG_TARGET_HAS_div2_i32) {
774 TCGv_i32 t0 = tcg_temp_new_i32();
775 tcg_gen_movi_i32(t0, 0);
776 tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
777 tcg_temp_free_i32(t0);
778 } else {
779 int sizemask = 0;
780 /* Return value and both arguments are 32-bit and unsigned. */
781 sizemask |= tcg_gen_sizemask(0, 0, 0);
782 sizemask |= tcg_gen_sizemask(1, 0, 0);
783 sizemask |= tcg_gen_sizemask(2, 0, 0);
784 tcg_gen_helper32(tcg_helper_remu_i32, sizemask, ret, arg1, arg2);
785 }
31d66551 786}
c896fe29
FB		 787
788#if TCG_TARGET_REG_BITS == 32
789
a7812ae4 790static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 791{
fe75bcf7 792 if (!TCGV_EQUAL_I64(ret, arg)) {
a7812ae4 793 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
4d07272d
BS		 794 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
795 }
c896fe29
FB		 796}
797
a7812ae4 798static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
c896fe29 799{
a7812ae4 800 tcg_gen_movi_i32(TCGV_LOW(ret), arg);
ac56dd48 801 tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
c896fe29
FB		 802}
803
a7812ae4
PB		 804static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
805 tcg_target_long offset)
c896fe29 806{
a7812ae4 807 tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
ac56dd48 808 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
c896fe29
FB		 809}
810
a7812ae4
PB		 811static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
812 tcg_target_long offset)
c896fe29 813{
a7812ae4
PB		 814 tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
815 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
c896fe29
FB		 816}
817
a7812ae4
PB		 818static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
819 tcg_target_long offset)
c896fe29 820{
a747723b 821 tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
ac56dd48 822 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
c896fe29
FB		 823}
824
a7812ae4
PB		 825static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
826 tcg_target_long offset)
c896fe29 827{
a7812ae4
PB		 828 tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
829 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
c896fe29
FB		 830}
831
a7812ae4
PB		 832static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
833 tcg_target_long offset)
c896fe29 834{
a7812ae4 835 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
ac56dd48 836 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
c896fe29
FB		 837}
838
a7812ae4
PB		 839static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
840 tcg_target_long offset)
c896fe29 841{
a7812ae4
PB		 842 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
843 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
c896fe29
FB		 844}
845
a7812ae4
PB		 846static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
847 tcg_target_long offset)
c896fe29
FB		 848{
849 /* since arg2 and ret have different types, they cannot be the
850 same temporary */
02eb19d0 851#ifdef HOST_WORDS_BIGENDIAN
ac56dd48 852 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
a7812ae4 853 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
c896fe29 854#else
a7812ae4 855 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
ac56dd48 856 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
c896fe29
FB		 857#endif
858}
859
a7812ae4
PB		 860static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
861 tcg_target_long offset)
c896fe29 862{
a7812ae4 863 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 864}
865
a7812ae4
PB		 866static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
867 tcg_target_long offset)
c896fe29 868{
a7812ae4 869 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 870}
871
a7812ae4
PB		 872static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
873 tcg_target_long offset)
c896fe29 874{
a7812ae4 875 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 876}
877
a7812ae4
PB		 878static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
879 tcg_target_long offset)
c896fe29 880{
02eb19d0 881#ifdef HOST_WORDS_BIGENDIAN
ac56dd48 882 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
a7812ae4 883 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
c896fe29 884#else
a7812ae4 885 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
ac56dd48 886 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
c896fe29
FB		 887#endif
888}
889
a7812ae4 890static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 891{
a7812ae4
PB		 892 tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
893 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
894 TCGV_HIGH(arg2));
212c328d
RH		 895 /* Allow the optimizer room to replace add2 with two moves. */
896 tcg_gen_op0(INDEX_op_nop);
c896fe29
FB		 897}
898
a7812ae4 899static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 900{
a7812ae4
PB		 901 tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
902 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
903 TCGV_HIGH(arg2));
212c328d
RH		 904 /* Allow the optimizer room to replace sub2 with two moves. */
905 tcg_gen_op0(INDEX_op_nop);
c896fe29
FB		 906}
907
a7812ae4 908static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 909{
a7812ae4 910 tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
ac56dd48 911 tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
c896fe29
FB		 912}
913
a7812ae4 914static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 915{
e5105083
AJ		 916 tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
917 tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
c896fe29
FB		 918}
919
a7812ae4 920static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 921{
e5105083
AJ		 922 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
923 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
c896fe29
FB		 924}
925
a7812ae4 926static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 927{
a7812ae4 928 tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
ac56dd48 929 tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
c896fe29
FB		 930}
931
a7812ae4 932static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 933{
e5105083
AJ		 934 tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
935 tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
c896fe29
FB		 936}
937
a7812ae4 938static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 939{
a7812ae4 940 tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
ac56dd48 941 tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
c896fe29
FB		 942}
943
944/* XXX: use generic code when basic block handling is OK or CPU
945 specific code (x86) */
a7812ae4 946static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 947{
2bece2c8
RH		 948 int sizemask = 0;
949 /* Return value and both arguments are 64-bit and signed. */
950 sizemask |= tcg_gen_sizemask(0, 1, 1);
951 sizemask |= tcg_gen_sizemask(1, 1, 1);
952 sizemask |= tcg_gen_sizemask(2, 1, 1);
953
954 tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2);
c896fe29
FB		 955}
956
a7812ae4 957static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29
FB		 958{
959 tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
960}
961
a7812ae4 962static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 963{
2bece2c8
RH		 964 int sizemask = 0;
965 /* Return value and both arguments are 64-bit and signed. */
966 sizemask |= tcg_gen_sizemask(0, 1, 1);
967 sizemask |= tcg_gen_sizemask(1, 1, 1);
968 sizemask |= tcg_gen_sizemask(2, 1, 1);
969
970 tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2);
c896fe29
FB		 971}
972
a7812ae4 973static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29
FB		 974{
975 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
976}
977
a7812ae4 978static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 979{
2bece2c8
RH		 980 int sizemask = 0;
981 /* Return value and both arguments are 64-bit and signed. */
982 sizemask |= tcg_gen_sizemask(0, 1, 1);
983 sizemask |= tcg_gen_sizemask(1, 1, 1);
984 sizemask |= tcg_gen_sizemask(2, 1, 1);
985
986 tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2);
c896fe29
FB		 987}
988
a7812ae4 989static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29
FB		 990{
991 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
992}
993
8a56e840
RH		 994static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
995 TCGv_i64 arg2, int label_index)
c896fe29 996{
0aed257f
RH		 997 if (cond == TCG_COND_ALWAYS) {
998 tcg_gen_br(label_index);
999 } else if (cond != TCG_COND_NEVER) {
1000 tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
1001 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
1002 TCGV_HIGH(arg2), cond, label_index);
1003 }
c896fe29
FB		 1004}
1005
8a56e840 1006static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
5105c556
AJ		 1007 TCGv_i64 arg1, TCGv_i64 arg2)
1008{
0aed257f
RH		 1009 if (cond == TCG_COND_ALWAYS) {
1010 tcg_gen_movi_i32(TCGV_LOW(ret), 1);
1011 } else if (cond == TCG_COND_NEVER) {
1012 tcg_gen_movi_i32(TCGV_LOW(ret), 0);
1013 } else {
1014 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
1015 TCGV_LOW(arg1), TCGV_HIGH(arg1),
1016 TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
1017 }
5105c556
AJ		 1018 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1019}
1020
a7812ae4 1021static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1022{
a7812ae4
PB		 1023 TCGv_i64 t0;
1024 TCGv_i32 t1;
c896fe29 1025
a7812ae4
PB		 1026 t0 = tcg_temp_new_i64();
1027 t1 = tcg_temp_new_i32();
1028
03271524
RH		 1029 if (TCG_TARGET_HAS_mulu2_i32) {
1030 tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
1031 TCGV_LOW(arg1), TCGV_LOW(arg2));
1032 /* Allow the optimizer room to replace mulu2 with two moves. */
1033 tcg_gen_op0(INDEX_op_nop);
1034 } else {
1035 tcg_debug_assert(TCG_TARGET_HAS_muluh_i32);
1036 tcg_gen_op3_i32(INDEX_op_mul_i32, TCGV_LOW(t0),
1037 TCGV_LOW(arg1), TCGV_LOW(arg2));
1038 tcg_gen_op3_i32(INDEX_op_muluh_i32, TCGV_HIGH(t0),
1039 TCGV_LOW(arg1), TCGV_LOW(arg2));
1040 }
a7812ae4
PB		 1041
1042 tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
ac56dd48 1043 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
a7812ae4 1044 tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
ac56dd48 1045 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
a7812ae4 1046
c896fe29 1047 tcg_gen_mov_i64(ret, t0);
a7812ae4
PB		 1048 tcg_temp_free_i64(t0);
1049 tcg_temp_free_i32(t1);
c896fe29
FB		 1050}
1051
a7812ae4 1052static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1053{
2bece2c8
RH		 1054 int sizemask = 0;
1055 /* Return value and both arguments are 64-bit and signed. */
1056 sizemask |= tcg_gen_sizemask(0, 1, 1);
1057 sizemask |= tcg_gen_sizemask(1, 1, 1);
1058 sizemask |= tcg_gen_sizemask(2, 1, 1);
1059
1060 tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
c896fe29
FB		 1061}
1062
a7812ae4 1063static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1064{
2bece2c8
RH		 1065 int sizemask = 0;
1066 /* Return value and both arguments are 64-bit and signed. */
1067 sizemask |= tcg_gen_sizemask(0, 1, 1);
1068 sizemask |= tcg_gen_sizemask(1, 1, 1);
1069 sizemask |= tcg_gen_sizemask(2, 1, 1);
1070
1071 tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
c896fe29
FB		 1072}
1073
a7812ae4 1074static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1075{
2bece2c8
RH		 1076 int sizemask = 0;
1077 /* Return value and both arguments are 64-bit and unsigned. */
1078 sizemask |= tcg_gen_sizemask(0, 1, 0);
1079 sizemask |= tcg_gen_sizemask(1, 1, 0);
1080 sizemask |= tcg_gen_sizemask(2, 1, 0);
1081
1082 tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
c896fe29
FB		 1083}
1084
a7812ae4 1085static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1086{
2bece2c8
RH		 1087 int sizemask = 0;
1088 /* Return value and both arguments are 64-bit and unsigned. */
1089 sizemask |= tcg_gen_sizemask(0, 1, 0);
1090 sizemask |= tcg_gen_sizemask(1, 1, 0);
1091 sizemask |= tcg_gen_sizemask(2, 1, 0);
1092
1093 tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
c896fe29
FB		 1094}
1095
1096#else
1097
a7812ae4 1098static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1099{
fe75bcf7 1100 if (!TCGV_EQUAL_I64(ret, arg))
a7812ae4 1101 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
c896fe29
FB		 1102}
1103
a7812ae4 1104static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
c896fe29 1105{
a7812ae4 1106 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
c896fe29
FB		 1107}
1108
6bd4b08a 1109static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
ac56dd48 1110 tcg_target_long offset)
c896fe29 1111{
a7812ae4 1112 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
c896fe29
FB		 1113}
1114
6bd4b08a 1115static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
ac56dd48 1116 tcg_target_long offset)
c896fe29 1117{
a7812ae4 1118 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
c896fe29
FB		 1119}
1120
6bd4b08a 1121static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
ac56dd48 1122 tcg_target_long offset)
c896fe29 1123{
a7812ae4 1124 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
c896fe29
FB		 1125}
1126
6bd4b08a 1127static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
ac56dd48 1128 tcg_target_long offset)
c896fe29 1129{
a7812ae4 1130 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
c896fe29
FB		 1131}
1132
6bd4b08a 1133static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
ac56dd48 1134 tcg_target_long offset)
c896fe29 1135{
a7812ae4 1136 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
c896fe29
FB		 1137}
1138
6bd4b08a 1139static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
ac56dd48 1140 tcg_target_long offset)
c896fe29 1141{
a7812ae4 1142 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
c896fe29
FB		 1143}
1144
6bd4b08a 1145static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 1146{
a7812ae4 1147 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
c896fe29
FB		 1148}
1149
6bd4b08a 1150static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
ac56dd48 1151 tcg_target_long offset)
c896fe29 1152{
a7812ae4 1153 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
c896fe29
FB		 1154}
1155
6bd4b08a 1156static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
ac56dd48 1157 tcg_target_long offset)
c896fe29 1158{
a7812ae4 1159 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
c896fe29
FB		 1160}
1161
6bd4b08a 1162static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
ac56dd48 1163 tcg_target_long offset)
c896fe29 1164{
a7812ae4 1165 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
c896fe29
FB		 1166}
1167
6bd4b08a 1168static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset)
c896fe29 1169{
a7812ae4 1170 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
c896fe29
FB		 1171}
1172
a7812ae4 1173static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1174{
a7812ae4 1175 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
c896fe29
FB		 1176}
1177
a7812ae4 1178static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1179{
a7812ae4 1180 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
c896fe29
FB		 1181}
1182
a7812ae4 1183static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1184{
7fc81051
AJ		 1185 if (TCGV_EQUAL_I64(arg1, arg2)) {
1186 tcg_gen_mov_i64(ret, arg1);
1187 } else {
1188 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
1189 }
c896fe29
FB		 1190}
1191
42ce3e20 1192static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
c896fe29 1193{
42ce3e20
RH		 1194 TCGv_i64 t0;
1195 /* Some cases can be optimized here. */
1196 switch (arg2) {
1197 case 0:
1198 tcg_gen_movi_i64(ret, 0);
1199 return;
1200 case 0xffffffffffffffffull:
1201 tcg_gen_mov_i64(ret, arg1);
1202 return;
1203 case 0xffull:
1204 /* Don't recurse with tcg_gen_ext8u_i32. */
1205 if (TCG_TARGET_HAS_ext8u_i64) {
1206 tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1);
1207 return;
1208 }
1209 break;
1210 case 0xffffu:
1211 if (TCG_TARGET_HAS_ext16u_i64) {
1212 tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1);
1213 return;
1214 }
1215 break;
1216 case 0xffffffffull:
1217 if (TCG_TARGET_HAS_ext32u_i64) {
1218 tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1);
1219 return;
1220 }
1221 break;
1222 }
1223 t0 = tcg_const_i64(arg2);
e8996ee0 1224 tcg_gen_and_i64(ret, arg1, t0);
a7812ae4 1225 tcg_temp_free_i64(t0);
c896fe29
FB		 1226}
1227
a7812ae4 1228static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1229{
7fc81051
AJ		 1230 if (TCGV_EQUAL_I64(arg1, arg2)) {
1231 tcg_gen_mov_i64(ret, arg1);
1232 } else {
1233 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
1234 }
c896fe29
FB		 1235}
1236
a7812ae4 1237static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 1238{
d81ada7f
RH		 1239 /* Some cases can be optimized here. */
1240 if (arg2 == -1) {
1241 tcg_gen_movi_i64(ret, -1);
1242 } else if (arg2 == 0) {
1243 tcg_gen_mov_i64(ret, arg1);
1244 } else {
1245 TCGv_i64 t0 = tcg_const_i64(arg2);
1246 tcg_gen_or_i64(ret, arg1, t0);
1247 tcg_temp_free_i64(t0);
1248 }
c896fe29
FB		 1249}
1250
a7812ae4 1251static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1252{
7fc81051
AJ		 1253 if (TCGV_EQUAL_I64(arg1, arg2)) {
1254 tcg_gen_movi_i64(ret, 0);
1255 } else {
1256 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
1257 }
c896fe29
FB		 1258}
1259
a7812ae4 1260static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 1261{
6f3bb33e
RH		 1262 /* Some cases can be optimized here. */
1263 if (arg2 == 0) {
1264 tcg_gen_mov_i64(ret, arg1);
1265 } else if (arg2 == -1 && TCG_TARGET_HAS_not_i64) {
1266 /* Don't recurse with tcg_gen_not_i64. */
1267 tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1);
1268 } else {
1269 TCGv_i64 t0 = tcg_const_i64(arg2);
1270 tcg_gen_xor_i64(ret, arg1, t0);
1271 tcg_temp_free_i64(t0);
1272 }
c896fe29
FB		 1273}
1274
a7812ae4 1275static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1276{
a7812ae4 1277 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
c896fe29
FB		 1278}
1279
a7812ae4 1280static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 1281{
34151a20
FB		 1282 if (arg2 == 0) {
1283 tcg_gen_mov_i64(ret, arg1);
1284 } else {
a7812ae4 1285 TCGv_i64 t0 = tcg_const_i64(arg2);
e8996ee0 1286 tcg_gen_shl_i64(ret, arg1, t0);
a7812ae4 1287 tcg_temp_free_i64(t0);
34151a20 1288 }
c896fe29
FB		 1289}
1290
a7812ae4 1291static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1292{
a7812ae4 1293 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
c896fe29
FB		 1294}
1295
a7812ae4 1296static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 1297{
34151a20
FB		 1298 if (arg2 == 0) {
1299 tcg_gen_mov_i64(ret, arg1);
1300 } else {
a7812ae4 1301 TCGv_i64 t0 = tcg_const_i64(arg2);
e8996ee0 1302 tcg_gen_shr_i64(ret, arg1, t0);
a7812ae4 1303 tcg_temp_free_i64(t0);
34151a20 1304 }
c896fe29
FB		 1305}
1306
a7812ae4 1307static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1308{
a7812ae4 1309 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
c896fe29
FB		 1310}
1311
a7812ae4 1312static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
c896fe29 1313{
34151a20
FB		 1314 if (arg2 == 0) {
1315 tcg_gen_mov_i64(ret, arg1);
1316 } else {
a7812ae4 1317 TCGv_i64 t0 = tcg_const_i64(arg2);
e8996ee0 1318 tcg_gen_sar_i64(ret, arg1, t0);
a7812ae4 1319 tcg_temp_free_i64(t0);
34151a20 1320 }
c896fe29
FB		 1321}
1322
8a56e840
RH		 1323static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
1324 TCGv_i64 arg2, int label_index)
c896fe29 1325{
0aed257f
RH		 1326 if (cond == TCG_COND_ALWAYS) {
1327 tcg_gen_br(label_index);
1328 } else if (cond != TCG_COND_NEVER) {
1329 tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1330 }
c896fe29
FB		 1331}
1332
8a56e840 1333static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
5105c556
AJ		 1334 TCGv_i64 arg1, TCGv_i64 arg2)
1335{
0aed257f
RH		 1336 if (cond == TCG_COND_ALWAYS) {
1337 tcg_gen_movi_i64(ret, 1);
1338 } else if (cond == TCG_COND_NEVER) {
1339 tcg_gen_movi_i64(ret, 0);
1340 } else {
1341 tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
1342 }
5105c556
AJ		 1343}
1344
a7812ae4 1345static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 1346{
a7812ae4 1347 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
c896fe29
FB		 1348}
1349
31d66551
AJ		 1350static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1351{
25c4d9cc
RH		 1352 if (TCG_TARGET_HAS_div_i64) {
1353 tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1354 } else if (TCG_TARGET_HAS_div2_i64) {
1355 TCGv_i64 t0 = tcg_temp_new_i64();
1356 tcg_gen_sari_i64(t0, arg1, 63);
1357 tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1358 tcg_temp_free_i64(t0);
1359 } else {
1360 int sizemask = 0;
1361 /* Return value and both arguments are 64-bit and signed. */
1362 sizemask |= tcg_gen_sizemask(0, 1, 1);
1363 sizemask |= tcg_gen_sizemask(1, 1, 1);
1364 sizemask |= tcg_gen_sizemask(2, 1, 1);
1365 tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
1366 }
31d66551
AJ		 1367}
1368
1369static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1370{
ca675f46 1371 if (TCG_TARGET_HAS_rem_i64) {
25c4d9cc 1372 tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
ca675f46
RH		 1373 } else if (TCG_TARGET_HAS_div_i64) {
1374 TCGv_i64 t0 = tcg_temp_new_i64();
1375 tcg_gen_op3_i64(INDEX_op_div_i64, t0, arg1, arg2);
1376 tcg_gen_mul_i64(t0, t0, arg2);
1377 tcg_gen_sub_i64(ret, arg1, t0);
1378 tcg_temp_free_i64(t0);
25c4d9cc
RH		 1379 } else if (TCG_TARGET_HAS_div2_i64) {
1380 TCGv_i64 t0 = tcg_temp_new_i64();
1381 tcg_gen_sari_i64(t0, arg1, 63);
1382 tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1383 tcg_temp_free_i64(t0);
1384 } else {
1385 int sizemask = 0;
1386 /* Return value and both arguments are 64-bit and signed. */
1387 sizemask |= tcg_gen_sizemask(0, 1, 1);
1388 sizemask |= tcg_gen_sizemask(1, 1, 1);
1389 sizemask |= tcg_gen_sizemask(2, 1, 1);
1390 tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1391 }
31d66551
AJ		 1392}
1393
1394static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1395{
25c4d9cc
RH		 1396 if (TCG_TARGET_HAS_div_i64) {
1397 tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1398 } else if (TCG_TARGET_HAS_div2_i64) {
1399 TCGv_i64 t0 = tcg_temp_new_i64();
1400 tcg_gen_movi_i64(t0, 0);
1401 tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1402 tcg_temp_free_i64(t0);
1403 } else {
1404 int sizemask = 0;
1405 /* Return value and both arguments are 64-bit and unsigned. */
1406 sizemask |= tcg_gen_sizemask(0, 1, 0);
1407 sizemask |= tcg_gen_sizemask(1, 1, 0);
1408 sizemask |= tcg_gen_sizemask(2, 1, 0);
1409 tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1410 }
31d66551
AJ		 1411}
1412
1413static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1414{
ca675f46 1415 if (TCG_TARGET_HAS_rem_i64) {
25c4d9cc 1416 tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
ca675f46
RH		 1417 } else if (TCG_TARGET_HAS_div_i64) {
1418 TCGv_i64 t0 = tcg_temp_new_i64();
1419 tcg_gen_op3_i64(INDEX_op_divu_i64, t0, arg1, arg2);
1420 tcg_gen_mul_i64(t0, t0, arg2);
1421 tcg_gen_sub_i64(ret, arg1, t0);
1422 tcg_temp_free_i64(t0);
25c4d9cc
RH		 1423 } else if (TCG_TARGET_HAS_div2_i64) {
1424 TCGv_i64 t0 = tcg_temp_new_i64();
1425 tcg_gen_movi_i64(t0, 0);
1426 tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1427 tcg_temp_free_i64(t0);
1428 } else {
1429 int sizemask = 0;
1430 /* Return value and both arguments are 64-bit and unsigned. */
1431 sizemask |= tcg_gen_sizemask(0, 1, 0);
1432 sizemask |= tcg_gen_sizemask(1, 1, 0);
1433 sizemask |= tcg_gen_sizemask(2, 1, 0);
1434 tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1435 }
31d66551 1436}
25c4d9cc 1437#endif /* TCG_TARGET_REG_BITS == 32 */
c896fe29 1438
a7812ae4 1439static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
6359706f
AJ		 1440{
1441 /* some cases can be optimized here */
1442 if (arg2 == 0) {
1443 tcg_gen_mov_i64(ret, arg1);
1444 } else {
a7812ae4 1445 TCGv_i64 t0 = tcg_const_i64(arg2);
6359706f 1446 tcg_gen_add_i64(ret, arg1, t0);
a7812ae4 1447 tcg_temp_free_i64(t0);
6359706f
AJ		 1448 }
1449}
1450
a7812ae4 1451static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
0045734a 1452{
a7812ae4 1453 TCGv_i64 t0 = tcg_const_i64(arg1);
0045734a 1454 tcg_gen_sub_i64(ret, t0, arg2);
a7812ae4 1455 tcg_temp_free_i64(t0);
0045734a
AJ		 1456}
1457
a7812ae4 1458static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
6359706f
AJ		 1459{
1460 /* some cases can be optimized here */
1461 if (arg2 == 0) {
1462 tcg_gen_mov_i64(ret, arg1);
1463 } else {
a7812ae4 1464 TCGv_i64 t0 = tcg_const_i64(arg2);
6359706f 1465 tcg_gen_sub_i64(ret, arg1, t0);
a7812ae4 1466 tcg_temp_free_i64(t0);
6359706f
AJ		 1467 }
1468}
8a56e840
RH		 1469static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1,
1470 int64_t arg2, int label_index)
f02bb954 1471{
0aed257f
RH		 1472 if (cond == TCG_COND_ALWAYS) {
1473 tcg_gen_br(label_index);
1474 } else if (cond != TCG_COND_NEVER) {
1475 TCGv_i64 t0 = tcg_const_i64(arg2);
1476 tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1477 tcg_temp_free_i64(t0);
1478 }
f02bb954
AJ		 1479}
1480
8a56e840
RH		 1481static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1482 TCGv_i64 arg1, int64_t arg2)
5105c556
AJ		 1483{
1484 TCGv_i64 t0 = tcg_const_i64(arg2);
1485 tcg_gen_setcond_i64(cond, ret, arg1, t0);
1486 tcg_temp_free_i64(t0);
1487}
1488
a7812ae4 1489static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
f02bb954 1490{
a7812ae4 1491 TCGv_i64 t0 = tcg_const_i64(arg2);
f02bb954 1492 tcg_gen_mul_i64(ret, arg1, t0);
a7812ae4 1493 tcg_temp_free_i64(t0);
f02bb954
AJ		 1494}
1495
6359706f 1496
c896fe29
FB		 1497/***************************************/
1498/* optional operations */
1499
a7812ae4 1500static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 1501{
25c4d9cc
RH		 1502 if (TCG_TARGET_HAS_ext8s_i32) {
1503 tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1504 } else {
1505 tcg_gen_shli_i32(ret, arg, 24);
1506 tcg_gen_sari_i32(ret, ret, 24);
1507 }
c896fe29
FB		 1508}
1509
a7812ae4 1510static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 1511{
25c4d9cc
RH		 1512 if (TCG_TARGET_HAS_ext16s_i32) {
1513 tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1514 } else {
1515 tcg_gen_shli_i32(ret, arg, 16);
1516 tcg_gen_sari_i32(ret, ret, 16);
1517 }
c896fe29
FB		 1518}
1519
a7812ae4 1520static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
86831435 1521{
25c4d9cc
RH		 1522 if (TCG_TARGET_HAS_ext8u_i32) {
1523 tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg);
1524 } else {
1525 tcg_gen_andi_i32(ret, arg, 0xffu);
1526 }
86831435
PB		 1527}
1528
a7812ae4 1529static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
86831435 1530{
25c4d9cc
RH		 1531 if (TCG_TARGET_HAS_ext16u_i32) {
1532 tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg);
1533 } else {
1534 tcg_gen_andi_i32(ret, arg, 0xffffu);
1535 }
86831435
PB		 1536}
1537
c896fe29 1538/* Note: we assume the two high bytes are set to zero */
a7812ae4 1539static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 1540{
25c4d9cc
RH		 1541 if (TCG_TARGET_HAS_bswap16_i32) {
1542 tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1543 } else {
1544 TCGv_i32 t0 = tcg_temp_new_i32();
c896fe29 1545
25c4d9cc
RH		 1546 tcg_gen_ext8u_i32(t0, arg);
1547 tcg_gen_shli_i32(t0, t0, 8);
1548 tcg_gen_shri_i32(ret, arg, 8);
1549 tcg_gen_or_i32(ret, ret, t0);
1550 tcg_temp_free_i32(t0);
1551 }
c896fe29
FB		 1552}
1553
66896cb8 1554static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 1555{
25c4d9cc
RH		 1556 if (TCG_TARGET_HAS_bswap32_i32) {
1557 tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1558 } else {
1559 TCGv_i32 t0, t1;
1560 t0 = tcg_temp_new_i32();
1561 t1 = tcg_temp_new_i32();
c896fe29 1562
25c4d9cc 1563 tcg_gen_shli_i32(t0, arg, 24);
c896fe29 1564
25c4d9cc
RH		 1565 tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1566 tcg_gen_shli_i32(t1, t1, 8);
1567 tcg_gen_or_i32(t0, t0, t1);
c896fe29 1568
25c4d9cc
RH		 1569 tcg_gen_shri_i32(t1, arg, 8);
1570 tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1571 tcg_gen_or_i32(t0, t0, t1);
c896fe29 1572
25c4d9cc
RH		 1573 tcg_gen_shri_i32(t1, arg, 24);
1574 tcg_gen_or_i32(ret, t0, t1);
1575 tcg_temp_free_i32(t0);
1576 tcg_temp_free_i32(t1);
1577 }
c896fe29
FB		 1578}
1579
1580#if TCG_TARGET_REG_BITS == 32
a7812ae4 1581static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1582{
a7812ae4
PB		 1583 tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1584 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
c896fe29
FB		 1585}
1586
a7812ae4 1587static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1588{
a7812ae4
PB		 1589 tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1590 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
c896fe29
FB		 1591}
1592
a7812ae4 1593static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1594{
a7812ae4
PB		 1595 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1596 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
c896fe29
FB		 1597}
1598
a7812ae4 1599static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
86831435 1600{
a7812ae4 1601 tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
86831435
PB		 1602 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1603}
1604
a7812ae4 1605static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
86831435 1606{
a7812ae4 1607 tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
86831435
PB		 1608 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1609}
1610
a7812ae4 1611static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
86831435 1612{
a7812ae4 1613 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
86831435
PB		 1614 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1615}
1616
4bb7a41e
RH		 1617static inline void tcg_gen_trunc_shr_i64_i32(TCGv_i32 ret, TCGv_i64 arg,
1618 unsigned int count)
c896fe29 1619{
4bb7a41e
RH		 1620 tcg_debug_assert(count < 64);
1621 if (count >= 32) {
1622 tcg_gen_shri_i32(ret, TCGV_HIGH(arg), count - 32);
1623 } else if (count == 0) {
1624 tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1625 } else {
1626 TCGv_i64 t = tcg_temp_new_i64();
1627 tcg_gen_shri_i64(t, arg, count);
1628 tcg_gen_mov_i32(ret, TCGV_LOW(t));
1629 tcg_temp_free_i64(t);
1630 }
c896fe29
FB		 1631}
1632
a7812ae4 1633static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
c896fe29 1634{
a7812ae4 1635 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
ac56dd48 1636 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
c896fe29
FB		 1637}
1638
a7812ae4 1639static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
c896fe29 1640{
a7812ae4
PB		 1641 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1642 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
c896fe29
FB		 1643}
1644
9a5c57fd
AJ		 1645/* Note: we assume the six high bytes are set to zero */
1646static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1647{
1648 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1649 tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1650}
1651
1652/* Note: we assume the four high bytes are set to zero */
1653static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1654{
1655 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1656 tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1657}
1658
66896cb8 1659static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1660{
a7812ae4
PB		 1661 TCGv_i32 t0, t1;
1662 t0 = tcg_temp_new_i32();
1663 t1 = tcg_temp_new_i32();
c896fe29 1664
66896cb8
AJ		 1665 tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1666 tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
a7812ae4 1667 tcg_gen_mov_i32(TCGV_LOW(ret), t1);
ac56dd48 1668 tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
a7812ae4
PB		 1669 tcg_temp_free_i32(t0);
1670 tcg_temp_free_i32(t1);
c896fe29
FB		 1671}
1672#else
1673
a7812ae4 1674static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1675{
25c4d9cc
RH		 1676 if (TCG_TARGET_HAS_ext8s_i64) {
1677 tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1678 } else {
1679 tcg_gen_shli_i64(ret, arg, 56);
1680 tcg_gen_sari_i64(ret, ret, 56);
1681 }
c896fe29
FB		 1682}
1683
a7812ae4 1684static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1685{
25c4d9cc
RH		 1686 if (TCG_TARGET_HAS_ext16s_i64) {
1687 tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1688 } else {
1689 tcg_gen_shli_i64(ret, arg, 48);
1690 tcg_gen_sari_i64(ret, ret, 48);
1691 }
c896fe29
FB		 1692}
1693
a7812ae4 1694static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1695{
25c4d9cc
RH		 1696 if (TCG_TARGET_HAS_ext32s_i64) {
1697 tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1698 } else {
1699 tcg_gen_shli_i64(ret, arg, 32);
1700 tcg_gen_sari_i64(ret, ret, 32);
1701 }
c896fe29
FB		 1702}
1703
a7812ae4 1704static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
86831435 1705{
25c4d9cc
RH		 1706 if (TCG_TARGET_HAS_ext8u_i64) {
1707 tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg);
1708 } else {
1709 tcg_gen_andi_i64(ret, arg, 0xffu);
1710 }
86831435
PB		 1711}
1712
a7812ae4 1713static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
86831435 1714{
25c4d9cc
RH		 1715 if (TCG_TARGET_HAS_ext16u_i64) {
1716 tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg);
1717 } else {
1718 tcg_gen_andi_i64(ret, arg, 0xffffu);
1719 }
86831435
PB		 1720}
1721
a7812ae4 1722static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
86831435 1723{
25c4d9cc
RH		 1724 if (TCG_TARGET_HAS_ext32u_i64) {
1725 tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg);
1726 } else {
1727 tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1728 }
86831435
PB		 1729}
1730
4bb7a41e
RH		 1731static inline void tcg_gen_trunc_shr_i64_i32(TCGv_i32 ret, TCGv_i64 arg,
1732 unsigned int count)
c896fe29 1733{
4bb7a41e
RH		 1734 tcg_debug_assert(count < 64);
1735 if (TCG_TARGET_HAS_trunc_shr_i32) {
1736 tcg_gen_op3i_i32(INDEX_op_trunc_shr_i32, ret,
1737 MAKE_TCGV_I32(GET_TCGV_I64(arg)), count);
1738 } else if (count == 0) {
1739 tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1740 } else {
1741 TCGv_i64 t = tcg_temp_new_i64();
1742 tcg_gen_shri_i64(t, arg, count);
1743 tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(t)));
1744 tcg_temp_free_i64(t);
1745 }
c896fe29
FB		 1746}
1747
1748/* Note: we assume the target supports move between 32 and 64 bit
1749 registers */
a7812ae4 1750static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
c896fe29 1751{
cfc86988 1752 tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
c896fe29
FB		 1753}
1754
1755/* Note: we assume the target supports move between 32 and 64 bit
1756 registers */
a7812ae4 1757static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
c896fe29 1758{
a7812ae4 1759 tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
c896fe29
FB		 1760}
1761
9a5c57fd
AJ		 1762/* Note: we assume the six high bytes are set to zero */
1763static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1764{
25c4d9cc
RH		 1765 if (TCG_TARGET_HAS_bswap16_i64) {
1766 tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
1767 } else {
1768 TCGv_i64 t0 = tcg_temp_new_i64();
9a5c57fd 1769
25c4d9cc
RH		 1770 tcg_gen_ext8u_i64(t0, arg);
1771 tcg_gen_shli_i64(t0, t0, 8);
1772 tcg_gen_shri_i64(ret, arg, 8);
1773 tcg_gen_or_i64(ret, ret, t0);
1774 tcg_temp_free_i64(t0);
1775 }
9a5c57fd
AJ		 1776}
1777
1778/* Note: we assume the four high bytes are set to zero */
1779static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1780{
25c4d9cc
RH		 1781 if (TCG_TARGET_HAS_bswap32_i64) {
1782 tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
1783 } else {
1784 TCGv_i64 t0, t1;
1785 t0 = tcg_temp_new_i64();
1786 t1 = tcg_temp_new_i64();
9a5c57fd 1787
25c4d9cc
RH		 1788 tcg_gen_shli_i64(t0, arg, 24);
1789 tcg_gen_ext32u_i64(t0, t0);
9a5c57fd 1790
25c4d9cc
RH		 1791 tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1792 tcg_gen_shli_i64(t1, t1, 8);
1793 tcg_gen_or_i64(t0, t0, t1);
9a5c57fd 1794
25c4d9cc
RH		 1795 tcg_gen_shri_i64(t1, arg, 8);
1796 tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1797 tcg_gen_or_i64(t0, t0, t1);
9a5c57fd 1798
25c4d9cc
RH		 1799 tcg_gen_shri_i64(t1, arg, 24);
1800 tcg_gen_or_i64(ret, t0, t1);
1801 tcg_temp_free_i64(t0);
1802 tcg_temp_free_i64(t1);
1803 }
9a5c57fd
AJ		 1804}
1805
66896cb8 1806static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 1807{
25c4d9cc
RH		 1808 if (TCG_TARGET_HAS_bswap64_i64) {
1809 tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1810 } else {
1811 TCGv_i64 t0 = tcg_temp_new_i64();
1812 TCGv_i64 t1 = tcg_temp_new_i64();
c896fe29 1813
25c4d9cc 1814 tcg_gen_shli_i64(t0, arg, 56);
c896fe29 1815
25c4d9cc
RH		 1816 tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1817 tcg_gen_shli_i64(t1, t1, 40);
1818 tcg_gen_or_i64(t0, t0, t1);
c896fe29 1819
25c4d9cc
RH		 1820 tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1821 tcg_gen_shli_i64(t1, t1, 24);
1822 tcg_gen_or_i64(t0, t0, t1);
c896fe29 1823
25c4d9cc
RH		 1824 tcg_gen_andi_i64(t1, arg, 0xff000000);
1825 tcg_gen_shli_i64(t1, t1, 8);
1826 tcg_gen_or_i64(t0, t0, t1);
c896fe29 1827
25c4d9cc
RH		 1828 tcg_gen_shri_i64(t1, arg, 8);
1829 tcg_gen_andi_i64(t1, t1, 0xff000000);
1830 tcg_gen_or_i64(t0, t0, t1);
c896fe29 1831
25c4d9cc
RH		 1832 tcg_gen_shri_i64(t1, arg, 24);
1833 tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1834 tcg_gen_or_i64(t0, t0, t1);
c896fe29 1835
25c4d9cc
RH		 1836 tcg_gen_shri_i64(t1, arg, 40);
1837 tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1838 tcg_gen_or_i64(t0, t0, t1);
c896fe29 1839
25c4d9cc
RH		 1840 tcg_gen_shri_i64(t1, arg, 56);
1841 tcg_gen_or_i64(ret, t0, t1);
1842 tcg_temp_free_i64(t0);
1843 tcg_temp_free_i64(t1);
1844 }
c896fe29
FB		 1845}
1846
1847#endif
1848
a7812ae4 1849static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
390efc54 1850{
25c4d9cc
RH		 1851 if (TCG_TARGET_HAS_neg_i32) {
1852 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1853 } else {
1854 TCGv_i32 t0 = tcg_const_i32(0);
1855 tcg_gen_sub_i32(ret, t0, arg);
1856 tcg_temp_free_i32(t0);
1857 }
390efc54
PB		 1858}
1859
a7812ae4 1860static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
390efc54 1861{
25c4d9cc
RH		 1862 if (TCG_TARGET_HAS_neg_i64) {
1863 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1864 } else {
1865 TCGv_i64 t0 = tcg_const_i64(0);
1866 tcg_gen_sub_i64(ret, t0, arg);
1867 tcg_temp_free_i64(t0);
1868 }
390efc54
PB		 1869}
1870
a7812ae4 1871static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
0b6ce4cf 1872{
25c4d9cc
RH		 1873 if (TCG_TARGET_HAS_not_i32) {
1874 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1875 } else {
1876 tcg_gen_xori_i32(ret, arg, -1);
1877 }
0b6ce4cf
FB		 1878}
1879
a7812ae4 1880static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
0b6ce4cf 1881{
25c4d9cc
RH		 1882#if TCG_TARGET_REG_BITS == 64
1883 if (TCG_TARGET_HAS_not_i64) {
1884 tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1885 } else {
1886 tcg_gen_xori_i64(ret, arg, -1);
1887 }
1888#else
a10f9f4f
RH		 1889 tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1890 tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
d2604285 1891#endif
0b6ce4cf 1892}
5ff9d6a4 1893
a7812ae4 1894static inline void tcg_gen_discard_i32(TCGv_i32 arg)
5ff9d6a4 1895{
a7812ae4 1896 tcg_gen_op1_i32(INDEX_op_discard, arg);
5ff9d6a4
FB		 1897}
1898
a7812ae4 1899static inline void tcg_gen_discard_i64(TCGv_i64 arg)
5ff9d6a4 1900{
25c4d9cc 1901#if TCG_TARGET_REG_BITS == 32
a7812ae4 1902 tcg_gen_discard_i32(TCGV_LOW(arg));
5ff9d6a4 1903 tcg_gen_discard_i32(TCGV_HIGH(arg));
5ff9d6a4 1904#else
a7812ae4 1905 tcg_gen_op1_i64(INDEX_op_discard, arg);
5ff9d6a4 1906#endif
25c4d9cc 1907}
5ff9d6a4 1908
a7812ae4 1909static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
f24cb33e 1910{
25c4d9cc
RH		 1911 if (TCG_TARGET_HAS_andc_i32) {
1912 tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
1913 } else {
1914 TCGv_i32 t0 = tcg_temp_new_i32();
1915 tcg_gen_not_i32(t0, arg2);
1916 tcg_gen_and_i32(ret, arg1, t0);
1917 tcg_temp_free_i32(t0);
1918 }
f24cb33e
AJ		 1919}
1920
a7812ae4 1921static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
f24cb33e 1922{
25c4d9cc
RH		 1923#if TCG_TARGET_REG_BITS == 64
1924 if (TCG_TARGET_HAS_andc_i64) {
1925 tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
1926 } else {
1927 TCGv_i64 t0 = tcg_temp_new_i64();
1928 tcg_gen_not_i64(t0, arg2);
1929 tcg_gen_and_i64(ret, arg1, t0);
1930 tcg_temp_free_i64(t0);
1931 }
1932#else
241cbed4
RH		 1933 tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1934 tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
241cbed4 1935#endif
f24cb33e
AJ		 1936}
1937
a7812ae4 1938static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
f24cb33e 1939{
25c4d9cc
RH		 1940 if (TCG_TARGET_HAS_eqv_i32) {
1941 tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2);
1942 } else {
1943 tcg_gen_xor_i32(ret, arg1, arg2);
1944 tcg_gen_not_i32(ret, ret);
1945 }
f24cb33e
AJ		 1946}
1947
a7812ae4 1948static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
f24cb33e 1949{
25c4d9cc
RH		 1950#if TCG_TARGET_REG_BITS == 64
1951 if (TCG_TARGET_HAS_eqv_i64) {
1952 tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2);
1953 } else {
1954 tcg_gen_xor_i64(ret, arg1, arg2);
1955 tcg_gen_not_i64(ret, ret);
1956 }
1957#else
8d625cf1
RH		 1958 tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1959 tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
8d625cf1 1960#endif
f24cb33e
AJ		 1961}
1962
a7812ae4 1963static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
f24cb33e 1964{
25c4d9cc
RH		 1965 if (TCG_TARGET_HAS_nand_i32) {
1966 tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
1967 } else {
1968 tcg_gen_and_i32(ret, arg1, arg2);
1969 tcg_gen_not_i32(ret, ret);
1970 }
f24cb33e
AJ		 1971}
1972
a7812ae4 1973static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
f24cb33e 1974{
25c4d9cc
RH		 1975#if TCG_TARGET_REG_BITS == 64
1976 if (TCG_TARGET_HAS_nand_i64) {
1977 tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
1978 } else {
1979 tcg_gen_and_i64(ret, arg1, arg2);
1980 tcg_gen_not_i64(ret, ret);
1981 }
1982#else
9940a96b
RH		 1983 tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1984 tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
9940a96b 1985#endif
f24cb33e
AJ		 1986}
1987
a7812ae4 1988static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
f24cb33e 1989{
25c4d9cc
RH		 1990 if (TCG_TARGET_HAS_nor_i32) {
1991 tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2);
1992 } else {
1993 tcg_gen_or_i32(ret, arg1, arg2);
1994 tcg_gen_not_i32(ret, ret);
1995 }
f24cb33e
AJ		 1996}
1997
a7812ae4 1998static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
f24cb33e 1999{
25c4d9cc
RH		 2000#if TCG_TARGET_REG_BITS == 64
2001 if (TCG_TARGET_HAS_nor_i64) {
2002 tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2);
2003 } else {
2004 tcg_gen_or_i64(ret, arg1, arg2);
2005 tcg_gen_not_i64(ret, ret);
2006 }
2007#else
32d98fbd
RH		 2008 tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
2009 tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
32d98fbd 2010#endif
f24cb33e
AJ		 2011}
2012
a7812ae4 2013static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
f24cb33e 2014{
25c4d9cc
RH		 2015 if (TCG_TARGET_HAS_orc_i32) {
2016 tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
2017 } else {
2018 TCGv_i32 t0 = tcg_temp_new_i32();
2019 tcg_gen_not_i32(t0, arg2);
2020 tcg_gen_or_i32(ret, arg1, t0);
2021 tcg_temp_free_i32(t0);
2022 }
f24cb33e
AJ		 2023}
2024
a7812ae4 2025static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
f24cb33e 2026{
25c4d9cc
RH		 2027#if TCG_TARGET_REG_BITS == 64
2028 if (TCG_TARGET_HAS_orc_i64) {
2029 tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
2030 } else {
2031 TCGv_i64 t0 = tcg_temp_new_i64();
2032 tcg_gen_not_i64(t0, arg2);
2033 tcg_gen_or_i64(ret, arg1, t0);
2034 tcg_temp_free_i64(t0);
2035 }
2036#else
791d1262
RH		 2037 tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
2038 tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
791d1262 2039#endif
f24cb33e
AJ		 2040}
2041
a7812ae4 2042static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
15824571 2043{
25c4d9cc
RH		 2044 if (TCG_TARGET_HAS_rot_i32) {
2045 tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
2046 } else {
2047 TCGv_i32 t0, t1;
15824571 2048
25c4d9cc
RH		 2049 t0 = tcg_temp_new_i32();
2050 t1 = tcg_temp_new_i32();
2051 tcg_gen_shl_i32(t0, arg1, arg2);
2052 tcg_gen_subfi_i32(t1, 32, arg2);
2053 tcg_gen_shr_i32(t1, arg1, t1);
2054 tcg_gen_or_i32(ret, t0, t1);
2055 tcg_temp_free_i32(t0);
2056 tcg_temp_free_i32(t1);
2057 }
15824571
AJ		 2058}
2059
a7812ae4 2060static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
15824571 2061{
25c4d9cc
RH		 2062 if (TCG_TARGET_HAS_rot_i64) {
2063 tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
2064 } else {
2065 TCGv_i64 t0, t1;
2066 t0 = tcg_temp_new_i64();
2067 t1 = tcg_temp_new_i64();
2068 tcg_gen_shl_i64(t0, arg1, arg2);
2069 tcg_gen_subfi_i64(t1, 64, arg2);
2070 tcg_gen_shr_i64(t1, arg1, t1);
2071 tcg_gen_or_i64(ret, t0, t1);
2072 tcg_temp_free_i64(t0);
2073 tcg_temp_free_i64(t1);
2074 }
15824571
AJ		 2075}
2076
a7812ae4 2077static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
15824571
AJ		 2078{
2079 /* some cases can be optimized here */
2080 if (arg2 == 0) {
2081 tcg_gen_mov_i32(ret, arg1);
25c4d9cc 2082 } else if (TCG_TARGET_HAS_rot_i32) {
d42f183c
AJ		 2083 TCGv_i32 t0 = tcg_const_i32(arg2);
2084 tcg_gen_rotl_i32(ret, arg1, t0);
2085 tcg_temp_free_i32(t0);
25c4d9cc 2086 } else {
a7812ae4
PB		 2087 TCGv_i32 t0, t1;
2088 t0 = tcg_temp_new_i32();
2089 t1 = tcg_temp_new_i32();
15824571
AJ		 2090 tcg_gen_shli_i32(t0, arg1, arg2);
2091 tcg_gen_shri_i32(t1, arg1, 32 - arg2);
2092 tcg_gen_or_i32(ret, t0, t1);
a7812ae4
PB		 2093 tcg_temp_free_i32(t0);
2094 tcg_temp_free_i32(t1);
15824571
AJ		 2095 }
2096}
2097
a7812ae4 2098static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
15824571
AJ		 2099{
2100 /* some cases can be optimized here */
2101 if (arg2 == 0) {
2102 tcg_gen_mov_i64(ret, arg1);
25c4d9cc 2103 } else if (TCG_TARGET_HAS_rot_i64) {
d42f183c
AJ		 2104 TCGv_i64 t0 = tcg_const_i64(arg2);
2105 tcg_gen_rotl_i64(ret, arg1, t0);
2106 tcg_temp_free_i64(t0);
25c4d9cc 2107 } else {
a7812ae4
PB		 2108 TCGv_i64 t0, t1;
2109 t0 = tcg_temp_new_i64();
2110 t1 = tcg_temp_new_i64();
15824571
AJ		 2111 tcg_gen_shli_i64(t0, arg1, arg2);
2112 tcg_gen_shri_i64(t1, arg1, 64 - arg2);
2113 tcg_gen_or_i64(ret, t0, t1);
a7812ae4
PB		 2114 tcg_temp_free_i64(t0);
2115 tcg_temp_free_i64(t1);
15824571
AJ		 2116 }
2117}
2118
a7812ae4 2119static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
15824571 2120{
25c4d9cc
RH		 2121 if (TCG_TARGET_HAS_rot_i32) {
2122 tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
2123 } else {
2124 TCGv_i32 t0, t1;
15824571 2125
25c4d9cc
RH		 2126 t0 = tcg_temp_new_i32();
2127 t1 = tcg_temp_new_i32();
2128 tcg_gen_shr_i32(t0, arg1, arg2);
2129 tcg_gen_subfi_i32(t1, 32, arg2);
2130 tcg_gen_shl_i32(t1, arg1, t1);
2131 tcg_gen_or_i32(ret, t0, t1);
2132 tcg_temp_free_i32(t0);
2133 tcg_temp_free_i32(t1);
2134 }
15824571
AJ		 2135}
2136
a7812ae4 2137static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
15824571 2138{
25c4d9cc
RH		 2139 if (TCG_TARGET_HAS_rot_i64) {
2140 tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
2141 } else {
2142 TCGv_i64 t0, t1;
2143 t0 = tcg_temp_new_i64();
2144 t1 = tcg_temp_new_i64();
2145 tcg_gen_shr_i64(t0, arg1, arg2);
2146 tcg_gen_subfi_i64(t1, 64, arg2);
2147 tcg_gen_shl_i64(t1, arg1, t1);
2148 tcg_gen_or_i64(ret, t0, t1);
2149 tcg_temp_free_i64(t0);
2150 tcg_temp_free_i64(t1);
2151 }
15824571
AJ		 2152}
2153
a7812ae4 2154static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
15824571
AJ		 2155{
2156 /* some cases can be optimized here */
2157 if (arg2 == 0) {
2158 tcg_gen_mov_i32(ret, arg1);
2159 } else {
2160 tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
2161 }
2162}
2163
a7812ae4 2164static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
15824571
AJ		 2165{
2166 /* some cases can be optimized here */
2167 if (arg2 == 0) {
de3526b2 2168 tcg_gen_mov_i64(ret, arg1);
15824571
AJ		 2169 } else {
2170 tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
2171 }
2172}
2173
b7767f0f 2174static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
0756e71c
RH		 2175 TCGv_i32 arg2, unsigned int ofs,
2176 unsigned int len)
b7767f0f 2177{
df072774
RH		 2178 uint32_t mask;
2179 TCGv_i32 t1;
2180
717e7036
RH		 2181 tcg_debug_assert(ofs < 32);
2182 tcg_debug_assert(len <= 32);
2183 tcg_debug_assert(ofs + len <= 32);
2184
df072774
RH		 2185 if (ofs == 0 && len == 32) {
2186 tcg_gen_mov_i32(ret, arg2);
2187 return;
2188 }
a4773324 2189 if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) {
25c4d9cc 2190 tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
df072774
RH		 2191 return;
2192 }
2193
2194 mask = (1u << len) - 1;
2195 t1 = tcg_temp_new_i32();
b7767f0f 2196
df072774 2197 if (ofs + len < 32) {
25c4d9cc
RH		 2198 tcg_gen_andi_i32(t1, arg2, mask);
2199 tcg_gen_shli_i32(t1, t1, ofs);
df072774
RH		 2200 } else {
2201 tcg_gen_shli_i32(t1, arg2, ofs);
25c4d9cc 2202 }
df072774
RH		 2203 tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
2204 tcg_gen_or_i32(ret, ret, t1);
2205
2206 tcg_temp_free_i32(t1);
b7767f0f
RH		 2207}
2208
2209static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
0756e71c
RH		 2210 TCGv_i64 arg2, unsigned int ofs,
2211 unsigned int len)
b7767f0f 2212{
df072774
RH		 2213 uint64_t mask;
2214 TCGv_i64 t1;
2215
717e7036
RH		 2216 tcg_debug_assert(ofs < 64);
2217 tcg_debug_assert(len <= 64);
2218 tcg_debug_assert(ofs + len <= 64);
2219
df072774
RH		 2220 if (ofs == 0 && len == 64) {
2221 tcg_gen_mov_i64(ret, arg2);
2222 return;
2223 }
a4773324 2224 if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) {
25c4d9cc 2225 tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
df072774
RH		 2226 return;
2227 }
b7767f0f 2228
df072774
RH		 2229#if TCG_TARGET_REG_BITS == 32
2230 if (ofs >= 32) {
2231 tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1),
2232 TCGV_LOW(arg2), ofs - 32, len);
ed605126 2233 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
df072774
RH		 2234 return;
2235 }
2236 if (ofs + len <= 32) {
2237 tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1),
2238 TCGV_LOW(arg2), ofs, len);
2f98c9db 2239 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
df072774
RH		 2240 return;
2241 }
2242#endif
2243
2244 mask = (1ull << len) - 1;
2245 t1 = tcg_temp_new_i64();
2246
2247 if (ofs + len < 64) {
25c4d9cc
RH		 2248 tcg_gen_andi_i64(t1, arg2, mask);
2249 tcg_gen_shli_i64(t1, t1, ofs);
df072774
RH		 2250 } else {
2251 tcg_gen_shli_i64(t1, arg2, ofs);
25c4d9cc 2252 }
df072774
RH		 2253 tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
2254 tcg_gen_or_i64(ret, ret, t1);
2255
2256 tcg_temp_free_i64(t1);
b7767f0f
RH		 2257}
2258
77276f65
RH		 2259static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low,
2260 TCGv_i32 high)
2261{
2262#if TCG_TARGET_REG_BITS == 32
2263 tcg_gen_mov_i32(TCGV_LOW(dest), low);
2264 tcg_gen_mov_i32(TCGV_HIGH(dest), high);
2265#else
2266 TCGv_i64 tmp = tcg_temp_new_i64();
2267 /* These extensions are only needed for type correctness.
2268 We may be able to do better given target specific information. */
2269 tcg_gen_extu_i32_i64(tmp, high);
2270 tcg_gen_extu_i32_i64(dest, low);
2271 /* If deposit is available, use it. Otherwise use the extra
2272 knowledge that we have of the zero-extensions above. */
2273 if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(32, 32)) {
2274 tcg_gen_deposit_i64(dest, dest, tmp, 32, 32);
2275 } else {
2276 tcg_gen_shli_i64(tmp, tmp, 32);
2277 tcg_gen_or_i64(dest, dest, tmp);
2278 }
2279 tcg_temp_free_i64(tmp);
2280#endif
2281}
2282
2283static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low,
2284 TCGv_i64 high)
2285{
2286 tcg_gen_deposit_i64(dest, low, high, 32, 32);
2287}
2288
4bb7a41e
RH		 2289static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
2290{
2291 tcg_gen_trunc_shr_i64_i32(ret, arg, 0);
2292}
2293
3c51a985
RH		 2294static inline void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg)
2295{
4bb7a41e
RH		 2296 tcg_gen_trunc_shr_i64_i32(lo, arg, 0);
2297 tcg_gen_trunc_shr_i64_i32(hi, arg, 32);
3c51a985
RH		 2298}
2299
2300static inline void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg)
2301{
2302 tcg_gen_ext32u_i64(lo, arg);
2303 tcg_gen_shri_i64(hi, arg, 32);
2304}
2305
ffc5ea09
RH		 2306static inline void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret,
2307 TCGv_i32 c1, TCGv_i32 c2,
2308 TCGv_i32 v1, TCGv_i32 v2)
2309{
2310 if (TCG_TARGET_HAS_movcond_i32) {
2311 tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond);
2312 } else {
2313 TCGv_i32 t0 = tcg_temp_new_i32();
2314 TCGv_i32 t1 = tcg_temp_new_i32();
2315 tcg_gen_setcond_i32(cond, t0, c1, c2);
2316 tcg_gen_neg_i32(t0, t0);
2317 tcg_gen_and_i32(t1, v1, t0);
2318 tcg_gen_andc_i32(ret, v2, t0);
2319 tcg_gen_or_i32(ret, ret, t1);
2320 tcg_temp_free_i32(t0);
2321 tcg_temp_free_i32(t1);
2322 }
2323}
2324
2325static inline void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret,
2326 TCGv_i64 c1, TCGv_i64 c2,
2327 TCGv_i64 v1, TCGv_i64 v2)
2328{
a463133e
RH		 2329#if TCG_TARGET_REG_BITS == 32
2330 TCGv_i32 t0 = tcg_temp_new_i32();
2331 TCGv_i32 t1 = tcg_temp_new_i32();
2332 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0,
2333 TCGV_LOW(c1), TCGV_HIGH(c1),
2334 TCGV_LOW(c2), TCGV_HIGH(c2), cond);
a463133e 2335
a80a6b63
RH		 2336 if (TCG_TARGET_HAS_movcond_i32) {
2337 tcg_gen_movi_i32(t1, 0);
2338 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, t1,
2339 TCGV_LOW(v1), TCGV_LOW(v2));
2340 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, t1,
2341 TCGV_HIGH(v1), TCGV_HIGH(v2));
2342 } else {
2343 tcg_gen_neg_i32(t0, t0);
a463133e 2344
a80a6b63
RH		 2345 tcg_gen_and_i32(t1, TCGV_LOW(v1), t0);
2346 tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0);
2347 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1);
a463133e 2348
a80a6b63
RH		 2349 tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0);
2350 tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0);
2351 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1);
2352 }
a463133e
RH		 2353 tcg_temp_free_i32(t0);
2354 tcg_temp_free_i32(t1);
2355#else
ffc5ea09
RH		 2356 if (TCG_TARGET_HAS_movcond_i64) {
2357 tcg_gen_op6i_i64(INDEX_op_movcond_i64, ret, c1, c2, v1, v2, cond);
2358 } else {
2359 TCGv_i64 t0 = tcg_temp_new_i64();
2360 TCGv_i64 t1 = tcg_temp_new_i64();
2361 tcg_gen_setcond_i64(cond, t0, c1, c2);
2362 tcg_gen_neg_i64(t0, t0);
2363 tcg_gen_and_i64(t1, v1, t0);
2364 tcg_gen_andc_i64(ret, v2, t0);
2365 tcg_gen_or_i64(ret, ret, t1);
2366 tcg_temp_free_i64(t0);
2367 tcg_temp_free_i64(t1);
2368 }
a463133e 2369#endif
ffc5ea09
RH		 2370}
2371
f6953a73
RH		 2372static inline void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
2373 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh)
2374{
2375 if (TCG_TARGET_HAS_add2_i32) {
2376 tcg_gen_op6_i32(INDEX_op_add2_i32, rl, rh, al, ah, bl, bh);
2377 /* Allow the optimizer room to replace add2 with two moves. */
2378 tcg_gen_op0(INDEX_op_nop);
2379 } else {
2380 TCGv_i64 t0 = tcg_temp_new_i64();
2381 TCGv_i64 t1 = tcg_temp_new_i64();
2382 tcg_gen_concat_i32_i64(t0, al, ah);
2383 tcg_gen_concat_i32_i64(t1, bl, bh);
2384 tcg_gen_add_i64(t0, t0, t1);
2385 tcg_gen_extr_i64_i32(rl, rh, t0);
2386 tcg_temp_free_i64(t0);
2387 tcg_temp_free_i64(t1);
2388 }
2389}
2390
2391static inline void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
2392 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh)
2393{
2394 if (TCG_TARGET_HAS_sub2_i32) {
2395 tcg_gen_op6_i32(INDEX_op_sub2_i32, rl, rh, al, ah, bl, bh);
2396 /* Allow the optimizer room to replace sub2 with two moves. */
2397 tcg_gen_op0(INDEX_op_nop);
2398 } else {
2399 TCGv_i64 t0 = tcg_temp_new_i64();
2400 TCGv_i64 t1 = tcg_temp_new_i64();
2401 tcg_gen_concat_i32_i64(t0, al, ah);
2402 tcg_gen_concat_i32_i64(t1, bl, bh);
2403 tcg_gen_sub_i64(t0, t0, t1);
2404 tcg_gen_extr_i64_i32(rl, rh, t0);
2405 tcg_temp_free_i64(t0);
2406 tcg_temp_free_i64(t1);
2407 }
2408}
2409
696a8be6
RH		 2410static inline void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh,
2411 TCGv_i32 arg1, TCGv_i32 arg2)
2412{
2413 if (TCG_TARGET_HAS_mulu2_i32) {
2414 tcg_gen_op4_i32(INDEX_op_mulu2_i32, rl, rh, arg1, arg2);
2415 /* Allow the optimizer room to replace mulu2 with two moves. */
2416 tcg_gen_op0(INDEX_op_nop);
03271524
RH		 2417 } else if (TCG_TARGET_HAS_muluh_i32) {
2418 TCGv_i32 t = tcg_temp_new_i32();
2419 tcg_gen_op3_i32(INDEX_op_mul_i32, t, arg1, arg2);
2420 tcg_gen_op3_i32(INDEX_op_muluh_i32, rh, arg1, arg2);
2421 tcg_gen_mov_i32(rl, t);
2422 tcg_temp_free_i32(t);
696a8be6
RH		 2423 } else {
2424 TCGv_i64 t0 = tcg_temp_new_i64();
2425 TCGv_i64 t1 = tcg_temp_new_i64();
2426 tcg_gen_extu_i32_i64(t0, arg1);
2427 tcg_gen_extu_i32_i64(t1, arg2);
2428 tcg_gen_mul_i64(t0, t0, t1);
2429 tcg_gen_extr_i64_i32(rl, rh, t0);
2430 tcg_temp_free_i64(t0);
2431 tcg_temp_free_i64(t1);
2432 }
2433}
2434
2435static inline void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh,
2436 TCGv_i32 arg1, TCGv_i32 arg2)
2437{
2438 if (TCG_TARGET_HAS_muls2_i32) {
2439 tcg_gen_op4_i32(INDEX_op_muls2_i32, rl, rh, arg1, arg2);
2440 /* Allow the optimizer room to replace muls2 with two moves. */
2441 tcg_gen_op0(INDEX_op_nop);
03271524
RH		 2442 } else if (TCG_TARGET_HAS_mulsh_i32) {
2443 TCGv_i32 t = tcg_temp_new_i32();
2444 tcg_gen_op3_i32(INDEX_op_mul_i32, t, arg1, arg2);
2445 tcg_gen_op3_i32(INDEX_op_mulsh_i32, rh, arg1, arg2);
2446 tcg_gen_mov_i32(rl, t);
2447 tcg_temp_free_i32(t);
f46fc4e6 2448 } else if (TCG_TARGET_REG_BITS == 32) {
f402f38f
RH		 2449 TCGv_i32 t0 = tcg_temp_new_i32();
2450 TCGv_i32 t1 = tcg_temp_new_i32();
2451 TCGv_i32 t2 = tcg_temp_new_i32();
2452 TCGv_i32 t3 = tcg_temp_new_i32();
f46fc4e6 2453 tcg_gen_mulu2_i32(t0, t1, arg1, arg2);
f402f38f
RH		 2454 /* Adjust for negative inputs. */
2455 tcg_gen_sari_i32(t2, arg1, 31);
2456 tcg_gen_sari_i32(t3, arg2, 31);
2457 tcg_gen_and_i32(t2, t2, arg2);
2458 tcg_gen_and_i32(t3, t3, arg1);
2459 tcg_gen_sub_i32(rh, t1, t2);
2460 tcg_gen_sub_i32(rh, rh, t3);
2461 tcg_gen_mov_i32(rl, t0);
2462 tcg_temp_free_i32(t0);
2463 tcg_temp_free_i32(t1);
2464 tcg_temp_free_i32(t2);
2465 tcg_temp_free_i32(t3);
696a8be6
RH		 2466 } else {
2467 TCGv_i64 t0 = tcg_temp_new_i64();
2468 TCGv_i64 t1 = tcg_temp_new_i64();
2469 tcg_gen_ext_i32_i64(t0, arg1);
2470 tcg_gen_ext_i32_i64(t1, arg2);
2471 tcg_gen_mul_i64(t0, t0, t1);
2472 tcg_gen_extr_i64_i32(rl, rh, t0);
2473 tcg_temp_free_i64(t0);
2474 tcg_temp_free_i64(t1);
2475 }
2476}
2477
f6953a73
RH		 2478static inline void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
2479 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
2480{
2481 if (TCG_TARGET_HAS_add2_i64) {
2482 tcg_gen_op6_i64(INDEX_op_add2_i64, rl, rh, al, ah, bl, bh);
2483 /* Allow the optimizer room to replace add2 with two moves. */
2484 tcg_gen_op0(INDEX_op_nop);
2485 } else {
2486 TCGv_i64 t0 = tcg_temp_new_i64();
2487 TCGv_i64 t1 = tcg_temp_new_i64();
2488 tcg_gen_add_i64(t0, al, bl);
2489 tcg_gen_setcond_i64(TCG_COND_LTU, t1, t0, al);
2490 tcg_gen_add_i64(rh, ah, bh);
2491 tcg_gen_add_i64(rh, rh, t1);
2492 tcg_gen_mov_i64(rl, t0);
2493 tcg_temp_free_i64(t0);
2494 tcg_temp_free_i64(t1);
2495 }
2496}
2497
2498static inline void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
2499 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
2500{
2501 if (TCG_TARGET_HAS_sub2_i64) {
2502 tcg_gen_op6_i64(INDEX_op_sub2_i64, rl, rh, al, ah, bl, bh);
2503 /* Allow the optimizer room to replace sub2 with two moves. */
2504 tcg_gen_op0(INDEX_op_nop);
2505 } else {
2506 TCGv_i64 t0 = tcg_temp_new_i64();
2507 TCGv_i64 t1 = tcg_temp_new_i64();
2508 tcg_gen_sub_i64(t0, al, bl);
2509 tcg_gen_setcond_i64(TCG_COND_LTU, t1, al, bl);
2510 tcg_gen_sub_i64(rh, ah, bh);
2511 tcg_gen_sub_i64(rh, rh, t1);
2512 tcg_gen_mov_i64(rl, t0);
2513 tcg_temp_free_i64(t0);
2514 tcg_temp_free_i64(t1);
2515 }
2516}
2517
696a8be6
RH		 2518static inline void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh,
2519 TCGv_i64 arg1, TCGv_i64 arg2)
2520{
2521 if (TCG_TARGET_HAS_mulu2_i64) {
2522 tcg_gen_op4_i64(INDEX_op_mulu2_i64, rl, rh, arg1, arg2);
2523 /* Allow the optimizer room to replace mulu2 with two moves. */
2524 tcg_gen_op0(INDEX_op_nop);
03271524
RH		 2525 } else if (TCG_TARGET_HAS_muluh_i64) {
2526 TCGv_i64 t = tcg_temp_new_i64();
2527 tcg_gen_op3_i64(INDEX_op_mul_i64, t, arg1, arg2);
2528 tcg_gen_op3_i64(INDEX_op_muluh_i64, rh, arg1, arg2);
2529 tcg_gen_mov_i64(rl, t);
2530 tcg_temp_free_i64(t);
696a8be6
RH		 2531 } else {
2532 TCGv_i64 t0 = tcg_temp_new_i64();
2533 int sizemask = 0;
2534 /* Return value and both arguments are 64-bit and unsigned. */
2535 sizemask |= tcg_gen_sizemask(0, 1, 0);
2536 sizemask |= tcg_gen_sizemask(1, 1, 0);
2537 sizemask |= tcg_gen_sizemask(2, 1, 0);
2538 tcg_gen_mul_i64(t0, arg1, arg2);
2539 tcg_gen_helper64(tcg_helper_muluh_i64, sizemask, rh, arg1, arg2);
2540 tcg_gen_mov_i64(rl, t0);
2541 tcg_temp_free_i64(t0);
2542 }
2543}
2544
2545static inline void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh,
2546 TCGv_i64 arg1, TCGv_i64 arg2)
2547{
2548 if (TCG_TARGET_HAS_muls2_i64) {
2549 tcg_gen_op4_i64(INDEX_op_muls2_i64, rl, rh, arg1, arg2);
2550 /* Allow the optimizer room to replace muls2 with two moves. */
2551 tcg_gen_op0(INDEX_op_nop);
03271524
RH		 2552 } else if (TCG_TARGET_HAS_mulsh_i64) {
2553 TCGv_i64 t = tcg_temp_new_i64();
2554 tcg_gen_op3_i64(INDEX_op_mul_i64, t, arg1, arg2);
2555 tcg_gen_op3_i64(INDEX_op_mulsh_i64, rh, arg1, arg2);
2556 tcg_gen_mov_i64(rl, t);
2557 tcg_temp_free_i64(t);
662deb90
RH		 2558 } else if (TCG_TARGET_HAS_mulu2_i64 || TCG_TARGET_HAS_muluh_i64) {
2559 TCGv_i64 t0 = tcg_temp_new_i64();
2560 TCGv_i64 t1 = tcg_temp_new_i64();
2561 TCGv_i64 t2 = tcg_temp_new_i64();
2562 TCGv_i64 t3 = tcg_temp_new_i64();
2563 tcg_gen_mulu2_i64(t0, t1, arg1, arg2);
2564 /* Adjust for negative inputs. */
2565 tcg_gen_sari_i64(t2, arg1, 63);
2566 tcg_gen_sari_i64(t3, arg2, 63);
2567 tcg_gen_and_i64(t2, t2, arg2);
2568 tcg_gen_and_i64(t3, t3, arg1);
2569 tcg_gen_sub_i64(rh, t1, t2);
2570 tcg_gen_sub_i64(rh, rh, t3);
2571 tcg_gen_mov_i64(rl, t0);
2572 tcg_temp_free_i64(t0);
2573 tcg_temp_free_i64(t1);
2574 tcg_temp_free_i64(t2);
2575 tcg_temp_free_i64(t3);
696a8be6
RH		 2576 } else {
2577 TCGv_i64 t0 = tcg_temp_new_i64();
2578 int sizemask = 0;
2579 /* Return value and both arguments are 64-bit and signed. */
2580 sizemask |= tcg_gen_sizemask(0, 1, 1);
2581 sizemask |= tcg_gen_sizemask(1, 1, 1);
2582 sizemask |= tcg_gen_sizemask(2, 1, 1);
2583 tcg_gen_mul_i64(t0, arg1, arg2);
2584 tcg_gen_helper64(tcg_helper_mulsh_i64, sizemask, rh, arg1, arg2);
2585 tcg_gen_mov_i64(rl, t0);
2586 tcg_temp_free_i64(t0);
2587 }
2588}
2589
c896fe29
FB		 2590/***************************************/
2591/* QEMU specific operations. Their type depend on the QEMU CPU
2592 type. */
2593#ifndef TARGET_LONG_BITS
2594#error must include QEMU headers
2595#endif
2596
a7812ae4
PB		 2597#if TARGET_LONG_BITS == 32
2598#define TCGv TCGv_i32
2599#define tcg_temp_new() tcg_temp_new_i32()
2600#define tcg_global_reg_new tcg_global_reg_new_i32
2601#define tcg_global_mem_new tcg_global_mem_new_i32
df9247b2 2602#define tcg_temp_local_new() tcg_temp_local_new_i32()
a7812ae4 2603#define tcg_temp_free tcg_temp_free_i32
a7812ae4 2604#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
afcb92be 2605#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x)
fe75bcf7 2606#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
f713d6ad
RH		 2607#define tcg_add_param_tl tcg_add_param_i32
2608#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
2609#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
a7812ae4
PB		 2610#else
2611#define TCGv TCGv_i64
2612#define tcg_temp_new() tcg_temp_new_i64()
2613#define tcg_global_reg_new tcg_global_reg_new_i64
2614#define tcg_global_mem_new tcg_global_mem_new_i64
df9247b2 2615#define tcg_temp_local_new() tcg_temp_local_new_i64()
a7812ae4 2616#define tcg_temp_free tcg_temp_free_i64
a7812ae4 2617#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
afcb92be 2618#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x)
fe75bcf7 2619#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
f713d6ad
RH		 2620#define tcg_add_param_tl tcg_add_param_i64
2621#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
2622#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
a7812ae4
PB		 2623#endif
2624
7e4597d7
FB		 2625/* debug info: write the PC of the corresponding QEMU CPU instruction */
2626static inline void tcg_gen_debug_insn_start(uint64_t pc)
2627{
2628 /* XXX: must really use a 32 bit size for TCGArg in all cases */
2629#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
bcb0126f
PB		 2630 tcg_gen_op2ii(INDEX_op_debug_insn_start,
2631 (uint32_t)(pc), (uint32_t)(pc >> 32));
7e4597d7
FB		 2632#else
2633 tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
2634#endif
2635}
2636
8cfd0495 2637static inline void tcg_gen_exit_tb(uintptr_t val)
c896fe29 2638{
ac56dd48 2639 tcg_gen_op1i(INDEX_op_exit_tb, val);
c896fe29
FB		 2640}
2641
0a209d4b
RH		 2642static inline void tcg_gen_goto_tb(unsigned idx)
2643{
2644 /* We only support two chained exits. */
2645 tcg_debug_assert(idx <= 1);
2646#ifdef CONFIG_DEBUG_TCG
2647 /* Verify that we havn't seen this numbered exit before. */
2648 tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) == 0);
2649 tcg_ctx.goto_tb_issue_mask |= 1 << idx;
2650#endif
ac56dd48 2651 tcg_gen_op1i(INDEX_op_goto_tb, idx);
c896fe29
FB		 2652}
2653
c896fe29 2654
f713d6ad
RH		 2655void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
2656void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
2657void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
2658void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
c896fe29 2659
ac56dd48 2660static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
c896fe29 2661{
f713d6ad 2662 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
c896fe29
FB		 2663}
2664
ac56dd48 2665static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
c896fe29 2666{
f713d6ad 2667 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
c896fe29
FB		 2668}
2669
ac56dd48 2670static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
c896fe29 2671{
f713d6ad 2672 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
c896fe29
FB		 2673}
2674
ac56dd48 2675static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
c896fe29 2676{
f713d6ad 2677 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
c896fe29
FB		 2678}
2679
ac56dd48 2680static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
c896fe29 2681{
f713d6ad 2682 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
c896fe29
FB		 2683}
2684
ac56dd48 2685static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
c896fe29 2686{
f713d6ad 2687 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
c896fe29
FB		 2688}
2689
a7812ae4 2690static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
c896fe29 2691{
f713d6ad 2692 tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ);
c896fe29
FB		 2693}
2694
ac56dd48 2695static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
c896fe29 2696{
f713d6ad 2697 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
c896fe29
FB		 2698}
2699
ac56dd48 2700static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
c896fe29 2701{
f713d6ad 2702 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
c896fe29
FB		 2703}
2704
ac56dd48 2705static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
c896fe29 2706{
f713d6ad 2707 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
c896fe29
FB		 2708}
2709
a7812ae4 2710static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
c896fe29 2711{
f713d6ad 2712 tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ);
c896fe29
FB		 2713}
2714
f8422f52 2715#if TARGET_LONG_BITS == 64
f8422f52
BS		 2716#define tcg_gen_movi_tl tcg_gen_movi_i64
2717#define tcg_gen_mov_tl tcg_gen_mov_i64
2718#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2719#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2720#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2721#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2722#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2723#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2724#define tcg_gen_ld_tl tcg_gen_ld_i64
2725#define tcg_gen_st8_tl tcg_gen_st8_i64
2726#define tcg_gen_st16_tl tcg_gen_st16_i64
2727#define tcg_gen_st32_tl tcg_gen_st32_i64
2728#define tcg_gen_st_tl tcg_gen_st_i64
2729#define tcg_gen_add_tl tcg_gen_add_i64
2730#define tcg_gen_addi_tl tcg_gen_addi_i64
2731#define tcg_gen_sub_tl tcg_gen_sub_i64
390efc54 2732#define tcg_gen_neg_tl tcg_gen_neg_i64
10460c8a 2733#define tcg_gen_subfi_tl tcg_gen_subfi_i64
f8422f52
BS		 2734#define tcg_gen_subi_tl tcg_gen_subi_i64
2735#define tcg_gen_and_tl tcg_gen_and_i64
2736#define tcg_gen_andi_tl tcg_gen_andi_i64
2737#define tcg_gen_or_tl tcg_gen_or_i64
2738#define tcg_gen_ori_tl tcg_gen_ori_i64
2739#define tcg_gen_xor_tl tcg_gen_xor_i64
2740#define tcg_gen_xori_tl tcg_gen_xori_i64
0b6ce4cf 2741#define tcg_gen_not_tl tcg_gen_not_i64
f8422f52
BS		 2742#define tcg_gen_shl_tl tcg_gen_shl_i64
2743#define tcg_gen_shli_tl tcg_gen_shli_i64
2744#define tcg_gen_shr_tl tcg_gen_shr_i64
2745#define tcg_gen_shri_tl tcg_gen_shri_i64
2746#define tcg_gen_sar_tl tcg_gen_sar_i64
2747#define tcg_gen_sari_tl tcg_gen_sari_i64
0cf767d6 2748#define tcg_gen_brcond_tl tcg_gen_brcond_i64
cb63669a 2749#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
be210acb 2750#define tcg_gen_setcond_tl tcg_gen_setcond_i64
add1e7ea 2751#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
f730fd27
TS		 2752#define tcg_gen_mul_tl tcg_gen_mul_i64
2753#define tcg_gen_muli_tl tcg_gen_muli_i64
ab36421e
AJ		 2754#define tcg_gen_div_tl tcg_gen_div_i64
2755#define tcg_gen_rem_tl tcg_gen_rem_i64
864951af
AJ		 2756#define tcg_gen_divu_tl tcg_gen_divu_i64
2757#define tcg_gen_remu_tl tcg_gen_remu_i64
a768e4b2 2758#define tcg_gen_discard_tl tcg_gen_discard_i64
e429073d
BS		 2759#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2760#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2761#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2762#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2763#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2764#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
0b6ce4cf
FB		 2765#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2766#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2767#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2768#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2769#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2770#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
911d79ba
AJ		 2771#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2772#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2773#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
945ca823 2774#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
3c51a985 2775#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
f24cb33e
AJ		 2776#define tcg_gen_andc_tl tcg_gen_andc_i64
2777#define tcg_gen_eqv_tl tcg_gen_eqv_i64
2778#define tcg_gen_nand_tl tcg_gen_nand_i64
2779#define tcg_gen_nor_tl tcg_gen_nor_i64
2780#define tcg_gen_orc_tl tcg_gen_orc_i64
15824571
AJ		 2781#define tcg_gen_rotl_tl tcg_gen_rotl_i64
2782#define tcg_gen_rotli_tl tcg_gen_rotli_i64
2783#define tcg_gen_rotr_tl tcg_gen_rotr_i64
2784#define tcg_gen_rotri_tl tcg_gen_rotri_i64
b7767f0f 2785#define tcg_gen_deposit_tl tcg_gen_deposit_i64
a98824ac 2786#define tcg_const_tl tcg_const_i64
bdffd4a9 2787#define tcg_const_local_tl tcg_const_local_i64
ffc5ea09 2788#define tcg_gen_movcond_tl tcg_gen_movcond_i64
f6953a73
RH		 2789#define tcg_gen_add2_tl tcg_gen_add2_i64
2790#define tcg_gen_sub2_tl tcg_gen_sub2_i64
696a8be6
RH		 2791#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
2792#define tcg_gen_muls2_tl tcg_gen_muls2_i64
f8422f52 2793#else
f8422f52
BS		 2794#define tcg_gen_movi_tl tcg_gen_movi_i32
2795#define tcg_gen_mov_tl tcg_gen_mov_i32
2796#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2797#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2798#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2799#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2800#define tcg_gen_ld32u_tl tcg_gen_ld_i32
2801#define tcg_gen_ld32s_tl tcg_gen_ld_i32
2802#define tcg_gen_ld_tl tcg_gen_ld_i32
2803#define tcg_gen_st8_tl tcg_gen_st8_i32
2804#define tcg_gen_st16_tl tcg_gen_st16_i32
2805#define tcg_gen_st32_tl tcg_gen_st_i32
2806#define tcg_gen_st_tl tcg_gen_st_i32
2807#define tcg_gen_add_tl tcg_gen_add_i32
2808#define tcg_gen_addi_tl tcg_gen_addi_i32
2809#define tcg_gen_sub_tl tcg_gen_sub_i32
390efc54 2810#define tcg_gen_neg_tl tcg_gen_neg_i32
0045734a 2811#define tcg_gen_subfi_tl tcg_gen_subfi_i32
f8422f52
BS		 2812#define tcg_gen_subi_tl tcg_gen_subi_i32
2813#define tcg_gen_and_tl tcg_gen_and_i32
2814#define tcg_gen_andi_tl tcg_gen_andi_i32
2815#define tcg_gen_or_tl tcg_gen_or_i32
2816#define tcg_gen_ori_tl tcg_gen_ori_i32
2817#define tcg_gen_xor_tl tcg_gen_xor_i32
2818#define tcg_gen_xori_tl tcg_gen_xori_i32
0b6ce4cf 2819#define tcg_gen_not_tl tcg_gen_not_i32
f8422f52
BS		 2820#define tcg_gen_shl_tl tcg_gen_shl_i32
2821#define tcg_gen_shli_tl tcg_gen_shli_i32
2822#define tcg_gen_shr_tl tcg_gen_shr_i32
2823#define tcg_gen_shri_tl tcg_gen_shri_i32
2824#define tcg_gen_sar_tl tcg_gen_sar_i32
2825#define tcg_gen_sari_tl tcg_gen_sari_i32
0cf767d6 2826#define tcg_gen_brcond_tl tcg_gen_brcond_i32
cb63669a 2827#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
be210acb 2828#define tcg_gen_setcond_tl tcg_gen_setcond_i32
add1e7ea 2829#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
f730fd27
TS		 2830#define tcg_gen_mul_tl tcg_gen_mul_i32
2831#define tcg_gen_muli_tl tcg_gen_muli_i32
ab36421e
AJ		 2832#define tcg_gen_div_tl tcg_gen_div_i32
2833#define tcg_gen_rem_tl tcg_gen_rem_i32
864951af
AJ		 2834#define tcg_gen_divu_tl tcg_gen_divu_i32
2835#define tcg_gen_remu_tl tcg_gen_remu_i32
a768e4b2 2836#define tcg_gen_discard_tl tcg_gen_discard_i32
e429073d
BS		 2837#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2838#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2839#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2840#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2841#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2842#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
0b6ce4cf
FB		 2843#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2844#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2845#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2846#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2847#define tcg_gen_ext32u_tl tcg_gen_mov_i32
2848#define tcg_gen_ext32s_tl tcg_gen_mov_i32
911d79ba
AJ		 2849#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2850#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
945ca823 2851#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
3c51a985 2852#define tcg_gen_extr_tl_i64 tcg_gen_extr_i32_i64
f24cb33e
AJ		 2853#define tcg_gen_andc_tl tcg_gen_andc_i32
2854#define tcg_gen_eqv_tl tcg_gen_eqv_i32
2855#define tcg_gen_nand_tl tcg_gen_nand_i32
2856#define tcg_gen_nor_tl tcg_gen_nor_i32
2857#define tcg_gen_orc_tl tcg_gen_orc_i32
15824571
AJ		 2858#define tcg_gen_rotl_tl tcg_gen_rotl_i32
2859#define tcg_gen_rotli_tl tcg_gen_rotli_i32
2860#define tcg_gen_rotr_tl tcg_gen_rotr_i32
2861#define tcg_gen_rotri_tl tcg_gen_rotri_i32
b7767f0f 2862#define tcg_gen_deposit_tl tcg_gen_deposit_i32
a98824ac 2863#define tcg_const_tl tcg_const_i32
bdffd4a9 2864#define tcg_const_local_tl tcg_const_local_i32
ffc5ea09 2865#define tcg_gen_movcond_tl tcg_gen_movcond_i32
f6953a73
RH		 2866#define tcg_gen_add2_tl tcg_gen_add2_i32
2867#define tcg_gen_sub2_tl tcg_gen_sub2_i32
696a8be6
RH		 2868#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
2869#define tcg_gen_muls2_tl tcg_gen_muls2_i32
f8422f52 2870#endif
6ddbc6e4 2871
71b92699 2872#if UINTPTR_MAX == UINT32_MAX
f713d6ad
RH		 2873# define tcg_gen_ld_ptr(R, A, O) \
2874 tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O))
2875# define tcg_gen_discard_ptr(A) \
2876 tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A))
2877# define tcg_gen_add_ptr(R, A, B) \
2878 tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B))
2879# define tcg_gen_addi_ptr(R, A, B) \
2880 tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B))
2881# define tcg_gen_ext_i32_ptr(R, A) \
2882 tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A))
2883#else
2884# define tcg_gen_ld_ptr(R, A, O) \
2885 tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O))
2886# define tcg_gen_discard_ptr(A) \
2887 tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A))
2888# define tcg_gen_add_ptr(R, A, B) \
2889 tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B))
2890# define tcg_gen_addi_ptr(R, A, B) \
2891 tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B))
2892# define tcg_gen_ext_i32_ptr(R, A) \
2893 tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
71b92699 2894#endif /* UINTPTR_MAX == UINT32_MAX */
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