[qemu.git] / hw / lm32 / lm32_boards.c

/*
 *  QEMU models for LatticeMico32 uclinux and evr32 boards.
 *
 *  Copyright (c) 2010 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/hw.h"
#include "hw/block/flash.h"
#include "hw/devices.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "sysemu/block-backend.h"
#include "elf.h"
#include "lm32_hwsetup.h"
#include "lm32.h"
#include "exec/address-spaces.h"
#include "sysemu/sysemu.h"

typedef struct {
    LM32CPU *cpu;
    hwaddr bootstrap_pc;
    hwaddr flash_base;
    hwaddr hwsetup_base;
    hwaddr initrd_base;
    size_t initrd_size;
    hwaddr cmdline_base;
} ResetInfo;

static void cpu_irq_handler(void *opaque, int irq, int level)
{
    LM32CPU *cpu = opaque;
    CPUState *cs = CPU(cpu);

    if (level) {
        cpu_interrupt(cs, CPU_INTERRUPT_HARD);
    } else {
        cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
    }
}

static void main_cpu_reset(void *opaque)
{
    ResetInfo *reset_info = opaque;
    CPULM32State *env = &reset_info->cpu->env;

    cpu_reset(CPU(reset_info->cpu));

    /* init defaults */
    env->pc = (uint32_t)reset_info->bootstrap_pc;
    env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
    env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
    env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
    env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
        reset_info->initrd_size);
    env->eba = reset_info->flash_base;
    env->deba = reset_info->flash_base;
}

static void lm32_evr_init(MachineState *machine)
{
    const char *cpu_model = machine->cpu_model;
    const char *kernel_filename = machine->kernel_filename;
    LM32CPU *cpu;
    CPULM32State *env;
    DriveInfo *dinfo;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq irq[32];
    ResetInfo *reset_info;
    int i;

    /* memory map */
    hwaddr flash_base  = 0x04000000;
    size_t flash_sector_size       = 256 * 1024;
    size_t flash_size              = 32 * 1024 * 1024;
    hwaddr ram_base    = 0x08000000;
    size_t ram_size                = 64 * 1024 * 1024;
    hwaddr timer0_base = 0x80002000;
    hwaddr uart0_base  = 0x80006000;
    hwaddr timer1_base = 0x8000a000;
    int uart0_irq                  = 0;
    int timer0_irq                 = 1;
    int timer1_irq                 = 3;

    reset_info = g_malloc0(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    cpu = cpu_lm32_init(cpu_model);
    if (cpu == NULL) {
        fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
        exit(1);
    }

    env = &cpu->env;
    reset_info->cpu = cpu;

    reset_info->flash_base = flash_base;

    memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram",
                                         ram_size);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          flash_sector_size, flash_size / flash_sector_size,
                          1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    lm32_uart_create(uart0_base, irq[uart0_irq], serial_hds[0]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init(serial_hds[1]);

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, EM_LATTICEMICO32, 0, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static void lm32_uclinux_init(MachineState *machine)
{
    const char *cpu_model = machine->cpu_model;
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    const char *initrd_filename = machine->initrd_filename;
    LM32CPU *cpu;
    CPULM32State *env;
    DriveInfo *dinfo;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq irq[32];
    HWSetup *hw;
    ResetInfo *reset_info;
    int i;

    /* memory map */
    hwaddr flash_base   = 0x04000000;
    size_t flash_sector_size        = 256 * 1024;
    size_t flash_size               = 32 * 1024 * 1024;
    hwaddr ram_base     = 0x08000000;
    size_t ram_size                 = 64 * 1024 * 1024;
    hwaddr uart0_base   = 0x80000000;
    hwaddr timer0_base  = 0x80002000;
    hwaddr timer1_base  = 0x80010000;
    hwaddr timer2_base  = 0x80012000;
    int uart0_irq                   = 0;
    int timer0_irq                  = 1;
    int timer1_irq                  = 20;
    int timer2_irq                  = 21;
    hwaddr hwsetup_base = 0x0bffe000;
    hwaddr cmdline_base = 0x0bfff000;
    hwaddr initrd_base  = 0x08400000;
    size_t initrd_max               = 0x01000000;

    reset_info = g_malloc0(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    cpu = cpu_lm32_init(cpu_model);
    if (cpu == NULL) {
        fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
        exit(1);
    }

    env = &cpu->env;
    reset_info->cpu = cpu;

    reset_info->flash_base = flash_base;

    memory_region_allocate_system_memory(phys_ram, NULL,
                                         "lm32_uclinux.sdram", ram_size);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          flash_sector_size, flash_size / flash_sector_size,
                          1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    lm32_uart_create(uart0_base, irq[uart0_irq], serial_hds[0]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
    sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init(serial_hds[1]);

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, EM_LATTICEMICO32, 0, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    /* generate a rom with the hardware description */
    hw = hwsetup_init();
    hwsetup_add_cpu(hw, "LM32", 75000000);
    hwsetup_add_flash(hw, "flash", flash_base, flash_size);
    hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
    hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
    hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
    hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
    hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
    hwsetup_add_trailer(hw);
    hwsetup_create_rom(hw, hwsetup_base);
    hwsetup_free(hw);

    reset_info->hwsetup_base = hwsetup_base;

    if (kernel_cmdline && strlen(kernel_cmdline)) {
        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
                kernel_cmdline);
        reset_info->cmdline_base = cmdline_base;
    }

    if (initrd_filename) {
        size_t initrd_size;
        initrd_size = load_image_targphys(initrd_filename, initrd_base,
                initrd_max);
        reset_info->initrd_base = initrd_base;
        reset_info->initrd_size = initrd_size;
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static void lm32_evr_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "LatticeMico32 EVR32 eval system";
    mc->init = lm32_evr_init;
    mc->is_default = 1;
}

static const TypeInfo lm32_evr_type = {
    .name = MACHINE_TYPE_NAME("lm32-evr"),
    .parent = TYPE_MACHINE,
    .class_init = lm32_evr_class_init,
};

static void lm32_uclinux_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems";
    mc->init = lm32_uclinux_init;
    mc->is_default = 0;
}

static const TypeInfo lm32_uclinux_type = {
    .name = MACHINE_TYPE_NAME("lm32-uclinux"),
    .parent = TYPE_MACHINE,
    .class_init = lm32_uclinux_class_init,
};

static void lm32_machine_init(void)
{
    type_register_static(&lm32_evr_type);
    type_register_static(&lm32_uclinux_type);
}

type_init(lm32_machine_init)
Commit	Line	Data
d821732a MW	1	/*
	2	* QEMU models for LatticeMico32 uclinux and evr32 boards.
	3	*
	4	* Copyright (c) 2010 Michael Walle <[email protected]>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
ea99dde1	20	#include "qemu/osdep.h"
4771d756 PB	21	#include "qemu-common.h"
4771d756 PB	22	#include "cpu.h"
83c9f4ca PB	23	#include "hw/sysbus.h"
83c9f4ca PB	24	#include "hw/hw.h"
0d09e41a	25	#include "hw/block/flash.h"
bd2be150	26	#include "hw/devices.h"
83c9f4ca PB	27	#include "hw/boards.h"
83c9f4ca PB	28	#include "hw/loader.h"
fa1d36df	29	#include "sysemu/block-backend.h"
d821732a	30	#include "elf.h"
47b43a1f PB	31	#include "lm32_hwsetup.h"
47b43a1f PB	32	#include "lm32.h"
022c62cb	33	#include "exec/address-spaces.h"
c2ddaa62	34	#include "sysemu/sysemu.h"
d821732a MW	35
d821732a MW	36	typedef struct {
b1435596	37	LM32CPU *cpu;
a8170e5e AK	38	hwaddr bootstrap_pc;
	39	hwaddr flash_base;
	40	hwaddr hwsetup_base;
	41	hwaddr initrd_base;
d821732a	42	size_t initrd_size;
a8170e5e	43	hwaddr cmdline_base;
d821732a MW	44	} ResetInfo;
	45
	46	static void cpu_irq_handler(void *opaque, int irq, int level)
	47	{
d8ed887b	48	LM32CPU *cpu = opaque;
d8ed887b	49	CPUState *cs = CPU(cpu);
d821732a MW	50
d821732a MW	51	if (level) {
c3affe56	52	cpu_interrupt(cs, CPU_INTERRUPT_HARD);
d821732a	53	} else {
d8ed887b	54	cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
d821732a MW	55	}
	56	}
	57
	58	static void main_cpu_reset(void *opaque)
	59	{
	60	ResetInfo *reset_info = opaque;
b1435596	61	CPULM32State *env = &reset_info->cpu->env;
d821732a	62
b1435596	63	cpu_reset(CPU(reset_info->cpu));
d821732a MW	64
	65	/* init defaults */
	66	env->pc = (uint32_t)reset_info->bootstrap_pc;
	67	env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
	68	env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
	69	env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
	70	env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
	71	reset_info->initrd_size);
	72	env->eba = reset_info->flash_base;
	73	env->deba = reset_info->flash_base;
	74	}
	75
3ef96221	76	static void lm32_evr_init(MachineState *machine)
d821732a	77	{
3ef96221 MA	78	const char *cpu_model = machine->cpu_model;
3ef96221 MA	79	const char *kernel_filename = machine->kernel_filename;
47dc4fa2	80	LM32CPU *cpu;
93a67402	81	CPULM32State *env;
d821732a	82	DriveInfo *dinfo;
88fa8031 AK	83	MemoryRegion *address_space_mem = get_system_memory();
88fa8031 AK	84	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
d4ef00af	85	qemu_irq irq[32];
d821732a MW	86	ResetInfo *reset_info;
	87	int i;
	88
	89	/* memory map */
a8170e5e	90	hwaddr flash_base = 0x04000000;
d821732a MW	91	size_t flash_sector_size = 256 * 1024;
d821732a MW	92	size_t flash_size = 32 * 1024 * 1024;
a8170e5e	93	hwaddr ram_base = 0x08000000;
d821732a	94	size_t ram_size = 64 * 1024 * 1024;
a8170e5e AK	95	hwaddr timer0_base = 0x80002000;
	96	hwaddr uart0_base = 0x80006000;
	97	hwaddr timer1_base = 0x8000a000;
d821732a MW	98	int uart0_irq = 0;
	99	int timer0_irq = 1;
	100	int timer1_irq = 3;
	101
7267c094	102	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a MW	103
	104	if (cpu_model == NULL) {
	105	cpu_model = "lm32-full";
	106	}
47dc4fa2	107	cpu = cpu_lm32_init(cpu_model);
f41152bd MW	108	if (cpu == NULL) {
	109	fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
	110	exit(1);
	111	}
	112
47dc4fa2	113	env = &cpu->env;
b1435596	114	reset_info->cpu = cpu;
d821732a MW	115
	116	reset_info->flash_base = flash_base;
	117
b7ccb83f DM	118	memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram",
b7ccb83f DM	119	ram_size);
88fa8031	120	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
d821732a	121
d821732a MW	122	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	123	/* Spansion S29NS128P */
cfe5f011	124	pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
4be74634	125	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
fa1d36df MA	126	flash_sector_size, flash_size / flash_sector_size,
fa1d36df MA	127	1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	128
d821732a MW	129	/* create irq lines */
d4ef00af	130	env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
d821732a MW	131	for (i = 0; i < 32; i++) {
	132	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	133	}
	134
7aaefcaf	135	lm32_uart_create(uart0_base, irq[uart0_irq], serial_hds[0]);
d821732a MW	136	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	137	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	138
	139	/* make sure juart isn't the first chardev */
c2ddaa62	140	env->juart_state = lm32_juart_init(serial_hds[1]);
d821732a MW	141
	142	reset_info->bootstrap_pc = flash_base;
	143
	144	if (kernel_filename) {
	145	uint64_t entry;
	146	int kernel_size;
	147
	148	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
7ef295ea	149	1, EM_LATTICEMICO32, 0, 0);
d821732a MW	150	reset_info->bootstrap_pc = entry;
	151
	152	if (kernel_size < 0) {
	153	kernel_size = load_image_targphys(kernel_filename, ram_base,
	154	ram_size);
	155	reset_info->bootstrap_pc = ram_base;
	156	}
	157
	158	if (kernel_size < 0) {
	159	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	160	kernel_filename);
	161	exit(1);
	162	}
	163	}
	164
	165	qemu_register_reset(main_cpu_reset, reset_info);
	166	}
	167
3ef96221	168	static void lm32_uclinux_init(MachineState *machine)
d821732a	169	{
3ef96221 MA	170	const char *cpu_model = machine->cpu_model;
	171	const char *kernel_filename = machine->kernel_filename;
	172	const char *kernel_cmdline = machine->kernel_cmdline;
	173	const char *initrd_filename = machine->initrd_filename;
47dc4fa2	174	LM32CPU *cpu;
93a67402	175	CPULM32State *env;
d821732a	176	DriveInfo *dinfo;
88fa8031 AK	177	MemoryRegion *address_space_mem = get_system_memory();
88fa8031 AK	178	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
d4ef00af	179	qemu_irq irq[32];
d821732a MW	180	HWSetup *hw;
	181	ResetInfo *reset_info;
	182	int i;
	183
	184	/* memory map */
a8170e5e	185	hwaddr flash_base = 0x04000000;
d821732a MW	186	size_t flash_sector_size = 256 * 1024;
d821732a MW	187	size_t flash_size = 32 * 1024 * 1024;
a8170e5e	188	hwaddr ram_base = 0x08000000;
d821732a	189	size_t ram_size = 64 * 1024 * 1024;
a8170e5e AK	190	hwaddr uart0_base = 0x80000000;
	191	hwaddr timer0_base = 0x80002000;
	192	hwaddr timer1_base = 0x80010000;
	193	hwaddr timer2_base = 0x80012000;
d821732a MW	194	int uart0_irq = 0;
	195	int timer0_irq = 1;
	196	int timer1_irq = 20;
	197	int timer2_irq = 21;
a8170e5e AK	198	hwaddr hwsetup_base = 0x0bffe000;
	199	hwaddr cmdline_base = 0x0bfff000;
	200	hwaddr initrd_base = 0x08400000;
d821732a MW	201	size_t initrd_max = 0x01000000;
d821732a MW	202
7267c094	203	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a MW	204
	205	if (cpu_model == NULL) {
	206	cpu_model = "lm32-full";
	207	}
47dc4fa2	208	cpu = cpu_lm32_init(cpu_model);
f41152bd MW	209	if (cpu == NULL) {
	210	fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
	211	exit(1);
	212	}
	213
47dc4fa2	214	env = &cpu->env;
b1435596	215	reset_info->cpu = cpu;
d821732a MW	216
	217	reset_info->flash_base = flash_base;
	218
b7ccb83f DM	219	memory_region_allocate_system_memory(phys_ram, NULL,
b7ccb83f DM	220	"lm32_uclinux.sdram", ram_size);
88fa8031	221	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
d821732a	222
d821732a MW	223	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	224	/* Spansion S29NS128P */
cfe5f011	225	pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
4be74634	226	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
fa1d36df MA	227	flash_sector_size, flash_size / flash_sector_size,
fa1d36df MA	228	1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	229
d821732a MW	230	/* create irq lines */
d4ef00af	231	env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
d821732a MW	232	for (i = 0; i < 32; i++) {
	233	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	234	}
	235
7aaefcaf	236	lm32_uart_create(uart0_base, irq[uart0_irq], serial_hds[0]);
d821732a MW	237	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	238	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	239	sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
	240
	241	/* make sure juart isn't the first chardev */
c2ddaa62	242	env->juart_state = lm32_juart_init(serial_hds[1]);
d821732a MW	243
	244	reset_info->bootstrap_pc = flash_base;
	245
	246	if (kernel_filename) {
	247	uint64_t entry;
	248	int kernel_size;
	249
	250	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
7ef295ea	251	1, EM_LATTICEMICO32, 0, 0);
d821732a MW	252	reset_info->bootstrap_pc = entry;
	253
	254	if (kernel_size < 0) {
	255	kernel_size = load_image_targphys(kernel_filename, ram_base,
	256	ram_size);
	257	reset_info->bootstrap_pc = ram_base;
	258	}
	259
	260	if (kernel_size < 0) {
	261	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	262	kernel_filename);
	263	exit(1);
	264	}
	265	}
	266
	267	/* generate a rom with the hardware description */
	268	hw = hwsetup_init();
	269	hwsetup_add_cpu(hw, "LM32", 75000000);
	270	hwsetup_add_flash(hw, "flash", flash_base, flash_size);
	271	hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
	272	hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
	273	hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
	274	hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
	275	hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
	276	hwsetup_add_trailer(hw);
	277	hwsetup_create_rom(hw, hwsetup_base);
	278	hwsetup_free(hw);
	279
	280	reset_info->hwsetup_base = hwsetup_base;
	281
	282	if (kernel_cmdline && strlen(kernel_cmdline)) {
	283	pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
	284	kernel_cmdline);
	285	reset_info->cmdline_base = cmdline_base;
	286	}
	287
	288	if (initrd_filename) {
	289	size_t initrd_size;
	290	initrd_size = load_image_targphys(initrd_filename, initrd_base,
	291	initrd_max);
	292	reset_info->initrd_base = initrd_base;
	293	reset_info->initrd_size = initrd_size;
	294	}
	295
	296	qemu_register_reset(main_cpu_reset, reset_info);
	297	}
	298
8a661aea	299	static void lm32_evr_class_init(ObjectClass oc, void data)
d821732a	300	{
8a661aea AF	301	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	302
e264d29d EH	303	mc->desc = "LatticeMico32 EVR32 eval system";
	304	mc->init = lm32_evr_init;
	305	mc->is_default = 1;
d821732a MW	306	}
d821732a MW	307
8a661aea AF	308	static const TypeInfo lm32_evr_type = {
	309	.name = MACHINE_TYPE_NAME("lm32-evr"),
	310	.parent = TYPE_MACHINE,
	311	.class_init = lm32_evr_class_init,
	312	};
e264d29d	313
8a661aea	314	static void lm32_uclinux_class_init(ObjectClass oc, void data)
e264d29d	315	{
8a661aea AF	316	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	317
e264d29d EH	318	mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems";
	319	mc->init = lm32_uclinux_init;
	320	mc->is_default = 0;
	321	}
	322
8a661aea AF	323	static const TypeInfo lm32_uclinux_type = {
	324	.name = MACHINE_TYPE_NAME("lm32-uclinux"),
	325	.parent = TYPE_MACHINE,
	326	.class_init = lm32_uclinux_class_init,
	327	};
	328
	329	static void lm32_machine_init(void)
	330	{
	331	type_register_static(&lm32_evr_type);
	332	type_register_static(&lm32_uclinux_type);
	333	}
	334
0e6aac87	335	type_init(lm32_machine_init)