[qemu.git] / hw / lm32 / lm32_boards.c

/*
 *  QEMU models for LatticeMico32 uclinux and evr32 boards.
 *
 *  Copyright (c) 2010 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "hw/sysbus.h"
#include "hw/hw.h"
#include "hw/block/flash.h"
#include "hw/devices.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "sysemu/block-backend.h"
#include "elf.h"
#include "lm32_hwsetup.h"
#include "lm32.h"
#include "exec/address-spaces.h"

typedef struct {
    LM32CPU *cpu;
    hwaddr bootstrap_pc;
    hwaddr flash_base;
    hwaddr hwsetup_base;
    hwaddr initrd_base;
    size_t initrd_size;
    hwaddr cmdline_base;
} ResetInfo;

static void cpu_irq_handler(void *opaque, int irq, int level)
{
    LM32CPU *cpu = opaque;
    CPUState *cs = CPU(cpu);

    if (level) {
        cpu_interrupt(cs, CPU_INTERRUPT_HARD);
    } else {
        cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
    }
}

static void main_cpu_reset(void *opaque)
{
    ResetInfo *reset_info = opaque;
    CPULM32State *env = &reset_info->cpu->env;

    cpu_reset(CPU(reset_info->cpu));

    /* init defaults */
    env->pc = (uint32_t)reset_info->bootstrap_pc;
    env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
    env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
    env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
    env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
        reset_info->initrd_size);
    env->eba = reset_info->flash_base;
    env->deba = reset_info->flash_base;
}

static void lm32_evr_init(MachineState *machine)
{
    const char *cpu_model = machine->cpu_model;
    const char *kernel_filename = machine->kernel_filename;
    LM32CPU *cpu;
    CPULM32State *env;
    DriveInfo *dinfo;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq irq[32];
    ResetInfo *reset_info;
    int i;

    /* memory map */
    hwaddr flash_base  = 0x04000000;
    size_t flash_sector_size       = 256 * 1024;
    size_t flash_size              = 32 * 1024 * 1024;
    hwaddr ram_base    = 0x08000000;
    size_t ram_size                = 64 * 1024 * 1024;
    hwaddr timer0_base = 0x80002000;
    hwaddr uart0_base  = 0x80006000;
    hwaddr timer1_base = 0x8000a000;
    int uart0_irq                  = 0;
    int timer0_irq                 = 1;
    int timer1_irq                 = 3;

    reset_info = g_malloc0(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    cpu = cpu_lm32_init(cpu_model);
    if (cpu == NULL) {
        fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
        exit(1);
    }

    env = &cpu->env;
    reset_info->cpu = cpu;

    reset_info->flash_base = flash_base;

    memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram",
                                         ram_size);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          flash_sector_size, flash_size / flash_sector_size,
                          1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init();

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, EM_LATTICEMICO32, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static void lm32_uclinux_init(MachineState *machine)
{
    const char *cpu_model = machine->cpu_model;
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    const char *initrd_filename = machine->initrd_filename;
    LM32CPU *cpu;
    CPULM32State *env;
    DriveInfo *dinfo;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq irq[32];
    HWSetup *hw;
    ResetInfo *reset_info;
    int i;

    /* memory map */
    hwaddr flash_base   = 0x04000000;
    size_t flash_sector_size        = 256 * 1024;
    size_t flash_size               = 32 * 1024 * 1024;
    hwaddr ram_base     = 0x08000000;
    size_t ram_size                 = 64 * 1024 * 1024;
    hwaddr uart0_base   = 0x80000000;
    hwaddr timer0_base  = 0x80002000;
    hwaddr timer1_base  = 0x80010000;
    hwaddr timer2_base  = 0x80012000;
    int uart0_irq                   = 0;
    int timer0_irq                  = 1;
    int timer1_irq                  = 20;
    int timer2_irq                  = 21;
    hwaddr hwsetup_base = 0x0bffe000;
    hwaddr cmdline_base = 0x0bfff000;
    hwaddr initrd_base  = 0x08400000;
    size_t initrd_max               = 0x01000000;

    reset_info = g_malloc0(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    cpu = cpu_lm32_init(cpu_model);
    if (cpu == NULL) {
        fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
        exit(1);
    }

    env = &cpu->env;
    reset_info->cpu = cpu;

    reset_info->flash_base = flash_base;

    memory_region_allocate_system_memory(phys_ram, NULL,
                                         "lm32_uclinux.sdram", ram_size);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          flash_sector_size, flash_size / flash_sector_size,
                          1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
    sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init();

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, EM_LATTICEMICO32, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    /* generate a rom with the hardware description */
    hw = hwsetup_init();
    hwsetup_add_cpu(hw, "LM32", 75000000);
    hwsetup_add_flash(hw, "flash", flash_base, flash_size);
    hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
    hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
    hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
    hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
    hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
    hwsetup_add_trailer(hw);
    hwsetup_create_rom(hw, hwsetup_base);
    hwsetup_free(hw);

    reset_info->hwsetup_base = hwsetup_base;

    if (kernel_cmdline && strlen(kernel_cmdline)) {
        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
                kernel_cmdline);
        reset_info->cmdline_base = cmdline_base;
    }

    if (initrd_filename) {
        size_t initrd_size;
        initrd_size = load_image_targphys(initrd_filename, initrd_base,
                initrd_max);
        reset_info->initrd_base = initrd_base;
        reset_info->initrd_size = initrd_size;
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static void lm32_evr_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "LatticeMico32 EVR32 eval system";
    mc->init = lm32_evr_init;
    mc->is_default = 1;
}

static const TypeInfo lm32_evr_type = {
    .name = MACHINE_TYPE_NAME("lm32-evr"),
    .parent = TYPE_MACHINE,
    .class_init = lm32_evr_class_init,
};

static void lm32_uclinux_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems";
    mc->init = lm32_uclinux_init;
    mc->is_default = 0;
}

static const TypeInfo lm32_uclinux_type = {
    .name = MACHINE_TYPE_NAME("lm32-uclinux"),
    .parent = TYPE_MACHINE,
    .class_init = lm32_uclinux_class_init,
};

static void lm32_machine_init(void)
{
    type_register_static(&lm32_evr_type);
    type_register_static(&lm32_uclinux_type);
}

machine_init(lm32_machine_init)
Commit	Line	Data
d821732a MW	1	/*
	2	* QEMU models for LatticeMico32 uclinux and evr32 boards.
	3	*
	4	* Copyright (c) 2010 Michael Walle <[email protected]>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
83c9f4ca PB	20	#include "hw/sysbus.h"
83c9f4ca PB	21	#include "hw/hw.h"
0d09e41a	22	#include "hw/block/flash.h"
bd2be150	23	#include "hw/devices.h"
83c9f4ca PB	24	#include "hw/boards.h"
83c9f4ca PB	25	#include "hw/loader.h"
fa1d36df	26	#include "sysemu/block-backend.h"
d821732a	27	#include "elf.h"
47b43a1f PB	28	#include "lm32_hwsetup.h"
47b43a1f PB	29	#include "lm32.h"
022c62cb	30	#include "exec/address-spaces.h"
d821732a MW	31
d821732a MW	32	typedef struct {
b1435596	33	LM32CPU *cpu;
a8170e5e AK	34	hwaddr bootstrap_pc;
	35	hwaddr flash_base;
	36	hwaddr hwsetup_base;
	37	hwaddr initrd_base;
d821732a	38	size_t initrd_size;
a8170e5e	39	hwaddr cmdline_base;
d821732a MW	40	} ResetInfo;
	41
	42	static void cpu_irq_handler(void *opaque, int irq, int level)
	43	{
d8ed887b	44	LM32CPU *cpu = opaque;
d8ed887b	45	CPUState *cs = CPU(cpu);
d821732a MW	46
d821732a MW	47	if (level) {
c3affe56	48	cpu_interrupt(cs, CPU_INTERRUPT_HARD);
d821732a	49	} else {
d8ed887b	50	cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
d821732a MW	51	}
	52	}
	53
	54	static void main_cpu_reset(void *opaque)
	55	{
	56	ResetInfo *reset_info = opaque;
b1435596	57	CPULM32State *env = &reset_info->cpu->env;
d821732a	58
b1435596	59	cpu_reset(CPU(reset_info->cpu));
d821732a MW	60
	61	/* init defaults */
	62	env->pc = (uint32_t)reset_info->bootstrap_pc;
	63	env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
	64	env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
	65	env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
	66	env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
	67	reset_info->initrd_size);
	68	env->eba = reset_info->flash_base;
	69	env->deba = reset_info->flash_base;
	70	}
	71
3ef96221	72	static void lm32_evr_init(MachineState *machine)
d821732a	73	{
3ef96221 MA	74	const char *cpu_model = machine->cpu_model;
3ef96221 MA	75	const char *kernel_filename = machine->kernel_filename;
47dc4fa2	76	LM32CPU *cpu;
93a67402	77	CPULM32State *env;
d821732a	78	DriveInfo *dinfo;
88fa8031 AK	79	MemoryRegion *address_space_mem = get_system_memory();
88fa8031 AK	80	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
d4ef00af	81	qemu_irq irq[32];
d821732a MW	82	ResetInfo *reset_info;
	83	int i;
	84
	85	/* memory map */
a8170e5e	86	hwaddr flash_base = 0x04000000;
d821732a MW	87	size_t flash_sector_size = 256 * 1024;
d821732a MW	88	size_t flash_size = 32 * 1024 * 1024;
a8170e5e	89	hwaddr ram_base = 0x08000000;
d821732a	90	size_t ram_size = 64 * 1024 * 1024;
a8170e5e AK	91	hwaddr timer0_base = 0x80002000;
	92	hwaddr uart0_base = 0x80006000;
	93	hwaddr timer1_base = 0x8000a000;
d821732a MW	94	int uart0_irq = 0;
	95	int timer0_irq = 1;
	96	int timer1_irq = 3;
	97
7267c094	98	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a MW	99
	100	if (cpu_model == NULL) {
	101	cpu_model = "lm32-full";
	102	}
47dc4fa2	103	cpu = cpu_lm32_init(cpu_model);
f41152bd MW	104	if (cpu == NULL) {
	105	fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
	106	exit(1);
	107	}
	108
47dc4fa2	109	env = &cpu->env;
b1435596	110	reset_info->cpu = cpu;
d821732a MW	111
	112	reset_info->flash_base = flash_base;
	113
b7ccb83f DM	114	memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram",
b7ccb83f DM	115	ram_size);
88fa8031	116	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
d821732a	117
d821732a MW	118	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	119	/* Spansion S29NS128P */
cfe5f011	120	pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
4be74634	121	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
fa1d36df MA	122	flash_sector_size, flash_size / flash_sector_size,
fa1d36df MA	123	1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	124
d821732a MW	125	/* create irq lines */
d4ef00af	126	env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
d821732a MW	127	for (i = 0; i < 32; i++) {
	128	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	129	}
	130
	131	sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
	132	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	133	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	134
	135	/* make sure juart isn't the first chardev */
	136	env->juart_state = lm32_juart_init();
	137
	138	reset_info->bootstrap_pc = flash_base;
	139
	140	if (kernel_filename) {
	141	uint64_t entry;
	142	int kernel_size;
	143
	144	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
22d2fb4c	145	1, EM_LATTICEMICO32, 0);
d821732a MW	146	reset_info->bootstrap_pc = entry;
	147
	148	if (kernel_size < 0) {
	149	kernel_size = load_image_targphys(kernel_filename, ram_base,
	150	ram_size);
	151	reset_info->bootstrap_pc = ram_base;
	152	}
	153
	154	if (kernel_size < 0) {
	155	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	156	kernel_filename);
	157	exit(1);
	158	}
	159	}
	160
	161	qemu_register_reset(main_cpu_reset, reset_info);
	162	}
	163
3ef96221	164	static void lm32_uclinux_init(MachineState *machine)
d821732a	165	{
3ef96221 MA	166	const char *cpu_model = machine->cpu_model;
	167	const char *kernel_filename = machine->kernel_filename;
	168	const char *kernel_cmdline = machine->kernel_cmdline;
	169	const char *initrd_filename = machine->initrd_filename;
47dc4fa2	170	LM32CPU *cpu;
93a67402	171	CPULM32State *env;
d821732a	172	DriveInfo *dinfo;
88fa8031 AK	173	MemoryRegion *address_space_mem = get_system_memory();
88fa8031 AK	174	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
d4ef00af	175	qemu_irq irq[32];
d821732a MW	176	HWSetup *hw;
	177	ResetInfo *reset_info;
	178	int i;
	179
	180	/* memory map */
a8170e5e	181	hwaddr flash_base = 0x04000000;
d821732a MW	182	size_t flash_sector_size = 256 * 1024;
d821732a MW	183	size_t flash_size = 32 * 1024 * 1024;
a8170e5e	184	hwaddr ram_base = 0x08000000;
d821732a	185	size_t ram_size = 64 * 1024 * 1024;
a8170e5e AK	186	hwaddr uart0_base = 0x80000000;
	187	hwaddr timer0_base = 0x80002000;
	188	hwaddr timer1_base = 0x80010000;
	189	hwaddr timer2_base = 0x80012000;
d821732a MW	190	int uart0_irq = 0;
	191	int timer0_irq = 1;
	192	int timer1_irq = 20;
	193	int timer2_irq = 21;
a8170e5e AK	194	hwaddr hwsetup_base = 0x0bffe000;
	195	hwaddr cmdline_base = 0x0bfff000;
	196	hwaddr initrd_base = 0x08400000;
d821732a MW	197	size_t initrd_max = 0x01000000;
d821732a MW	198
7267c094	199	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a MW	200
	201	if (cpu_model == NULL) {
	202	cpu_model = "lm32-full";
	203	}
47dc4fa2	204	cpu = cpu_lm32_init(cpu_model);
f41152bd MW	205	if (cpu == NULL) {
	206	fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
	207	exit(1);
	208	}
	209
47dc4fa2	210	env = &cpu->env;
b1435596	211	reset_info->cpu = cpu;
d821732a MW	212
	213	reset_info->flash_base = flash_base;
	214
b7ccb83f DM	215	memory_region_allocate_system_memory(phys_ram, NULL,
b7ccb83f DM	216	"lm32_uclinux.sdram", ram_size);
88fa8031	217	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
d821732a	218
d821732a MW	219	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	220	/* Spansion S29NS128P */
cfe5f011	221	pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
4be74634	222	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
fa1d36df MA	223	flash_sector_size, flash_size / flash_sector_size,
fa1d36df MA	224	1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	225
d821732a MW	226	/* create irq lines */
d4ef00af	227	env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
d821732a MW	228	for (i = 0; i < 32; i++) {
	229	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	230	}
	231
	232	sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
	233	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	234	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	235	sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
	236
	237	/* make sure juart isn't the first chardev */
	238	env->juart_state = lm32_juart_init();
	239
	240	reset_info->bootstrap_pc = flash_base;
	241
	242	if (kernel_filename) {
	243	uint64_t entry;
	244	int kernel_size;
	245
	246	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
22d2fb4c	247	1, EM_LATTICEMICO32, 0);
d821732a MW	248	reset_info->bootstrap_pc = entry;
	249
	250	if (kernel_size < 0) {
	251	kernel_size = load_image_targphys(kernel_filename, ram_base,
	252	ram_size);
	253	reset_info->bootstrap_pc = ram_base;
	254	}
	255
	256	if (kernel_size < 0) {
	257	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	258	kernel_filename);
	259	exit(1);
	260	}
	261	}
	262
	263	/* generate a rom with the hardware description */
	264	hw = hwsetup_init();
	265	hwsetup_add_cpu(hw, "LM32", 75000000);
	266	hwsetup_add_flash(hw, "flash", flash_base, flash_size);
	267	hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
	268	hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
	269	hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
	270	hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
	271	hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
	272	hwsetup_add_trailer(hw);
	273	hwsetup_create_rom(hw, hwsetup_base);
	274	hwsetup_free(hw);
	275
	276	reset_info->hwsetup_base = hwsetup_base;
	277
	278	if (kernel_cmdline && strlen(kernel_cmdline)) {
	279	pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
	280	kernel_cmdline);
	281	reset_info->cmdline_base = cmdline_base;
	282	}
	283
	284	if (initrd_filename) {
	285	size_t initrd_size;
	286	initrd_size = load_image_targphys(initrd_filename, initrd_base,
	287	initrd_max);
	288	reset_info->initrd_base = initrd_base;
	289	reset_info->initrd_size = initrd_size;
	290	}
	291
	292	qemu_register_reset(main_cpu_reset, reset_info);
	293	}
	294
8a661aea	295	static void lm32_evr_class_init(ObjectClass oc, void data)
d821732a	296	{
8a661aea AF	297	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	298
e264d29d EH	299	mc->desc = "LatticeMico32 EVR32 eval system";
	300	mc->init = lm32_evr_init;
	301	mc->is_default = 1;
d821732a MW	302	}
d821732a MW	303
8a661aea AF	304	static const TypeInfo lm32_evr_type = {
	305	.name = MACHINE_TYPE_NAME("lm32-evr"),
	306	.parent = TYPE_MACHINE,
	307	.class_init = lm32_evr_class_init,
	308	};
e264d29d	309
8a661aea	310	static void lm32_uclinux_class_init(ObjectClass oc, void data)
e264d29d	311	{
8a661aea AF	312	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	313
e264d29d EH	314	mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems";
	315	mc->init = lm32_uclinux_init;
	316	mc->is_default = 0;
	317	}
	318
8a661aea AF	319	static const TypeInfo lm32_uclinux_type = {
	320	.name = MACHINE_TYPE_NAME("lm32-uclinux"),
	321	.parent = TYPE_MACHINE,
	322	.class_init = lm32_uclinux_class_init,
	323	};
	324
	325	static void lm32_machine_init(void)
	326	{
	327	type_register_static(&lm32_evr_type);
	328	type_register_static(&lm32_uclinux_type);
	329	}
	330
	331	machine_init(lm32_machine_init)