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[qemu.git] / hw / block / nand.c
CommitLineData
3e3d5815
AZ		 1/*
2 * Flash NAND memory emulation. Based on "16M x 8 Bit NAND Flash
3 * Memory" datasheet for the KM29U128AT / K9F2808U0A chips from
4 * Samsung Electronic.
5 *
6 * Copyright (c) 2006 Openedhand Ltd.
7 * Written by Andrzej Zaborowski <[email protected]>
8 *
d5f2fd58
JR		 9 * Support for additional features based on "MT29F2G16ABCWP 2Gx16"
10 * datasheet from Micron Technology and "NAND02G-B2C" datasheet
11 * from ST Microelectronics.
12 *
3e3d5815 13 * This code is licensed under the GNU GPL v2.
6b620ca3
PB		 14 *
15 * Contributions after 2012-01-13 are licensed under the terms of the
16 * GNU GPL, version 2 or (at your option) any later version.
3e3d5815
AZ		 17 */
18
19#ifndef NAND_IO
20
74c0e474
PM		 21#include "qemu/osdep.h"
22#include "hw/hw.h"
23#include "hw/block/flash.h"
4be74634 24#include "sysemu/block-backend.h"
7426aa72 25#include "hw/qdev.h"
da34e65c 26#include "qapi/error.h"
1de7afc9 27#include "qemu/error-report.h"
3e3d5815
AZ		 28
29# define NAND_CMD_READ0 0x00
30# define NAND_CMD_READ1 0x01
31# define NAND_CMD_READ2 0x50
32# define NAND_CMD_LPREAD2 0x30
33# define NAND_CMD_NOSERIALREAD2 0x35
34# define NAND_CMD_RANDOMREAD1 0x05
35# define NAND_CMD_RANDOMREAD2 0xe0
36# define NAND_CMD_READID 0x90
37# define NAND_CMD_RESET 0xff
38# define NAND_CMD_PAGEPROGRAM1 0x80
39# define NAND_CMD_PAGEPROGRAM2 0x10
40# define NAND_CMD_CACHEPROGRAM2 0x15
41# define NAND_CMD_BLOCKERASE1 0x60
42# define NAND_CMD_BLOCKERASE2 0xd0
43# define NAND_CMD_READSTATUS 0x70
44# define NAND_CMD_COPYBACKPRG1 0x85
45
46# define NAND_IOSTATUS_ERROR (1 << 0)
47# define NAND_IOSTATUS_PLANE0 (1 << 1)
48# define NAND_IOSTATUS_PLANE1 (1 << 2)
49# define NAND_IOSTATUS_PLANE2 (1 << 3)
50# define NAND_IOSTATUS_PLANE3 (1 << 4)
0bc472a9 51# define NAND_IOSTATUS_READY (1 << 6)
3e3d5815
AZ		 52# define NAND_IOSTATUS_UNPROTCT (1 << 7)
53
54# define MAX_PAGE 0x800
55# define MAX_OOB 0x40
56
d4220389 57typedef struct NANDFlashState NANDFlashState;
bc24a225 58struct NANDFlashState {
7426aa72
PC		 59 DeviceState parent_obj;
60
3e3d5815 61 uint8_t manf_id, chip_id;
48197dfa 62 uint8_t buswidth; /* in BYTES */
3e3d5815
AZ		 63 int size, pages;
64 int page_shift, oob_shift, erase_shift, addr_shift;
65 uint8_t *storage;
4be74634 66 BlockBackend *blk;
3e3d5815
AZ		 67 int mem_oob;
68
51db57f7 69 uint8_t cle, ale, ce, wp, gnd;
3e3d5815
AZ		 70
71 uint8_t io[MAX_PAGE + MAX_OOB + 0x400];
72 uint8_t *ioaddr;
73 int iolen;
74
d5f2fd58
JR		 75 uint32_t cmd;
76 uint64_t addr;
3e3d5815
AZ		 77 int addrlen;
78 int status;
79 int offset;
80
bc24a225
PB		 81 void (*blk_write)(NANDFlashState *s);
82 void (*blk_erase)(NANDFlashState *s);
d5f2fd58 83 void (*blk_load)(NANDFlashState *s, uint64_t addr, int offset);
7b9a3d86
JQ		 84
85 uint32_t ioaddr_vmstate;
3e3d5815
AZ		 86};
87
e12078cc
PC		 88#define TYPE_NAND "nand"
89
90#define NAND(obj) \
91 OBJECT_CHECK(NANDFlashState, (obj), TYPE_NAND)
92
89f640bc
PM		 93static void mem_and(uint8_t *dest, const uint8_t *src, size_t n)
94{
95 /* Like memcpy() but we logical-AND the data into the destination */
96 int i;
97 for (i = 0; i < n; i++) {
98 dest[i] &= src[i];
99 }
100}
101
3e3d5815
AZ		 102# define NAND_NO_AUTOINCR 0x00000001
103# define NAND_BUSWIDTH_16 0x00000002
104# define NAND_NO_PADDING 0x00000004
105# define NAND_CACHEPRG 0x00000008
106# define NAND_COPYBACK 0x00000010
107# define NAND_IS_AND 0x00000020
108# define NAND_4PAGE_ARRAY 0x00000040
109# define NAND_NO_READRDY 0x00000100
110# define NAND_SAMSUNG_LP (NAND_NO_PADDING | NAND_COPYBACK)
111
112# define NAND_IO
113
114# define PAGE(addr) ((addr) >> ADDR_SHIFT)
115# define PAGE_START(page) (PAGE(page) * (PAGE_SIZE + OOB_SIZE))
116# define PAGE_MASK ((1 << ADDR_SHIFT) - 1)
117# define OOB_SHIFT (PAGE_SHIFT - 5)
118# define OOB_SIZE (1 << OOB_SHIFT)
119# define SECTOR(addr) ((addr) >> (9 + ADDR_SHIFT - PAGE_SHIFT))
120# define SECTOR_OFFSET(addr) ((addr) & ((511 >> PAGE_SHIFT) << 8))
121
122# define PAGE_SIZE 256
123# define PAGE_SHIFT 8
124# define PAGE_SECTORS 1
125# define ADDR_SHIFT 8
126# include "nand.c"
127# define PAGE_SIZE 512
128# define PAGE_SHIFT 9
129# define PAGE_SECTORS 1
130# define ADDR_SHIFT 8
131# include "nand.c"
132# define PAGE_SIZE 2048
133# define PAGE_SHIFT 11
134# define PAGE_SECTORS 4
135# define ADDR_SHIFT 16
136# include "nand.c"
137
138/* Information based on Linux drivers/mtd/nand/nand_ids.c */
bc24a225 139static const struct {
3e3d5815
AZ		 140 int size;
141 int width;
142 int page_shift;
143 int erase_shift;
144 uint32_t options;
145} nand_flash_ids[0x100] = {
146 [0 ... 0xff] = { 0 },
147
148 [0x6e] = { 1, 8, 8, 4, 0 },
149 [0x64] = { 2, 8, 8, 4, 0 },
150 [0x6b] = { 4, 8, 9, 4, 0 },
151 [0xe8] = { 1, 8, 8, 4, 0 },
152 [0xec] = { 1, 8, 8, 4, 0 },
153 [0xea] = { 2, 8, 8, 4, 0 },
154 [0xd5] = { 4, 8, 9, 4, 0 },
155 [0xe3] = { 4, 8, 9, 4, 0 },
156 [0xe5] = { 4, 8, 9, 4, 0 },
157 [0xd6] = { 8, 8, 9, 4, 0 },
158
159 [0x39] = { 8, 8, 9, 4, 0 },
160 [0xe6] = { 8, 8, 9, 4, 0 },
161 [0x49] = { 8, 16, 9, 4, NAND_BUSWIDTH_16 },
162 [0x59] = { 8, 16, 9, 4, NAND_BUSWIDTH_16 },
163
164 [0x33] = { 16, 8, 9, 5, 0 },
165 [0x73] = { 16, 8, 9, 5, 0 },
166 [0x43] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
167 [0x53] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
168
169 [0x35] = { 32, 8, 9, 5, 0 },
170 [0x75] = { 32, 8, 9, 5, 0 },
171 [0x45] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
172 [0x55] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
173
174 [0x36] = { 64, 8, 9, 5, 0 },
175 [0x76] = { 64, 8, 9, 5, 0 },
176 [0x46] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
177 [0x56] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
178
179 [0x78] = { 128, 8, 9, 5, 0 },
180 [0x39] = { 128, 8, 9, 5, 0 },
181 [0x79] = { 128, 8, 9, 5, 0 },
182 [0x72] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
183 [0x49] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
184 [0x74] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
185 [0x59] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
186
187 [0x71] = { 256, 8, 9, 5, 0 },
188
189 /*
190 * These are the new chips with large page size. The pagesize and the
191 * erasesize is determined from the extended id bytes
192 */
193# define LP_OPTIONS (NAND_SAMSUNG_LP | NAND_NO_READRDY | NAND_NO_AUTOINCR)
194# define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
195
196 /* 512 Megabit */
197 [0xa2] = { 64, 8, 0, 0, LP_OPTIONS },
198 [0xf2] = { 64, 8, 0, 0, LP_OPTIONS },
199 [0xb2] = { 64, 16, 0, 0, LP_OPTIONS16 },
200 [0xc2] = { 64, 16, 0, 0, LP_OPTIONS16 },
201
202 /* 1 Gigabit */
203 [0xa1] = { 128, 8, 0, 0, LP_OPTIONS },
204 [0xf1] = { 128, 8, 0, 0, LP_OPTIONS },
205 [0xb1] = { 128, 16, 0, 0, LP_OPTIONS16 },
206 [0xc1] = { 128, 16, 0, 0, LP_OPTIONS16 },
207
208 /* 2 Gigabit */
209 [0xaa] = { 256, 8, 0, 0, LP_OPTIONS },
210 [0xda] = { 256, 8, 0, 0, LP_OPTIONS },
211 [0xba] = { 256, 16, 0, 0, LP_OPTIONS16 },
212 [0xca] = { 256, 16, 0, 0, LP_OPTIONS16 },
213
214 /* 4 Gigabit */
215 [0xac] = { 512, 8, 0, 0, LP_OPTIONS },
216 [0xdc] = { 512, 8, 0, 0, LP_OPTIONS },
217 [0xbc] = { 512, 16, 0, 0, LP_OPTIONS16 },
218 [0xcc] = { 512, 16, 0, 0, LP_OPTIONS16 },
219
220 /* 8 Gigabit */
221 [0xa3] = { 1024, 8, 0, 0, LP_OPTIONS },
222 [0xd3] = { 1024, 8, 0, 0, LP_OPTIONS },
223 [0xb3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
224 [0xc3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
225
226 /* 16 Gigabit */
227 [0xa5] = { 2048, 8, 0, 0, LP_OPTIONS },
228 [0xd5] = { 2048, 8, 0, 0, LP_OPTIONS },
229 [0xb5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
230 [0xc5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
231};
232
d4220389 233static void nand_reset(DeviceState *dev)
3e3d5815 234{
e12078cc 235 NANDFlashState *s = NAND(dev);
3e3d5815
AZ		 236 s->cmd = NAND_CMD_READ0;
237 s->addr = 0;
238 s->addrlen = 0;
239 s->iolen = 0;
240 s->offset = 0;
241 s->status &= NAND_IOSTATUS_UNPROTCT;
0bc472a9 242 s->status |= NAND_IOSTATUS_READY;
3e3d5815
AZ		 243}
244
48197dfa
JR		 245static inline void nand_pushio_byte(NANDFlashState *s, uint8_t value)
246{
247 s->ioaddr[s->iolen++] = value;
248 for (value = s->buswidth; --value;) {
249 s->ioaddr[s->iolen++] = 0;
250 }
251}
252
bc24a225 253static void nand_command(NANDFlashState *s)
3e3d5815 254{
fccd2613 255 unsigned int offset;
3e3d5815
AZ		 256 switch (s->cmd) {
257 case NAND_CMD_READ0:
258 s->iolen = 0;
259 break;
260
261 case NAND_CMD_READID:
3e3d5815 262 s->ioaddr = s->io;
48197dfa
JR		 263 s->iolen = 0;
264 nand_pushio_byte(s, s->manf_id);
265 nand_pushio_byte(s, s->chip_id);
266 nand_pushio_byte(s, 'Q'); /* Don't-care byte (often 0xa5) */
267 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
268 /* Page Size, Block Size, Spare Size; bit 6 indicates
269 * 8 vs 16 bit width NAND.
270 */
271 nand_pushio_byte(s, (s->buswidth == 2) ? 0x55 : 0x15);
272 } else {
273 nand_pushio_byte(s, 0xc0); /* Multi-plane */
274 }
3e3d5815
AZ		 275 break;
276
277 case NAND_CMD_RANDOMREAD2:
278 case NAND_CMD_NOSERIALREAD2:
279 if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP))
280 break;
fccd2613
EI		 281 offset = s->addr & ((1 << s->addr_shift) - 1);
282 s->blk_load(s, s->addr, offset);
283 if (s->gnd)
284 s->iolen = (1 << s->page_shift) - offset;
285 else
286 s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
3e3d5815
AZ		 287 break;
288
289 case NAND_CMD_RESET:
e12078cc 290 nand_reset(DEVICE(s));
3e3d5815
AZ		 291 break;
292
293 case NAND_CMD_PAGEPROGRAM1:
294 s->ioaddr = s->io;
295 s->iolen = 0;
296 break;
297
298 case NAND_CMD_PAGEPROGRAM2:
299 if (s->wp) {
300 s->blk_write(s);
301 }
302 break;
303
304 case NAND_CMD_BLOCKERASE1:
305 break;
306
307 case NAND_CMD_BLOCKERASE2:
32aea752 308 s->addr &= (1ull << s->addrlen * 8) - 1;
1984745e
PC		 309 s->addr <<= nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP ?
310 16 : 8;
3e3d5815
AZ		 311
312 if (s->wp) {
313 s->blk_erase(s);
314 }
315 break;
316
317 case NAND_CMD_READSTATUS:
3e3d5815 318 s->ioaddr = s->io;
48197dfa
JR		 319 s->iolen = 0;
320 nand_pushio_byte(s, s->status);
3e3d5815
AZ		 321 break;
322
323 default:
324 printf("%s: Unknown NAND command 0x%02x\n", __FUNCTION__, s->cmd);
325 }
326}
327
7b9a3d86 328static void nand_pre_save(void *opaque)
aa941b94 329{
e12078cc 330 NANDFlashState *s = NAND(opaque);
7b9a3d86
JQ		 331
332 s->ioaddr_vmstate = s->ioaddr - s->io;
aa941b94
AZ		 333}
334
7b9a3d86 335static int nand_post_load(void *opaque, int version_id)
aa941b94 336{
e12078cc 337 NANDFlashState *s = NAND(opaque);
7b9a3d86
JQ		 338
339 if (s->ioaddr_vmstate > sizeof(s->io)) {
aa941b94 340 return -EINVAL;
7b9a3d86
JQ		 341 }
342 s->ioaddr = s->io + s->ioaddr_vmstate;
aa941b94 343
aa941b94
AZ		 344 return 0;
345}
346
7b9a3d86
JQ		 347static const VMStateDescription vmstate_nand = {
348 .name = "nand",
ac2466cd
AZ		 349 .version_id = 1,
350 .minimum_version_id = 1,
7b9a3d86
JQ		 351 .pre_save = nand_pre_save,
352 .post_load = nand_post_load,
8f1e884b 353 .fields = (VMStateField[]) {
7b9a3d86
JQ		 354 VMSTATE_UINT8(cle, NANDFlashState),
355 VMSTATE_UINT8(ale, NANDFlashState),
356 VMSTATE_UINT8(ce, NANDFlashState),
357 VMSTATE_UINT8(wp, NANDFlashState),
358 VMSTATE_UINT8(gnd, NANDFlashState),
359 VMSTATE_BUFFER(io, NANDFlashState),
360 VMSTATE_UINT32(ioaddr_vmstate, NANDFlashState),
361 VMSTATE_INT32(iolen, NANDFlashState),
362 VMSTATE_UINT32(cmd, NANDFlashState),
d5f2fd58 363 VMSTATE_UINT64(addr, NANDFlashState),
7b9a3d86
JQ		 364 VMSTATE_INT32(addrlen, NANDFlashState),
365 VMSTATE_INT32(status, NANDFlashState),
366 VMSTATE_INT32(offset, NANDFlashState),
367 /* XXX: do we want to save s->storage too? */
368 VMSTATE_END_OF_LIST()
369 }
370};
371
d47a5d9b 372static void nand_realize(DeviceState *dev, Error **errp)
d4220389
JR		 373{
374 int pagesize;
e12078cc 375 NANDFlashState *s = NAND(dev);
a17c17a2
KW		 376 int ret;
377
d4220389
JR		 378
379 s->buswidth = nand_flash_ids[s->chip_id].width >> 3;
380 s->size = nand_flash_ids[s->chip_id].size << 20;
381 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
382 s->page_shift = 11;
383 s->erase_shift = 6;
384 } else {
385 s->page_shift = nand_flash_ids[s->chip_id].page_shift;
386 s->erase_shift = nand_flash_ids[s->chip_id].erase_shift;
387 }
388
389 switch (1 << s->page_shift) {
390 case 256:
391 nand_init_256(s);
392 break;
393 case 512:
394 nand_init_512(s);
395 break;
396 case 2048:
397 nand_init_2048(s);
398 break;
399 default:
eec5eb42 400 error_setg(errp, "Unsupported NAND block size %#x",
d47a5d9b
PC		 401 1 << s->page_shift);
402 return;
d4220389
JR		 403 }
404
405 pagesize = 1 << s->oob_shift;
406 s->mem_oob = 1;
4be74634
MA		 407 if (s->blk) {
408 if (blk_is_read_only(s->blk)) {
d47a5d9b
PC		 409 error_setg(errp, "Can't use a read-only drive");
410 return;
3fc3abf7 411 }
a17c17a2
KW		 412 ret = blk_set_perm(s->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE,
413 BLK_PERM_ALL, errp);
414 if (ret < 0) {
415 return;
416 }
4be74634 417 if (blk_getlength(s->blk) >=
3fc3abf7
JR		 418 (s->pages << s->page_shift) + (s->pages << s->oob_shift)) {
419 pagesize = 0;
420 s->mem_oob = 0;
421 }
422 } else {
d4220389
JR		 423 pagesize += 1 << s->page_shift;
424 }
425 if (pagesize) {
7267c094 426 s->storage = (uint8_t *) memset(g_malloc(s->pages * pagesize),
d4220389
JR		 427 0xff, s->pages * pagesize);
428 }
429 /* Give s->ioaddr a sane value in case we save state before it is used. */
430 s->ioaddr = s->io;
d4220389
JR		 431}
432
999e12bb
AL		 433static Property nand_properties[] = {
434 DEFINE_PROP_UINT8("manufacturer_id", NANDFlashState, manf_id, 0),
435 DEFINE_PROP_UINT8("chip_id", NANDFlashState, chip_id, 0),
4be74634 436 DEFINE_PROP_DRIVE("drive", NANDFlashState, blk),
999e12bb
AL		 437 DEFINE_PROP_END_OF_LIST(),
438};
439
440static void nand_class_init(ObjectClass *klass, void *data)
441{
39bffca2 442 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 443
d47a5d9b 444 dc->realize = nand_realize;
39bffca2
AL		 445 dc->reset = nand_reset;
446 dc->vmsd = &vmstate_nand;
447 dc->props = nand_properties;
999e12bb
AL		 448}
449
8c43a6f0 450static const TypeInfo nand_info = {
e12078cc 451 .name = TYPE_NAND,
7426aa72 452 .parent = TYPE_DEVICE,
39bffca2
AL		 453 .instance_size = sizeof(NANDFlashState),
454 .class_init = nand_class_init,
d4220389
JR		 455};
456
83f7d43a 457static void nand_register_types(void)
d4220389 458{
39bffca2 459 type_register_static(&nand_info);
d4220389
JR		 460}
461
3e3d5815
AZ		 462/*
463 * Chip inputs are CLE, ALE, CE, WP, GND and eight I/O pins. Chip
464 * outputs are R/B and eight I/O pins.
465 *
466 * CE, WP and R/B are active low.
467 */
d4220389 468void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
51db57f7 469 uint8_t ce, uint8_t wp, uint8_t gnd)
3e3d5815 470{
e12078cc
PC		 471 NANDFlashState *s = NAND(dev);
472
3e3d5815
AZ		 473 s->cle = cle;
474 s->ale = ale;
475 s->ce = ce;
476 s->wp = wp;
477 s->gnd = gnd;
1984745e 478 if (wp) {
3e3d5815 479 s->status |= NAND_IOSTATUS_UNPROTCT;
1984745e 480 } else {
3e3d5815 481 s->status &= ~NAND_IOSTATUS_UNPROTCT;
1984745e 482 }
3e3d5815
AZ		 483}
484
d4220389 485void nand_getpins(DeviceState *dev, int *rb)
3e3d5815
AZ		 486{
487 *rb = 1;
488}
489
d4220389 490void nand_setio(DeviceState *dev, uint32_t value)
3e3d5815 491{
48197dfa 492 int i;
e12078cc
PC		 493 NANDFlashState *s = NAND(dev);
494
3e3d5815
AZ		 495 if (!s->ce && s->cle) {
496 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
497 if (s->cmd == NAND_CMD_READ0 && value == NAND_CMD_LPREAD2)
498 return;
499 if (value == NAND_CMD_RANDOMREAD1) {
500 s->addr &= ~((1 << s->addr_shift) - 1);
501 s->addrlen = 0;
502 return;
503 }
504 }
1984745e 505 if (value == NAND_CMD_READ0) {
3e3d5815 506 s->offset = 0;
1984745e 507 } else if (value == NAND_CMD_READ1) {
3e3d5815
AZ		 508 s->offset = 0x100;
509 value = NAND_CMD_READ0;
1984745e 510 } else if (value == NAND_CMD_READ2) {
3e3d5815
AZ		 511 s->offset = 1 << s->page_shift;
512 value = NAND_CMD_READ0;
513 }
514
515 s->cmd = value;
516
517 if (s->cmd == NAND_CMD_READSTATUS ||
518 s->cmd == NAND_CMD_PAGEPROGRAM2 ||
519 s->cmd == NAND_CMD_BLOCKERASE1 ||
520 s->cmd == NAND_CMD_BLOCKERASE2 ||
521 s->cmd == NAND_CMD_NOSERIALREAD2 ||
522 s->cmd == NAND_CMD_RANDOMREAD2 ||
1984745e 523 s->cmd == NAND_CMD_RESET) {
3e3d5815 524 nand_command(s);
1984745e 525 }
3e3d5815
AZ		 526
527 if (s->cmd != NAND_CMD_RANDOMREAD2) {
528 s->addrlen = 0;
3e3d5815
AZ		 529 }
530 }
531
532 if (s->ale) {
fccd2613 533 unsigned int shift = s->addrlen * 8;
a184e74f
RV		 534 uint64_t mask = ~(0xffull << shift);
535 uint64_t v = (uint64_t)value << shift;
fccd2613
EI		 536
537 s->addr = (s->addr & mask) | v;
3e3d5815
AZ		 538 s->addrlen ++;
539
48197dfa
JR		 540 switch (s->addrlen) {
541 case 1:
542 if (s->cmd == NAND_CMD_READID) {
543 nand_command(s);
544 }
545 break;
546 case 2: /* fix cache address as a byte address */
547 s->addr <<= (s->buswidth - 1);
548 break;
549 case 3:
550 if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
551 (s->cmd == NAND_CMD_READ0 ||
552 s->cmd == NAND_CMD_PAGEPROGRAM1)) {
553 nand_command(s);
554 }
555 break;
556 case 4:
557 if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
558 nand_flash_ids[s->chip_id].size < 256 && /* 1Gb or less */
559 (s->cmd == NAND_CMD_READ0 ||
560 s->cmd == NAND_CMD_PAGEPROGRAM1)) {
561 nand_command(s);
562 }
563 break;
564 case 5:
565 if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
566 nand_flash_ids[s->chip_id].size >= 256 && /* 2Gb or more */
567 (s->cmd == NAND_CMD_READ0 ||
568 s->cmd == NAND_CMD_PAGEPROGRAM1)) {
569 nand_command(s);
570 }
571 break;
572 default:
573 break;
574 }
3e3d5815
AZ		 575 }
576
577 if (!s->cle && !s->ale && s->cmd == NAND_CMD_PAGEPROGRAM1) {
48197dfa
JR		 578 if (s->iolen < (1 << s->page_shift) + (1 << s->oob_shift)) {
579 for (i = s->buswidth; i--; value >>= 8) {
580 s->io[s->iolen ++] = (uint8_t) (value & 0xff);
581 }
582 }
3e3d5815
AZ		 583 } else if (!s->cle && !s->ale && s->cmd == NAND_CMD_COPYBACKPRG1) {
584 if ((s->addr & ((1 << s->addr_shift) - 1)) <
585 (1 << s->page_shift) + (1 << s->oob_shift)) {
48197dfa
JR		 586 for (i = s->buswidth; i--; s->addr++, value >>= 8) {
587 s->io[s->iolen + (s->addr & ((1 << s->addr_shift) - 1))] =
588 (uint8_t) (value & 0xff);
589 }
3e3d5815
AZ		 590 }
591 }
592}
593
d4220389 594uint32_t nand_getio(DeviceState *dev)
3e3d5815
AZ		 595{
596 int offset;
48197dfa 597 uint32_t x = 0;
e12078cc 598 NANDFlashState *s = NAND(dev);
5fafdf24 599
3e3d5815
AZ		 600 /* Allow sequential reading */
601 if (!s->iolen && s->cmd == NAND_CMD_READ0) {
d5f2fd58 602 offset = (int) (s->addr & ((1 << s->addr_shift) - 1)) + s->offset;
3e3d5815
AZ		 603 s->offset = 0;
604
605 s->blk_load(s, s->addr, offset);
606 if (s->gnd)
607 s->iolen = (1 << s->page_shift) - offset;
608 else
609 s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
610 }
611
1984745e 612 if (s->ce || s->iolen <= 0) {
3e3d5815 613 return 0;
1984745e 614 }
3e3d5815 615
48197dfa
JR		 616 for (offset = s->buswidth; offset--;) {
617 x |= s->ioaddr[offset] << (offset << 3);
618 }
d72245fb
JR		 619 /* after receiving READ STATUS command all subsequent reads will
620 * return the status register value until another command is issued
621 */
622 if (s->cmd != NAND_CMD_READSTATUS) {
623 s->addr += s->buswidth;
624 s->ioaddr += s->buswidth;
625 s->iolen -= s->buswidth;
626 }
48197dfa
JR		 627 return x;
628}
629
d4220389 630uint32_t nand_getbuswidth(DeviceState *dev)
48197dfa 631{
d4220389 632 NANDFlashState *s = (NANDFlashState *) dev;
48197dfa 633 return s->buswidth << 3;
3e3d5815
AZ		 634}
635
4be74634 636DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id)
3e3d5815 637{
d4220389 638 DeviceState *dev;
3e3d5815
AZ		 639
640 if (nand_flash_ids[chip_id].size == 0) {
2ac71179 641 hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__);
3e3d5815 642 }
6749695e 643 dev = DEVICE(object_new(TYPE_NAND));
d4220389
JR		 644 qdev_prop_set_uint8(dev, "manufacturer_id", manf_id);
645 qdev_prop_set_uint8(dev, "chip_id", chip_id);
4be74634 646 if (blk) {
6231a6da 647 qdev_prop_set_drive(dev, "drive", blk, &error_fatal);
3e3d5815
AZ		 648 }
649
d4220389
JR		 650 qdev_init_nofail(dev);
651 return dev;
3e3d5815
AZ		 652}
653
83f7d43a 654type_init(nand_register_types)
3e3d5815
AZ		 655
656#else
657
658/* Program a single page */
bc24a225 659static void glue(nand_blk_write_, PAGE_SIZE)(NANDFlashState *s)
3e3d5815 660{
d5f2fd58 661 uint64_t off, page, sector, soff;
3e3d5815
AZ		 662 uint8_t iobuf[(PAGE_SECTORS + 2) * 0x200];
663 if (PAGE(s->addr) >= s->pages)
664 return;
665
4be74634 666 if (!s->blk) {
89f640bc 667 mem_and(s->storage + PAGE_START(s->addr) + (s->addr & PAGE_MASK) +
3e3d5815
AZ		 668 s->offset, s->io, s->iolen);
669 } else if (s->mem_oob) {
670 sector = SECTOR(s->addr);
671 off = (s->addr & PAGE_MASK) + s->offset;
672 soff = SECTOR_OFFSET(s->addr);
9fc0d361
EB		 673 if (blk_pread(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
674 PAGE_SECTORS << BDRV_SECTOR_BITS) < 0) {
d5f2fd58 675 printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
3e3d5815
AZ		 676 return;
677 }
678
89f640bc 679 mem_and(iobuf + (soff | off), s->io, MIN(s->iolen, PAGE_SIZE - off));
3e3d5815
AZ		 680 if (off + s->iolen > PAGE_SIZE) {
681 page = PAGE(s->addr);
89f640bc 682 mem_and(s->storage + (page << OOB_SHIFT), s->io + PAGE_SIZE - off,
3e3d5815
AZ		 683 MIN(OOB_SIZE, off + s->iolen - PAGE_SIZE));
684 }
685
9fc0d361
EB		 686 if (blk_pwrite(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
687 PAGE_SECTORS << BDRV_SECTOR_BITS, 0) < 0) {
d5f2fd58 688 printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
7a608f56 689 }
3e3d5815
AZ		 690 } else {
691 off = PAGE_START(s->addr) + (s->addr & PAGE_MASK) + s->offset;
692 sector = off >> 9;
693 soff = off & 0x1ff;
9fc0d361
EB		 694 if (blk_pread(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
695 (PAGE_SECTORS + 2) << BDRV_SECTOR_BITS) < 0) {
d5f2fd58 696 printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
3e3d5815
AZ		 697 return;
698 }
699
89f640bc 700 mem_and(iobuf + soff, s->io, s->iolen);
3e3d5815 701
9fc0d361
EB		 702 if (blk_pwrite(s->blk, sector << BDRV_SECTOR_BITS, iobuf,
703 (PAGE_SECTORS + 2) << BDRV_SECTOR_BITS, 0) < 0) {
d5f2fd58 704 printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
7a608f56 705 }
3e3d5815
AZ		 706 }
707 s->offset = 0;
708}
709
710/* Erase a single block */
bc24a225 711static void glue(nand_blk_erase_, PAGE_SIZE)(NANDFlashState *s)
3e3d5815 712{
d5f2fd58 713 uint64_t i, page, addr;
3e3d5815
AZ		 714 uint8_t iobuf[0x200] = { [0 ... 0x1ff] = 0xff, };
715 addr = s->addr & ~((1 << (ADDR_SHIFT + s->erase_shift)) - 1);
716
1984745e 717 if (PAGE(addr) >= s->pages) {
3e3d5815 718 return;
1984745e 719 }
3e3d5815 720
4be74634 721 if (!s->blk) {
3e3d5815
AZ		 722 memset(s->storage + PAGE_START(addr),
723 0xff, (PAGE_SIZE + OOB_SIZE) << s->erase_shift);
724 } else if (s->mem_oob) {
725 memset(s->storage + (PAGE(addr) << OOB_SHIFT),
726 0xff, OOB_SIZE << s->erase_shift);
727 i = SECTOR(addr);
8e37ca6d 728 page = SECTOR(addr + (1 << (ADDR_SHIFT + s->erase_shift)));
3e3d5815 729 for (; i < page; i ++)
9fc0d361
EB		 730 if (blk_pwrite(s->blk, i << BDRV_SECTOR_BITS, iobuf,
731 BDRV_SECTOR_SIZE, 0) < 0) {
d5f2fd58 732 printf("%s: write error in sector %" PRIu64 "\n", __func__, i);
7a608f56 733 }
3e3d5815
AZ		 734 } else {
735 addr = PAGE_START(addr);
736 page = addr >> 9;
9fc0d361
EB		 737 if (blk_pread(s->blk, page << BDRV_SECTOR_BITS, iobuf,
738 BDRV_SECTOR_SIZE) < 0) {
d5f2fd58 739 printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
7a608f56 740 }
3e3d5815 741 memset(iobuf + (addr & 0x1ff), 0xff, (~addr & 0x1ff) + 1);
9fc0d361
EB		 742 if (blk_pwrite(s->blk, page << BDRV_SECTOR_BITS, iobuf,
743 BDRV_SECTOR_SIZE, 0) < 0) {
d5f2fd58 744 printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
7a608f56 745 }
3e3d5815
AZ		 746
747 memset(iobuf, 0xff, 0x200);
748 i = (addr & ~0x1ff) + 0x200;
749 for (addr += ((PAGE_SIZE + OOB_SIZE) << s->erase_shift) - 0x200;
1984745e 750 i < addr; i += 0x200) {
9fc0d361 751 if (blk_pwrite(s->blk, i, iobuf, BDRV_SECTOR_SIZE, 0) < 0) {
d5f2fd58
JR		 752 printf("%s: write error in sector %" PRIu64 "\n",
753 __func__, i >> 9);
7a608f56 754 }
1984745e 755 }
3e3d5815
AZ		 756
757 page = i >> 9;
9fc0d361
EB		 758 if (blk_pread(s->blk, page << BDRV_SECTOR_BITS, iobuf,
759 BDRV_SECTOR_SIZE) < 0) {
d5f2fd58 760 printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
7a608f56 761 }
a07dec22 762 memset(iobuf, 0xff, ((addr - 1) & 0x1ff) + 1);
9fc0d361
EB		 763 if (blk_pwrite(s->blk, page << BDRV_SECTOR_BITS, iobuf,
764 BDRV_SECTOR_SIZE, 0) < 0) {
d5f2fd58 765 printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
7a608f56 766 }
3e3d5815
AZ		 767 }
768}
769
bc24a225 770static void glue(nand_blk_load_, PAGE_SIZE)(NANDFlashState *s,
d5f2fd58 771 uint64_t addr, int offset)
3e3d5815 772{
1984745e 773 if (PAGE(addr) >= s->pages) {
3e3d5815 774 return;
1984745e 775 }
3e3d5815 776
4be74634 777 if (s->blk) {
3e3d5815 778 if (s->mem_oob) {
9fc0d361
EB		 779 if (blk_pread(s->blk, SECTOR(addr) << BDRV_SECTOR_BITS, s->io,
780 PAGE_SECTORS << BDRV_SECTOR_BITS) < 0) {
d5f2fd58
JR		 781 printf("%s: read error in sector %" PRIu64 "\n",
782 __func__, SECTOR(addr));
7a608f56 783 }
3e3d5815
AZ		 784 memcpy(s->io + SECTOR_OFFSET(s->addr) + PAGE_SIZE,
785 s->storage + (PAGE(s->addr) << OOB_SHIFT),
786 OOB_SIZE);
787 s->ioaddr = s->io + SECTOR_OFFSET(s->addr) + offset;
788 } else {
9fc0d361
EB		 789 if (blk_pread(s->blk, PAGE_START(addr), s->io,
790 (PAGE_SECTORS + 2) << BDRV_SECTOR_BITS) < 0) {
d5f2fd58
JR		 791 printf("%s: read error in sector %" PRIu64 "\n",
792 __func__, PAGE_START(addr) >> 9);
7a608f56 793 }
3e3d5815
AZ		 794 s->ioaddr = s->io + (PAGE_START(addr) & 0x1ff) + offset;
795 }
796 } else {
797 memcpy(s->io, s->storage + PAGE_START(s->addr) +
798 offset, PAGE_SIZE + OOB_SIZE - offset);
799 s->ioaddr = s->io;
800 }
3e3d5815
AZ		 801}
802
bc24a225 803static void glue(nand_init_, PAGE_SIZE)(NANDFlashState *s)
3e3d5815
AZ		 804{
805 s->oob_shift = PAGE_SHIFT - 5;
806 s->pages = s->size >> PAGE_SHIFT;
807 s->addr_shift = ADDR_SHIFT;
808
809 s->blk_erase = glue(nand_blk_erase_, PAGE_SIZE);
810 s->blk_write = glue(nand_blk_write_, PAGE_SIZE);
811 s->blk_load = glue(nand_blk_load_, PAGE_SIZE);
812}
813
814# undef PAGE_SIZE
815# undef PAGE_SHIFT
816# undef PAGE_SECTORS
817# undef ADDR_SHIFT
818#endif /* NAND_IO */
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