[qemu.git] / hw / m48t59.c

/*
 * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
 *
 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "nvram.h"
#include "isa.h"
#include "qemu-timer.h"
#include "sysemu.h"

//#define DEBUG_NVRAM

#if defined(DEBUG_NVRAM)
#define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
#else
#define NVRAM_PRINTF(fmt, args...) do { } while (0)
#endif

/*
 * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
 * alarm and a watchdog timer and related control registers. In the
 * PPC platform there is also a nvram lock function.
 */
struct m48t59_t {
    /* Model parameters */
    int type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
    /* Hardware parameters */
    qemu_irq IRQ;
    int mem_index;
    target_phys_addr_t mem_base;
    uint32_t io_base;
    uint16_t size;
    /* RTC management */
    time_t   time_offset;
    time_t   stop_time;
    /* Alarm & watchdog */
    time_t   alarm;
    struct QEMUTimer *alrm_timer;
    struct QEMUTimer *wd_timer;
    /* NVRAM storage */
    uint8_t  lock;
    uint16_t addr;
    uint8_t *buffer;
};

/* Fake timer functions */
/* Generic helpers for BCD */
static inline uint8_t toBCD (uint8_t value)
{
    return (((value / 10) % 10) << 4) | (value % 10);
}

static inline uint8_t fromBCD (uint8_t BCD)
{
    return ((BCD >> 4) * 10) + (BCD & 0x0F);
}

/* RTC management helpers */
static void get_time (m48t59_t *NVRAM, struct tm *tm)
{
    time_t t;

    t = time(NULL) + NVRAM->time_offset;
#ifdef _WIN32
    memcpy(tm,localtime(&t),sizeof(*tm));
#else
    if (rtc_utc)
        gmtime_r (&t, tm);
    else
        localtime_r (&t, tm) ;
#endif
}

static void set_time (m48t59_t *NVRAM, struct tm *tm)
{
    time_t now, new_time;

    new_time = mktime(tm);
    now = time(NULL);
    NVRAM->time_offset = new_time - now;
}

/* Alarm management */
static void alarm_cb (void *opaque)
{
    struct tm tm, tm_now;
    uint64_t next_time;
    m48t59_t *NVRAM = opaque;

    qemu_set_irq(NVRAM->IRQ, 1);
    if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
	(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	/* Repeat once a month */
	get_time(NVRAM, &tm_now);
	memcpy(&tm, &tm_now, sizeof(struct tm));
	tm.tm_mon++;
	if (tm.tm_mon == 13) {
	    tm.tm_mon = 1;
	    tm.tm_year++;
	}
	next_time = mktime(&tm);
    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	       (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	       (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	/* Repeat once a day */
	next_time = 24 * 60 * 60 + mktime(&tm_now);
    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	       (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	/* Repeat once an hour */
	next_time = 60 * 60 + mktime(&tm_now);
    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	/* Repeat once a minute */
	next_time = 60 + mktime(&tm_now);
    } else {
	/* Repeat once a second */
	next_time = 1 + mktime(&tm_now);
    }
    qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
    qemu_set_irq(NVRAM->IRQ, 0);
}


static void get_alarm (m48t59_t *NVRAM, struct tm *tm)
{
#ifdef _WIN32
    memcpy(tm,localtime(&NVRAM->alarm),sizeof(*tm));
#else
    if (rtc_utc)
        gmtime_r (&NVRAM->alarm, tm);
    else
        localtime_r (&NVRAM->alarm, tm);
#endif
}

static void set_alarm (m48t59_t *NVRAM, struct tm *tm)
{
    NVRAM->alarm = mktime(tm);
    if (NVRAM->alrm_timer != NULL) {
        qemu_del_timer(NVRAM->alrm_timer);
        if (NVRAM->alarm - time(NULL) > 0)
            qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
    }
}

/* Watchdog management */
static void watchdog_cb (void *opaque)
{
    m48t59_t *NVRAM = opaque;

    NVRAM->buffer[0x1FF0] |= 0x80;
    if (NVRAM->buffer[0x1FF7] & 0x80) {
	NVRAM->buffer[0x1FF7] = 0x00;
	NVRAM->buffer[0x1FFC] &= ~0x40;
        /* May it be a hw CPU Reset instead ? */
        qemu_system_reset_request();
    } else {
	qemu_set_irq(NVRAM->IRQ, 1);
	qemu_set_irq(NVRAM->IRQ, 0);
    }
}

static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
{
    uint64_t interval; /* in 1/16 seconds */

    NVRAM->buffer[0x1FF0] &= ~0x80;
    if (NVRAM->wd_timer != NULL) {
        qemu_del_timer(NVRAM->wd_timer);
        if (value != 0) {
            interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
            qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
                           ((interval * 1000) >> 4));
        }
    }
}

/* Direct access to NVRAM */
void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
{
    m48t59_t *NVRAM = opaque;
    struct tm tm;
    int tmp;

    if (addr > 0x1FF8 && addr < 0x2000)
	NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);

    /* check for NVRAM access */
    if ((NVRAM->type == 2 && addr < 0x7f8) ||
        (NVRAM->type == 8 && addr < 0x1ff8) ||
        (NVRAM->type == 59 && addr < 0x1ff0))
        goto do_write;

    /* TOD access */
    switch (addr) {
    case 0x1FF0:
        /* flags register : read-only */
        break;
    case 0x1FF1:
        /* unused */
        break;
    case 0x1FF2:
        /* alarm seconds */
        tmp = fromBCD(val & 0x7F);
        if (tmp >= 0 && tmp <= 59) {
            get_alarm(NVRAM, &tm);
            tm.tm_sec = tmp;
            NVRAM->buffer[0x1FF2] = val;
            set_alarm(NVRAM, &tm);
        }
        break;
    case 0x1FF3:
        /* alarm minutes */
        tmp = fromBCD(val & 0x7F);
        if (tmp >= 0 && tmp <= 59) {
            get_alarm(NVRAM, &tm);
            tm.tm_min = tmp;
            NVRAM->buffer[0x1FF3] = val;
            set_alarm(NVRAM, &tm);
        }
        break;
    case 0x1FF4:
        /* alarm hours */
        tmp = fromBCD(val & 0x3F);
        if (tmp >= 0 && tmp <= 23) {
            get_alarm(NVRAM, &tm);
            tm.tm_hour = tmp;
            NVRAM->buffer[0x1FF4] = val;
            set_alarm(NVRAM, &tm);
        }
        break;
    case 0x1FF5:
        /* alarm date */
        tmp = fromBCD(val & 0x1F);
        if (tmp != 0) {
            get_alarm(NVRAM, &tm);
            tm.tm_mday = tmp;
            NVRAM->buffer[0x1FF5] = val;
            set_alarm(NVRAM, &tm);
        }
        break;
    case 0x1FF6:
        /* interrupts */
        NVRAM->buffer[0x1FF6] = val;
        break;
    case 0x1FF7:
        /* watchdog */
        NVRAM->buffer[0x1FF7] = val;
        set_up_watchdog(NVRAM, val);
        break;
    case 0x1FF8:
    case 0x07F8:
        /* control */
       NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
        break;
    case 0x1FF9:
    case 0x07F9:
        /* seconds (BCD) */
	tmp = fromBCD(val & 0x7F);
	if (tmp >= 0 && tmp <= 59) {
	    get_time(NVRAM, &tm);
	    tm.tm_sec = tmp;
	    set_time(NVRAM, &tm);
	}
       if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
	    if (val & 0x80) {
		NVRAM->stop_time = time(NULL);
	    } else {
		NVRAM->time_offset += NVRAM->stop_time - time(NULL);
		NVRAM->stop_time = 0;
	    }
	}
       NVRAM->buffer[addr] = val & 0x80;
        break;
    case 0x1FFA:
    case 0x07FA:
        /* minutes (BCD) */
	tmp = fromBCD(val & 0x7F);
	if (tmp >= 0 && tmp <= 59) {
	    get_time(NVRAM, &tm);
	    tm.tm_min = tmp;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFB:
    case 0x07FB:
        /* hours (BCD) */
	tmp = fromBCD(val & 0x3F);
	if (tmp >= 0 && tmp <= 23) {
	    get_time(NVRAM, &tm);
	    tm.tm_hour = tmp;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFC:
    case 0x07FC:
        /* day of the week / century */
	tmp = fromBCD(val & 0x07);
	get_time(NVRAM, &tm);
	tm.tm_wday = tmp;
	set_time(NVRAM, &tm);
        NVRAM->buffer[addr] = val & 0x40;
        break;
    case 0x1FFD:
    case 0x07FD:
        /* date */
	tmp = fromBCD(val & 0x1F);
	if (tmp != 0) {
	    get_time(NVRAM, &tm);
	    tm.tm_mday = tmp;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFE:
    case 0x07FE:
        /* month */
	tmp = fromBCD(val & 0x1F);
	if (tmp >= 1 && tmp <= 12) {
	    get_time(NVRAM, &tm);
	    tm.tm_mon = tmp - 1;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFF:
    case 0x07FF:
        /* year */
	tmp = fromBCD(val);
	if (tmp >= 0 && tmp <= 99) {
	    get_time(NVRAM, &tm);
            if (NVRAM->type == 8)
                tm.tm_year = fromBCD(val) + 68; // Base year is 1968
            else
                tm.tm_year = fromBCD(val);
	    set_time(NVRAM, &tm);
	}
        break;
    default:
        /* Check lock registers state */
        if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
            break;
        if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
            break;
    do_write:
        if (addr < NVRAM->size) {
            NVRAM->buffer[addr] = val & 0xFF;
	}
        break;
    }
}

uint32_t m48t59_read (void *opaque, uint32_t addr)
{
    m48t59_t *NVRAM = opaque;
    struct tm tm;
    uint32_t retval = 0xFF;

    /* check for NVRAM access */
    if ((NVRAM->type == 2 && addr < 0x078f) ||
        (NVRAM->type == 8 && addr < 0x1ff8) ||
        (NVRAM->type == 59 && addr < 0x1ff0))
        goto do_read;

    /* TOD access */
    switch (addr) {
    case 0x1FF0:
        /* flags register */
	goto do_read;
    case 0x1FF1:
        /* unused */
	retval = 0;
        break;
    case 0x1FF2:
        /* alarm seconds */
	goto do_read;
    case 0x1FF3:
        /* alarm minutes */
	goto do_read;
    case 0x1FF4:
        /* alarm hours */
	goto do_read;
    case 0x1FF5:
        /* alarm date */
	goto do_read;
    case 0x1FF6:
        /* interrupts */
	goto do_read;
    case 0x1FF7:
	/* A read resets the watchdog */
	set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
	goto do_read;
    case 0x1FF8:
    case 0x07F8:
        /* control */
	goto do_read;
    case 0x1FF9:
    case 0x07F9:
        /* seconds (BCD) */
        get_time(NVRAM, &tm);
        retval = (NVRAM->buffer[addr] & 0x80) | toBCD(tm.tm_sec);
        break;
    case 0x1FFA:
    case 0x07FA:
        /* minutes (BCD) */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_min);
        break;
    case 0x1FFB:
    case 0x07FB:
        /* hours (BCD) */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_hour);
        break;
    case 0x1FFC:
    case 0x07FC:
        /* day of the week / century */
        get_time(NVRAM, &tm);
        retval = NVRAM->buffer[addr] | tm.tm_wday;
        break;
    case 0x1FFD:
    case 0x07FD:
        /* date */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_mday);
        break;
    case 0x1FFE:
    case 0x07FE:
        /* month */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_mon + 1);
        break;
    case 0x1FFF:
    case 0x07FF:
        /* year */
        get_time(NVRAM, &tm);
        if (NVRAM->type == 8)
            retval = toBCD(tm.tm_year - 68); // Base year is 1968
        else
            retval = toBCD(tm.tm_year);
        break;
    default:
        /* Check lock registers state */
        if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
            break;
        if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
            break;
    do_read:
        if (addr < NVRAM->size) {
            retval = NVRAM->buffer[addr];
	}
        break;
    }
    if (addr > 0x1FF9 && addr < 0x2000)
       NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);

    return retval;
}

void m48t59_set_addr (void *opaque, uint32_t addr)
{
    m48t59_t *NVRAM = opaque;

    NVRAM->addr = addr;
}

void m48t59_toggle_lock (void *opaque, int lock)
{
    m48t59_t *NVRAM = opaque;

    NVRAM->lock ^= 1 << lock;
}

/* IO access to NVRAM */
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
{
    m48t59_t *NVRAM = opaque;

    addr -= NVRAM->io_base;
    NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
    switch (addr) {
    case 0:
        NVRAM->addr &= ~0x00FF;
        NVRAM->addr |= val;
        break;
    case 1:
        NVRAM->addr &= ~0xFF00;
        NVRAM->addr |= val << 8;
        break;
    case 3:
        m48t59_write(NVRAM, val, NVRAM->addr);
        NVRAM->addr = 0x0000;
        break;
    default:
        break;
    }
}

static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
{
    m48t59_t *NVRAM = opaque;
    uint32_t retval;

    addr -= NVRAM->io_base;
    switch (addr) {
    case 3:
        retval = m48t59_read(NVRAM, NVRAM->addr);
        break;
    default:
        retval = -1;
        break;
    }
    NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);

    return retval;
}

static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    m48t59_t *NVRAM = opaque;

    addr -= NVRAM->mem_base;
    m48t59_write(NVRAM, addr, value & 0xff);
}

static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    m48t59_t *NVRAM = opaque;

    addr -= NVRAM->mem_base;
    m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
    m48t59_write(NVRAM, addr + 1, value & 0xff);
}

static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    m48t59_t *NVRAM = opaque;

    addr -= NVRAM->mem_base;
    m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
    m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
    m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
    m48t59_write(NVRAM, addr + 3, value & 0xff);
}

static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
{
    m48t59_t *NVRAM = opaque;
    uint32_t retval;

    addr -= NVRAM->mem_base;
    retval = m48t59_read(NVRAM, addr);
    return retval;
}

static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
{
    m48t59_t *NVRAM = opaque;
    uint32_t retval;

    addr -= NVRAM->mem_base;
    retval = m48t59_read(NVRAM, addr) << 8;
    retval |= m48t59_read(NVRAM, addr + 1);
    return retval;
}

static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
{
    m48t59_t *NVRAM = opaque;
    uint32_t retval;

    addr -= NVRAM->mem_base;
    retval = m48t59_read(NVRAM, addr) << 24;
    retval |= m48t59_read(NVRAM, addr + 1) << 16;
    retval |= m48t59_read(NVRAM, addr + 2) << 8;
    retval |= m48t59_read(NVRAM, addr + 3);
    return retval;
}

static CPUWriteMemoryFunc *nvram_write[] = {
    &nvram_writeb,
    &nvram_writew,
    &nvram_writel,
};

static CPUReadMemoryFunc *nvram_read[] = {
    &nvram_readb,
    &nvram_readw,
    &nvram_readl,
};

static void m48t59_save(QEMUFile *f, void *opaque)
{
    m48t59_t *s = opaque;

    qemu_put_8s(f, &s->lock);
    qemu_put_be16s(f, &s->addr);
    qemu_put_buffer(f, s->buffer, s->size);
}

static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
{
    m48t59_t *s = opaque;

    if (version_id != 1)
        return -EINVAL;

    qemu_get_8s(f, &s->lock);
    qemu_get_be16s(f, &s->addr);
    qemu_get_buffer(f, s->buffer, s->size);

    return 0;
}

static void m48t59_reset(void *opaque)
{
    m48t59_t *NVRAM = opaque;

    if (NVRAM->alrm_timer != NULL)
        qemu_del_timer(NVRAM->alrm_timer);

    if (NVRAM->wd_timer != NULL)
        qemu_del_timer(NVRAM->wd_timer);
}

/* Initialisation routine */
m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
                       uint32_t io_base, uint16_t size,
                       int type)
{
    m48t59_t *s;
    target_phys_addr_t save_base;

    s = qemu_mallocz(sizeof(m48t59_t));
    if (!s)
	return NULL;
    s->buffer = qemu_mallocz(size);
    if (!s->buffer) {
        qemu_free(s);
        return NULL;
    }
    s->IRQ = IRQ;
    s->size = size;
    s->mem_base = mem_base;
    s->io_base = io_base;
    s->addr = 0;
    s->type = type;
    if (io_base != 0) {
        register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
        register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
    }
    if (mem_base != 0) {
        s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
        cpu_register_physical_memory(mem_base, size, s->mem_index);
    }
    if (type == 59) {
        s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
        s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
    }
    s->lock = 0;

    qemu_register_reset(m48t59_reset, s);
    save_base = mem_base ? mem_base : io_base;
    register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s);

    return s;
}
Commit	Line	Data
a541f297	1	/*
819385c5	2	* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
5fafdf24	3	*
3ccacc4a	4	* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
5fafdf24	5	*
a541f297 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "nvram.h"
	26	#include "isa.h"
	27	#include "qemu-timer.h"
	28	#include "sysemu.h"
a541f297	29
13ab5daa	30	//#define DEBUG_NVRAM
a541f297	31
13ab5daa	32	#if defined(DEBUG_NVRAM)
a541f297 FB	33	#define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
	34	#else
	35	#define NVRAM_PRINTF(fmt, args...) do { } while (0)
	36	#endif
	37
819385c5	38	/*
4aed2c33	39	* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
819385c5 FB	40	* alarm and a watchdog timer and related control registers. In the
	41	* PPC platform there is also a nvram lock function.
	42	*/
c5df018e	43	struct m48t59_t {
819385c5	44	/* Model parameters */
4aed2c33	45	int type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
a541f297	46	/* Hardware parameters */
d537cf6c	47	qemu_irq IRQ;
e1bb04f7	48	int mem_index;
5dcb6b91	49	target_phys_addr_t mem_base;
a541f297 FB	50	uint32_t io_base;
	51	uint16_t size;
	52	/* RTC management */
	53	time_t time_offset;
	54	time_t stop_time;
	55	/* Alarm & watchdog */
	56	time_t alarm;
	57	struct QEMUTimer *alrm_timer;
	58	struct QEMUTimer *wd_timer;
	59	/* NVRAM storage */
13ab5daa	60	uint8_t lock;
a541f297 FB	61	uint16_t addr;
a541f297 FB	62	uint8_t *buffer;
c5df018e	63	};
a541f297 FB	64
	65	/* Fake timer functions */
	66	/* Generic helpers for BCD */
	67	static inline uint8_t toBCD (uint8_t value)
	68	{
	69	return (((value / 10) % 10) << 4) \| (value % 10);
	70	}
	71
	72	static inline uint8_t fromBCD (uint8_t BCD)
	73	{
	74	return ((BCD >> 4) * 10) + (BCD & 0x0F);
	75	}
	76
	77	/* RTC management helpers */
	78	static void get_time (m48t59_t NVRAM, struct tm tm)
	79	{
	80	time_t t;
	81
	82	t = time(NULL) + NVRAM->time_offset;
d157e205 FB	83	#ifdef _WIN32
	84	memcpy(tm,localtime(&t),sizeof(*tm));
	85	#else
36cbaae5 BS	86	if (rtc_utc)
	87	gmtime_r (&t, tm);
	88	else
	89	localtime_r (&t, tm) ;
d157e205	90	#endif
a541f297 FB	91	}
	92
	93	static void set_time (m48t59_t NVRAM, struct tm tm)
	94	{
	95	time_t now, new_time;
3b46e624	96
a541f297 FB	97	new_time = mktime(tm);
	98	now = time(NULL);
	99	NVRAM->time_offset = new_time - now;
	100	}
	101
	102	/* Alarm management */
	103	static void alarm_cb (void *opaque)
	104	{
	105	struct tm tm, tm_now;
	106	uint64_t next_time;
	107	m48t59_t *NVRAM = opaque;
	108
d537cf6c	109	qemu_set_irq(NVRAM->IRQ, 1);
5fafdf24	110	if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
a541f297 FB	111	(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	112	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	113	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	114	/* Repeat once a month */
	115	get_time(NVRAM, &tm_now);
	116	memcpy(&tm, &tm_now, sizeof(struct tm));
	117	tm.tm_mon++;
	118	if (tm.tm_mon == 13) {
	119	tm.tm_mon = 1;
	120	tm.tm_year++;
	121	}
	122	next_time = mktime(&tm);
	123	} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	124	(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	125	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	126	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	127	/* Repeat once a day */
	128	next_time = 24 * 60 * 60 + mktime(&tm_now);
	129	} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	130	(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	131	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	132	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	133	/* Repeat once an hour */
	134	next_time = 60 * 60 + mktime(&tm_now);
	135	} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	136	(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	137	(NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
	138	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
	139	/* Repeat once a minute */
	140	next_time = 60 + mktime(&tm_now);
	141	} else {
	142	/* Repeat once a second */
	143	next_time = 1 + mktime(&tm_now);
	144	}
	145	qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
d537cf6c	146	qemu_set_irq(NVRAM->IRQ, 0);
a541f297 FB	147	}
	148
	149
	150	static void get_alarm (m48t59_t NVRAM, struct tm tm)
	151	{
d157e205 FB	152	#ifdef _WIN32
	153	memcpy(tm,localtime(&NVRAM->alarm),sizeof(*tm));
	154	#else
36cbaae5 BS	155	if (rtc_utc)
	156	gmtime_r (&NVRAM->alarm, tm);
	157	else
	158	localtime_r (&NVRAM->alarm, tm);
d157e205	159	#endif
a541f297 FB	160	}
	161
	162	static void set_alarm (m48t59_t NVRAM, struct tm tm)
	163	{
	164	NVRAM->alarm = mktime(tm);
	165	if (NVRAM->alrm_timer != NULL) {
	166	qemu_del_timer(NVRAM->alrm_timer);
868d585a JM	167	if (NVRAM->alarm - time(NULL) > 0)
868d585a JM	168	qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
a541f297	169	}
a541f297 FB	170	}
	171
	172	/* Watchdog management */
	173	static void watchdog_cb (void *opaque)
	174	{
	175	m48t59_t *NVRAM = opaque;
	176
	177	NVRAM->buffer[0x1FF0] \|= 0x80;
	178	if (NVRAM->buffer[0x1FF7] & 0x80) {
	179	NVRAM->buffer[0x1FF7] = 0x00;
	180	NVRAM->buffer[0x1FFC] &= ~0x40;
13ab5daa	181	/* May it be a hw CPU Reset instead ? */
d7d02e3c	182	qemu_system_reset_request();
a541f297	183	} else {
d537cf6c PB	184	qemu_set_irq(NVRAM->IRQ, 1);
d537cf6c PB	185	qemu_set_irq(NVRAM->IRQ, 0);
a541f297 FB	186	}
	187	}
	188
	189	static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
	190	{
	191	uint64_t interval; /* in 1/16 seconds */
	192
868d585a	193	NVRAM->buffer[0x1FF0] &= ~0x80;
a541f297 FB	194	if (NVRAM->wd_timer != NULL) {
a541f297 FB	195	qemu_del_timer(NVRAM->wd_timer);
868d585a JM	196	if (value != 0) {
	197	interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
	198	qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
	199	((interval * 1000) >> 4));
	200	}
a541f297 FB	201	}
	202	}
	203
	204	/* Direct access to NVRAM */
897b4c6c	205	void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
a541f297	206	{
897b4c6c	207	m48t59_t *NVRAM = opaque;
a541f297 FB	208	struct tm tm;
	209	int tmp;
	210
819385c5 FB	211	if (addr > 0x1FF8 && addr < 0x2000)
819385c5 FB	212	NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
4aed2c33 BS	213
	214	/* check for NVRAM access */
	215	if ((NVRAM->type == 2 && addr < 0x7f8) \|\|
	216	(NVRAM->type == 8 && addr < 0x1ff8) \|\|
	217	(NVRAM->type == 59 && addr < 0x1ff0))
819385c5	218	goto do_write;
4aed2c33 BS	219
4aed2c33 BS	220	/* TOD access */
819385c5	221	switch (addr) {
a541f297 FB	222	case 0x1FF0:
	223	/* flags register : read-only */
	224	break;
	225	case 0x1FF1:
	226	/* unused */
	227	break;
	228	case 0x1FF2:
	229	/* alarm seconds */
819385c5 FB	230	tmp = fromBCD(val & 0x7F);
	231	if (tmp >= 0 && tmp <= 59) {
	232	get_alarm(NVRAM, &tm);
	233	tm.tm_sec = tmp;
	234	NVRAM->buffer[0x1FF2] = val;
	235	set_alarm(NVRAM, &tm);
	236	}
a541f297 FB	237	break;
	238	case 0x1FF3:
	239	/* alarm minutes */
819385c5 FB	240	tmp = fromBCD(val & 0x7F);
	241	if (tmp >= 0 && tmp <= 59) {
	242	get_alarm(NVRAM, &tm);
	243	tm.tm_min = tmp;
	244	NVRAM->buffer[0x1FF3] = val;
	245	set_alarm(NVRAM, &tm);
	246	}
a541f297 FB	247	break;
	248	case 0x1FF4:
	249	/* alarm hours */
819385c5 FB	250	tmp = fromBCD(val & 0x3F);
	251	if (tmp >= 0 && tmp <= 23) {
	252	get_alarm(NVRAM, &tm);
	253	tm.tm_hour = tmp;
	254	NVRAM->buffer[0x1FF4] = val;
	255	set_alarm(NVRAM, &tm);
	256	}
a541f297 FB	257	break;
	258	case 0x1FF5:
	259	/* alarm date */
819385c5 FB	260	tmp = fromBCD(val & 0x1F);
	261	if (tmp != 0) {
	262	get_alarm(NVRAM, &tm);
	263	tm.tm_mday = tmp;
	264	NVRAM->buffer[0x1FF5] = val;
	265	set_alarm(NVRAM, &tm);
	266	}
a541f297 FB	267	break;
	268	case 0x1FF6:
	269	/* interrupts */
819385c5	270	NVRAM->buffer[0x1FF6] = val;
a541f297 FB	271	break;
	272	case 0x1FF7:
	273	/* watchdog */
819385c5 FB	274	NVRAM->buffer[0x1FF7] = val;
819385c5 FB	275	set_up_watchdog(NVRAM, val);
a541f297 FB	276	break;
a541f297 FB	277	case 0x1FF8:
4aed2c33	278	case 0x07F8:
a541f297	279	/* control */
4aed2c33	280	NVRAM->buffer[addr] = (val & ~0xA0) \| 0x90;
a541f297 FB	281	break;
a541f297 FB	282	case 0x1FF9:
4aed2c33	283	case 0x07F9:
a541f297 FB	284	/* seconds (BCD) */
	285	tmp = fromBCD(val & 0x7F);
	286	if (tmp >= 0 && tmp <= 59) {
	287	get_time(NVRAM, &tm);
	288	tm.tm_sec = tmp;
	289	set_time(NVRAM, &tm);
	290	}
4aed2c33	291	if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
a541f297 FB	292	if (val & 0x80) {
	293	NVRAM->stop_time = time(NULL);
	294	} else {
	295	NVRAM->time_offset += NVRAM->stop_time - time(NULL);
	296	NVRAM->stop_time = 0;
	297	}
	298	}
4aed2c33	299	NVRAM->buffer[addr] = val & 0x80;
a541f297 FB	300	break;
a541f297 FB	301	case 0x1FFA:
4aed2c33	302	case 0x07FA:
a541f297 FB	303	/* minutes (BCD) */
	304	tmp = fromBCD(val & 0x7F);
	305	if (tmp >= 0 && tmp <= 59) {
	306	get_time(NVRAM, &tm);
	307	tm.tm_min = tmp;
	308	set_time(NVRAM, &tm);
	309	}
	310	break;
	311	case 0x1FFB:
4aed2c33	312	case 0x07FB:
a541f297 FB	313	/* hours (BCD) */
	314	tmp = fromBCD(val & 0x3F);
	315	if (tmp >= 0 && tmp <= 23) {
	316	get_time(NVRAM, &tm);
	317	tm.tm_hour = tmp;
	318	set_time(NVRAM, &tm);
	319	}
	320	break;
	321	case 0x1FFC:
4aed2c33	322	case 0x07FC:
a541f297 FB	323	/* day of the week / century */
	324	tmp = fromBCD(val & 0x07);
	325	get_time(NVRAM, &tm);
	326	tm.tm_wday = tmp;
	327	set_time(NVRAM, &tm);
4aed2c33	328	NVRAM->buffer[addr] = val & 0x40;
a541f297 FB	329	break;
a541f297 FB	330	case 0x1FFD:
4aed2c33	331	case 0x07FD:
a541f297 FB	332	/* date */
	333	tmp = fromBCD(val & 0x1F);
	334	if (tmp != 0) {
	335	get_time(NVRAM, &tm);
	336	tm.tm_mday = tmp;
	337	set_time(NVRAM, &tm);
	338	}
	339	break;
	340	case 0x1FFE:
4aed2c33	341	case 0x07FE:
a541f297 FB	342	/* month */
	343	tmp = fromBCD(val & 0x1F);
	344	if (tmp >= 1 && tmp <= 12) {
	345	get_time(NVRAM, &tm);
	346	tm.tm_mon = tmp - 1;
	347	set_time(NVRAM, &tm);
	348	}
	349	break;
	350	case 0x1FFF:
4aed2c33	351	case 0x07FF:
a541f297 FB	352	/* year */
	353	tmp = fromBCD(val);
	354	if (tmp >= 0 && tmp <= 99) {
	355	get_time(NVRAM, &tm);
180b700d FB	356	if (NVRAM->type == 8)
	357	tm.tm_year = fromBCD(val) + 68; // Base year is 1968
	358	else
	359	tm.tm_year = fromBCD(val);
a541f297 FB	360	set_time(NVRAM, &tm);
	361	}
	362	break;
	363	default:
13ab5daa	364	/* Check lock registers state */
819385c5	365	if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
13ab5daa	366	break;
819385c5	367	if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
13ab5daa	368	break;
819385c5 FB	369	do_write:
	370	if (addr < NVRAM->size) {
	371	NVRAM->buffer[addr] = val & 0xFF;
a541f297 FB	372	}
	373	break;
	374	}
	375	}
	376
897b4c6c	377	uint32_t m48t59_read (void *opaque, uint32_t addr)
a541f297	378	{
897b4c6c	379	m48t59_t *NVRAM = opaque;
a541f297 FB	380	struct tm tm;
	381	uint32_t retval = 0xFF;
	382
4aed2c33 BS	383	/* check for NVRAM access */
	384	if ((NVRAM->type == 2 && addr < 0x078f) \|\|
	385	(NVRAM->type == 8 && addr < 0x1ff8) \|\|
	386	(NVRAM->type == 59 && addr < 0x1ff0))
819385c5	387	goto do_read;
4aed2c33 BS	388
4aed2c33 BS	389	/* TOD access */
819385c5	390	switch (addr) {
a541f297 FB	391	case 0x1FF0:
	392	/* flags register */
	393	goto do_read;
	394	case 0x1FF1:
	395	/* unused */
	396	retval = 0;
	397	break;
	398	case 0x1FF2:
	399	/* alarm seconds */
	400	goto do_read;
	401	case 0x1FF3:
	402	/* alarm minutes */
	403	goto do_read;
	404	case 0x1FF4:
	405	/* alarm hours */
	406	goto do_read;
	407	case 0x1FF5:
	408	/* alarm date */
	409	goto do_read;
	410	case 0x1FF6:
	411	/* interrupts */
	412	goto do_read;
	413	case 0x1FF7:
	414	/* A read resets the watchdog */
	415	set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
	416	goto do_read;
	417	case 0x1FF8:
4aed2c33	418	case 0x07F8:
a541f297 FB	419	/* control */
	420	goto do_read;
	421	case 0x1FF9:
4aed2c33	422	case 0x07F9:
a541f297 FB	423	/* seconds (BCD) */
a541f297 FB	424	get_time(NVRAM, &tm);
4aed2c33	425	retval = (NVRAM->buffer[addr] & 0x80) \| toBCD(tm.tm_sec);
a541f297 FB	426	break;
a541f297 FB	427	case 0x1FFA:
4aed2c33	428	case 0x07FA:
a541f297 FB	429	/* minutes (BCD) */
	430	get_time(NVRAM, &tm);
	431	retval = toBCD(tm.tm_min);
	432	break;
	433	case 0x1FFB:
4aed2c33	434	case 0x07FB:
a541f297 FB	435	/* hours (BCD) */
	436	get_time(NVRAM, &tm);
	437	retval = toBCD(tm.tm_hour);
	438	break;
	439	case 0x1FFC:
4aed2c33	440	case 0x07FC:
a541f297 FB	441	/* day of the week / century */
a541f297 FB	442	get_time(NVRAM, &tm);
4aed2c33	443	retval = NVRAM->buffer[addr] \| tm.tm_wday;
a541f297 FB	444	break;
a541f297 FB	445	case 0x1FFD:
4aed2c33	446	case 0x07FD:
a541f297 FB	447	/* date */
	448	get_time(NVRAM, &tm);
	449	retval = toBCD(tm.tm_mday);
	450	break;
	451	case 0x1FFE:
4aed2c33	452	case 0x07FE:
a541f297 FB	453	/* month */
	454	get_time(NVRAM, &tm);
	455	retval = toBCD(tm.tm_mon + 1);
	456	break;
	457	case 0x1FFF:
4aed2c33	458	case 0x07FF:
a541f297 FB	459	/* year */
a541f297 FB	460	get_time(NVRAM, &tm);
5fafdf24	461	if (NVRAM->type == 8)
180b700d FB	462	retval = toBCD(tm.tm_year - 68); // Base year is 1968
	463	else
	464	retval = toBCD(tm.tm_year);
a541f297 FB	465	break;
a541f297 FB	466	default:
13ab5daa	467	/* Check lock registers state */
819385c5	468	if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
13ab5daa	469	break;
819385c5	470	if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
13ab5daa	471	break;
819385c5 FB	472	do_read:
	473	if (addr < NVRAM->size) {
	474	retval = NVRAM->buffer[addr];
a541f297 FB	475	}
	476	break;
	477	}
819385c5	478	if (addr > 0x1FF9 && addr < 0x2000)
9ed1e667	479	NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
a541f297 FB	480
	481	return retval;
	482	}
	483
897b4c6c	484	void m48t59_set_addr (void *opaque, uint32_t addr)
a541f297	485	{
897b4c6c JM	486	m48t59_t *NVRAM = opaque;
897b4c6c JM	487
a541f297 FB	488	NVRAM->addr = addr;
	489	}
	490
897b4c6c	491	void m48t59_toggle_lock (void *opaque, int lock)
13ab5daa	492	{
897b4c6c JM	493	m48t59_t *NVRAM = opaque;
897b4c6c JM	494
13ab5daa FB	495	NVRAM->lock ^= 1 << lock;
	496	}
	497
a541f297 FB	498	/* IO access to NVRAM */
	499	static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
	500	{
	501	m48t59_t *NVRAM = opaque;
	502
	503	addr -= NVRAM->io_base;
9ed1e667	504	NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
a541f297 FB	505	switch (addr) {
	506	case 0:
	507	NVRAM->addr &= ~0x00FF;
	508	NVRAM->addr \|= val;
	509	break;
	510	case 1:
	511	NVRAM->addr &= ~0xFF00;
	512	NVRAM->addr \|= val << 8;
	513	break;
	514	case 3:
819385c5	515	m48t59_write(NVRAM, val, NVRAM->addr);
a541f297 FB	516	NVRAM->addr = 0x0000;
	517	break;
	518	default:
	519	break;
	520	}
	521	}
	522
	523	static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
	524	{
	525	m48t59_t *NVRAM = opaque;
13ab5daa	526	uint32_t retval;
a541f297	527
13ab5daa FB	528	addr -= NVRAM->io_base;
	529	switch (addr) {
	530	case 3:
819385c5	531	retval = m48t59_read(NVRAM, NVRAM->addr);
13ab5daa FB	532	break;
	533	default:
	534	retval = -1;
	535	break;
	536	}
9ed1e667	537	NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
a541f297	538
13ab5daa	539	return retval;
a541f297 FB	540	}
a541f297 FB	541
e1bb04f7 FB	542	static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
	543	{
	544	m48t59_t *NVRAM = opaque;
3b46e624	545
e1bb04f7	546	addr -= NVRAM->mem_base;
819385c5	547	m48t59_write(NVRAM, addr, value & 0xff);
e1bb04f7 FB	548	}
	549
	550	static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
	551	{
	552	m48t59_t *NVRAM = opaque;
3b46e624	553
e1bb04f7	554	addr -= NVRAM->mem_base;
819385c5 FB	555	m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
819385c5 FB	556	m48t59_write(NVRAM, addr + 1, value & 0xff);
e1bb04f7 FB	557	}
	558
	559	static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
	560	{
	561	m48t59_t *NVRAM = opaque;
3b46e624	562
e1bb04f7	563	addr -= NVRAM->mem_base;
819385c5 FB	564	m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
	565	m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
	566	m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
	567	m48t59_write(NVRAM, addr + 3, value & 0xff);
e1bb04f7 FB	568	}
	569
	570	static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
	571	{
	572	m48t59_t *NVRAM = opaque;
819385c5	573	uint32_t retval;
3b46e624	574
e1bb04f7	575	addr -= NVRAM->mem_base;
819385c5	576	retval = m48t59_read(NVRAM, addr);
e1bb04f7 FB	577	return retval;
	578	}
	579
	580	static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
	581	{
	582	m48t59_t *NVRAM = opaque;
819385c5	583	uint32_t retval;
3b46e624	584
e1bb04f7	585	addr -= NVRAM->mem_base;
819385c5 FB	586	retval = m48t59_read(NVRAM, addr) << 8;
819385c5 FB	587	retval \|= m48t59_read(NVRAM, addr + 1);
e1bb04f7 FB	588	return retval;
	589	}
	590
	591	static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
	592	{
	593	m48t59_t *NVRAM = opaque;
819385c5	594	uint32_t retval;
e1bb04f7	595
819385c5 FB	596	addr -= NVRAM->mem_base;
	597	retval = m48t59_read(NVRAM, addr) << 24;
	598	retval \|= m48t59_read(NVRAM, addr + 1) << 16;
	599	retval \|= m48t59_read(NVRAM, addr + 2) << 8;
	600	retval \|= m48t59_read(NVRAM, addr + 3);
e1bb04f7 FB	601	return retval;
	602	}
	603
	604	static CPUWriteMemoryFunc *nvram_write[] = {
	605	&nvram_writeb,
	606	&nvram_writew,
	607	&nvram_writel,
	608	};
	609
	610	static CPUReadMemoryFunc *nvram_read[] = {
	611	&nvram_readb,
	612	&nvram_readw,
	613	&nvram_readl,
	614	};
819385c5	615
3ccacc4a BS	616	static void m48t59_save(QEMUFile f, void opaque)
	617	{
	618	m48t59_t *s = opaque;
	619
	620	qemu_put_8s(f, &s->lock);
	621	qemu_put_be16s(f, &s->addr);
	622	qemu_put_buffer(f, s->buffer, s->size);
	623	}
	624
	625	static int m48t59_load(QEMUFile f, void opaque, int version_id)
	626	{
	627	m48t59_t *s = opaque;
	628
	629	if (version_id != 1)
	630	return -EINVAL;
	631
	632	qemu_get_8s(f, &s->lock);
	633	qemu_get_be16s(f, &s->addr);
	634	qemu_get_buffer(f, s->buffer, s->size);
	635
	636	return 0;
	637	}
	638
	639	static void m48t59_reset(void *opaque)
	640	{
	641	m48t59_t *NVRAM = opaque;
	642
	643	if (NVRAM->alrm_timer != NULL)
	644	qemu_del_timer(NVRAM->alrm_timer);
	645
	646	if (NVRAM->wd_timer != NULL)
	647	qemu_del_timer(NVRAM->wd_timer);
	648	}
	649
a541f297	650	/* Initialisation routine */
5dcb6b91	651	m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
819385c5 FB	652	uint32_t io_base, uint16_t size,
819385c5 FB	653	int type)
a541f297	654	{
c5df018e	655	m48t59_t *s;
5dcb6b91	656	target_phys_addr_t save_base;
a541f297	657
c5df018e FB	658	s = qemu_mallocz(sizeof(m48t59_t));
c5df018e FB	659	if (!s)
a541f297	660	return NULL;
c5df018e FB	661	s->buffer = qemu_mallocz(size);
	662	if (!s->buffer) {
	663	qemu_free(s);
	664	return NULL;
	665	}
	666	s->IRQ = IRQ;
	667	s->size = size;
e1bb04f7	668	s->mem_base = mem_base;
c5df018e FB	669	s->io_base = io_base;
c5df018e FB	670	s->addr = 0;
819385c5 FB	671	s->type = type;
	672	if (io_base != 0) {
	673	register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
	674	register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
	675	}
e1bb04f7 FB	676	if (mem_base != 0) {
e1bb04f7 FB	677	s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
4aed2c33	678	cpu_register_physical_memory(mem_base, size, s->mem_index);
e1bb04f7	679	}
819385c5 FB	680	if (type == 59) {
	681	s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
	682	s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
	683	}
13ab5daa FB	684	s->lock = 0;
13ab5daa FB	685
3ccacc4a BS	686	qemu_register_reset(m48t59_reset, s);
	687	save_base = mem_base ? mem_base : io_base;
	688	register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s);
	689
c5df018e	690	return s;
a541f297	691	}