[qemu.git] / hw / tcx.c

/*
 * QEMU TCX Frame buffer
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "sun4m.h"
#include "console.h"
#include "pixel_ops.h"

#define MAXX 1024
#define MAXY 768
#define TCX_DAC_NREGS 16
#define TCX_THC_NREGS_8  0x081c
#define TCX_THC_NREGS_24 0x1000
#define TCX_TEC_NREGS    0x1000

typedef struct TCXState {
    target_phys_addr_t addr;
    DisplayState *ds;
    uint8_t *vram;
    uint32_t *vram24, *cplane;
    ram_addr_t vram_offset, vram24_offset, cplane_offset;
    uint16_t width, height, depth;
    uint8_t r[256], g[256], b[256];
    uint32_t palette[256];
    uint8_t dac_index, dac_state;
} TCXState;

static void tcx_screen_dump(void *opaque, const char *filename);
static void tcx24_screen_dump(void *opaque, const char *filename);
static void tcx_invalidate_display(void *opaque);
static void tcx24_invalidate_display(void *opaque);

static void update_palette_entries(TCXState *s, int start, int end)
{
    int i;
    for(i = start; i < end; i++) {
        switch(ds_get_bits_per_pixel(s->ds)) {
        default:
        case 8:
            s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
            break;
        case 15:
            s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
            break;
        case 16:
            s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
            break;
        case 32:
            if (is_surface_bgr(s->ds->surface))
                s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
            else
                s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
            break;
        }
    }
    if (s->depth == 24)
        tcx24_invalidate_display(s);
    else
        tcx_invalidate_display(s);
}

static void tcx_draw_line32(TCXState *s1, uint8_t *d,
                            const uint8_t *s, int width)
{
    int x;
    uint8_t val;
    uint32_t *p = (uint32_t *)d;

    for(x = 0; x < width; x++) {
        val = *s++;
        *p++ = s1->palette[val];
    }
}

static void tcx_draw_line16(TCXState *s1, uint8_t *d,
                            const uint8_t *s, int width)
{
    int x;
    uint8_t val;
    uint16_t *p = (uint16_t *)d;

    for(x = 0; x < width; x++) {
        val = *s++;
        *p++ = s1->palette[val];
    }
}

static void tcx_draw_line8(TCXState *s1, uint8_t *d,
                           const uint8_t *s, int width)
{
    int x;
    uint8_t val;

    for(x = 0; x < width; x++) {
        val = *s++;
        *d++ = s1->palette[val];
    }
}

/*
  XXX Could be much more optimal:
  * detect if line/page/whole screen is in 24 bit mode
  * if destination is also BGR, use memcpy
  */
static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
                                     const uint8_t *s, int width,
                                     const uint32_t *cplane,
                                     const uint32_t *s24)
{
    int x, bgr, r, g, b;
    uint8_t val, *p8;
    uint32_t *p = (uint32_t *)d;
    uint32_t dval;

    bgr = is_surface_bgr(s1->ds->surface);
    for(x = 0; x < width; x++, s++, s24++) {
        if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) {
            // 24-bit direct, BGR order
            p8 = (uint8_t *)s24;
            p8++;
            b = *p8++;
            g = *p8++;
            r = *p8++;
            if (bgr)
                dval = rgb_to_pixel32bgr(r, g, b);
            else
                dval = rgb_to_pixel32(r, g, b);
        } else {
            val = *s;
            dval = s1->palette[val];
        }
        *p++ = dval;
    }
}

static inline int check_dirty(ram_addr_t page, ram_addr_t page24,
                              ram_addr_t cpage)
{
    int ret;
    unsigned int off;

    ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
    for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) {
        ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG);
        ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG);
    }
    return ret;
}

static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
                               ram_addr_t page_max, ram_addr_t page24,
                              ram_addr_t cpage)
{
    cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
                                    VGA_DIRTY_FLAG);
    page_min -= ts->vram_offset;
    page_max -= ts->vram_offset;
    cpu_physical_memory_reset_dirty(page24 + page_min * 4,
                                    page24 + page_max * 4 + TARGET_PAGE_SIZE,
                                    VGA_DIRTY_FLAG);
    cpu_physical_memory_reset_dirty(cpage + page_min * 4,
                                    cpage + page_max * 4 + TARGET_PAGE_SIZE,
                                    VGA_DIRTY_FLAG);
}

/* Fixed line length 1024 allows us to do nice tricks not possible on
   VGA... */
static void tcx_update_display(void *opaque)
{
    TCXState *ts = opaque;
    ram_addr_t page, page_min, page_max;
    int y, y_start, dd, ds;
    uint8_t *d, *s;
    void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);

    if (ds_get_bits_per_pixel(ts->ds) == 0)
        return;
    page = ts->vram_offset;
    y_start = -1;
    page_min = -1;
    page_max = 0;
    d = ds_get_data(ts->ds);
    s = ts->vram;
    dd = ds_get_linesize(ts->ds);
    ds = 1024;

    switch (ds_get_bits_per_pixel(ts->ds)) {
    case 32:
        f = tcx_draw_line32;
        break;
    case 15:
    case 16:
        f = tcx_draw_line16;
        break;
    default:
    case 8:
        f = tcx_draw_line8;
        break;
    case 0:
        return;
    }

    for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
        if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
            if (y_start < 0)
                y_start = y;
            if (page < page_min)
                page_min = page;
            if (page > page_max)
                page_max = page;
            f(ts, d, s, ts->width);
            d += dd;
            s += ds;
            f(ts, d, s, ts->width);
            d += dd;
            s += ds;
            f(ts, d, s, ts->width);
            d += dd;
            s += ds;
            f(ts, d, s, ts->width);
            d += dd;
            s += ds;
        } else {
            if (y_start >= 0) {
                /* flush to display */
                dpy_update(ts->ds, 0, y_start,
                           ts->width, y - y_start);
                y_start = -1;
            }
            d += dd * 4;
            s += ds * 4;
        }
    }
    if (y_start >= 0) {
        /* flush to display */
        dpy_update(ts->ds, 0, y_start,
                   ts->width, y - y_start);
    }
    /* reset modified pages */
    if (page_max >= page_min) {
        cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
                                        VGA_DIRTY_FLAG);
    }
}

static void tcx24_update_display(void *opaque)
{
    TCXState *ts = opaque;
    ram_addr_t page, page_min, page_max, cpage, page24;
    int y, y_start, dd, ds;
    uint8_t *d, *s;
    uint32_t *cptr, *s24;

    if (ds_get_bits_per_pixel(ts->ds) != 32)
            return;
    page = ts->vram_offset;
    page24 = ts->vram24_offset;
    cpage = ts->cplane_offset;
    y_start = -1;
    page_min = -1;
    page_max = 0;
    d = ds_get_data(ts->ds);
    s = ts->vram;
    s24 = ts->vram24;
    cptr = ts->cplane;
    dd = ds_get_linesize(ts->ds);
    ds = 1024;

    for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
            page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
        if (check_dirty(page, page24, cpage)) {
            if (y_start < 0)
                y_start = y;
            if (page < page_min)
                page_min = page;
            if (page > page_max)
                page_max = page;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
        } else {
            if (y_start >= 0) {
                /* flush to display */
                dpy_update(ts->ds, 0, y_start,
                           ts->width, y - y_start);
                y_start = -1;
            }
            d += dd * 4;
            s += ds * 4;
            cptr += ds * 4;
            s24 += ds * 4;
        }
    }
    if (y_start >= 0) {
        /* flush to display */
        dpy_update(ts->ds, 0, y_start,
                   ts->width, y - y_start);
    }
    /* reset modified pages */
    if (page_max >= page_min) {
        reset_dirty(ts, page_min, page_max, page24, cpage);
    }
}

static void tcx_invalidate_display(void *opaque)
{
    TCXState *s = opaque;
    int i;

    for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) {
        cpu_physical_memory_set_dirty(s->vram_offset + i);
    }
}

static void tcx24_invalidate_display(void *opaque)
{
    TCXState *s = opaque;
    int i;

    tcx_invalidate_display(s);
    for (i = 0; i < MAXX*MAXY * 4; i += TARGET_PAGE_SIZE) {
        cpu_physical_memory_set_dirty(s->vram24_offset + i);
        cpu_physical_memory_set_dirty(s->cplane_offset + i);
    }
}

static void tcx_save(QEMUFile *f, void *opaque)
{
    TCXState *s = opaque;

    qemu_put_be16s(f, &s->height);
    qemu_put_be16s(f, &s->width);
    qemu_put_be16s(f, &s->depth);
    qemu_put_buffer(f, s->r, 256);
    qemu_put_buffer(f, s->g, 256);
    qemu_put_buffer(f, s->b, 256);
    qemu_put_8s(f, &s->dac_index);
    qemu_put_8s(f, &s->dac_state);
}

static int tcx_load(QEMUFile *f, void *opaque, int version_id)
{
    TCXState *s = opaque;
    uint32_t dummy;

    if (version_id != 3 && version_id != 4)
        return -EINVAL;

    if (version_id == 3) {
        qemu_get_be32s(f, &dummy);
        qemu_get_be32s(f, &dummy);
        qemu_get_be32s(f, &dummy);
    }
    qemu_get_be16s(f, &s->height);
    qemu_get_be16s(f, &s->width);
    qemu_get_be16s(f, &s->depth);
    qemu_get_buffer(f, s->r, 256);
    qemu_get_buffer(f, s->g, 256);
    qemu_get_buffer(f, s->b, 256);
    qemu_get_8s(f, &s->dac_index);
    qemu_get_8s(f, &s->dac_state);
    update_palette_entries(s, 0, 256);
    if (s->depth == 24)
        tcx24_invalidate_display(s);
    else
        tcx_invalidate_display(s);

    return 0;
}

static void tcx_reset(void *opaque)
{
    TCXState *s = opaque;

    /* Initialize palette */
    memset(s->r, 0, 256);
    memset(s->g, 0, 256);
    memset(s->b, 0, 256);
    s->r[255] = s->g[255] = s->b[255] = 255;
    update_palette_entries(s, 0, 256);
    memset(s->vram, 0, MAXX*MAXY);
    cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset +
                                    MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG);
    s->dac_index = 0;
    s->dac_state = 0;
}

static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    TCXState *s = opaque;

    switch (addr) {
    case 0:
        s->dac_index = val >> 24;
        s->dac_state = 0;
        break;
    case 4:
        switch (s->dac_state) {
        case 0:
            s->r[s->dac_index] = val >> 24;
            update_palette_entries(s, s->dac_index, s->dac_index + 1);
            s->dac_state++;
            break;
        case 1:
            s->g[s->dac_index] = val >> 24;
            update_palette_entries(s, s->dac_index, s->dac_index + 1);
            s->dac_state++;
            break;
        case 2:
            s->b[s->dac_index] = val >> 24;
            update_palette_entries(s, s->dac_index, s->dac_index + 1);
            s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
        default:
            s->dac_state = 0;
            break;
        }
        break;
    default:
        break;
    }
    return;
}

static CPUReadMemoryFunc *tcx_dac_read[3] = {
    NULL,
    NULL,
    tcx_dac_readl,
};

static CPUWriteMemoryFunc *tcx_dac_write[3] = {
    NULL,
    NULL,
    tcx_dac_writel,
};

static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr,
                             uint32_t val)
{
}

static CPUReadMemoryFunc *tcx_dummy_read[3] = {
    NULL,
    NULL,
    tcx_dummy_readl,
};

static CPUWriteMemoryFunc *tcx_dummy_write[3] = {
    NULL,
    NULL,
    tcx_dummy_writel,
};

void tcx_init(target_phys_addr_t addr, int vram_size, int width, int height,
              int depth)
{
    TCXState *s;
    int io_memory, dummy_memory;
    ram_addr_t vram_offset;
    int size;
    uint8_t *vram_base;

    vram_offset = qemu_ram_alloc(vram_size * (1 + 4 + 4));
    vram_base = qemu_get_ram_ptr(vram_offset);

    s = qemu_mallocz(sizeof(TCXState));
    s->addr = addr;
    s->vram_offset = vram_offset;
    s->width = width;
    s->height = height;
    s->depth = depth;

    // 8-bit plane
    s->vram = vram_base;
    size = vram_size;
    cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset);
    vram_offset += size;
    vram_base += size;

    io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
    cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS,
                                 io_memory);

    dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
                                          s);
    cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS,
                                 dummy_memory);
    if (depth == 24) {
        // 24-bit plane
        size = vram_size * 4;
        s->vram24 = (uint32_t *)vram_base;
        s->vram24_offset = vram_offset;
        cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset);
        vram_offset += size;
        vram_base += size;

        // Control plane
        size = vram_size * 4;
        s->cplane = (uint32_t *)vram_base;
        s->cplane_offset = vram_offset;
        cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
        s->ds = graphic_console_init(tcx24_update_display,
                                     tcx24_invalidate_display,
                                     tcx24_screen_dump, NULL, s);
    } else {
        cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
                                     dummy_memory);
        s->ds = graphic_console_init(tcx_update_display,
                                     tcx_invalidate_display,
                                     tcx_screen_dump, NULL, s);
    }
    // NetBSD writes here even with 8-bit display
    cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
                                 dummy_memory);

    register_savevm("tcx", addr, 4, tcx_save, tcx_load, s);
    qemu_register_reset(tcx_reset, s);
    tcx_reset(s);
    qemu_console_resize(s->ds, width, height);
}

static void tcx_screen_dump(void *opaque, const char *filename)
{
    TCXState *s = opaque;
    FILE *f;
    uint8_t *d, *d1, v;
    int y, x;

    f = fopen(filename, "wb");
    if (!f)
        return;
    fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
    d1 = s->vram;
    for(y = 0; y < s->height; y++) {
        d = d1;
        for(x = 0; x < s->width; x++) {
            v = *d;
            fputc(s->r[v], f);
            fputc(s->g[v], f);
            fputc(s->b[v], f);
            d++;
        }
        d1 += MAXX;
    }
    fclose(f);
    return;
}

static void tcx24_screen_dump(void *opaque, const char *filename)
{
    TCXState *s = opaque;
    FILE *f;
    uint8_t *d, *d1, v;
    uint32_t *s24, *cptr, dval;
    int y, x;

    f = fopen(filename, "wb");
    if (!f)
        return;
    fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
    d1 = s->vram;
    s24 = s->vram24;
    cptr = s->cplane;
    for(y = 0; y < s->height; y++) {
        d = d1;
        for(x = 0; x < s->width; x++, d++, s24++) {
            if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
                dval = *s24 & 0x00ffffff;
                fputc((dval >> 16) & 0xff, f);
                fputc((dval >> 8) & 0xff, f);
                fputc(dval & 0xff, f);
            } else {
                v = *d;
                fputc(s->r[v], f);
                fputc(s->g[v], f);
                fputc(s->b[v], f);
            }
        }
        d1 += MAXX;
    }
    fclose(f);
    return;
}
Commit	Line	Data
420557e8	1	/*
6f7e9aec	2	* QEMU TCX Frame buffer
5fafdf24	3	*
6f7e9aec	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
420557e8 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "sun4m.h"
	26	#include "console.h"
94470844	27	#include "pixel_ops.h"
420557e8	28
420557e8 FB	29	#define MAXX 1024
420557e8 FB	30	#define MAXY 768
6f7e9aec	31	#define TCX_DAC_NREGS 16
8508b89e BS	32	#define TCX_THC_NREGS_8 0x081c
	33	#define TCX_THC_NREGS_24 0x1000
	34	#define TCX_TEC_NREGS 0x1000
420557e8	35
420557e8	36	typedef struct TCXState {
5dcb6b91	37	target_phys_addr_t addr;
420557e8	38	DisplayState *ds;
8d5f07fa	39	uint8_t *vram;
eee0b836 BS	40	uint32_t vram24, cplane;
	41	ram_addr_t vram_offset, vram24_offset, cplane_offset;
	42	uint16_t width, height, depth;
e80cfcfc	43	uint8_t r[256], g[256], b[256];
21206a10	44	uint32_t palette[256];
6f7e9aec	45	uint8_t dac_index, dac_state;
420557e8 FB	46	} TCXState;
420557e8 FB	47
95219897	48	static void tcx_screen_dump(void opaque, const char filename);
eee0b836	49	static void tcx24_screen_dump(void opaque, const char filename);
97e7df27 BS	50	static void tcx_invalidate_display(void *opaque);
97e7df27 BS	51	static void tcx24_invalidate_display(void *opaque);
95219897	52
21206a10 FB	53	static void update_palette_entries(TCXState *s, int start, int end)
	54	{
	55	int i;
	56	for(i = start; i < end; i++) {
0e1f5a0c	57	switch(ds_get_bits_per_pixel(s->ds)) {
21206a10 FB	58	default:
	59	case 8:
	60	s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
	61	break;
	62	case 15:
8927bcfd	63	s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
21206a10 FB	64	break;
21206a10 FB	65	case 16:
8927bcfd	66	s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
21206a10 FB	67	break;
21206a10 FB	68	case 32:
7b5d76da AL	69	if (is_surface_bgr(s->ds->surface))
	70	s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
	71	else
	72	s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
21206a10 FB	73	break;
	74	}
	75	}
97e7df27 BS	76	if (s->depth == 24)
	77	tcx24_invalidate_display(s);
	78	else
	79	tcx_invalidate_display(s);
21206a10 FB	80	}
21206a10 FB	81
5fafdf24	82	static void tcx_draw_line32(TCXState s1, uint8_t d,
f930d07e	83	const uint8_t *s, int width)
420557e8	84	{
e80cfcfc FB	85	int x;
e80cfcfc FB	86	uint8_t val;
8bdc2159	87	uint32_t p = (uint32_t )d;
e80cfcfc FB	88
e80cfcfc FB	89	for(x = 0; x < width; x++) {
f930d07e	90	val = *s++;
8bdc2159	91	*p++ = s1->palette[val];
e80cfcfc	92	}
420557e8 FB	93	}
420557e8 FB	94
5fafdf24	95	static void tcx_draw_line16(TCXState s1, uint8_t d,
f930d07e	96	const uint8_t *s, int width)
e80cfcfc FB	97	{
	98	int x;
	99	uint8_t val;
8bdc2159	100	uint16_t p = (uint16_t )d;
8d5f07fa	101
e80cfcfc	102	for(x = 0; x < width; x++) {
f930d07e	103	val = *s++;
8bdc2159	104	*p++ = s1->palette[val];
e80cfcfc FB	105	}
	106	}
	107
5fafdf24	108	static void tcx_draw_line8(TCXState s1, uint8_t d,
f930d07e	109	const uint8_t *s, int width)
420557e8	110	{
e80cfcfc FB	111	int x;
	112	uint8_t val;
	113
	114	for(x = 0; x < width; x++) {
f930d07e	115	val = *s++;
21206a10	116	*d++ = s1->palette[val];
420557e8	117	}
420557e8 FB	118	}
420557e8 FB	119
688ea2eb BS	120	/*
	121	XXX Could be much more optimal:
	122	* detect if line/page/whole screen is in 24 bit mode
	123	* if destination is also BGR, use memcpy
	124	*/
eee0b836 BS	125	static inline void tcx24_draw_line32(TCXState s1, uint8_t d,
	126	const uint8_t *s, int width,
	127	const uint32_t *cplane,
	128	const uint32_t *s24)
	129	{
7b5d76da	130	int x, bgr, r, g, b;
688ea2eb	131	uint8_t val, *p8;
eee0b836 BS	132	uint32_t p = (uint32_t )d;
	133	uint32_t dval;
	134
7b5d76da	135	bgr = is_surface_bgr(s1->ds->surface);
eee0b836	136	for(x = 0; x < width; x++, s++, s24++) {
688ea2eb BS	137	if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) {
	138	// 24-bit direct, BGR order
	139	p8 = (uint8_t *)s24;
	140	p8++;
	141	b = *p8++;
	142	g = *p8++;
	143	r = *p8++;
7b5d76da AL	144	if (bgr)
	145	dval = rgb_to_pixel32bgr(r, g, b);
	146	else
	147	dval = rgb_to_pixel32(r, g, b);
eee0b836 BS	148	} else {
	149	val = *s;
	150	dval = s1->palette[val];
	151	}
	152	*p++ = dval;
	153	}
	154	}
	155
22548760	156	static inline int check_dirty(ram_addr_t page, ram_addr_t page24,
eee0b836 BS	157	ram_addr_t cpage)
	158	{
	159	int ret;
	160	unsigned int off;
	161
	162	ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
	163	for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) {
	164	ret \|= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG);
	165	ret \|= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG);
	166	}
	167	return ret;
	168	}
	169
	170	static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
	171	ram_addr_t page_max, ram_addr_t page24,
	172	ram_addr_t cpage)
	173	{
	174	cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
	175	VGA_DIRTY_FLAG);
	176	page_min -= ts->vram_offset;
	177	page_max -= ts->vram_offset;
	178	cpu_physical_memory_reset_dirty(page24 + page_min * 4,
	179	page24 + page_max * 4 + TARGET_PAGE_SIZE,
	180	VGA_DIRTY_FLAG);
	181	cpu_physical_memory_reset_dirty(cpage + page_min * 4,
	182	cpage + page_max * 4 + TARGET_PAGE_SIZE,
	183	VGA_DIRTY_FLAG);
	184	}
	185
e80cfcfc FB	186	/* Fixed line length 1024 allows us to do nice tricks not possible on
e80cfcfc FB	187	VGA... */
95219897	188	static void tcx_update_display(void *opaque)
420557e8	189	{
e80cfcfc	190	TCXState *ts = opaque;
550be127 FB	191	ram_addr_t page, page_min, page_max;
550be127 FB	192	int y, y_start, dd, ds;
e80cfcfc	193	uint8_t d, s;
b3ceef24	194	void (f)(TCXState s1, uint8_t dst, const uint8_t src, int width);
e80cfcfc	195
0e1f5a0c	196	if (ds_get_bits_per_pixel(ts->ds) == 0)
f930d07e	197	return;
6f7e9aec	198	page = ts->vram_offset;
e80cfcfc	199	y_start = -1;
c0c440f3	200	page_min = -1;
550be127	201	page_max = 0;
0e1f5a0c	202	d = ds_get_data(ts->ds);
6f7e9aec	203	s = ts->vram;
0e1f5a0c	204	dd = ds_get_linesize(ts->ds);
e80cfcfc FB	205	ds = 1024;
e80cfcfc FB	206
0e1f5a0c	207	switch (ds_get_bits_per_pixel(ts->ds)) {
e80cfcfc	208	case 32:
f930d07e BS	209	f = tcx_draw_line32;
f930d07e BS	210	break;
21206a10 FB	211	case 15:
21206a10 FB	212	case 16:
f930d07e BS	213	f = tcx_draw_line16;
f930d07e BS	214	break;
e80cfcfc FB	215	default:
e80cfcfc FB	216	case 8:
f930d07e BS	217	f = tcx_draw_line8;
f930d07e BS	218	break;
e80cfcfc	219	case 0:
f930d07e	220	return;
e80cfcfc	221	}
3b46e624	222
6f7e9aec	223	for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
f930d07e BS	224	if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
f930d07e BS	225	if (y_start < 0)
e80cfcfc FB	226	y_start = y;
	227	if (page < page_min)
	228	page_min = page;
	229	if (page > page_max)
	230	page_max = page;
f930d07e BS	231	f(ts, d, s, ts->width);
	232	d += dd;
	233	s += ds;
	234	f(ts, d, s, ts->width);
	235	d += dd;
	236	s += ds;
	237	f(ts, d, s, ts->width);
	238	d += dd;
	239	s += ds;
	240	f(ts, d, s, ts->width);
	241	d += dd;
	242	s += ds;
	243	} else {
e80cfcfc FB	244	if (y_start >= 0) {
e80cfcfc FB	245	/* flush to display */
5fafdf24	246	dpy_update(ts->ds, 0, y_start,
6f7e9aec	247	ts->width, y - y_start);
e80cfcfc FB	248	y_start = -1;
e80cfcfc FB	249	}
f930d07e BS	250	d += dd * 4;
	251	s += ds * 4;
	252	}
e80cfcfc FB	253	}
e80cfcfc FB	254	if (y_start >= 0) {
f930d07e BS	255	/* flush to display */
	256	dpy_update(ts->ds, 0, y_start,
	257	ts->width, y - y_start);
e80cfcfc FB	258	}
e80cfcfc FB	259	/* reset modified pages */
c0c440f3	260	if (page_max >= page_min) {
0a962c02 FB	261	cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
0a962c02 FB	262	VGA_DIRTY_FLAG);
e80cfcfc	263	}
420557e8 FB	264	}
420557e8 FB	265
eee0b836 BS	266	static void tcx24_update_display(void *opaque)
	267	{
	268	TCXState *ts = opaque;
	269	ram_addr_t page, page_min, page_max, cpage, page24;
	270	int y, y_start, dd, ds;
	271	uint8_t d, s;
	272	uint32_t cptr, s24;
	273
0e1f5a0c	274	if (ds_get_bits_per_pixel(ts->ds) != 32)
eee0b836 BS	275	return;
	276	page = ts->vram_offset;
	277	page24 = ts->vram24_offset;
	278	cpage = ts->cplane_offset;
	279	y_start = -1;
c0c440f3	280	page_min = -1;
eee0b836	281	page_max = 0;
0e1f5a0c	282	d = ds_get_data(ts->ds);
eee0b836 BS	283	s = ts->vram;
	284	s24 = ts->vram24;
	285	cptr = ts->cplane;
0e1f5a0c	286	dd = ds_get_linesize(ts->ds);
eee0b836 BS	287	ds = 1024;
	288
	289	for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
	290	page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
22548760	291	if (check_dirty(page, page24, cpage)) {
eee0b836 BS	292	if (y_start < 0)
	293	y_start = y;
	294	if (page < page_min)
	295	page_min = page;
	296	if (page > page_max)
	297	page_max = page;
	298	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	299	d += dd;
	300	s += ds;
	301	cptr += ds;
	302	s24 += ds;
	303	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	304	d += dd;
	305	s += ds;
	306	cptr += ds;
	307	s24 += ds;
	308	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	309	d += dd;
	310	s += ds;
	311	cptr += ds;
	312	s24 += ds;
	313	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	314	d += dd;
	315	s += ds;
	316	cptr += ds;
	317	s24 += ds;
	318	} else {
	319	if (y_start >= 0) {
	320	/* flush to display */
	321	dpy_update(ts->ds, 0, y_start,
	322	ts->width, y - y_start);
	323	y_start = -1;
	324	}
	325	d += dd * 4;
	326	s += ds * 4;
	327	cptr += ds * 4;
	328	s24 += ds * 4;
	329	}
	330	}
	331	if (y_start >= 0) {
	332	/* flush to display */
	333	dpy_update(ts->ds, 0, y_start,
	334	ts->width, y - y_start);
	335	}
	336	/* reset modified pages */
c0c440f3	337	if (page_max >= page_min) {
eee0b836 BS	338	reset_dirty(ts, page_min, page_max, page24, cpage);
	339	}
	340	}
	341
95219897	342	static void tcx_invalidate_display(void *opaque)
420557e8	343	{
e80cfcfc FB	344	TCXState *s = opaque;
	345	int i;
	346
	347	for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) {
f930d07e	348	cpu_physical_memory_set_dirty(s->vram_offset + i);
e80cfcfc	349	}
420557e8 FB	350	}
420557e8 FB	351
eee0b836 BS	352	static void tcx24_invalidate_display(void *opaque)
	353	{
	354	TCXState *s = opaque;
	355	int i;
	356
	357	tcx_invalidate_display(s);
	358	for (i = 0; i < MAXXMAXY 4; i += TARGET_PAGE_SIZE) {
	359	cpu_physical_memory_set_dirty(s->vram24_offset + i);
	360	cpu_physical_memory_set_dirty(s->cplane_offset + i);
	361	}
	362	}
	363
e80cfcfc	364	static void tcx_save(QEMUFile f, void opaque)
420557e8 FB	365	{
420557e8 FB	366	TCXState *s = opaque;
3b46e624	367
b6c4f71f BS	368	qemu_put_be16s(f, &s->height);
	369	qemu_put_be16s(f, &s->width);
	370	qemu_put_be16s(f, &s->depth);
e80cfcfc FB	371	qemu_put_buffer(f, s->r, 256);
	372	qemu_put_buffer(f, s->g, 256);
	373	qemu_put_buffer(f, s->b, 256);
6f7e9aec FB	374	qemu_put_8s(f, &s->dac_index);
6f7e9aec FB	375	qemu_put_8s(f, &s->dac_state);
420557e8 FB	376	}
420557e8 FB	377
e80cfcfc	378	static int tcx_load(QEMUFile f, void opaque, int version_id)
420557e8	379	{
e80cfcfc	380	TCXState *s = opaque;
fda77c2d BS	381	uint32_t dummy;
	382
	383	if (version_id != 3 && version_id != 4)
e80cfcfc FB	384	return -EINVAL;
e80cfcfc FB	385
fda77c2d	386	if (version_id == 3) {
b6c4f71f BS	387	qemu_get_be32s(f, &dummy);
	388	qemu_get_be32s(f, &dummy);
	389	qemu_get_be32s(f, &dummy);
fda77c2d	390	}
b6c4f71f BS	391	qemu_get_be16s(f, &s->height);
	392	qemu_get_be16s(f, &s->width);
	393	qemu_get_be16s(f, &s->depth);
e80cfcfc FB	394	qemu_get_buffer(f, s->r, 256);
	395	qemu_get_buffer(f, s->g, 256);
	396	qemu_get_buffer(f, s->b, 256);
6f7e9aec FB	397	qemu_get_8s(f, &s->dac_index);
6f7e9aec FB	398	qemu_get_8s(f, &s->dac_state);
21206a10	399	update_palette_entries(s, 0, 256);
97e7df27 BS	400	if (s->depth == 24)
	401	tcx24_invalidate_display(s);
	402	else
	403	tcx_invalidate_display(s);
5425a216	404
e80cfcfc	405	return 0;
420557e8 FB	406	}
420557e8 FB	407
e80cfcfc	408	static void tcx_reset(void *opaque)
420557e8	409	{
e80cfcfc FB	410	TCXState *s = opaque;
	411
	412	/* Initialize palette */
	413	memset(s->r, 0, 256);
	414	memset(s->g, 0, 256);
	415	memset(s->b, 0, 256);
	416	s->r[255] = s->g[255] = s->b[255] = 255;
21206a10	417	update_palette_entries(s, 0, 256);
e80cfcfc	418	memset(s->vram, 0, MAXX*MAXY);
eee0b836 BS	419	cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset +
eee0b836 BS	420	MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG);
6f7e9aec FB	421	s->dac_index = 0;
	422	s->dac_state = 0;
	423	}
	424
	425	static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
	426	{
	427	return 0;
	428	}
	429
	430	static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	431	{
	432	TCXState *s = opaque;
6f7e9aec	433
e64d7d59	434	switch (addr) {
6f7e9aec	435	case 0:
f930d07e BS	436	s->dac_index = val >> 24;
	437	s->dac_state = 0;
	438	break;
e64d7d59	439	case 4:
f930d07e BS	440	switch (s->dac_state) {
	441	case 0:
	442	s->r[s->dac_index] = val >> 24;
21206a10	443	update_palette_entries(s, s->dac_index, s->dac_index + 1);
f930d07e BS	444	s->dac_state++;
	445	break;
	446	case 1:
	447	s->g[s->dac_index] = val >> 24;
21206a10	448	update_palette_entries(s, s->dac_index, s->dac_index + 1);
f930d07e BS	449	s->dac_state++;
	450	break;
	451	case 2:
	452	s->b[s->dac_index] = val >> 24;
21206a10	453	update_palette_entries(s, s->dac_index, s->dac_index + 1);
5c8cdbf8	454	s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
f930d07e BS	455	default:
	456	s->dac_state = 0;
	457	break;
	458	}
	459	break;
6f7e9aec	460	default:
f930d07e	461	break;
6f7e9aec FB	462	}
6f7e9aec FB	463	return;
420557e8 FB	464	}
420557e8 FB	465
6f7e9aec	466	static CPUReadMemoryFunc *tcx_dac_read[3] = {
7c560456 BS	467	NULL,
7c560456 BS	468	NULL,
6f7e9aec FB	469	tcx_dac_readl,
	470	};
	471
	472	static CPUWriteMemoryFunc *tcx_dac_write[3] = {
7c560456 BS	473	NULL,
7c560456 BS	474	NULL,
6f7e9aec FB	475	tcx_dac_writel,
	476	};
	477
8508b89e BS	478	static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr)
	479	{
	480	return 0;
	481	}
	482
	483	static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr,
	484	uint32_t val)
	485	{
	486	}
	487
	488	static CPUReadMemoryFunc *tcx_dummy_read[3] = {
7c560456 BS	489	NULL,
7c560456 BS	490	NULL,
8508b89e BS	491	tcx_dummy_readl,
	492	};
	493
	494	static CPUWriteMemoryFunc *tcx_dummy_write[3] = {
7c560456 BS	495	NULL,
7c560456 BS	496	NULL,
8508b89e BS	497	tcx_dummy_writel,
	498	};
	499
dc828ca1	500	void tcx_init(target_phys_addr_t addr, int vram_size, int width, int height,
eee0b836	501	int depth)
420557e8 FB	502	{
420557e8 FB	503	TCXState *s;
8508b89e	504	int io_memory, dummy_memory;
dc828ca1	505	ram_addr_t vram_offset;
eee0b836	506	int size;
dc828ca1 PB	507	uint8_t *vram_base;
dc828ca1 PB	508
520860ef	509	vram_offset = qemu_ram_alloc(vram_size * (1 + 4 + 4));
dc828ca1	510	vram_base = qemu_get_ram_ptr(vram_offset);
420557e8 FB	511
420557e8 FB	512	s = qemu_mallocz(sizeof(TCXState));
8d5f07fa	513	s->addr = addr;
e80cfcfc	514	s->vram_offset = vram_offset;
6f7e9aec FB	515	s->width = width;
6f7e9aec FB	516	s->height = height;
eee0b836 BS	517	s->depth = depth;
	518
	519	// 8-bit plane
	520	s->vram = vram_base;
	521	size = vram_size;
5dcb6b91	522	cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset);
eee0b836 BS	523	vram_offset += size;
eee0b836 BS	524	vram_base += size;
e80cfcfc	525
6f7e9aec	526	io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
77f193da BS	527	cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS,
77f193da BS	528	io_memory);
eee0b836	529
8508b89e BS	530	dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
8508b89e BS	531	s);
5dcb6b91	532	cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS,
8508b89e	533	dummy_memory);
eee0b836 BS	534	if (depth == 24) {
	535	// 24-bit plane
	536	size = vram_size * 4;
	537	s->vram24 = (uint32_t *)vram_base;
	538	s->vram24_offset = vram_offset;
5dcb6b91	539	cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset);
eee0b836 BS	540	vram_offset += size;
	541	vram_base += size;
	542
	543	// Control plane
	544	size = vram_size * 4;
	545	s->cplane = (uint32_t *)vram_base;
	546	s->cplane_offset = vram_offset;
5dcb6b91	547	cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
3023f332 AL	548	s->ds = graphic_console_init(tcx24_update_display,
	549	tcx24_invalidate_display,
	550	tcx24_screen_dump, NULL, s);
eee0b836	551	} else {
5dcb6b91	552	cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
8508b89e	553	dummy_memory);
3023f332 AL	554	s->ds = graphic_console_init(tcx_update_display,
	555	tcx_invalidate_display,
	556	tcx_screen_dump, NULL, s);
eee0b836	557	}
f96f4c9d	558	// NetBSD writes here even with 8-bit display
5dcb6b91	559	cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
f96f4c9d	560	dummy_memory);
e80cfcfc	561
fda77c2d	562	register_savevm("tcx", addr, 4, tcx_save, tcx_load, s);
e80cfcfc FB	563	qemu_register_reset(tcx_reset, s);
e80cfcfc FB	564	tcx_reset(s);
3023f332	565	qemu_console_resize(s->ds, width, height);
420557e8 FB	566	}
420557e8 FB	567
95219897	568	static void tcx_screen_dump(void opaque, const char filename)
8d5f07fa	569	{
e80cfcfc	570	TCXState *s = opaque;
8d5f07fa	571	FILE *f;
e80cfcfc	572	uint8_t d, d1, v;
8d5f07fa FB	573	int y, x;
	574
	575	f = fopen(filename, "wb");
	576	if (!f)
e80cfcfc	577	return;
6f7e9aec FB	578	fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
	579	d1 = s->vram;
	580	for(y = 0; y < s->height; y++) {
8d5f07fa	581	d = d1;
6f7e9aec	582	for(x = 0; x < s->width; x++) {
8d5f07fa	583	v = *d;
e80cfcfc FB	584	fputc(s->r[v], f);
	585	fputc(s->g[v], f);
	586	fputc(s->b[v], f);
8d5f07fa FB	587	d++;
8d5f07fa FB	588	}
e80cfcfc	589	d1 += MAXX;
8d5f07fa FB	590	}
	591	fclose(f);
	592	return;
	593	}
	594
eee0b836 BS	595	static void tcx24_screen_dump(void opaque, const char filename)
	596	{
	597	TCXState *s = opaque;
	598	FILE *f;
	599	uint8_t d, d1, v;
	600	uint32_t s24, cptr, dval;
	601	int y, x;
8d5f07fa	602
eee0b836 BS	603	f = fopen(filename, "wb");
	604	if (!f)
	605	return;
	606	fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
	607	d1 = s->vram;
	608	s24 = s->vram24;
	609	cptr = s->cplane;
	610	for(y = 0; y < s->height; y++) {
	611	d = d1;
	612	for(x = 0; x < s->width; x++, d++, s24++) {
	613	if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
	614	dval = *s24 & 0x00ffffff;
	615	fputc((dval >> 16) & 0xff, f);
	616	fputc((dval >> 8) & 0xff, f);
	617	fputc(dval & 0xff, f);
	618	} else {
	619	v = *d;
	620	fputc(s->r[v], f);
	621	fputc(s->g[v], f);
	622	fputc(s->b[v], f);
	623	}
	624	}
	625	d1 += MAXX;
	626	}
	627	fclose(f);
	628	return;
	629	}