[qemu.git] / hw / tcx.c

/*
 * QEMU TCX Frame buffer
 * 
 * Copyright (c) 2003-2005 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

#define MAXX 1024
#define MAXY 768
#define TCX_DAC_NREGS 16
#define TCX_THC_NREGS_8  0x081c
#define TCX_THC_NREGS_24 0x1000
#define TCX_TEC_NREGS    0x1000

typedef struct TCXState {
    target_phys_addr_t addr;
    DisplayState *ds;
    uint8_t *vram;
    uint32_t *vram24, *cplane;
    ram_addr_t vram_offset, vram24_offset, cplane_offset;
    uint16_t width, height, depth;
    uint8_t r[256], g[256], b[256];
    uint32_t palette[256];
    uint8_t dac_index, dac_state;
} TCXState;

static void tcx_screen_dump(void *opaque, const char *filename);
static void tcx24_screen_dump(void *opaque, const char *filename);

/* XXX: unify with vga draw line functions */
static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
{
    return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
}

static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
{
    return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
}

static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
{
    return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
}

static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
{
    return (r << 16) | (g << 8) | b;
}

static void update_palette_entries(TCXState *s, int start, int end)
{
    int i;
    for(i = start; i < end; i++) {
        switch(s->ds->depth) {
        default:
        case 8:
            s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
            break;
        case 15:
            s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
            break;
        case 16:
            s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
            break;
        case 32:
            s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
            break;
        }
    }
}

static void tcx_draw_line32(TCXState *s1, uint8_t *d, 
			    const uint8_t *s, int width)
{
    int x;
    uint8_t val;
    uint32_t *p = (uint32_t *)d;

    for(x = 0; x < width; x++) {
	val = *s++;
        *p++ = s1->palette[val];
    }
}

static void tcx_draw_line16(TCXState *s1, uint8_t *d, 
			    const uint8_t *s, int width)
{
    int x;
    uint8_t val;
    uint16_t *p = (uint16_t *)d;

    for(x = 0; x < width; x++) {
	val = *s++;
        *p++ = s1->palette[val];
    }
}

static void tcx_draw_line8(TCXState *s1, uint8_t *d, 
			   const uint8_t *s, int width)
{
    int x;
    uint8_t val;

    for(x = 0; x < width; x++) {
	val = *s++;
        *d++ = s1->palette[val];
    }
}

static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
                                     const uint8_t *s, int width,
                                     const uint32_t *cplane,
                                     const uint32_t *s24)
{
    int x;
    uint8_t val;
    uint32_t *p = (uint32_t *)d;
    uint32_t dval;

    for(x = 0; x < width; x++, s++, s24++) {
        if ((bswap32(*cplane++) & 0xff000000) == 0x03000000) { // 24-bit direct
            dval = bswap32(*s24) & 0x00ffffff;
        } else {
            val = *s;
            dval = s1->palette[val];
        }
        *p++ = dval;
    }
}

static inline int check_dirty(TCXState *ts, ram_addr_t page, ram_addr_t page24,
                              ram_addr_t cpage)
{
    int ret;
    unsigned int off;

    ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
    for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) {
        ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG);
        ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG);
    }
    return ret;
}

static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
                               ram_addr_t page_max, ram_addr_t page24,
                              ram_addr_t cpage)
{
    cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
                                    VGA_DIRTY_FLAG);
    page_min -= ts->vram_offset;
    page_max -= ts->vram_offset;
    cpu_physical_memory_reset_dirty(page24 + page_min * 4,
                                    page24 + page_max * 4 + TARGET_PAGE_SIZE,
                                    VGA_DIRTY_FLAG);
    cpu_physical_memory_reset_dirty(cpage + page_min * 4,
                                    cpage + page_max * 4 + TARGET_PAGE_SIZE,
                                    VGA_DIRTY_FLAG);
}

/* Fixed line length 1024 allows us to do nice tricks not possible on
   VGA... */
static void tcx_update_display(void *opaque)
{
    TCXState *ts = opaque;
    ram_addr_t page, page_min, page_max;
    int y, y_start, dd, ds;
    uint8_t *d, *s;
    void (*f)(TCXState *s1, uint8_t *d, const uint8_t *s, int width);

    if (ts->ds->depth == 0)
	return;
    page = ts->vram_offset;
    y_start = -1;
    page_min = 0xffffffff;
    page_max = 0;
    d = ts->ds->data;
    s = ts->vram;
    dd = ts->ds->linesize;
    ds = 1024;

    switch (ts->ds->depth) {
    case 32:
	f = tcx_draw_line32;
	break;
    case 15:
    case 16:
	f = tcx_draw_line16;
	break;
    default:
    case 8:
	f = tcx_draw_line8;
	break;
    case 0:
	return;
    }
    
    for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
	if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
	    if (y_start < 0)
                y_start = y;
            if (page < page_min)
                page_min = page;
            if (page > page_max)
                page_max = page;
	    f(ts, d, s, ts->width);
	    d += dd;
	    s += ds;
	    f(ts, d, s, ts->width);
	    d += dd;
	    s += ds;
	    f(ts, d, s, ts->width);
	    d += dd;
	    s += ds;
	    f(ts, d, s, ts->width);
	    d += dd;
	    s += ds;
	} else {
            if (y_start >= 0) {
                /* flush to display */
                dpy_update(ts->ds, 0, y_start, 
                           ts->width, y - y_start);
                y_start = -1;
            }
	    d += dd * 4;
	    s += ds * 4;
	}
    }
    if (y_start >= 0) {
	/* flush to display */
	dpy_update(ts->ds, 0, y_start, 
		   ts->width, y - y_start);
    }
    /* reset modified pages */
    if (page_min <= page_max) {
        cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
                                        VGA_DIRTY_FLAG);
    }
}

static void tcx24_update_display(void *opaque)
{
    TCXState *ts = opaque;
    ram_addr_t page, page_min, page_max, cpage, page24;
    int y, y_start, dd, ds;
    uint8_t *d, *s;
    uint32_t *cptr, *s24;

    if (ts->ds->depth != 32)
            return;
    page = ts->vram_offset;
    page24 = ts->vram24_offset;
    cpage = ts->cplane_offset;
    y_start = -1;
    page_min = 0xffffffff;
    page_max = 0;
    d = ts->ds->data;
    s = ts->vram;
    s24 = ts->vram24;
    cptr = ts->cplane;
    dd = ts->ds->linesize;
    ds = 1024;

    for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
            page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
        if (check_dirty(ts, page, page24, cpage)) {
            if (y_start < 0)
                y_start = y;
            if (page < page_min)
                page_min = page;
            if (page > page_max)
                page_max = page;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
        } else {
            if (y_start >= 0) {
                /* flush to display */
                dpy_update(ts->ds, 0, y_start,
                           ts->width, y - y_start);
                y_start = -1;
            }
            d += dd * 4;
            s += ds * 4;
            cptr += ds * 4;
            s24 += ds * 4;
        }
    }
    if (y_start >= 0) {
        /* flush to display */
        dpy_update(ts->ds, 0, y_start,
                   ts->width, y - y_start);
    }
    /* reset modified pages */
    if (page_min <= page_max) {
        reset_dirty(ts, page_min, page_max, page24, cpage);
    }
}

static void tcx_invalidate_display(void *opaque)
{
    TCXState *s = opaque;
    int i;

    for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) {
	cpu_physical_memory_set_dirty(s->vram_offset + i);
    }
}

static void tcx24_invalidate_display(void *opaque)
{
    TCXState *s = opaque;
    int i;

    tcx_invalidate_display(s);
    for (i = 0; i < MAXX*MAXY * 4; i += TARGET_PAGE_SIZE) {
        cpu_physical_memory_set_dirty(s->vram24_offset + i);
        cpu_physical_memory_set_dirty(s->cplane_offset + i);
    }
}

static void tcx_save(QEMUFile *f, void *opaque)
{
    TCXState *s = opaque;
    
    qemu_put_be32s(f, (uint32_t *)&s->vram);
    qemu_put_be32s(f, (uint32_t *)&s->vram24);
    qemu_put_be32s(f, (uint32_t *)&s->cplane);
    qemu_put_be16s(f, (uint16_t *)&s->height);
    qemu_put_be16s(f, (uint16_t *)&s->width);
    qemu_put_be16s(f, (uint16_t *)&s->depth);
    qemu_put_buffer(f, s->r, 256);
    qemu_put_buffer(f, s->g, 256);
    qemu_put_buffer(f, s->b, 256);
    qemu_put_8s(f, &s->dac_index);
    qemu_put_8s(f, &s->dac_state);
}

static int tcx_load(QEMUFile *f, void *opaque, int version_id)
{
    TCXState *s = opaque;
    
    if (version_id != 3)
        return -EINVAL;

    qemu_get_be32s(f, (uint32_t *)&s->vram);
    qemu_get_be32s(f, (uint32_t *)&s->vram24);
    qemu_get_be32s(f, (uint32_t *)&s->cplane);
    qemu_get_be16s(f, (uint16_t *)&s->height);
    qemu_get_be16s(f, (uint16_t *)&s->width);
    qemu_get_be16s(f, (uint16_t *)&s->depth);
    qemu_get_buffer(f, s->r, 256);
    qemu_get_buffer(f, s->g, 256);
    qemu_get_buffer(f, s->b, 256);
    qemu_get_8s(f, &s->dac_index);
    qemu_get_8s(f, &s->dac_state);
    update_palette_entries(s, 0, 256);
    tcx_invalidate_display(s);

    return 0;
}

static void tcx_reset(void *opaque)
{
    TCXState *s = opaque;

    /* Initialize palette */
    memset(s->r, 0, 256);
    memset(s->g, 0, 256);
    memset(s->b, 0, 256);
    s->r[255] = s->g[255] = s->b[255] = 255;
    update_palette_entries(s, 0, 256);
    memset(s->vram, 0, MAXX*MAXY);
    cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset +
                                    MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG);
    s->dac_index = 0;
    s->dac_state = 0;
}

static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    TCXState *s = opaque;
    uint32_t saddr;

    saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2;
    switch (saddr) {
    case 0:
	s->dac_index = val >> 24;
	s->dac_state = 0;
	break;
    case 1:
	switch (s->dac_state) {
	case 0:
	    s->r[s->dac_index] = val >> 24;
            update_palette_entries(s, s->dac_index, s->dac_index + 1);
	    s->dac_state++;
	    break;
	case 1:
	    s->g[s->dac_index] = val >> 24;
            update_palette_entries(s, s->dac_index, s->dac_index + 1);
	    s->dac_state++;
	    break;
	case 2:
	    s->b[s->dac_index] = val >> 24;
            update_palette_entries(s, s->dac_index, s->dac_index + 1);
            s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
	default:
	    s->dac_state = 0;
	    break;
	}
	break;
    default:
	break;
    }
    return;
}

static CPUReadMemoryFunc *tcx_dac_read[3] = {
    tcx_dac_readl,
    tcx_dac_readl,
    tcx_dac_readl,
};

static CPUWriteMemoryFunc *tcx_dac_write[3] = {
    tcx_dac_writel,
    tcx_dac_writel,
    tcx_dac_writel,
};

static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr,
                             uint32_t val)
{
}

static CPUReadMemoryFunc *tcx_dummy_read[3] = {
    tcx_dummy_readl,
    tcx_dummy_readl,
    tcx_dummy_readl,
};

static CPUWriteMemoryFunc *tcx_dummy_write[3] = {
    tcx_dummy_writel,
    tcx_dummy_writel,
    tcx_dummy_writel,
};

void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
              unsigned long vram_offset, int vram_size, int width, int height,
              int depth)
{
    TCXState *s;
    int io_memory, dummy_memory;
    int size;

    s = qemu_mallocz(sizeof(TCXState));
    if (!s)
        return;
    s->ds = ds;
    s->addr = addr;
    s->vram_offset = vram_offset;
    s->width = width;
    s->height = height;
    s->depth = depth;

    // 8-bit plane
    s->vram = vram_base;
    size = vram_size;
    cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset);
    vram_offset += size;
    vram_base += size;

    io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
    cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS, io_memory);

    dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
                                          s);
    cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS,
                                 dummy_memory);
    if (depth == 24) {
        // 24-bit plane
        size = vram_size * 4;
        s->vram24 = (uint32_t *)vram_base;
        s->vram24_offset = vram_offset;
        cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset);
        vram_offset += size;
        vram_base += size;

        // Control plane
        size = vram_size * 4;
        s->cplane = (uint32_t *)vram_base;
        s->cplane_offset = vram_offset;
        cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
        graphic_console_init(s->ds, tcx24_update_display,
                             tcx24_invalidate_display, tcx24_screen_dump, s);
    } else {
        cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
                                     dummy_memory);
        graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display,
                             tcx_screen_dump, s);
    }
    // NetBSD writes here even with 8-bit display
    cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
                                 dummy_memory);

    register_savevm("tcx", addr, 3, tcx_save, tcx_load, s);
    qemu_register_reset(tcx_reset, s);
    tcx_reset(s);
    dpy_resize(s->ds, width, height);
}

static void tcx_screen_dump(void *opaque, const char *filename)
{
    TCXState *s = opaque;
    FILE *f;
    uint8_t *d, *d1, v;
    int y, x;

    f = fopen(filename, "wb");
    if (!f)
        return;
    fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
    d1 = s->vram;
    for(y = 0; y < s->height; y++) {
        d = d1;
        for(x = 0; x < s->width; x++) {
            v = *d;
            fputc(s->r[v], f);
            fputc(s->g[v], f);
            fputc(s->b[v], f);
            d++;
        }
        d1 += MAXX;
    }
    fclose(f);
    return;
}

static void tcx24_screen_dump(void *opaque, const char *filename)
{
    TCXState *s = opaque;
    FILE *f;
    uint8_t *d, *d1, v;
    uint32_t *s24, *cptr, dval;
    int y, x;

    f = fopen(filename, "wb");
    if (!f)
        return;
    fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
    d1 = s->vram;
    s24 = s->vram24;
    cptr = s->cplane;
    for(y = 0; y < s->height; y++) {
        d = d1;
        for(x = 0; x < s->width; x++, d++, s24++) {
            if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
                dval = *s24 & 0x00ffffff;
                fputc((dval >> 16) & 0xff, f);
                fputc((dval >> 8) & 0xff, f);
                fputc(dval & 0xff, f);
            } else {
                v = *d;
                fputc(s->r[v], f);
                fputc(s->g[v], f);
                fputc(s->b[v], f);
            }
        }
        d1 += MAXX;
    }
    fclose(f);
    return;
}
Commit	Line	Data
420557e8	1	/*
6f7e9aec	2	* QEMU TCX Frame buffer
420557e8	3	*
6f7e9aec	4	* Copyright (c) 2003-2005 Fabrice Bellard
420557e8 FB	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25
420557e8 FB	26	#define MAXX 1024
420557e8 FB	27	#define MAXY 768
6f7e9aec	28	#define TCX_DAC_NREGS 16
8508b89e BS	29	#define TCX_THC_NREGS_8 0x081c
	30	#define TCX_THC_NREGS_24 0x1000
	31	#define TCX_TEC_NREGS 0x1000
420557e8	32
420557e8	33	typedef struct TCXState {
5dcb6b91	34	target_phys_addr_t addr;
420557e8	35	DisplayState *ds;
8d5f07fa	36	uint8_t *vram;
eee0b836 BS	37	uint32_t vram24, cplane;
	38	ram_addr_t vram_offset, vram24_offset, cplane_offset;
	39	uint16_t width, height, depth;
e80cfcfc	40	uint8_t r[256], g[256], b[256];
21206a10	41	uint32_t palette[256];
6f7e9aec	42	uint8_t dac_index, dac_state;
420557e8 FB	43	} TCXState;
420557e8 FB	44
95219897	45	static void tcx_screen_dump(void opaque, const char filename);
eee0b836	46	static void tcx24_screen_dump(void opaque, const char filename);
95219897	47
21206a10 FB	48	/* XXX: unify with vga draw line functions */
	49	static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
	50	{
	51	return ((r >> 5) << 5) \| ((g >> 5) << 2) \| (b >> 6);
	52	}
	53
	54	static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
	55	{
	56	return ((r >> 3) << 10) \| ((g >> 3) << 5) \| (b >> 3);
	57	}
	58
	59	static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
	60	{
	61	return ((r >> 3) << 11) \| ((g >> 2) << 5) \| (b >> 3);
	62	}
	63
	64	static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
	65	{
	66	return (r << 16) \| (g << 8) \| b;
	67	}
	68
	69	static void update_palette_entries(TCXState *s, int start, int end)
	70	{
	71	int i;
	72	for(i = start; i < end; i++) {
	73	switch(s->ds->depth) {
	74	default:
	75	case 8:
	76	s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
	77	break;
	78	case 15:
	79	s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
	80	break;
	81	case 16:
	82	s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
	83	break;
	84	case 32:
	85	s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
	86	break;
	87	}
	88	}
	89	}
	90
e80cfcfc FB	91	static void tcx_draw_line32(TCXState s1, uint8_t d,
e80cfcfc FB	92	const uint8_t *s, int width)
420557e8	93	{
e80cfcfc FB	94	int x;
e80cfcfc FB	95	uint8_t val;
8bdc2159	96	uint32_t p = (uint32_t )d;
e80cfcfc FB	97
	98	for(x = 0; x < width; x++) {
	99	val = *s++;
8bdc2159	100	*p++ = s1->palette[val];
e80cfcfc	101	}
420557e8 FB	102	}
420557e8 FB	103
21206a10	104	static void tcx_draw_line16(TCXState s1, uint8_t d,
e80cfcfc FB	105	const uint8_t *s, int width)
	106	{
	107	int x;
	108	uint8_t val;
8bdc2159	109	uint16_t p = (uint16_t )d;
8d5f07fa	110
e80cfcfc FB	111	for(x = 0; x < width; x++) {
e80cfcfc FB	112	val = *s++;
8bdc2159	113	*p++ = s1->palette[val];
e80cfcfc FB	114	}
	115	}
	116
	117	static void tcx_draw_line8(TCXState s1, uint8_t d,
	118	const uint8_t *s, int width)
420557e8	119	{
e80cfcfc FB	120	int x;
	121	uint8_t val;
	122
	123	for(x = 0; x < width; x++) {
	124	val = *s++;
21206a10	125	*d++ = s1->palette[val];
420557e8	126	}
420557e8 FB	127	}
420557e8 FB	128
eee0b836 BS	129	static inline void tcx24_draw_line32(TCXState s1, uint8_t d,
	130	const uint8_t *s, int width,
	131	const uint32_t *cplane,
	132	const uint32_t *s24)
	133	{
	134	int x;
	135	uint8_t val;
	136	uint32_t p = (uint32_t )d;
	137	uint32_t dval;
	138
	139	for(x = 0; x < width; x++, s++, s24++) {
	140	if ((bswap32(*cplane++) & 0xff000000) == 0x03000000) { // 24-bit direct
	141	dval = bswap32(*s24) & 0x00ffffff;
	142	} else {
	143	val = *s;
	144	dval = s1->palette[val];
	145	}
	146	*p++ = dval;
	147	}
	148	}
	149
	150	static inline int check_dirty(TCXState *ts, ram_addr_t page, ram_addr_t page24,
	151	ram_addr_t cpage)
	152	{
	153	int ret;
	154	unsigned int off;
	155
	156	ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
	157	for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) {
	158	ret \|= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG);
	159	ret \|= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG);
	160	}
	161	return ret;
	162	}
	163
	164	static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
	165	ram_addr_t page_max, ram_addr_t page24,
	166	ram_addr_t cpage)
	167	{
	168	cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
	169	VGA_DIRTY_FLAG);
	170	page_min -= ts->vram_offset;
	171	page_max -= ts->vram_offset;
	172	cpu_physical_memory_reset_dirty(page24 + page_min * 4,
	173	page24 + page_max * 4 + TARGET_PAGE_SIZE,
	174	VGA_DIRTY_FLAG);
	175	cpu_physical_memory_reset_dirty(cpage + page_min * 4,
	176	cpage + page_max * 4 + TARGET_PAGE_SIZE,
	177	VGA_DIRTY_FLAG);
	178	}
	179
e80cfcfc FB	180	/* Fixed line length 1024 allows us to do nice tricks not possible on
e80cfcfc FB	181	VGA... */
95219897	182	static void tcx_update_display(void *opaque)
420557e8	183	{
e80cfcfc	184	TCXState *ts = opaque;
550be127 FB	185	ram_addr_t page, page_min, page_max;
550be127 FB	186	int y, y_start, dd, ds;
e80cfcfc FB	187	uint8_t d, s;
	188	void (f)(TCXState s1, uint8_t d, const uint8_t s, int width);
	189
	190	if (ts->ds->depth == 0)
	191	return;
6f7e9aec	192	page = ts->vram_offset;
e80cfcfc	193	y_start = -1;
550be127 FB	194	page_min = 0xffffffff;
550be127 FB	195	page_max = 0;
e80cfcfc	196	d = ts->ds->data;
6f7e9aec	197	s = ts->vram;
e80cfcfc FB	198	dd = ts->ds->linesize;
	199	ds = 1024;
	200
	201	switch (ts->ds->depth) {
	202	case 32:
	203	f = tcx_draw_line32;
	204	break;
21206a10 FB	205	case 15:
	206	case 16:
	207	f = tcx_draw_line16;
e80cfcfc FB	208	break;
	209	default:
	210	case 8:
	211	f = tcx_draw_line8;
	212	break;
	213	case 0:
	214	return;
	215	}
662f3c86	216
6f7e9aec	217	for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
0a962c02	218	if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
e80cfcfc FB	219	if (y_start < 0)
	220	y_start = y;
	221	if (page < page_min)
	222	page_min = page;
	223	if (page > page_max)
	224	page_max = page;
6f7e9aec	225	f(ts, d, s, ts->width);
e80cfcfc FB	226	d += dd;
e80cfcfc FB	227	s += ds;
6f7e9aec	228	f(ts, d, s, ts->width);
e80cfcfc FB	229	d += dd;
e80cfcfc FB	230	s += ds;
6f7e9aec	231	f(ts, d, s, ts->width);
e80cfcfc FB	232	d += dd;
e80cfcfc FB	233	s += ds;
6f7e9aec	234	f(ts, d, s, ts->width);
e80cfcfc FB	235	d += dd;
	236	s += ds;
	237	} else {
	238	if (y_start >= 0) {
	239	/* flush to display */
	240	dpy_update(ts->ds, 0, y_start,
6f7e9aec	241	ts->width, y - y_start);
e80cfcfc FB	242	y_start = -1;
	243	}
	244	d += dd * 4;
	245	s += ds * 4;
	246	}
	247	}
	248	if (y_start >= 0) {
	249	/* flush to display */
	250	dpy_update(ts->ds, 0, y_start,
6f7e9aec	251	ts->width, y - y_start);
e80cfcfc FB	252	}
e80cfcfc FB	253	/* reset modified pages */
550be127	254	if (page_min <= page_max) {
0a962c02 FB	255	cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
0a962c02 FB	256	VGA_DIRTY_FLAG);
e80cfcfc	257	}
420557e8 FB	258	}
420557e8 FB	259
eee0b836 BS	260	static void tcx24_update_display(void *opaque)
	261	{
	262	TCXState *ts = opaque;
	263	ram_addr_t page, page_min, page_max, cpage, page24;
	264	int y, y_start, dd, ds;
	265	uint8_t d, s;
	266	uint32_t cptr, s24;
	267
	268	if (ts->ds->depth != 32)
	269	return;
	270	page = ts->vram_offset;
	271	page24 = ts->vram24_offset;
	272	cpage = ts->cplane_offset;
	273	y_start = -1;
	274	page_min = 0xffffffff;
	275	page_max = 0;
	276	d = ts->ds->data;
	277	s = ts->vram;
	278	s24 = ts->vram24;
	279	cptr = ts->cplane;
	280	dd = ts->ds->linesize;
	281	ds = 1024;
	282
	283	for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
	284	page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
	285	if (check_dirty(ts, page, page24, cpage)) {
	286	if (y_start < 0)
	287	y_start = y;
	288	if (page < page_min)
	289	page_min = page;
	290	if (page > page_max)
	291	page_max = page;
	292	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	293	d += dd;
	294	s += ds;
	295	cptr += ds;
	296	s24 += ds;
	297	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	298	d += dd;
	299	s += ds;
	300	cptr += ds;
	301	s24 += ds;
	302	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	303	d += dd;
	304	s += ds;
	305	cptr += ds;
	306	s24 += ds;
	307	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	308	d += dd;
	309	s += ds;
	310	cptr += ds;
	311	s24 += ds;
	312	} else {
	313	if (y_start >= 0) {
	314	/* flush to display */
	315	dpy_update(ts->ds, 0, y_start,
	316	ts->width, y - y_start);
	317	y_start = -1;
	318	}
	319	d += dd * 4;
	320	s += ds * 4;
	321	cptr += ds * 4;
	322	s24 += ds * 4;
	323	}
324	}
325	if (y_start >= 0) {
326	/* flush to display */
327	dpy_update(ts->ds, 0, y_start,
328	ts->width, y - y_start);
329	}
330	/* reset modified pages */
331	if (page_min <= page_max) {
332	reset_dirty(ts, page_min, page_max, page24, cpage);
333	}
334	}
335
95219897	336	static void tcx_invalidate_display(void *opaque)
420557e8	337	{
e80cfcfc FB	338	TCXState *s = opaque;
	339	int i;
	340
	341	for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) {
e80cfcfc	342	cpu_physical_memory_set_dirty(s->vram_offset + i);
e80cfcfc	343	}
420557e8 FB	344	}
420557e8 FB	345
eee0b836 BS	346	static void tcx24_invalidate_display(void *opaque)
	347	{
	348	TCXState *s = opaque;
	349	int i;
	350
	351	tcx_invalidate_display(s);
	352	for (i = 0; i < MAXXMAXY 4; i += TARGET_PAGE_SIZE) {
	353	cpu_physical_memory_set_dirty(s->vram24_offset + i);
	354	cpu_physical_memory_set_dirty(s->cplane_offset + i);
	355	}
	356	}
	357
e80cfcfc	358	static void tcx_save(QEMUFile f, void opaque)
420557e8 FB	359	{
420557e8 FB	360	TCXState *s = opaque;
e80cfcfc	361
e80cfcfc	362	qemu_put_be32s(f, (uint32_t *)&s->vram);
eee0b836 BS	363	qemu_put_be32s(f, (uint32_t *)&s->vram24);
eee0b836 BS	364	qemu_put_be32s(f, (uint32_t *)&s->cplane);
6f7e9aec FB	365	qemu_put_be16s(f, (uint16_t *)&s->height);
6f7e9aec FB	366	qemu_put_be16s(f, (uint16_t *)&s->width);
eee0b836	367	qemu_put_be16s(f, (uint16_t *)&s->depth);
e80cfcfc FB	368	qemu_put_buffer(f, s->r, 256);
	369	qemu_put_buffer(f, s->g, 256);
	370	qemu_put_buffer(f, s->b, 256);
6f7e9aec FB	371	qemu_put_8s(f, &s->dac_index);
6f7e9aec FB	372	qemu_put_8s(f, &s->dac_state);
420557e8 FB	373	}
420557e8 FB	374
e80cfcfc	375	static int tcx_load(QEMUFile f, void opaque, int version_id)
420557e8	376	{
e80cfcfc FB	377	TCXState *s = opaque;
e80cfcfc FB	378
5dcb6b91	379	if (version_id != 3)
e80cfcfc FB	380	return -EINVAL;
e80cfcfc FB	381
e80cfcfc	382	qemu_get_be32s(f, (uint32_t *)&s->vram);
eee0b836 BS	383	qemu_get_be32s(f, (uint32_t *)&s->vram24);
eee0b836 BS	384	qemu_get_be32s(f, (uint32_t *)&s->cplane);
6f7e9aec FB	385	qemu_get_be16s(f, (uint16_t *)&s->height);
6f7e9aec FB	386	qemu_get_be16s(f, (uint16_t *)&s->width);
eee0b836	387	qemu_get_be16s(f, (uint16_t *)&s->depth);
e80cfcfc FB	388	qemu_get_buffer(f, s->r, 256);
	389	qemu_get_buffer(f, s->g, 256);
	390	qemu_get_buffer(f, s->b, 256);
6f7e9aec FB	391	qemu_get_8s(f, &s->dac_index);
6f7e9aec FB	392	qemu_get_8s(f, &s->dac_state);
21206a10	393	update_palette_entries(s, 0, 256);
5425a216 BS	394	tcx_invalidate_display(s);
5425a216 BS	395
e80cfcfc	396	return 0;
420557e8 FB	397	}
420557e8 FB	398
e80cfcfc	399	static void tcx_reset(void *opaque)
420557e8	400	{
e80cfcfc FB	401	TCXState *s = opaque;
	402
	403	/* Initialize palette */
	404	memset(s->r, 0, 256);
	405	memset(s->g, 0, 256);
	406	memset(s->b, 0, 256);
	407	s->r[255] = s->g[255] = s->b[255] = 255;
21206a10	408	update_palette_entries(s, 0, 256);
e80cfcfc	409	memset(s->vram, 0, MAXX*MAXY);
eee0b836 BS	410	cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset +
eee0b836 BS	411	MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG);
6f7e9aec FB	412	s->dac_index = 0;
	413	s->dac_state = 0;
	414	}
	415
	416	static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
	417	{
	418	return 0;
	419	}
	420
	421	static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	422	{
	423	TCXState *s = opaque;
	424	uint32_t saddr;
	425
	426	saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2;
	427	switch (saddr) {
	428	case 0:
	429	s->dac_index = val >> 24;
	430	s->dac_state = 0;
	431	break;
	432	case 1:
	433	switch (s->dac_state) {
	434	case 0:
	435	s->r[s->dac_index] = val >> 24;
21206a10	436	update_palette_entries(s, s->dac_index, s->dac_index + 1);
6f7e9aec FB	437	s->dac_state++;
	438	break;
	439	case 1:
	440	s->g[s->dac_index] = val >> 24;
21206a10	441	update_palette_entries(s, s->dac_index, s->dac_index + 1);
6f7e9aec FB	442	s->dac_state++;
	443	break;
	444	case 2:
	445	s->b[s->dac_index] = val >> 24;
21206a10	446	update_palette_entries(s, s->dac_index, s->dac_index + 1);
5c8cdbf8	447	s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
6f7e9aec FB	448	default:
	449	s->dac_state = 0;
	450	break;
	451	}
	452	break;
	453	default:
	454	break;
	455	}
	456	return;
420557e8 FB	457	}
420557e8 FB	458
6f7e9aec FB	459	static CPUReadMemoryFunc *tcx_dac_read[3] = {
	460	tcx_dac_readl,
	461	tcx_dac_readl,
	462	tcx_dac_readl,
	463	};
	464
	465	static CPUWriteMemoryFunc *tcx_dac_write[3] = {
	466	tcx_dac_writel,
	467	tcx_dac_writel,
	468	tcx_dac_writel,
	469	};
	470
8508b89e BS	471	static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr)
	472	{
	473	return 0;
	474	}
	475
	476	static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr,
	477	uint32_t val)
	478	{
	479	}
	480
	481	static CPUReadMemoryFunc *tcx_dummy_read[3] = {
	482	tcx_dummy_readl,
	483	tcx_dummy_readl,
	484	tcx_dummy_readl,
	485	};
	486
	487	static CPUWriteMemoryFunc *tcx_dummy_write[3] = {
	488	tcx_dummy_writel,
	489	tcx_dummy_writel,
	490	tcx_dummy_writel,
	491	};
	492
5dcb6b91	493	void tcx_init(DisplayState ds, target_phys_addr_t addr, uint8_t vram_base,
eee0b836 BS	494	unsigned long vram_offset, int vram_size, int width, int height,
eee0b836 BS	495	int depth)
420557e8 FB	496	{
420557e8 FB	497	TCXState *s;
8508b89e	498	int io_memory, dummy_memory;
eee0b836	499	int size;
420557e8 FB	500
	501	s = qemu_mallocz(sizeof(TCXState));
	502	if (!s)
95219897	503	return;
420557e8	504	s->ds = ds;
8d5f07fa	505	s->addr = addr;
e80cfcfc	506	s->vram_offset = vram_offset;
6f7e9aec FB	507	s->width = width;
6f7e9aec FB	508	s->height = height;
eee0b836 BS	509	s->depth = depth;
	510
	511	// 8-bit plane
	512	s->vram = vram_base;
	513	size = vram_size;
5dcb6b91	514	cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset);
eee0b836 BS	515	vram_offset += size;
eee0b836 BS	516	vram_base += size;
e80cfcfc	517
6f7e9aec	518	io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
5dcb6b91	519	cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS, io_memory);
eee0b836	520
8508b89e BS	521	dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
8508b89e BS	522	s);
5dcb6b91	523	cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS,
8508b89e	524	dummy_memory);
eee0b836 BS	525	if (depth == 24) {
	526	// 24-bit plane
	527	size = vram_size * 4;
	528	s->vram24 = (uint32_t *)vram_base;
	529	s->vram24_offset = vram_offset;
5dcb6b91	530	cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset);
eee0b836 BS	531	vram_offset += size;
	532	vram_base += size;
	533
	534	// Control plane
	535	size = vram_size * 4;
	536	s->cplane = (uint32_t *)vram_base;
	537	s->cplane_offset = vram_offset;
5dcb6b91	538	cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
8508b89e BS	539	graphic_console_init(s->ds, tcx24_update_display,
8508b89e BS	540	tcx24_invalidate_display, tcx24_screen_dump, s);
eee0b836	541	} else {
5dcb6b91	542	cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
8508b89e	543	dummy_memory);
eee0b836 BS	544	graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display,
	545	tcx_screen_dump, s);
	546	}
f96f4c9d	547	// NetBSD writes here even with 8-bit display
5dcb6b91	548	cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
f96f4c9d	549	dummy_memory);
e80cfcfc	550
5dcb6b91	551	register_savevm("tcx", addr, 3, tcx_save, tcx_load, s);
e80cfcfc FB	552	qemu_register_reset(tcx_reset, s);
e80cfcfc FB	553	tcx_reset(s);
6f7e9aec	554	dpy_resize(s->ds, width, height);
420557e8 FB	555	}
420557e8 FB	556
95219897	557	static void tcx_screen_dump(void opaque, const char filename)
8d5f07fa	558	{
e80cfcfc	559	TCXState *s = opaque;
8d5f07fa	560	FILE *f;
e80cfcfc	561	uint8_t d, d1, v;
8d5f07fa FB	562	int y, x;
	563
	564	f = fopen(filename, "wb");
	565	if (!f)
e80cfcfc	566	return;
6f7e9aec FB	567	fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
	568	d1 = s->vram;
	569	for(y = 0; y < s->height; y++) {
8d5f07fa	570	d = d1;
6f7e9aec	571	for(x = 0; x < s->width; x++) {
8d5f07fa	572	v = *d;
e80cfcfc FB	573	fputc(s->r[v], f);
	574	fputc(s->g[v], f);
	575	fputc(s->b[v], f);
8d5f07fa FB	576	d++;
8d5f07fa FB	577	}
e80cfcfc	578	d1 += MAXX;
8d5f07fa FB	579	}
	580	fclose(f);
	581	return;
	582	}
	583
eee0b836 BS	584	static void tcx24_screen_dump(void opaque, const char filename)
	585	{
	586	TCXState *s = opaque;
	587	FILE *f;
	588	uint8_t d, d1, v;
	589	uint32_t s24, cptr, dval;
	590	int y, x;
8d5f07fa	591
eee0b836 BS	592	f = fopen(filename, "wb");
	593	if (!f)
	594	return;
	595	fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
	596	d1 = s->vram;
	597	s24 = s->vram24;
	598	cptr = s->cplane;
	599	for(y = 0; y < s->height; y++) {
	600	d = d1;
	601	for(x = 0; x < s->width; x++, d++, s24++) {
	602	if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
	603	dval = *s24 & 0x00ffffff;
	604	fputc((dval >> 16) & 0xff, f);
	605	fputc((dval >> 8) & 0xff, f);
	606	fputc(dval & 0xff, f);
	607	} else {
	608	v = *d;
	609	fputc(s->r[v], f);
	610	fputc(s->g[v], f);
	611	fputc(s->b[v], f);
	612	}
	613	}
	614	d1 += MAXX;
	615	}
	616	fclose(f);
	617	return;
	618	}