[qemu.git] / target-cris / op_helper.c

/*
 *  CRIS helper routines
 *
 *  Copyright (c) 2007 AXIS Communications
 *  Written by Edgar E. Iglesias
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "mmu.h"
#include "helper.h"
#include "qemu/host-utils.h"

//#define CRIS_OP_HELPER_DEBUG


#ifdef CRIS_OP_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA_ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif

#if !defined(CONFIG_USER_ONLY)
#include "exec/softmmu_exec.h"

#define MMUSUFFIX _mmu

#define SHIFT 0
#include "exec/softmmu_template.h"

#define SHIFT 1
#include "exec/softmmu_template.h"

#define SHIFT 2
#include "exec/softmmu_template.h"

#define SHIFT 3
#include "exec/softmmu_template.h"

/* Try to fill the TLB and return an exception if error. If retaddr is
   NULL, it means that the function was called in C code (i.e. not
   from generated code or from helper.c) */
void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
              uintptr_t retaddr)
{
    int ret;

    D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
          env->pc, env->pregs[PR_EDA], (void *)retaddr);
    ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            if (cpu_restore_state(env, retaddr)) {
		/* Evaluate flags after retranslation.  */
                helper_top_evaluate_flags(env);
            }
        }
        cpu_loop_exit(env);
    }
}

#endif

void helper_raise_exception(CPUCRISState *env, uint32_t index)
{
	env->exception_index = index;
        cpu_loop_exit(env);
}

void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
{
#if !defined(CONFIG_USER_ONLY)
	pid &= 0xff;
	if (pid != (env->pregs[PR_PID] & 0xff))
		cris_mmu_flush_pid(env, env->pregs[PR_PID]);
#endif
}

void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
{
#if !defined(CONFIG_USER_ONLY)
	tlb_flush_page(env, env->pregs[PR_SPC]);
	tlb_flush_page(env, new_spc);
#endif
}

void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
{
	qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
}

/* Used by the tlb decoder.  */
#define EXTRACT_FIELD(src, start, end) \
	    (((src) >> start) & ((1 << (end - start + 1)) - 1))

void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
{
	uint32_t srs;
	srs = env->pregs[PR_SRS];
	srs &= 3;
	env->sregs[srs][sreg] = env->regs[reg];

#if !defined(CONFIG_USER_ONLY)
	if (srs == 1 || srs == 2) {
		if (sreg == 6) {
			/* Writes to tlb-hi write to mm_cause as a side 
			   effect.  */
			env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
			env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
		}
		else if (sreg == 5) {
			uint32_t set;
			uint32_t idx;
			uint32_t lo, hi;
			uint32_t vaddr;
			int tlb_v;

			idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
			set >>= 4;
			set &= 3;

			idx &= 15;
			/* We've just made a write to tlb_lo.  */
			lo = env->sregs[SFR_RW_MM_TLB_LO];
			/* Writes are done via r_mm_cause.  */
			hi = env->sregs[SFR_R_MM_CAUSE];

			vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
					      13, 31);
			vaddr <<= TARGET_PAGE_BITS;
			tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
					    3, 3);
			env->tlbsets[srs - 1][set][idx].lo = lo;
			env->tlbsets[srs - 1][set][idx].hi = hi;

			D_LOG("tlb flush vaddr=%x v=%d pc=%x\n", 
				  vaddr, tlb_v, env->pc);
			if (tlb_v) {
				tlb_flush_page(env, vaddr);
			}
		}
	}
#endif
}

void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg)
{
	uint32_t srs;
	env->pregs[PR_SRS] &= 3;
	srs = env->pregs[PR_SRS];
	
#if !defined(CONFIG_USER_ONLY)
	if (srs == 1 || srs == 2)
	{
		uint32_t set;
		uint32_t idx;
		uint32_t lo, hi;

		idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
		set >>= 4;
		set &= 3;
		idx &= 15;

		/* Update the mirror regs.  */
		hi = env->tlbsets[srs - 1][set][idx].hi;
		lo = env->tlbsets[srs - 1][set][idx].lo;
		env->sregs[SFR_RW_MM_TLB_HI] = hi;
		env->sregs[SFR_RW_MM_TLB_LO] = lo;
	}
#endif
	env->regs[reg] = env->sregs[srs][sreg];
}

static void cris_ccs_rshift(CPUCRISState *env)
{
	uint32_t ccs;

	/* Apply the ccs shift.  */
	ccs = env->pregs[PR_CCS];
	ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
	if (ccs & U_FLAG)
	{
		/* Enter user mode.  */
		env->ksp = env->regs[R_SP];
		env->regs[R_SP] = env->pregs[PR_USP];
	}

	env->pregs[PR_CCS] = ccs;
}

void helper_rfe(CPUCRISState *env)
{
	int rflag = env->pregs[PR_CCS] & R_FLAG;

	D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n", 
		 env->pregs[PR_ERP], env->pregs[PR_PID],
		 env->pregs[PR_CCS],
		 env->btarget);

	cris_ccs_rshift(env);

	/* RFE sets the P_FLAG only if the R_FLAG is not set.  */
	if (!rflag)
		env->pregs[PR_CCS] |= P_FLAG;
}

void helper_rfn(CPUCRISState *env)
{
	int rflag = env->pregs[PR_CCS] & R_FLAG;

	D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n", 
		 env->pregs[PR_ERP], env->pregs[PR_PID],
		 env->pregs[PR_CCS],
		 env->btarget);

	cris_ccs_rshift(env);

	/* Set the P_FLAG only if the R_FLAG is not set.  */
	if (!rflag)
		env->pregs[PR_CCS] |= P_FLAG;

	/* Always set the M flag.  */
	env->pregs[PR_CCS] |= M_FLAG_V32;
}

uint32_t helper_lz(uint32_t t0)
{
	return clz32(t0);
}

uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t ccs)
{
	/* FIXME: clean this up.  */

	/* des ref:
	   The N flag is set according to the selected bit in the dest reg.
	   The Z flag is set if the selected bit and all bits to the right are
	   zero.
	   The X flag is cleared.
	   Other flags are left untouched.
	   The destination reg is not affected.*/
	unsigned int fz, sbit, bset, mask, masked_t0;

	sbit = t1 & 31;
	bset = !!(t0 & (1 << sbit));
	mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
	masked_t0 = t0 & mask;
	fz = !(masked_t0 | bset);

	/* Clear the X, N and Z flags.  */
	ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
	if (env->pregs[PR_VR] < 32)
		ccs &= ~(V_FLAG | C_FLAG);
	/* Set the N and Z flags accordingly.  */
	ccs |= (bset << 3) | (fz << 2);
	return ccs;
}

static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
                                                uint32_t flags, uint32_t ccs)
{
	unsigned int x, z, mask;

	/* Extended arithmetics, leave the z flag alone.  */
	x = env->cc_x;
	mask = env->cc_mask | X_FLAG;
        if (x) {
		z = flags & Z_FLAG;
		mask = mask & ~z;
	}
	flags &= mask;

	/* all insn clear the x-flag except setf or clrf.  */
	ccs &= ~mask;
	ccs |= flags;
	return ccs;
}

uint32_t helper_evaluate_flags_muls(CPUCRISState *env,
                                    uint32_t ccs, uint32_t res, uint32_t mof)
{
	uint32_t flags = 0;
	int64_t tmp;
	int dneg;

	dneg = ((int32_t)res) < 0;

	tmp = mof;
	tmp <<= 32;
	tmp |= res;
	if (tmp == 0)
		flags |= Z_FLAG;
	else if (tmp < 0)
		flags |= N_FLAG;
	if ((dneg && mof != -1)
	    || (!dneg && mof != 0))
		flags |= V_FLAG;
        return evaluate_flags_writeback(env, flags, ccs);
}

uint32_t helper_evaluate_flags_mulu(CPUCRISState *env,
                                    uint32_t ccs, uint32_t res, uint32_t mof)
{
	uint32_t flags = 0;
	uint64_t tmp;

	tmp = mof;
	tmp <<= 32;
	tmp |= res;
	if (tmp == 0)
		flags |= Z_FLAG;
	else if (tmp >> 63)
		flags |= N_FLAG;
	if (mof)
		flags |= V_FLAG;

        return evaluate_flags_writeback(env, flags, ccs);
}

uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs,
				   uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = src & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= R_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= R_FLAG;
	}

        return evaluate_flags_writeback(env, flags, ccs);
}

uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs,
				     uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = src & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= C_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= C_FLAG;
	}

        return evaluate_flags_writeback(env, flags, ccs);
}

uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs,
				     uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = (~src) & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= C_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= C_FLAG;
	}

	flags ^= C_FLAG;
        return evaluate_flags_writeback(env, flags, ccs);
}

uint32_t helper_evaluate_flags_move_4(CPUCRISState *env,
                                      uint32_t ccs, uint32_t res)
{
	uint32_t flags = 0;

	if ((int32_t)res < 0)
		flags |= N_FLAG;
	else if (res == 0L)
		flags |= Z_FLAG;

        return evaluate_flags_writeback(env, flags, ccs);
}
uint32_t helper_evaluate_flags_move_2(CPUCRISState *env,
                                      uint32_t ccs, uint32_t res)
{
	uint32_t flags = 0;

	if ((int16_t)res < 0L)
		flags |= N_FLAG;
	else if (res == 0)
		flags |= Z_FLAG;

        return evaluate_flags_writeback(env, flags, ccs);
}

/* TODO: This is expensive. We could split things up and only evaluate part of
   CCR on a need to know basis. For now, we simply re-evaluate everything.  */
void helper_evaluate_flags(CPUCRISState *env)
{
	uint32_t src, dst, res;
	uint32_t flags = 0;

	src = env->cc_src;
	dst = env->cc_dest;
	res = env->cc_result;

	if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
		src = ~src;

	/* Now, evaluate the flags. This stuff is based on
	   Per Zander's CRISv10 simulator.  */
	switch (env->cc_size)
	{
		case 1:
			if ((res & 0x80L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x80L) == 0L)
				    && ((dst & 0x80L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x80L) != 0L)
					 && ((dst & 0x80L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if ((res & 0xFFL) == 0L)
				{
					flags |= Z_FLAG;
				}
				if (((src & 0x80L) != 0L)
				    && ((dst & 0x80L) != 0L))
				{
					flags |= V_FLAG;
				}
				if ((dst & 0x80L) != 0L
				    || (src & 0x80L) != 0L)
				{
					flags |= C_FLAG;
				}
			}
			break;
		case 2:
			if ((res & 0x8000L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x8000L) == 0L)
				    && ((dst & 0x8000L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x8000L) != 0L)
					 && ((dst & 0x8000L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if ((res & 0xFFFFL) == 0L)
				{
					flags |= Z_FLAG;
				}
				if (((src & 0x8000L) != 0L)
				    && ((dst & 0x8000L) != 0L))
				{
					flags |= V_FLAG;
				}
				if ((dst & 0x8000L) != 0L
				    || (src & 0x8000L) != 0L)
				{
					flags |= C_FLAG;
				}
			}
			break;
		case 4:
			if ((res & 0x80000000L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x80000000L) == 0L)
				    && ((dst & 0x80000000L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x80000000L) != 0L) &&
					 ((dst & 0x80000000L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if (res == 0L)
					flags |= Z_FLAG;
				if (((src & 0x80000000L) != 0L)
				    && ((dst & 0x80000000L) != 0L))
					flags |= V_FLAG;
				if ((dst & 0x80000000L) != 0L
				    || (src & 0x80000000L) != 0L)
					flags |= C_FLAG;
			}
			break;
		default:
			break;
	}

	if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
		flags ^= C_FLAG;

        env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
                                                      env->pregs[PR_CCS]);
}

void helper_top_evaluate_flags(CPUCRISState *env)
{
	switch (env->cc_op)
	{
		case CC_OP_MCP:
                        env->pregs[PR_CCS] = helper_evaluate_flags_mcp(env,
					env->pregs[PR_CCS], env->cc_src,
					env->cc_dest, env->cc_result);
			break;
		case CC_OP_MULS:
                        env->pregs[PR_CCS] = helper_evaluate_flags_muls(env,
					env->pregs[PR_CCS], env->cc_result,
					env->pregs[PR_MOF]);
			break;
		case CC_OP_MULU:
                        env->pregs[PR_CCS] = helper_evaluate_flags_mulu(env,
					env->pregs[PR_CCS], env->cc_result,
					env->pregs[PR_MOF]);
			break;
		case CC_OP_MOVE:
		case CC_OP_AND:
		case CC_OP_OR:
		case CC_OP_XOR:
		case CC_OP_ASR:
		case CC_OP_LSR:
		case CC_OP_LSL:
		switch (env->cc_size)
		{
			case 4:
				env->pregs[PR_CCS] =
                                        helper_evaluate_flags_move_4(env,
							env->pregs[PR_CCS],
							env->cc_result);
				break;
			case 2:
				env->pregs[PR_CCS] =
                                        helper_evaluate_flags_move_2(env,
							env->pregs[PR_CCS],
							env->cc_result);
				break;
			default:
                                helper_evaluate_flags(env);
				break;
		}
		break;
		case CC_OP_FLAGS:
			/* live.  */
			break;
		case CC_OP_SUB:
		case CC_OP_CMP:
			if (env->cc_size == 4)
				env->pregs[PR_CCS] =
                                        helper_evaluate_flags_sub_4(env,
						env->pregs[PR_CCS],
						env->cc_src, env->cc_dest,
						env->cc_result);
			else
                                helper_evaluate_flags(env);
			break;
		default:
		{
			switch (env->cc_size)
			{
			case 4:
				env->pregs[PR_CCS] =
                                        helper_evaluate_flags_alu_4(env,
						env->pregs[PR_CCS],
						env->cc_src, env->cc_dest,
						env->cc_result);
				break;
			default:
                                helper_evaluate_flags(env);
				break;
			}
		}
		break;
	}
}
Commit	Line	Data
81fdc5f8 TS	1	/*
	2	* CRIS helper routines
	3	*
	4	* Copyright (c) 2007 AXIS Communications
	5	* Written by Edgar E. Iglesias
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
81fdc5f8 TS	19	*/
81fdc5f8 TS	20
3e457172	21	#include "cpu.h"
786c02f1	22	#include "mmu.h"
30abcfc7	23	#include "helper.h"
1de7afc9	24	#include "qemu/host-utils.h"
81fdc5f8	25
d12d51d5 AL	26	//#define CRIS_OP_HELPER_DEBUG
	27
	28
	29	#ifdef CRIS_OP_HELPER_DEBUG
	30	#define D(x) x
3f668b6c	31	#define D_LOG(...) qemu_log(__VA_ARGS__)
d12d51d5	32	#else
e2eef170	33	#define D(x)
d12d51d5 AL	34	#define D_LOG(...) do { } while (0)
d12d51d5 AL	35	#endif
e2eef170 PB	36
e2eef170 PB	37	#if !defined(CONFIG_USER_ONLY)
022c62cb	38	#include "exec/softmmu_exec.h"
e2eef170	39
81fdc5f8	40	#define MMUSUFFIX _mmu
81fdc5f8 TS	41
81fdc5f8 TS	42	#define SHIFT 0
022c62cb	43	#include "exec/softmmu_template.h"
81fdc5f8 TS	44
81fdc5f8 TS	45	#define SHIFT 1
022c62cb	46	#include "exec/softmmu_template.h"
81fdc5f8 TS	47
81fdc5f8 TS	48	#define SHIFT 2
022c62cb	49	#include "exec/softmmu_template.h"
81fdc5f8 TS	50
81fdc5f8 TS	51	#define SHIFT 3
022c62cb	52	#include "exec/softmmu_template.h"
81fdc5f8 TS	53
	54	/* Try to fill the TLB and return an exception if error. If retaddr is
	55	NULL, it means that the function was called in C code (i.e. not
	56	from generated code or from helper.c) */
cf7e0c80	57	void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
20503968	58	uintptr_t retaddr)
81fdc5f8	59	{
81fdc5f8 TS	60	int ret;
81fdc5f8 TS	61
20503968	62	D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
ff057ccb	63	env->pc, env->pregs[PR_EDA], (void *)retaddr);
97b348e7	64	ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
551bd27f	65	if (unlikely(ret)) {
81fdc5f8 TS	66	if (retaddr) {
81fdc5f8 TS	67	/* now we have a real cpu fault */
a8a826a3	68	if (cpu_restore_state(env, retaddr)) {
30abcfc7	69	/* Evaluate flags after retranslation. */
febc9920	70	helper_top_evaluate_flags(env);
81fdc5f8 TS	71	}
81fdc5f8 TS	72	}
1162c041	73	cpu_loop_exit(env);
81fdc5f8	74	}
81fdc5f8 TS	75	}
81fdc5f8 TS	76
e2eef170 PB	77	#endif
e2eef170 PB	78
febc9920	79	void helper_raise_exception(CPUCRISState *env, uint32_t index)
786c02f1	80	{
dceaf394	81	env->exception_index = index;
1162c041	82	cpu_loop_exit(env);
786c02f1 EI	83	}
786c02f1 EI	84
febc9920	85	void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
cf1d97f0 EI	86	{
cf1d97f0 EI	87	#if !defined(CONFIG_USER_ONLY)
28de16da EI	88	pid &= 0xff;
	89	if (pid != (env->pregs[PR_PID] & 0xff))
	90	cris_mmu_flush_pid(env, env->pregs[PR_PID]);
cf1d97f0 EI	91	#endif
	92	}
	93
febc9920	94	void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
a1aebcb8 EI	95	{
	96	#if !defined(CONFIG_USER_ONLY)
	97	tlb_flush_page(env, env->pregs[PR_SPC]);
	98	tlb_flush_page(env, new_spc);
	99	#endif
	100	}
	101
30abcfc7	102	void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
b41f7df0	103	{
93fcfe39	104	qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
b41f7df0 EI	105	}
b41f7df0 EI	106
cf1d97f0 EI	107	/* Used by the tlb decoder. */
	108	#define EXTRACT_FIELD(src, start, end) \
	109	(((src) >> start) & ((1 << (end - start + 1)) - 1))
	110
febc9920	111	void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
dceaf394 EI	112	{
	113	uint32_t srs;
	114	srs = env->pregs[PR_SRS];
	115	srs &= 3;
	116	env->sregs[srs][sreg] = env->regs[reg];
	117
	118	#if !defined(CONFIG_USER_ONLY)
	119	if (srs == 1 \|\| srs == 2) {
	120	if (sreg == 6) {
	121	/* Writes to tlb-hi write to mm_cause as a side
	122	effect. */
6913ba56 EI	123	env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
6913ba56 EI	124	env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
dceaf394 EI	125	}
	126	else if (sreg == 5) {
	127	uint32_t set;
	128	uint32_t idx;
	129	uint32_t lo, hi;
	130	uint32_t vaddr;
cf1d97f0	131	int tlb_v;
dceaf394 EI	132
	133	idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
	134	set >>= 4;
	135	set &= 3;
	136
	137	idx &= 15;
	138	/* We've just made a write to tlb_lo. */
	139	lo = env->sregs[SFR_RW_MM_TLB_LO];
	140	/* Writes are done via r_mm_cause. */
	141	hi = env->sregs[SFR_R_MM_CAUSE];
cf1d97f0 EI	142
	143	vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
	144	13, 31);
	145	vaddr <<= TARGET_PAGE_BITS;
	146	tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
	147	3, 3);
dceaf394 EI	148	env->tlbsets[srs - 1][set][idx].lo = lo;
dceaf394 EI	149	env->tlbsets[srs - 1][set][idx].hi = hi;
cf1d97f0	150
d12d51d5 AL	151	D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
d12d51d5 AL	152	vaddr, tlb_v, env->pc);
3e18c6bf EI	153	if (tlb_v) {
	154	tlb_flush_page(env, vaddr);
	155	}
dceaf394 EI	156	}
	157	}
	158	#endif
	159	}
	160
febc9920	161	void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg)
dceaf394 EI	162	{
	163	uint32_t srs;
	164	env->pregs[PR_SRS] &= 3;
	165	srs = env->pregs[PR_SRS];
	166
	167	#if !defined(CONFIG_USER_ONLY)
	168	if (srs == 1 \|\| srs == 2)
	169	{
	170	uint32_t set;
	171	uint32_t idx;
	172	uint32_t lo, hi;
	173
	174	idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
	175	set >>= 4;
	176	set &= 3;
	177	idx &= 15;
	178
	179	/* Update the mirror regs. */
	180	hi = env->tlbsets[srs - 1][set][idx].hi;
	181	lo = env->tlbsets[srs - 1][set][idx].lo;
	182	env->sregs[SFR_RW_MM_TLB_HI] = hi;
	183	env->sregs[SFR_RW_MM_TLB_LO] = lo;
	184	}
	185	#endif
	186	env->regs[reg] = env->sregs[srs][sreg];
dceaf394 EI	187	}
dceaf394 EI	188
a1170bfd	189	static void cris_ccs_rshift(CPUCRISState *env)
dceaf394 EI	190	{
	191	uint32_t ccs;
	192
	193	/* Apply the ccs shift. */
	194	ccs = env->pregs[PR_CCS];
	195	ccs = (ccs & 0xc0000000) \| ((ccs & 0x0fffffff) >> 10);
	196	if (ccs & U_FLAG)
	197	{
	198	/* Enter user mode. */
	199	env->ksp = env->regs[R_SP];
	200	env->regs[R_SP] = env->pregs[PR_USP];
	201	}
	202
	203	env->pregs[PR_CCS] = ccs;
	204	}
	205
febc9920	206	void helper_rfe(CPUCRISState *env)
b41f7df0	207	{
bf443337 EI	208	int rflag = env->pregs[PR_CCS] & R_FLAG;
bf443337 EI	209
d12d51d5	210	D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
b41f7df0 EI	211	env->pregs[PR_ERP], env->pregs[PR_PID],
b41f7df0 EI	212	env->pregs[PR_CCS],
d12d51d5	213	env->btarget);
dceaf394 EI	214
	215	cris_ccs_rshift(env);
	216
	217	/* RFE sets the P_FLAG only if the R_FLAG is not set. */
bf443337	218	if (!rflag)
dceaf394	219	env->pregs[PR_CCS] \|= P_FLAG;
b41f7df0 EI	220	}
b41f7df0 EI	221
febc9920	222	void helper_rfn(CPUCRISState *env)
5bf8f1ab EI	223	{
	224	int rflag = env->pregs[PR_CCS] & R_FLAG;
	225
d12d51d5	226	D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
5bf8f1ab EI	227	env->pregs[PR_ERP], env->pregs[PR_PID],
5bf8f1ab EI	228	env->pregs[PR_CCS],
d12d51d5	229	env->btarget);
5bf8f1ab EI	230
	231	cris_ccs_rshift(env);
	232
	233	/* Set the P_FLAG only if the R_FLAG is not set. */
	234	if (!rflag)
	235	env->pregs[PR_CCS] \|= P_FLAG;
	236
8219314b LP	237	/* Always set the M flag. */
8219314b LP	238	env->pregs[PR_CCS] \|= M_FLAG_V32;
5bf8f1ab EI	239	}
5bf8f1ab EI	240
c38ac98d EI	241	uint32_t helper_lz(uint32_t t0)
	242	{
	243	return clz32(t0);
	244	}
	245
febc9920	246	uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t ccs)
abd5c94e EI	247	{
	248	/* FIXME: clean this up. */
	249
	250	/* des ref:
	251	The N flag is set according to the selected bit in the dest reg.
	252	The Z flag is set if the selected bit and all bits to the right are
	253	zero.
	254	The X flag is cleared.
	255	Other flags are left untouched.
	256	The destination reg is not affected.*/
	257	unsigned int fz, sbit, bset, mask, masked_t0;
	258
	259	sbit = t1 & 31;
	260	bset = !!(t0 & (1 << sbit));
	261	mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
	262	masked_t0 = t0 & mask;
	263	fz = !(masked_t0 \| bset);
	264
	265	/* Clear the X, N and Z flags. */
	266	ccs = ccs & ~(X_FLAG \| N_FLAG \| Z_FLAG);
95475216 EI	267	if (env->pregs[PR_VR] < 32)
95475216 EI	268	ccs &= ~(V_FLAG \| C_FLAG);
abd5c94e EI	269	/* Set the N and Z flags accordingly. */
	270	ccs \|= (bset << 3) \| (fz << 2);
	271	return ccs;
	272	}
	273
febc9920 AJ	274	static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
febc9920 AJ	275	uint32_t flags, uint32_t ccs)
b41f7df0	276	{
a8cf66bb	277	unsigned int x, z, mask;
b41f7df0 EI	278
b41f7df0 EI	279	/* Extended arithmetics, leave the z flag alone. */
30abcfc7	280	x = env->cc_x;
a8cf66bb EI	281	mask = env->cc_mask \| X_FLAG;
	282	if (x) {
	283	z = flags & Z_FLAG;
	284	mask = mask & ~z;
	285	}
	286	flags &= mask;
b41f7df0 EI	287
b41f7df0 EI	288	/* all insn clear the x-flag except setf or clrf. */
6231868b EI	289	ccs &= ~mask;
	290	ccs \|= flags;
	291	return ccs;
b41f7df0 EI	292	}
b41f7df0 EI	293
febc9920 AJ	294	uint32_t helper_evaluate_flags_muls(CPUCRISState *env,
febc9920 AJ	295	uint32_t ccs, uint32_t res, uint32_t mof)
b41f7df0	296	{
b41f7df0	297	uint32_t flags = 0;
dceaf394	298	int64_t tmp;
b41f7df0 EI	299	int dneg;
b41f7df0 EI	300
b41f7df0 EI	301	dneg = ((int32_t)res) < 0;
b41f7df0 EI	302
dceaf394 EI	303	tmp = mof;
	304	tmp <<= 32;
	305	tmp \|= res;
b41f7df0 EI	306	if (tmp == 0)
	307	flags \|= Z_FLAG;
	308	else if (tmp < 0)
	309	flags \|= N_FLAG;
	310	if ((dneg && mof != -1)
	311	\|\| (!dneg && mof != 0))
	312	flags \|= V_FLAG;
febc9920	313	return evaluate_flags_writeback(env, flags, ccs);
b41f7df0 EI	314	}
b41f7df0 EI	315
febc9920 AJ	316	uint32_t helper_evaluate_flags_mulu(CPUCRISState *env,
febc9920 AJ	317	uint32_t ccs, uint32_t res, uint32_t mof)
b41f7df0	318	{
b41f7df0	319	uint32_t flags = 0;
dceaf394	320	uint64_t tmp;
b41f7df0	321
dceaf394 EI	322	tmp = mof;
	323	tmp <<= 32;
	324	tmp \|= res;
b41f7df0 EI	325	if (tmp == 0)
	326	flags \|= Z_FLAG;
	327	else if (tmp >> 63)
	328	flags \|= N_FLAG;
	329	if (mof)
	330	flags \|= V_FLAG;
	331
febc9920	332	return evaluate_flags_writeback(env, flags, ccs);
b41f7df0 EI	333	}
b41f7df0 EI	334
febc9920	335	uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs,
6231868b	336	uint32_t src, uint32_t dst, uint32_t res)
b41f7df0	337	{
b41f7df0 EI	338	uint32_t flags = 0;
b41f7df0 EI	339
6231868b EI	340	src = src & 0x80000000;
6231868b EI	341	dst = dst & 0x80000000;
b41f7df0 EI	342
	343	if ((res & 0x80000000L) != 0L)
	344	{
	345	flags \|= N_FLAG;
a8cf66bb	346	if (!src && !dst)
b41f7df0	347	flags \|= V_FLAG;
a8cf66bb	348	else if (src & dst)
b41f7df0	349	flags \|= R_FLAG;
b41f7df0 EI	350	}
	351	else
	352	{
	353	if (res == 0L)
	354	flags \|= Z_FLAG;
a8cf66bb	355	if (src & dst)
b41f7df0	356	flags \|= V_FLAG;
a8cf66bb	357	if (dst \| src)
b41f7df0 EI	358	flags \|= R_FLAG;
	359	}
	360
febc9920	361	return evaluate_flags_writeback(env, flags, ccs);
b41f7df0 EI	362	}
b41f7df0 EI	363
febc9920	364	uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs,
6231868b	365	uint32_t src, uint32_t dst, uint32_t res)
b41f7df0	366	{
b41f7df0 EI	367	uint32_t flags = 0;
b41f7df0 EI	368
6231868b EI	369	src = src & 0x80000000;
6231868b EI	370	dst = dst & 0x80000000;
30abcfc7	371
a8cf66bb	372	if ((res & 0x80000000L) != 0L)
30abcfc7	373	{
a8cf66bb EI	374	flags \|= N_FLAG;
	375	if (!src && !dst)
	376	flags \|= V_FLAG;
	377	else if (src & dst)
	378	flags \|= C_FLAG;
	379	}
	380	else
	381	{
	382	if (res == 0L)
	383	flags \|= Z_FLAG;
	384	if (src & dst)
	385	flags \|= V_FLAG;
	386	if (dst \| src)
	387	flags \|= C_FLAG;
30abcfc7 EI	388	}
30abcfc7 EI	389
febc9920	390	return evaluate_flags_writeback(env, flags, ccs);
a8cf66bb EI	391	}
a8cf66bb EI	392
febc9920	393	uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs,
6231868b	394	uint32_t src, uint32_t dst, uint32_t res)
a8cf66bb	395	{
a8cf66bb EI	396	uint32_t flags = 0;
a8cf66bb EI	397
6231868b EI	398	src = (~src) & 0x80000000;
6231868b EI	399	dst = dst & 0x80000000;
b41f7df0 EI	400
	401	if ((res & 0x80000000L) != 0L)
	402	{
	403	flags \|= N_FLAG;
a8cf66bb	404	if (!src && !dst)
b41f7df0	405	flags \|= V_FLAG;
a8cf66bb	406	else if (src & dst)
b41f7df0	407	flags \|= C_FLAG;
b41f7df0 EI	408	}
	409	else
	410	{
	411	if (res == 0L)
	412	flags \|= Z_FLAG;
a8cf66bb	413	if (src & dst)
b41f7df0	414	flags \|= V_FLAG;
a8cf66bb	415	if (dst \| src)
b41f7df0 EI	416	flags \|= C_FLAG;
	417	}
	418
a8cf66bb	419	flags ^= C_FLAG;
febc9920	420	return evaluate_flags_writeback(env, flags, ccs);
b41f7df0 EI	421	}
b41f7df0 EI	422
febc9920 AJ	423	uint32_t helper_evaluate_flags_move_4(CPUCRISState *env,
febc9920 AJ	424	uint32_t ccs, uint32_t res)
b41f7df0	425	{
b41f7df0 EI	426	uint32_t flags = 0;
b41f7df0 EI	427
b41f7df0 EI	428	if ((int32_t)res < 0)
	429	flags \|= N_FLAG;
	430	else if (res == 0L)
	431	flags \|= Z_FLAG;
	432
febc9920	433	return evaluate_flags_writeback(env, flags, ccs);
b41f7df0	434	}
febc9920 AJ	435	uint32_t helper_evaluate_flags_move_2(CPUCRISState *env,
febc9920 AJ	436	uint32_t ccs, uint32_t res)
b41f7df0	437	{
b41f7df0	438	uint32_t flags = 0;
b41f7df0 EI	439
	440	if ((int16_t)res < 0L)
	441	flags \|= N_FLAG;
	442	else if (res == 0)
	443	flags \|= Z_FLAG;
	444
febc9920	445	return evaluate_flags_writeback(env, flags, ccs);
b41f7df0 EI	446	}
	447
	448	/* TODO: This is expensive. We could split things up and only evaluate part of
	449	CCR on a need to know basis. For now, we simply re-evaluate everything. */
febc9920	450	void helper_evaluate_flags(CPUCRISState *env)
b41f7df0	451	{
6231868b	452	uint32_t src, dst, res;
b41f7df0 EI	453	uint32_t flags = 0;
	454
	455	src = env->cc_src;
	456	dst = env->cc_dest;
	457	res = env->cc_result;
	458
30abcfc7 EI	459	if (env->cc_op == CC_OP_SUB \|\| env->cc_op == CC_OP_CMP)
30abcfc7 EI	460	src = ~src;
b41f7df0 EI	461
	462	/* Now, evaluate the flags. This stuff is based on
	463	Per Zander's CRISv10 simulator. */
	464	switch (env->cc_size)
	465	{
	466	case 1:
	467	if ((res & 0x80L) != 0L)
	468	{
	469	flags \|= N_FLAG;
	470	if (((src & 0x80L) == 0L)
	471	&& ((dst & 0x80L) == 0L))
	472	{
	473	flags \|= V_FLAG;
	474	}
	475	else if (((src & 0x80L) != 0L)
	476	&& ((dst & 0x80L) != 0L))
	477	{
	478	flags \|= C_FLAG;
	479	}
	480	}
	481	else
	482	{
	483	if ((res & 0xFFL) == 0L)
	484	{
	485	flags \|= Z_FLAG;
	486	}
	487	if (((src & 0x80L) != 0L)
	488	&& ((dst & 0x80L) != 0L))
	489	{
	490	flags \|= V_FLAG;
	491	}
	492	if ((dst & 0x80L) != 0L
	493	\|\| (src & 0x80L) != 0L)
	494	{
	495	flags \|= C_FLAG;
	496	}
	497	}
	498	break;
	499	case 2:
	500	if ((res & 0x8000L) != 0L)
	501	{
	502	flags \|= N_FLAG;
	503	if (((src & 0x8000L) == 0L)
	504	&& ((dst & 0x8000L) == 0L))
	505	{
	506	flags \|= V_FLAG;
	507	}
	508	else if (((src & 0x8000L) != 0L)
	509	&& ((dst & 0x8000L) != 0L))
	510	{
	511	flags \|= C_FLAG;
	512	}
	513	}
	514	else
	515	{
	516	if ((res & 0xFFFFL) == 0L)
	517	{
	518	flags \|= Z_FLAG;
	519	}
	520	if (((src & 0x8000L) != 0L)
	521	&& ((dst & 0x8000L) != 0L))
	522	{
	523	flags \|= V_FLAG;
	524	}
525	if ((dst & 0x8000L) != 0L
526	\|\| (src & 0x8000L) != 0L)
527	{
528	flags \|= C_FLAG;
529	}
530	}
531	break;
532	case 4:
533	if ((res & 0x80000000L) != 0L)
534	{
535	flags \|= N_FLAG;
536	if (((src & 0x80000000L) == 0L)
537	&& ((dst & 0x80000000L) == 0L))
538	{
539	flags \|= V_FLAG;
540	}
541	else if (((src & 0x80000000L) != 0L) &&
542	((dst & 0x80000000L) != 0L))
543	{
544	flags \|= C_FLAG;
545	}
546	}
547	else
548	{
549	if (res == 0L)
550	flags \|= Z_FLAG;
551	if (((src & 0x80000000L) != 0L)
552	&& ((dst & 0x80000000L) != 0L))
553	flags \|= V_FLAG;
554	if ((dst & 0x80000000L) != 0L
555	\|\| (src & 0x80000000L) != 0L)
556	flags \|= C_FLAG;
557	}
558	break;
559	default:
560	break;
561	}
562
6231868b	563	if (env->cc_op == CC_OP_SUB \|\| env->cc_op == CC_OP_CMP)
b41f7df0	564	flags ^= C_FLAG;
6231868b	565
febc9920 AJ	566	env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
febc9920 AJ	567	env->pregs[PR_CCS]);
b41f7df0	568	}
30abcfc7	569
febc9920	570	void helper_top_evaluate_flags(CPUCRISState *env)
30abcfc7 EI	571	{
	572	switch (env->cc_op)
	573	{
	574	case CC_OP_MCP:
febc9920	575	env->pregs[PR_CCS] = helper_evaluate_flags_mcp(env,
6231868b EI	576	env->pregs[PR_CCS], env->cc_src,
6231868b EI	577	env->cc_dest, env->cc_result);
30abcfc7 EI	578	break;
30abcfc7 EI	579	case CC_OP_MULS:
febc9920	580	env->pregs[PR_CCS] = helper_evaluate_flags_muls(env,
6231868b EI	581	env->pregs[PR_CCS], env->cc_result,
6231868b EI	582	env->pregs[PR_MOF]);
30abcfc7 EI	583	break;
30abcfc7 EI	584	case CC_OP_MULU:
febc9920	585	env->pregs[PR_CCS] = helper_evaluate_flags_mulu(env,
6231868b EI	586	env->pregs[PR_CCS], env->cc_result,
6231868b EI	587	env->pregs[PR_MOF]);
30abcfc7 EI	588	break;
	589	case CC_OP_MOVE:
	590	case CC_OP_AND:
	591	case CC_OP_OR:
	592	case CC_OP_XOR:
	593	case CC_OP_ASR:
	594	case CC_OP_LSR:
	595	case CC_OP_LSL:
6231868b EI	596	switch (env->cc_size)
	597	{
	598	case 4:
	599	env->pregs[PR_CCS] =
febc9920	600	helper_evaluate_flags_move_4(env,
6231868b EI	601	env->pregs[PR_CCS],
	602	env->cc_result);
	603	break;
	604	case 2:
	605	env->pregs[PR_CCS] =
febc9920	606	helper_evaluate_flags_move_2(env,
6231868b EI	607	env->pregs[PR_CCS],
	608	env->cc_result);
	609	break;
	610	default:
febc9920	611	helper_evaluate_flags(env);
6231868b EI	612	break;
	613	}
	614	break;
30abcfc7 EI	615	case CC_OP_FLAGS:
	616	/* live. */
	617	break;
a8cf66bb EI	618	case CC_OP_SUB:
	619	case CC_OP_CMP:
	620	if (env->cc_size == 4)
6231868b	621	env->pregs[PR_CCS] =
febc9920	622	helper_evaluate_flags_sub_4(env,
6231868b EI	623	env->pregs[PR_CCS],
	624	env->cc_src, env->cc_dest,
	625	env->cc_result);
a8cf66bb	626	else
febc9920	627	helper_evaluate_flags(env);
a8cf66bb	628	break;
30abcfc7 EI	629	default:
	630	{
	631	switch (env->cc_size)
	632	{
6231868b EI	633	case 4:
6231868b EI	634	env->pregs[PR_CCS] =
febc9920	635	helper_evaluate_flags_alu_4(env,
6231868b EI	636	env->pregs[PR_CCS],
	637	env->cc_src, env->cc_dest,
	638	env->cc_result);
	639	break;
	640	default:
febc9920	641	helper_evaluate_flags(env);
6231868b	642	break;
30abcfc7 EI	643	}
	644	}
	645	break;
	646	}
	647	}